#include "jesd_timer.h"

#include "ucp_ecpri.h"
#include "phy_para.h"
#include "mtimer_com.h"
#include "mtimer_drv.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "ucp_js_ctrl.h"
#include "inter_vector.h"
#include "jesd204.h"
#include "ctc_intr.h"
#include "typedef.h"
#include "jesd_csu.h"
#include "jesd_csu_nr_7ds2u.h"
#include "dw_apb_gpio.h"
#include "ecs_rfm_dm_mgt.h"
#include "ucp_mtimer.h"
#include "mtimer_cal.h"
#include "log_server.h"
#include "gtimer_drv.h"
#include "gpio_drv.h"
#include "jesd_orx_timer.h"

#ifdef TEST_ENABLE
#include "jesd_test.h"
#endif

extern stPhyScsPara* phyPara;
//extern stSfnPara     gCellSfnPara[2];
extern uint32_t		 gScsId;

uint32_t gJesdTestMode = 0;
uint32_t gJesdIOMode = JESD_CSU_CTRL;
uint32_t gJesdTFMode = TDD_MODE;

uint32_t gJesdAlarmSfnCnt = 0;

extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara 		gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerSfnCal 		gMtimerSfnCalPara[SCS_MAX_NUM];

int32_t gCsuTxAdvanceNs = JESD_TX_ADVANCE_NS;
int32_t gCsuProtocolRx = JESD_RX_ADVANCE_NS;
int32_t gCsuRxAdvanceNs = JESD_RX_ADVANCE_NS - JESD_RRU_TD;

extern void rfm1_fapi_callback();

extern void phy_sniffer_data_proc();

extern uint32_t reCfgFlag;
extern uint32_t gJesdListInitFinished;

void jesd_init(uint8_t option)
{
	int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
	int32_t flag = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);	// 0xB8
#endif
	phy_para_init(PROTOCOL_JESD, option);

	do_write(JESD_RF_TXOFF2RXON, JESD_TXRX_CHANGE_GAP);
	do_write(JESD_RF_TXON2PP1S, JESD_RF_ON_GAP);

	do_write(CSU_RX_TD_SAMPLE, JESD_RRU_TD);
	do_write(CSU_TX_ADVANCE_SAMPLE, gCsuTxAdvanceNs);

	while (JESD_CLK_INIT > (do_read_volatile(SERDES_INIT_FLAG_ADDR)))	// wait jesd serdes clk init finished
	{
		ucp_nop(1);
	}
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);	// 0xB8
#endif

    jesd_para_init();
    jesd_mtimer_init(MTIMER_JESD_RX0_ID, NR_SCS_30K, 10);
    jesd_mtimer_init(MTIMER_JESD_RX1_ID, NR_SCS_30K, 10);
#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);	// 0xB8
#endif

#if 0
	if (JESD_CSU_CTRL == gJesdIOMode)
	{
	    jesd_csu_init_nr_7ds2u();
	}
	else if (JESD_IO_CTRL == gJesdIOMode)
	{
		jesd_csu_init_nr_7ds2u_iomode();
	}

#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);	// 0x1B8
#endif
#endif
}

// 协议规定的接收提前量，NR提前13us，LTE不提前，LTE模式下，需在建小区之前，调用该接口，修改协议提前量
void jesd_set_protocol_rx_advance(uint32_t rxAdvance)
{
    gCsuProtocolRx = rxAdvance;
}

void jesd_delay_init()
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	JesdDelay_t* jesd_delay_ptr = pEcsDmLocalMgt->jesd_delay_ptr;
	
	jesd_delay_ptr->tx_offset = JESD_INT_DELAY*2; 
	jesd_delay_ptr->rx_offset = JESD_INT_DELAY*2; 
	jesd_delay_ptr->tdd_offset = JESD_INT_DELAY + EDMA_OFFSET; 
	jesd_delay_ptr->jesd_10ms2pp1s_txoffset = jesd_delay_ptr->tx_offset; // advance ns
	jesd_delay_ptr->jesd_10ms2pp1s_rxoffset = jesd_delay_ptr->rx_offset; // gpsOffset - pJesdDelay->rxOffset; // delay ns
	jesd_delay_ptr->jesd_tdd2pp1s_offset = jesd_delay_ptr->tdd_offset; // advance ns as positive number
}

int32_t jesd_mtimer_init(int32_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
{
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
	stMtimerSfnCal* pMtimerCalPara = &gMtimerSfnCalPara[nTmrId];
	
	memset(pMtimerInt, 0, sizeof(stMtimerIntStat));
	memset(pMtimerSfn, 0, sizeof(stMtimerPhyPara));
	memset(pMtimerCalPara, 0, sizeof(stMtimerSfnCal));
	
	jesd_delay_init();
	if (MTIMER_JESD_RX0_ID == nTmrId)
	{
		mtimer_para_init(MTIMER_JESD_RX0_ID, nScsId, nTddSlotNum);
		mtimer_para_init(MTIMER_JESD_TX0_ID, nScsId, nTddSlotNum);
	}
	else if (MTIMER_JESD_RX1_ID == nTmrId)
	{
		mtimer_para_init(MTIMER_JESD_RX1_ID, nScsId, nTddSlotNum);
	}
	else
	{
		return -1;
	}
	
    jesd_timer_init(nTmrId, nScsId, nTddSlotNum);
	
	return 0;
}

int32_t jesd_timer_init(int32_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
{
	if ((MTIMER_JESD_RX0_ID != nTmrId) && (MTIMER_JESD_RX1_ID != nTmrId))
	{
		return -1;
	}
	
	jesd_1pps_src_init(MTIMER_PP1S_SRC_TOD);
	mtimer_clear_all_event(nTmrId);
	set_jesd_tmr_period(nTmrId);
	//set_jesd_1pps_scratch(nTmrId);
	set_jesd_sfn_offset(nTmrId);
	
	if (MTIMER_JESD_RX0_ID == nTmrId)
	{
		//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
		//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
		mtimer_clear_all_event(MTIMER_JESD_TX0_ID);
		set_jesd_tmr_period(MTIMER_JESD_TX0_ID);
	}
	
	set_jesd_timer_int(nTmrId);

	return 0;
}

int32_t get_jesd_timer_point_para(int32_t nTmrId, int32_t tmrPoint, uint32_t* tempL, uint16_t* tempM, uint16_t* tempH)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	
        while (tmrPoint < 0)
	{
		tmrPoint += pMtimerPara->tddPeriod; //SFN_PERIOD;
	}
	
	*tempL = pMtimerPara->tmrMsPeriod * (tmrPoint % pMtimerPara->slotPeriod) / 1000;
	*tempM = tmrPoint / pMtimerPara->slotPeriod;
	if (0 == *tempL)
	{
		*tempM = (*tempM > 0) ? (*tempM - 1) : (pMtimerPara->tempM_max);
	}
	*tempL = (*tempL > 0) ? (*tempL - 1) : (pMtimerPara->tempL_max);
	
	return 0;
}

int32_t get_jesd_timer_pointns_para(int32_t nTmrId, int32_t tmrPoint, uint32_t* tempL, uint16_t* tempM, uint16_t* tempH)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	uint32_t nSlotPeriodNs = pMtimerPara->slotPeriod*1000;
	
    while (tmrPoint < 0)
	{
		tmrPoint += (pMtimerPara->tddPeriod*1000); //SFN_PERIOD;
	}
	
	*tempL = (uint64_t)pMtimerPara->tmrMsPeriod * (tmrPoint % nSlotPeriodNs) / 1000000;
	*tempM = tmrPoint / nSlotPeriodNs;
	if (0 == *tempL)
	{
		*tempM = (*tempM > 0) ? (*tempM - 1) : (pMtimerPara->tempM_max);
	}
	*tempL = (*tempL > 0) ? (*tempL - 1) : (pMtimerPara->tempL_max);
	
	return 0;
}

int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
{
	if (NULL == my_jesdtmr)
	{
		return -1;
	}
	
	uint32_t gapSymbolCnt = SLOT_SYMBOL_NUM - my_jesdtmr->num_t_dl_symb[0] - my_jesdtmr->num_t_ul_symb[0];	// 14-6-4=4
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	stMtimerPara* pMtimerTxPara = pEcsDmLocalMgt->pMtimerPara[nTmrId+2];
	JesdDelay_t*  pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
	uint32_t tdd = pMtimerPara->tddPeriod; // us
	uint32_t slotUs = pMtimerPara->slotPeriod;
	uint32_t longSymbCost = slotUs*1000*LONGCP_SAM_CNT/SLOT_SAM_CNT;	// ns
	uint32_t shortSymbCost = slotUs*1000*SHORTCP_SAM_CNT/SLOT_SAM_CNT;	// ns
	uint8_t dlSlotCnt = 0;
	uint8_t dlSymbolCnt = 0;
	
	//if (TDD_2500US_DOUBLE == pMtimerPara->frameType)
	{
		//tdd = tdd>>1;
	}

	if (FDD_MODE == gJesdTFMode)
	{
		pMtimerTxPara->txCsuOn[0].timerPoint = tdd*1000.0 - gCsuTxAdvanceNs - pJesdDelay->gps_offset*1000.0 - pMtimerInt->tmrPP1sCost; // pJesdDelay->jesd_10ms2pp1s_txoffset;
		//pMtimerTxPara->txCsuOn[0].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
		get_jesd_timer_pointns_para(nTmrId+2, pMtimerTxPara->txCsuOn[0].timerPoint, &pMtimerTxPara->txCsuOn[0].pointL, 
			&pMtimerTxPara->txCsuOn[0].pointM, &pMtimerTxPara->txCsuOn[0].pointH);
		
		pMtimerPara->rxCsuOn[0].timerPoint =  tdd*1000.0 - gCsuRxAdvanceNs - pJesdDelay->gps_offset*1000.0 - pMtimerInt->tmrPP1sCost;
		//pMtimerPara->rxCsuOn[0].timerPoint = tdd - gCsuRxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
		get_jesd_timer_pointns_para(nTmrId, pMtimerPara->rxCsuOn[0].timerPoint, &pMtimerPara->rxCsuOn[0].pointL, 
			&pMtimerPara->rxCsuOn[0].pointM, &pMtimerPara->rxCsuOn[0].pointH);
		
		debug_write((DBG_DDR_IDX_DRV_BASE+48+(0<<2)), pMtimerTxPara->txCsuOn[0].timerPoint); // 0xC0
		debug_write((DBG_DDR_IDX_DRV_BASE+50+(0<<2)), pMtimerPara->rxCsuOn[0].timerPoint); // 0xC8
	}
    else
    {
		for (int i = 0; i < 2; i++)
		{
			if ((TDD_2500US_DOUBLE == pMtimerPara->frameType) && (i&0x1))
			{
				dlSlotCnt = my_jesdtmr->num_t_dl[1];
				dlSymbolCnt = my_jesdtmr->num_t_dl_symb[1];
			}
			else
			{
				dlSlotCnt = my_jesdtmr->num_t_dl[0];
				dlSymbolCnt = my_jesdtmr->num_t_dl_symb[0];
			}
			pMtimerTxPara->txCsuOn[i].timerPoint = tdd*1000.0 - gCsuTxAdvanceNs - pJesdDelay->gps_offset*1000.0 - pMtimerInt->tmrPP1sCost; // pJesdDelay->jesd_10ms2pp1s_txoffset;
			//pMtimerTxPara->txCsuOn[i].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
			get_jesd_timer_pointns_para(nTmrId+2, pMtimerTxPara->txCsuOn[i].timerPoint, &pMtimerTxPara->txCsuOn[i].pointL, 
				&pMtimerTxPara->txCsuOn[i].pointM, &pMtimerTxPara->txCsuOn[i].pointH);
			
			pMtimerTxPara->txCsuOff[i].timerPoint = dlSlotCnt*slotUs*1000.0 + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost) - pJesdDelay->gps_offset*1000.0 - pMtimerInt->tmrPP1sCost; // pJesdDelay->jesd_10ms2pp1s_txoffset;
			//pMtimerTxPara->txCsuOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
			get_jesd_timer_pointns_para(nTmrId+2, pMtimerTxPara->txCsuOff[i].timerPoint, &pMtimerTxPara->txCsuOff[i].pointL, 
				&pMtimerTxPara->txCsuOff[i].pointM, &pMtimerTxPara->txCsuOff[i].pointH);
			
			pMtimerPara->rxCsuOn[i].timerPoint = pMtimerTxPara->txCsuOff[i].timerPoint + gapSymbolCnt*shortSymbCost - gCsuRxAdvanceNs;
			//pMtimerPara->rxCsuOn[i].timerPoint = pMtimerTxPara->txCsuOff[i].timerPoint + (gapSymbolCnt*shortSymbCost - gCsuRxAdvanceNs)/1000;
			get_jesd_timer_pointns_para(nTmrId, pMtimerPara->rxCsuOn[i].timerPoint, &pMtimerPara->rxCsuOn[i].pointL, 
				&pMtimerPara->rxCsuOn[i].pointM, &pMtimerPara->rxCsuOn[i].pointH);
			
			pMtimerPara->rxCsuOff[i].timerPoint = tdd*1000.0 - gCsuRxAdvanceNs - pJesdDelay->gps_offset*1000.0 - pMtimerInt->tmrPP1sCost; // pJesdDelay->jesd_10ms2pp1s_txoffset;
			//pMtimerPara->rxCsuOff[i].timerPoint = tdd - gCsuRxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
			get_jesd_timer_pointns_para(nTmrId, pMtimerPara->rxCsuOff[i].timerPoint, &pMtimerPara->rxCsuOff[i].pointL, 
				&pMtimerPara->rxCsuOff[i].pointM, &pMtimerPara->rxCsuOff[i].pointH);

			debug_write((DBG_DDR_IDX_DRV_BASE+992+(i<<2)), pMtimerTxPara->txCsuOn[i].timerPoint);   // 0xF80
			debug_write((DBG_DDR_IDX_DRV_BASE+993+(i<<2)), pMtimerTxPara->txCsuOff[i].timerPoint); // 0xF84
			debug_write((DBG_DDR_IDX_DRV_BASE+994+(i<<2)), pMtimerPara->rxCsuOn[i].timerPoint);     // 0xF88
			debug_write((DBG_DDR_IDX_DRV_BASE+995+(i<<2)), pMtimerPara->rxCsuOff[i].timerPoint);    // 0xF8C
#if 0
		    debug_write((DBG_DDR_IDX_DRV_BASE+960+(i<<3)), pMtimerTxPara->txCsuOn[i].timerPoint);	// 0xF00
		    debug_write((DBG_DDR_IDX_DRV_BASE+961+(i<<3)), pMtimerTxPara->txCsuOn[i].timerPoint+pMtimerTxPara->tddPeriod);	    // 0xF04
		    debug_write((DBG_DDR_IDX_DRV_BASE+962+(i<<3)), pMtimerTxPara->txCsuOn[i].pointL);	    // 0xF04
		    debug_write((DBG_DDR_IDX_DRV_BASE+963+(i<<3)), pMtimerTxPara->txCsuOn[i].pointM);	    // 0xF08

			debug_write((DBG_DDR_IDX_DRV_BASE+964+(i<<3)), pMtimerTxPara->txCsuOff[i].timerPoint);	// 0xF10
		    debug_write((DBG_DDR_IDX_DRV_BASE+965+(i<<3)), pMtimerTxPara->txCsuOff[i].timerPoint+pMtimerTxPara->tddPeriod);	            // 0xF04
			debug_write((DBG_DDR_IDX_DRV_BASE+966+(i<<3)), pMtimerTxPara->txCsuOff[i].pointL);		// 0xF14
			debug_write((DBG_DDR_IDX_DRV_BASE+967+(i<<3)), pMtimerTxPara->txCsuOff[i].pointM);		// 0xF18
			//debug_write((DBG_DDR_IDX_DRV_BASE+967+(i<<3)), pMtimerTxPara->txCsuOff[i].pointH);		// 0xF1C
#endif
		}
    }
	
	return 0;
}

int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
{
	if (NULL == my_jesdtmr)
	{
		return -1;
	}
	
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	JesdDelay_t*  pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
	uint32_t tdd = pMtimerPara->tddPeriod;
	uint32_t slotUs = pMtimerPara->slotPeriod;
	uint32_t longSymbCost = slotUs*1000*LONGCP_SAM_CNT/SLOT_SAM_CNT;	// ns
	uint32_t shortSymbCost = slotUs*1000*SHORTCP_SAM_CNT/SLOT_SAM_CNT;	// ns
	uint8_t dlSlotCnt = 0;
	uint8_t dlSymbolCnt = 0;
	
	//if (TDD_2500US_DOUBLE == pMtimerPara->frameType)
	{
		//tdd = tdd>>1;
	}

	for (int i = 0; i < 2; i++)
	{
		if ((TDD_2500US_DOUBLE == pMtimerPara->frameType) && (i&0x1))
		{
			dlSlotCnt = my_jesdtmr->num_t_dl[1];
			dlSymbolCnt = my_jesdtmr->num_t_dl_symb[1];
		}
		else
		{
			dlSlotCnt = my_jesdtmr->num_t_dl[0];
			dlSymbolCnt = my_jesdtmr->num_t_dl_symb[0];
		}
		pMtimerPara->txRfOn[i].timerPoint = tdd * 1000 - do_read_volatile(JESD_RF_TXON2PP1S) - pJesdDelay->gps_offset * 1000 - pMtimerInt->tmrPP1sCost; // pJesdDelay->jesd_10ms2pp1s_txoffset; //JESD_RF_ON_GAP; // tdd-8us
		//pMtimerPara->txRfOn[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXON2PP1S) - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset; //JESD_RF_ON_GAP; // tdd-8us
		get_jesd_timer_pointns_para(nTmrId, pMtimerPara->txRfOn[i].timerPoint, &pMtimerPara->txRfOn[i].pointL, 
			&pMtimerPara->txRfOn[i].pointM, &pMtimerPara->txRfOn[i].pointH);
		
		pMtimerPara->txRfOff[i].timerPoint = dlSlotCnt*slotUs*1000 + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost) - pJesdDelay->gps_offset*1000 - pMtimerInt->tmrPP1sCost; // pJesdDelay->jesd_10ms2pp1s_txoffset;
		//pMtimerPara->txRfOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
		get_jesd_timer_pointns_para(nTmrId, pMtimerPara->txRfOff[i].timerPoint, &pMtimerPara->txRfOff[i].pointL, 
			&pMtimerPara->txRfOff[i].pointM, &pMtimerPara->txRfOff[i].pointH);
		
		pMtimerPara->rxRfOn[i].timerPoint = pMtimerPara->txRfOff[i].timerPoint + do_read_volatile(JESD_RF_TXOFF2RXON); //JESD_TXRX_CHANGE_GAP;
		//pMtimerPara->rxRfOn[i].timerPoint = pMtimerPara->txRfOff[i].timerPoint + do_read_volatile(JESD_RF_TXOFF2RXON); //JESD_TXRX_CHANGE_GAP;
		get_jesd_timer_pointns_para(nTmrId, pMtimerPara->rxRfOn[i].timerPoint, &pMtimerPara->rxRfOn[i].pointL, 
			&pMtimerPara->rxRfOn[i].pointM, &pMtimerPara->rxRfOn[i].pointH);
		
		pMtimerPara->rxRfOff[i].timerPoint = tdd * 1000 - do_read_volatile(JESD_RF_TXOFF2RXON) - pJesdDelay->gps_offset * 1000 - pMtimerInt->tmrPP1sCost; // pJesdDelay->jesd_10ms2pp1s_txoffset; //JESD_TXRX_CHANGE_GAP; // tdd-13us
		//pMtimerPara->rxRfOff[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXOFF2RXON) - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset; //JESD_TXRX_CHANGE_GAP; // tdd-13us
		get_jesd_timer_pointns_para(nTmrId, pMtimerPara->rxRfOff[i].timerPoint, &pMtimerPara->rxRfOff[i].pointL, 
			&pMtimerPara->rxRfOff[i].pointM, &pMtimerPara->rxRfOff[i].pointH);

		debug_write((DBG_DDR_IDX_DRV_BASE+1000+(i<<2)), pMtimerPara->txRfOn[i].timerPoint); // 0xFA0
		debug_write((DBG_DDR_IDX_DRV_BASE+1001+(i<<2)), pMtimerPara->txRfOff[i].timerPoint);// 0xFA4
		debug_write((DBG_DDR_IDX_DRV_BASE+1002+(i<<2)), pMtimerPara->rxRfOn[i].timerPoint); // 0xFA8
		debug_write((DBG_DDR_IDX_DRV_BASE+1003+(i<<2)), pMtimerPara->rxRfOff[i].timerPoint);// 0xFAC
	}
	
	return 0;
}

int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
{
	if ((MTIMER_JESD_RX0_ID != nTmrId) && (MTIMER_JESD_RX1_ID != nTmrId))
	{
		return -1;
	}
	
	int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
	int32_t flag = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);	// 0xBC
#endif	
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	stMtimerPara* pMtimerTxPara = pEcsDmLocalMgt->pMtimerPara[nTmrId+2];
	JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];

	uint32_t addr = (uint32_t)&(phyPara[my_jesdtmr->scsId].gpsOffset);
	uint16_t gpsOffset = do_read_volatile_short(addr);

	pJesdDelay->gps_offset = gpsOffset;
	pJesdDelay->tx_offset = pMtimerInt->tmrPP1sCost * 5;
	pJesdDelay->rx_offset = pMtimerInt->tmrPP1sCost * 5;
	pJesdDelay->tdd_offset = pMtimerInt->tmrPP1sCost * 5 + EDMA_OFFSET;

    do_write(CPRI_ADVANCE_ADDR, pJesdDelay->tx_offset);
	do_write(CPRI_DELAY_ADDR, pJesdDelay->rx_offset);
    do_write(CPRI_TDD_ADVANCE_ADDR, pJesdDelay->tdd_offset);
	
	pJesdDelay->jesd_10ms2pp1s_txoffset = pJesdDelay->tx_offset + gpsOffset*1000; // advance ns
	pJesdDelay->jesd_10ms2pp1s_rxoffset = pJesdDelay->rx_offset + gpsOffset*1000; // gpsOffset - pJesdDelay->rxOffset; // delay ns
	pJesdDelay->jesd_tdd2pp1s_offset = gpsOffset*1000 + pJesdDelay->tdd_offset;   // advance us as positive number
	
    do_write(CPRI_TX_ADVANCE_PP1S_ADDR, pJesdDelay->jesd_10ms2pp1s_txoffset);
    do_write(CPRI_RX_ADVANCE_PP1S_ADDR, pJesdDelay->jesd_10ms2pp1s_rxoffset);
    do_write(CPRI_TDD_ADVANCE_PP1S_ADDR, pJesdDelay->jesd_tdd2pp1s_offset);

	int32_t scsId = my_jesdtmr->scsId;
	pMtimerPara->frameType = my_jesdtmr->frameType;
	pMtimerPara->scsId = scsId;
	pMtimerPara->runCoreId = (uint16_t)my_jesdtmr->runCoreId;
	pMtimerPara->tddPeriod = my_jesdtmr->t_period; // us
	pMtimerPara->tddSlotNum = my_jesdtmr->num_tti;
	pMtimerPara->slotPeriod = my_jesdtmr->t_us;
	pMtimerPara->slotMaxNum = my_jesdtmr->num_tti_per_sfn;

	pMtimerTxPara->tddPeriod = my_jesdtmr->t_period; // us
	pMtimerTxPara->tddSlotNum = my_jesdtmr->num_tti;
	pMtimerTxPara->slotPeriod = my_jesdtmr->t_us;
	pMtimerTxPara->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
	
	pMtimerSfn->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
	pMtimerSfn->slotNumPP1s = (pJesdDelay->jesd_10ms2pp1s_txoffset / (my_jesdtmr->t_us*1000)) % my_jesdtmr->num_tti_per_sfn;
	
	do_write_short((&(phyPara[scsId].slotNumOfTdd)), my_jesdtmr->num_tti);
	do_write_short((&(phyPara[scsId].mtimerId)), nTmrId);
	
	if (FDD_MODE == my_jesdtmr->frameType)
	{
		//gJesdIOMode = JESD_IO_CTRL;
		gJesdTFMode = FDD_MODE;
	}
	else if (TDD_2500US_DOUBLE == my_jesdtmr->frameType)
	{
	    pMtimerPara->tddPeriod = my_jesdtmr->t_period >> 1; // us
	    pMtimerPara->tddSlotNum = my_jesdtmr->num_tti >> 1;
	    pMtimerTxPara->tddPeriod = my_jesdtmr->t_period >> 1; // us
	    pMtimerTxPara->tddSlotNum = my_jesdtmr->num_tti >> 1;
	    //do_write_short((&(phyPara[scsId].slotNumOfTdd)), (my_jesdtmr->num_tti>>1));
	}
	__ucps2_synch(0);

	while (JESD_TRANS_INIT != (do_read_volatile(SERDES_INIT_FLAG_ADDR)))	// wait jesd serdes clk init finished
	{
		ucp_nop(1);
	}
	jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
	jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif

	pMtimerPara->tempL_max = pMtimerPara->tmrMsPeriod * pMtimerPara->slotPeriod / 1000 - 1;
	pMtimerPara->tempM_max = pMtimerPara->tddSlotNum-1;
	pMtimerPara->tempH_max = SFN_PERIOD / pMtimerPara->slotPeriod / pMtimerPara->tddSlotNum - 1;
	pMtimerTxPara->tempL_max = pMtimerTxPara->tmrMsPeriod * pMtimerPara->slotPeriod / 1000 - 1;
	pMtimerTxPara->tempM_max = pMtimerPara->tddSlotNum-1;
	pMtimerTxPara->tempH_max = SFN_PERIOD / pMtimerPara->slotPeriod / pMtimerPara->tddSlotNum - 1;

	//enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms);	// 10ms int
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);	// 0xBC
#endif

	set_jesd_sfn_offset(nTmrId);					// 10ms offset int, log
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);	// 0xBC
#endif

	//set_jesd_tx_slot_offset(nTmrId);
	//set_jesd_rx_slot_offset(nTmrId);
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);	// 0xBC
#endif

    if (MTIMER_JESD_RX0_ID == nTmrId)
	{
		set_jesd_tdd_offset(nTmrId);					// 5ms int, dma
#ifdef PALLADIUM_TEST
		flag++;
		debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
	
		if (JESD_CSU_CTRL == gJesdIOMode)
		{
			gCsuRxAdvanceNs = gCsuProtocolRx - do_read_volatile(CSU_RX_TD_SAMPLE);
			gCsuTxAdvanceNs = do_read_volatile(CSU_TX_ADVANCE_SAMPLE);

			if (FDD_MODE == gJesdTFMode)
			{
			    jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
			}
			else
			{
			    jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
			    jesd_timer_get_rf_point(nTmrId, my_jesdtmr);

			    set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
			    set_jesd_csuoff_point(MTIMER_JESD_RX0_ID, 0);
			    set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
			    set_jesd_csuoff_point(MTIMER_JESD_TX0_ID, 0);
		
			    set_jesd_rxon_point(nTmrId, 0);
			    set_jesd_rxoff_point(nTmrId, 0);
			    set_jesd_txon_point(nTmrId, 0);
			    set_jesd_txoff_point(nTmrId, 0);
			}
#ifdef PALLADIUM_TEST
			flag++;
			debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
		}
	}

	reCfgFlag = 1;
	pMtimerSfn->cellSetup = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+912), pMtimerSfn->txSfnNum);	// 0xE40
	debug_write((DBG_DDR_IDX_DRV_BASE+913), GET_STC_CNT());	        // 0xE44

	return 0;
}

int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
{
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
	
    if (MTIMER_JESD_RX0_ID == nTmrId)
	{
        clear_jesd_tdd_offset(nTmrId);
		
		clear_jesd_txon_point(nTmrId);
	    clear_jesd_txoff_point(nTmrId);
	    clear_jesd_rxon_point(nTmrId);
	    clear_jesd_rxoff_point(nTmrId);

		jesd_csu_clear_list();
	}
	clear_jesd_tx_slot_offset(nTmrId);
	clear_jesd_rx_slot_offset(nTmrId);
	
	pMtimerSfn->cellSetup = 0;
	
	if (LTE_SCS_ID == scsId)
	{
		//clear_jesd_lte_fapi_offset();
	}

	return 0;
}

void jesd_timer_rcfg_act(int32_t nTmrId)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
	int32_t nScsId = pMtimerPara->scsId;
	uint16_t runCore = pMtimerPara->runCoreId;
	uint32_t addr = (uint32_t)&(phyPara[nScsId].runCoreId);
	uint16_t cellCore = do_read_volatile_short(addr);

	set_jesd_tmr_period(nTmrId);					// set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
	if (MTIMER_JESD_RX0_ID == nTmrId)
	{
		set_jesd_tmr_period(MTIMER_JESD_TX0_ID);
	}

	//pMtimerSfn->txSfnNum = 0;
	pMtimerSfn->txSlotNum = pMtimerSfn->slotNumPP1s; // 0
	//pMtimerSfn->rxSfnNum = 0; // 1023;
	pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;

	//if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
	if (0 == pMtimerSfn->slotNumPP1s) // no frame header offset, and the first cell
	{
		//pMtimerSfn->txSfnNum++;
		//pMtimerSfn->txSfnNum &= 0x3FF;
		pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
		//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
	}
	addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
	do_write(addr, pMtimerSfn->txSfnNum);
	addr = (uint32_t)&(phyPara[nScsId].rxSfnNum);
	do_write(addr, pMtimerSfn->rxSfnNum);
	addr = (uint32_t)&(phyPara[nScsId].txSlotNum);
	do_write(addr, pMtimerSfn->txSlotNum);
	addr = (uint32_t)&(phyPara[nScsId].rxSlotNum);
	do_write(addr, pMtimerSfn->rxSlotNum);
	
	debug_write((DBG_DDR_IDX_DRV_BASE+556), cellCore);	// 0x8b0
	debug_write((DBG_DDR_IDX_DRV_BASE+557), runCore);	// 0x8b4
	debug_write((DBG_DDR_IDX_DRV_BASE+558), pMtimerSfn->txSfnNum);	// 0x8b8
	debug_write((DBG_DDR_IDX_DRV_BASE+559), pMtimerSfn->rxSfnNum);	// 0x8bc
	
	do_write(CTC_INT_TYPE_ADDR, nTmrId+1);
	// ape tmrpoints
	volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
	uint8_t apeId = 0;
	__ucps2_synch(0);
	while (32 > h1Pos)
	{
		apeId = 31 - h1Pos;
		if (8 <= apeId)
		{
			return;
		}

		set_ctc_cal_int(apeId);

		runCore &= (~(1 << apeId));
		h1Pos = __builtin_clz(runCore);
		__ucps2_synch(0);
	}

	reCfgFlag = 0; // 5;
	disable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms);	// disable 10ms int
	debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum);	// 0xE50
	debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT());	        // 0xE54
}

int32_t jesd_pin_ctrl(int32_t nTmrId)
{
	uint32_t tmrBaseAddr = 0;
	if ((MTIMER_JESD_RX1_ID == nTmrId) || (MTIMER_JESD_TX1_ID == nTmrId))
	{
		return -1;
	}
	tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;

	if (JESD_CSU_CTRL == gJesdIOMode)
	{
		do_write((tmrBaseAddr+MTMR_PIN_CTRL_REG), 0x3);		//CTRL_SEL
		do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), 0);		//IO ctrl
#if 0
        if (FDD_MODE == gJesdTFMode)
	    {
			set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
			set_jesd_rf_state(JESD_RF_TX, GPIO_ON);    // TxOn();
			set_jesd_rf_state(JESD_ANT_TX, GPIO_ON);   // TxOn();
			//set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF);    // RxOn();
			//set_jesd_rf_state(JESD_RF_RX, GPIO_OFF);    // RxOn();
			//set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF); // RxOn();
			set_jesd_rf_state(JESD_ANT_RX, GPIO_ON);    // RxOn();
			set_jesd_rf_state(JESD_RF_RX, GPIO_ON);    // RxOn();
		    set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn();
		}
#endif
	}
	else
	{
		do_write((tmrBaseAddr+MTMR_PIN_CTRL_REG), 0x1);				//CTRL_SEL
		do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), (1<<(4+(nTmrId>>1))));	//IO ctrl
		if (MTIMER_JESD_RX0_ID == nTmrId)
		{
			if (TDD_MODE == gJesdTFMode)
			{
			#if 1
			    set_jesd_rf_state(JESD_RF_RX, GPIO_OFF);    // RxOff();
			    set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF); // RxOff();
			    set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF); // RxOff();
			    ucp_nop(100000);
			    set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON);  // TxOn();
			    set_jesd_rf_state(JESD_RF_TX, GPIO_ON);     // TxOn();
			    set_jesd_rf_state(JESD_ANT_TX, GPIO_ON);    // TxOn();
		   #else
				set_jesd_rf_state(JESD_RF_TX, GPIO_OFF); 
				ucp_nop(100000);
				set_jesd_rf_state(JESD_RF_RX, GPIO_ON); 
		   #endif
			}
			else if (FDD_MODE == gJesdTFMode)
			{
			    set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
			    set_jesd_rf_state(JESD_RF_TX, GPIO_ON);    // TxOn();
			    set_jesd_rf_state(JESD_ANT_TX, GPIO_ON);   // TxOn();
			    set_jesd_rf_state(JESD_ANT_RX, GPIO_ON);    // RxOn();
			    set_jesd_rf_state(JESD_RF_RX, GPIO_ON);    // RxOn();
			    set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn();
			}
			else
			{
				return -1;
			}
		}
	}

	return 0;
}

void set_jesd_tmr_period(int32_t nTmrId)
{
	//uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	
	// 设置计数器溢出值
	uint32_t tempL = pMtimerPara->tmrMsPeriod * pMtimerPara->slotPeriod / 1000;
	uint32_t tempM = pMtimerPara->tddSlotNum;
	uint32_t tempH = SFN_PERIOD / pMtimerPara->slotPeriod / pMtimerPara->tddSlotNum;

	set_mtimer_period(nTmrId, tempL, tempM, tempH);
	
	//enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms);	// 10ms int
}

void jesd_1pps_src_init(uint8_t srcId)
{
	JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 16);
	JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 16);
}

void set_jesd_1pps_scratch(int32_t nTmrId)
{
	set_mtimer_1pps_scratch(nTmrId);
}

// 10ms
void set_jesd_sfn_offset(int32_t nTmrId)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
    uint32_t tmr0Point = SFN_PERIOD*1000 - pEcsDmLocalMgt->jesd_delay_ptr->jesd_10ms2pp1s_txoffset; // ns

	set_mtimer_tmrpoint_ns(nTmrId, MTMR_10ms_OFFSET, tmr0Point, MTIMER_MASK_62BIT);
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_10ms_OFFSET, MTMR_INT_10ms);
}

void set_jesd_tdd_offset(int32_t nTmrId)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
	
	uint32_t tmr2Point = pMtimerPara->tddPeriod*1000 - pJesdDelay->jesd_tdd2pp1s_offset;  // ns // 5ms
	set_mtimer_tmrpoint_ns(nTmrId, MTMR_TDD_OFFSET, tmr2Point, MTIMER_MASK_48BIT);
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_TDD_OFFSET, MTMR_INT_TDD_OFFSET);
}

void clear_jesd_tdd_offset(int32_t nTmrId)
{
	disable_mtimer_tmrpoint_int(nTmrId, MTMR_TDD_OFFSET, MTMR_INT_TDD_OFFSET);
}

void set_jesd_tx_slot_offset(int32_t nTmrId)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
	int32_t tmr3Point = SFN_PERIOD*1000 - pJesdDelay->jesd_10ms2pp1s_txoffset; // pJesdDelay->tx_offset; // ns
	
	set_mtimer_tmrpoint_ns(nTmrId, MTMR_TXSLOT_OFFSET, tmr3Point, MTIMER_MASK_32BIT);
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_TXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}

void clear_jesd_tx_slot_offset(int32_t nTmrId)
{
	disable_mtimer_tmrpoint_int(nTmrId, MTMR_TXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}

void set_jesd_rx_slot_offset(int32_t nTmrId)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
	int32_t tmr4Point = SFN_PERIOD*1000 - pJesdDelay->jesd_10ms2pp1s_txoffset; //gJesdDelay.rxOffset; //   // us
	
	set_mtimer_tmrpoint_ns(nTmrId, MTMR_RXSLOT_OFFSET, tmr4Point, MTIMER_MASK_32BIT);
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}

void clear_jesd_rx_slot_offset(int32_t nTmrId)
{
	disable_mtimer_tmrpoint_int(nTmrId, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}

int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
{
	uint32_t txOffset = 0;
	uint32_t rxOffset = 0;
	uint32_t runCore = apeCoreId;
	volatile uint32_t h1Pos = 0;
	uint8_t apeId = 0;
	int32_t tmrId = 0;

	EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
	pMtimerPara->runCoreId = apeCoreId;
	txOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;
	rxOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;

	enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms);	// 10ms int
	
	uint32_t tmr3Point = SFN_PERIOD*1000 - txOffset; // ns
	uint32_t tmr4Point = SFN_PERIOD*1000 - txOffset; // ns
	if (rxOffset < 0)
	{
		tmr4Point = (~rxOffset) + 1;
	}
	else
	{
		tmr4Point = SFN_PERIOD*1000 - rxOffset; // us
	}
	
	// ape tmrpoints
	h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
	while (32 > h1Pos)
	{
		apeId = 31 - h1Pos;
		if (8 <= apeId)
		{
			return -1;
		}
		// tx slot int
		tmrId = MTMR_APE0_TXSLOT + (apeId<<1);
		set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr3Point, MTIMER_MASK_32BIT);
		enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
		// rx slot int
		tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
		set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr4Point, MTIMER_MASK_32BIT);
		enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));

		runCore &= (~(1 << apeId));
		h1Pos = __builtin_clz(runCore);
	}
	
	reCfgFlag = 4;
	debug_write((DBG_DDR_IDX_DRV_BASE+914), pMtimerSfn->txSfnNum);	// 0xE48
	debug_write((DBG_DDR_IDX_DRV_BASE+915), GET_STC_CNT());	        // 0xE4c

	return 0;
}

int32_t clear_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
{
	uint32_t runCore = apeCoreId;
	volatile uint32_t h1Pos = 0;
	uint8_t apeId = 0;
	int32_t tmrId = 0;

	// ape tmrpoints
	h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
	while (32 > h1Pos)
	{
		apeId = 31 - h1Pos;
		if (8 <= apeId)
		{
			return -1;
		}
		// tx slot int
		tmrId = MTMR_APE0_TXSLOT + (apeId<<1);
		disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
		// rx slot int
		tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
		disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));

		runCore &= (~(1 << apeId));
		h1Pos = __builtin_clz(runCore);
	}

	return 0;
}

int32_t set_jesd_csuon_point(int32_t nTmrId, uint8_t nPointId)
{
	if ((MTIMER_JESD_RX0_ID != nTmrId) && (MTIMER_JESD_TX0_ID != nTmrId))
	{
		return -1;
	}

	EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
	uint32_t val = 0;
	//uint32_t tempL = 0; //pMtimerPara->tmrMsPeriod * (nTmrPoint % pMtimerPara->slotPeriod) / 1000;
	//uint32_t tempM = 0; //(nTmrPoint / pMtimerPara->slotPeriod) % periodM;
	
	if (MTIMER_JESD_RX0_ID == nTmrId)
	{
		/* rx 0 */
		val = do_read_volatile(tmrBaseAddr+MTMR_CMSK_REG);
		val |= (1<<16);
		do_write(tmrBaseAddr+MTMR_CMSK_REG, val);
#if 0
		tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->rxCsuOn[nPointId] % pMtimerPara->slotPeriod) / 1000; // rx start point
		tempM = pMtimerPara->rxCsuOn[nPointId] / pMtimerPara->slotPeriod;
		if (0 == tempL)
		{
			tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
		}
		tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
#endif
		do_write((tmrBaseAddr+MTMR_RXEN2CSU0L_REG), pMtimerPara->rxCsuOn[nPointId].pointL); /* csu RxOn */
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+116+(nTmrId<<2)), pMtimerPara->rxCsuOn[nPointId].pointL); // 0x1D0
#endif
		val = 0xC0000000 |  pMtimerPara->rxCsuOn[nPointId].pointM;			// special slot
		do_write((tmrBaseAddr+MTMR_RXEN2CSU0H_REG), val);	/* enable jesd rxdma */
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+117+(nTmrId<<2)), val); // 0x1D4
#endif
		__ucps2_synch(0);
		while (do_read_volatile(tmrBaseAddr+MTMR_RXEN2CSU0H_REG)&BIT31);
#if 0
		val = do_read_volatile(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2));
		val |= (1 << MTMR_CEVENT_RXEN2CSU0);
		do_write((tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2)), val);
#endif
	}
	else
	{
		/* tx 1 */
		val = do_read_volatile(tmrBaseAddr+MTMR_CMSK_REG);
		val |= (1<<22);
		do_write(tmrBaseAddr+MTMR_CMSK_REG, val);
#if 0		
		tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->txCsuOn[nPointId] % pMtimerPara->slotPeriod) / 1000;
		tempM = pMtimerPara->txCsuOn[nPointId] / pMtimerPara->slotPeriod;
		if (0 == tempL)
		{
			tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
		}
		tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
#endif		
		do_write((tmrBaseAddr+MTMR_TXEN2CSU1L_REG), pMtimerPara->txCsuOn[nPointId].pointL); // -TX_DELAY-OFFSET;					/* csu TxOn */
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+118+(nTmrId<<2)), pMtimerPara->txCsuOn[nPointId].pointL); // 0x1f8
#endif
		val = 0xC0000000 | pMtimerPara->txCsuOn[nPointId].pointM; 		// last slot of tdd
		do_write((tmrBaseAddr+MTMR_TXEN2CSU1H_REG), val);	/* enable jesd txdma */
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+119+(nTmrId<<2)), val); // 0x1fC
#endif
		__ucps2_synch(0);
		while (do_read_volatile(tmrBaseAddr+MTMR_TXEN2CSU1H_REG)&BIT31);
#if 0	
		val = do_read_volatile(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2));
		val |= (1 << MTMR_CEVENT_TXEN2CSU1);
		do_write(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2), val);
#endif
	}
	
	return 0;
}

int32_t set_jesd_csuoff_point(int32_t nTmrId, uint8_t nPointId)
{
	if ((MTIMER_JESD_RX0_ID != nTmrId) && (MTIMER_JESD_TX0_ID != nTmrId))
	{
		return -1;
	}

	EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
	uint32_t val = 0;
	//uint32_t tempL = 0; //pMtimerPara->tmrMsPeriod * (nTmrPoint % pMtimerPara->slotPeriod) / 1000;
	//uint32_t tempM = 0; //(nTmrPoint / pMtimerPara->slotPeriod) % periodM;
	
	if (MTIMER_JESD_RX0_ID == nTmrId)
	{
		/* rx 1*/
		val = do_read_volatile(tmrBaseAddr+MTMR_CMSK_REG);
		val |= (1<<18);
		do_write(tmrBaseAddr+MTMR_CMSK_REG, val);
#if 0
		tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->rxCsuOff[nPointId] % pMtimerPara->slotPeriod) / 1000;
		tempM = pMtimerPara->rxCsuOff[nPointId] / pMtimerPara->slotPeriod;
		if (0 == tempL)
		{
			tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
		}
		tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
#endif
		do_write((tmrBaseAddr+MTMR_RXEN2CSU1L_REG), pMtimerPara->rxCsuOff[nPointId].pointL); // -g_rfc_1us*(13-2)+RX_DELAY-OFFSET;//+CSU_RX_DELAY-OFFSET;			/* csu RxOff */
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+118+(nTmrId<<2)), pMtimerPara->rxCsuOff[nPointId].pointL); // 0x1D8
#endif
		val = 0x80000000 | pMtimerPara->rxCsuOff[nPointId].pointM;			// last slot of tdd
		do_write((tmrBaseAddr+MTMR_RXEN2CSU1H_REG), val);
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+119+(nTmrId<<2)), val); // 0x1DC
#endif
		__ucps2_synch(0);
		while (do_read_volatile(tmrBaseAddr+MTMR_RXEN2CSU1H_REG)&BIT31);
#if 0
		val = do_read_volatile(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2));
		val |= (1 << MTMR_CEVENT_RXEN2CSU1);
		do_write((tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2)), val);
#endif
	}
	else
	{
		/* tx 0*/
		val = do_read_volatile(tmrBaseAddr+MTMR_CMSK_REG);
		val |= (1<<20);
		do_write(tmrBaseAddr+MTMR_CMSK_REG, val);
#if 0		
		tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->txCsuOff[nPointId] % pMtimerPara->slotPeriod) / 1000; // -TX_DELAY+g_rfc_1us*(1)-OFFSET;
		tempM = pMtimerPara->txCsuOff[nPointId] / pMtimerPara->slotPeriod;
		if (0 == tempL)
		{
			tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
		}
		tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
#endif		
		do_write((tmrBaseAddr+MTMR_TXEN2CSU0L_REG), pMtimerPara->txCsuOff[nPointId].pointL); /* csu TxOff */
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+116+(nTmrId<<2)), pMtimerPara->txCsuOff[nPointId].pointL); // 0x1F0
#endif
		val = 0x80000000 | pMtimerPara->txCsuOff[nPointId].pointM;			// special slot
		do_write((tmrBaseAddr+MTMR_TXEN2CSU0H_REG), val);
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+117+(nTmrId<<2)), val); // 0x1f4
#endif
		__ucps2_synch(0);
		while (do_read_volatile(tmrBaseAddr+MTMR_TXEN2CSU0H_REG)&BIT31);

#if 0	
		val = do_read_volatile(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2));
		val |= (1 << MTMR_CEVENT_TXEN2CSU0);
		do_write(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2), val);
#endif
	}
	
	return 0;
}

void set_jesd_txon_point(int32_t nTmrId, uint8_t nPointId)
{
	uint32_t tmrBaseAddr = 0; 
	if (MTIMER_JESD_RX0_ID != nTmrId)
	{
		return;
	}
	tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	
	int32_t tmr29Point = pMtimerPara->txRfOn[nPointId].timerPoint;

	set_mtimer_tmrpoint_ns(nTmrId, MTMR_JESD_TXON, tmr29Point, MTIMER_MASK_48BIT);
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_TXON, MTMR_INT_TDD_OFFSET);
}

void clear_jesd_txon_point(int32_t nTmrId)
{
	disable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_TXON, MTMR_INT_TDD_OFFSET);
}


void set_jesd_txoff_point(int32_t nTmrId, uint8_t nPointId)
{
	uint32_t tmrBaseAddr = 0; 
	if (MTIMER_JESD_RX0_ID != nTmrId)
	{
		return;
	}
	tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
#if 1
	int32_t tmr28Point = pMtimerPara->txRfOff[nPointId].timerPoint;

	set_mtimer_tmrpoint_ns(nTmrId, MTMR_JESD_TXOFF, tmr28Point, MTIMER_MASK_48BIT);
#else
	uint32_t startTick = 0; 
	uint32_t cost = 0;
	do_write((tmrBaseAddr + MTMR_TnL_REG0 + (MTMR_JESD_TXOFF<<3)), pMtimerPara->txRfOff[nPointId].pointL);
	do_write((tmrBaseAddr + MTMR_TnH_REG0 + (MTMR_JESD_TXOFF<<3)), ((MTIMER_MASK_48BIT<<30) + pMtimerPara->txRfOff[nPointId].pointM));
	do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((MTMR_JESD_TXOFF>>5)<<2)), (1<<(MTMR_JESD_TXOFF&0x1F)));
	__ucps2_synch(0);
	startTick = GET_STC_CNT();
	while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((MTMR_JESD_TXOFF>>5)<<2)) & (1<<(MTMR_JESD_TXOFF&0x1F)));			// REQ reg, wait until the T0L and T0H set finished
	cost = GET_STC_CNT() - startTick;
	debug_write((DBG_DDR_IDX_DRV_BASE+121), cost); // 0x1e0
#endif
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_TXOFF, MTMR_INT_TDD_OFFSET);
}

void clear_jesd_txoff_point(int32_t nTmrId)
{
	disable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_TXOFF, MTMR_INT_TDD_OFFSET);
}

void set_jesd_rxon_point(int32_t nTmrId, uint8_t nPointId)
{
	uint32_t tmrBaseAddr = 0; 
	if (MTIMER_JESD_RX0_ID != nTmrId)
	{
		UCP_PRINT_EMPTY("jesd timer clear event error! nTmrId = 0x%x. \r\n", nTmrId);
		return;
	}
	tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
#if 1	
	int32_t tmr26Point = pMtimerPara->rxRfOn[nPointId].timerPoint;

	set_mtimer_tmrpoint_ns(nTmrId, MTMR_JESD_RXON, tmr26Point, MTIMER_MASK_48BIT);
#else
	do_write((tmrBaseAddr + MTMR_TnL_REG0 + (MTMR_JESD_RXON<<3)), pMtimerPara->rxRfOn[nPointId].pointL);
	do_write((tmrBaseAddr + MTMR_TnH_REG0 + (MTMR_JESD_RXON<<3)), ((MTIMER_MASK_48BIT<<30) + pMtimerPara->rxRfOn[nPointId].pointM));
	do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((MTMR_JESD_RXON>>5)<<2)), (1<<(MTMR_JESD_RXON&0x1F)));
	__ucps2_synch(0);
	while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((MTMR_JESD_RXON>>5)<<2)) & (1<<(MTMR_JESD_RXON&0x1F)));			// REQ reg, wait until the T0L and T0H set finished
#endif
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_RXON, MTMR_INT_TDD_OFFSET);
}

void clear_jesd_rxon_point(int32_t nTmrId)
{
	disable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_RXON, MTMR_INT_TDD_OFFSET);
}

void set_jesd_rxoff_point(int32_t nTmrId, uint8_t nPointId)
{
	uint32_t tmrBaseAddr = 0; 
	if (MTIMER_JESD_RX0_ID != nTmrId)
	{
		UCP_PRINT_EMPTY("jesd timer clear event error! nTmrId = 0x%x. \r\n", nTmrId);
		return;
	}
	tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	
	int32_t tmr27Point = pMtimerPara->rxRfOff[nPointId].timerPoint;

	set_mtimer_tmrpoint_ns(nTmrId, MTMR_CSU_INSERT, tmr27Point, MTIMER_MASK_48BIT);
	enable_mtimer_tmrpoint_int(nTmrId, MTMR_CSU_INSERT, MTMR_INT_TDD_OFFSET);
}

void clear_jesd_rxoff_point(int32_t nTmrId)
{
	disable_mtimer_tmrpoint_int(nTmrId, MTMR_CSU_INSERT, MTMR_INT_TDD_OFFSET);
}

void start_jesd_timer(int32_t nTmrId)
{
	start_mtimer(nTmrId);
}

void stop_jesd_timer(int32_t nTmrId)
{
	stop_mtimer(nTmrId);
}

int32_t set_jesd_timer_int(int32_t nTmrId)
{
	int32_t apeId = get_core_id();
	uint32_t intNum = 0;
	uint32_t baseIntNum = 0;
	irq_handler func10ms;
	irq_handler funcTdd;
	irq_handler funcSlot;
	
	if (MTIMER_JESD_RX0_ID == nTmrId)
	{
		baseIntNum = APC_JESD_RX0_SBU0_TMR_INTR0;
		func10ms = isr_jesd_10ms_rx0;
		funcTdd = isr_jesd_tdd_offset_rx0;
		funcSlot = isr_jesd_slot_rx0;
	}
	else if (MTIMER_JESD_RX1_ID == nTmrId)
	{
		baseIntNum = APC_JESD_RX1_SBU0_TMR_INTR0;
		func10ms = isr_jesd_10ms_rx1;
		funcTdd = NULL;
		funcSlot = isr_jesd_slot_rx1;
	}
	else
	{
		return -1;
	}
	
	// attach interrupt func
	int32_t ret = 0;
	intNum = baseIntNum + MTMR_INT_10ms;
	ret = smart_irq_request(intNum, func10ms);
	if (0 != ret)
	{
		debug_write(DBG_DDR_ERR_IDX(apeId, 34), ret);
	}

	intNum = baseIntNum + MTMR_INT_TDD_OFFSET;
	ret = smart_irq_request(intNum, funcTdd);
	if (0 != ret)
	{
		debug_write(DBG_DDR_ERR_IDX(apeId, 35), ret);
	}

	intNum = baseIntNum + MTMR_INT_SLOT_OFFSET;
	ret = smart_irq_request(intNum, funcSlot);
	if (0 != ret)
	{
		debug_write(DBG_DDR_ERR_IDX(apeId, 36), ret);
	}

	return 0;
}

uint32_t gRxOnCnt = 0;
uint32_t gRxOffCnt = 0;
uint32_t gTxOnCnt = 0;
uint32_t gTxOffCnt = 0;
uint32_t gRxCsuOnCnt = 0;
uint32_t gRxCsuOffCnt = 0;
uint32_t gTxCsuOnCnt = 0;
uint32_t gTxCsuOffCnt = 0;
uint32_t gPP1sFlag = 0;
void jesd_10ms_callback(uint8_t nTmrId)
{
	uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId*0x1000;
	uint32_t tmrIntcFlag = 0;
	uint32_t cEventFlag = 0;
	uint32_t tEventFlag = 0;
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[nTmrId];
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
	int32_t apeId = get_core_id();

	tmrIntcFlag = do_read_volatile(tmrBaseAddr+MTMR_INTC_REG) ;
	__ucps2_synch(0);
	if ((tmrIntcFlag & (1 << MTMR_INT_10ms)))  /* tmr int */
	{
		uint32_t cFlagAddr = tmrBaseAddr+MTMR_CINTF0_REG+2*(MTMR_INT_10ms<<2);
		uint32_t tFlagAddr = tmrBaseAddr+MTMR_TINTF00_REG+6*(MTMR_INT_10ms<<2);
		cEventFlag = do_read_volatile(cFlagAddr);
		tEventFlag = do_read_volatile(tFlagAddr);
		__ucps2_synch(0);
		if ((cEventFlag & BIT17) || (cEventFlag & BIT2) || (tEventFlag & (1<<MTMR_10ms_OFFSET)) || (tEventFlag & (1<<MTMR_TDD_OFFSET_10000)))
		{
			if (cEventFlag & BIT17) // 1pps int
			{
				do_write((tmrBaseAddr+MTMR_CEVENT_REG), BIT17);
				do_write(cFlagAddr, BIT17); // clear int flag
//uint32_t start = GET_STC_CNT();
				if (0 == pMtimerInt->pp1sIntCnt)
				{
					start_jesd_timer(nTmrId);
					gtimer2_start(0);
					if (MTIMER_JESD_RX0_ID == nTmrId)
					{
						start_jesd_timer(MTIMER_JESD_TX0_ID);
				        //debug_write((DBG_DDR_IDX_DRV_BASE+57), GET_STC_CNT());
					}
					pMtimerSfn->txSfnNum = 0;
					pMtimerInt->tmrPP1sCost = JESD_INT_DELAY; // GET_STC_CNT();
				}
				gPP1sFlag = 1;
				debug_write((DBG_DDR_IDX_DRV_BASE+70), GET_STC_CNT());     // 0x118
				//if (MTIMER_JESD_RX1_ID == nTmrId)
				if (MTIMER_JESD_RX0_ID == nTmrId)
				{
					mtimer_orx_adjust();
				}
	
#ifdef ENABLE_SFNCAL
				if (MTIMER_JESD_RX0_ID == nTmrId)
				{
					debug_write((DBG_DDR_IDX_DRV_BASE+69), pMtimerSfn->txSfnNum);
					mtimer_1pps_func(nTmrId);
				}
#endif
				pMtimerInt->pp1sIntCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+64+1+(nTmrId<<2)), pMtimerInt->pp1sIntCnt); // 0x104, 0x114

	
#ifdef PALLADIUM_TEST
				uint32_t val = 0;
				for (int32_t core = 0; core < 12; core++)
				{
					val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((core<<2)<<2));
					debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2))), val);	// 0xd00
					
					val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((1+(core<<2))<<2));
					debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 1), val);	// 0xd00
					
					val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((2+(core<<2))<<2));
					debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 2), val);	// 0xd00
					
					val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((3+(core<<2))<<2));
					debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 3), val);	// 0xd00
				}
#endif
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start));	// 0x480
			}
			if (tEventFlag & (1<<MTMR_10ms_OFFSET))				// 10ms offset int
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_10ms_OFFSET));
				do_write(tFlagAddr, (1<<MTMR_10ms_OFFSET));	// clear int flag
				pMtimerInt->sfnOffsetIntFlag = 1;
				pMtimerInt->sfnOffsetIntCnt++;
				if (0 == pMtimerSfn->cellSetup)
				{
					pMtimerSfn->txSfnNum++;
					pMtimerSfn->txSfnNum &= 0x3FF;
					do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2)+(nTmrId<<5), pMtimerSfn->txSfnNum);
				}
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C
				if (6 > gPP1sFlag)
				{
				    debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (1<<30))); // 0xD0
				    gPP1sFlag++;
				}
#endif
				if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == (pMtimerInt->sfnOffsetIntCnt&0x3)))
				{
					spu_log_server_isr();
				}
			}
			if (cEventFlag & (1<<MTMR_CEVENT_CNT14H)) 			 // 10ms int
			{
				do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_CNT14H));
				do_write(cFlagAddr, (1<<MTMR_CEVENT_CNT14H));	// clear int flag
				pMtimerInt->sfnIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(nTmrId<<2)), pMtimerInt->sfnIntCnt);	// 0x108
#endif
				uint16_t runCore = do_read_volatile_short(&(phyPara[gScsId].runCoreId));
				if (((runCore & pMtimerPara->runCoreId) == pMtimerPara->runCoreId) && (4 == reCfgFlag))
				{
					debug_write((DBG_DDR_IDX_DRV_BASE+907), GET_STC_CNT()); // 0xe2c	// timer restart finished
//uint32_t start = GET_STC_CNT();
					jesd_timer_rcfg_act(nTmrId);
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
					pMtimerCal->sfnCalFinished = 1;
					pMtimerInt->tddOffsetIntCnt = 0;
					debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
					debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
				}
			}
			if ((tEventFlag & (1<<MTMR_TDD_OFFSET_10000)) && (MTIMER_JESD_RX1_ID == nTmrId))			// orx 25ms timer int
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET_10000));
				do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET_10000)); // clear int flag
				pMtimerInt->insOffsetIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+73), pMtimerInt->insOffsetIntCnt); // 0x124
#endif
				jesd_csu_orx_start(0);
				
				debug_write((DBG_DDR_IDX_DRV_BASE+61), GET_STC_CNT()); // 0xF4
				uint64_t rt_val = get_mtimer_rt_scr_value(MTIMER_JESD_RX1_ID);
				debug_write((DBG_DDR_IDX_DRV_BASE+52), rt_val&0xFFFFFFFF); // 0xD0
				debug_write((DBG_DDR_IDX_DRV_BASE+53), rt_val>>32); // 0xD4
				
				stop_jesd_orx_timer();
				// phy callback
				//phy_sniffer_data_proc();
			}
			cEventFlag = do_read_volatile(cFlagAddr);
			tEventFlag = do_read_volatile(tFlagAddr);
		}
		do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_10ms));			// clear int
	}
}

void isr_jesd_10ms_rx0(void)
{
	uint32_t tmrId = MTIMER_JESD_RX0_ID;

	jesd_10ms_callback(tmrId);
}

void isr_jesd_10ms_rx1(void)
{
	uint32_t tmrId = MTIMER_JESD_RX1_ID;

	jesd_10ms_callback(tmrId);
}

void jesd_tdd_callback(uint8_t nTmrId)
{
	uint32_t tmrIntcFlag = 0;
	uint32_t tEventFlag = 0;
	uint32_t cEventFlag = 0;
	uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId*0x1000;
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	
	uint32_t tddVal = (1<<MTMR_TDD_OFFSET);
	uint32_t rfCtlVal = (1<<MTMR_JESD_TXOFF)|(1<<MTMR_JESD_TXON)|(1<<MTMR_JESD_RXON)|(1<<MTMR_CSU_INSERT);
	uint32_t csuCtlVal = (1<<MTMR_CEVENT_RXEN2CSU0) | (1<<MTMR_CEVENT_RXEN2CSU1) | (1<<MTMR_CEVENT_TXEN2CSU0) | (1<<MTMR_CEVENT_TXEN2CSU1);

	tmrIntcFlag = do_read_volatile(tmrBaseAddr+MTMR_INTC_REG);
	__ucps2_synch(0);
	if ((tmrIntcFlag & (1 << MTMR_INT_TDD_OFFSET)))  /* tmr int */
	{
		uint32_t cFlagAddr = tmrBaseAddr+MTMR_CINTF0_REG+2*(MTMR_INT_TDD_OFFSET<<2);
		uint32_t tFlagAddr = tmrBaseAddr+MTMR_TINTF00_REG+6*(MTMR_INT_TDD_OFFSET<<2);
		cEventFlag = do_read_volatile(cFlagAddr);
		tEventFlag = do_read_volatile(tFlagAddr);
		__ucps2_synch(0);
		
		if ((tEventFlag & (tddVal | rfCtlVal)) || (cEventFlag & (csuCtlVal)))
		{
			if (tEventFlag & tddVal) // tdd offset // 2.5/7.5/5/10ms offset
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (tEventFlag & tddVal));
				do_write(tFlagAddr, (tEventFlag & tddVal)); // clear int flag
				pMtimerInt->tddOffsetIntCnt++;
				// start_csu_timing
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+64+4), pMtimerInt->tddOffsetIntCnt); // 0x110
#endif

				uint8_t nListId = 0;
				if ((TDD_2500US_DOUBLE == pMtimerPara->frameType) && (pMtimerInt->tddOffsetIntCnt&0x1))
				{
					nListId = 1;
				}
				if ((1 == gJesdListInitFinished) && (FDD_MODE == gJesdTFMode))
				{
				    jesd_csu_rx_list_desc0_flush(0, nListId);
				}
				
				jesd_csu_tx_start(nListId);
				if ((FDD_MODE == gJesdTFMode) || (JESD_IO_CTRL == gJesdIOMode))
				{
					jesd_csu_rx_start(nListId);
				}

				if ((1 == gJesdListInitFinished) && (FDD_MODE == gJesdTFMode))
				{
			        set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
			        set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
				}

			}
			if (tEventFlag & (1<<MTMR_JESD_RXON)) 		// rx on int
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_RXON));
				do_write(tFlagAddr, (1<<MTMR_JESD_RXON));	// clear int flag
				gRxOnCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+78), gRxOnCnt); // 0x138

				set_jesd_all_rf_state(1, GPIO_ON);
				//set_jesd_rf_state(JESD_ANT_RX, GPIO_ON);
				//set_jesd_rf_state(JESD_RF_RX, GPIO_ON);
				//set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON);
				
				uint8_t nListId = 0;
				if ((TDD_2500US_DOUBLE == pMtimerPara->frameType) && (pMtimerInt->tddOffsetIntCnt&0x1))
				{
					nListId = 1;
				}
				jesd_csu_rx_start(nListId);
			}
			if (tEventFlag & (1<<MTMR_CSU_INSERT)) 		// rx off int
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_CSU_INSERT));
				do_write(tFlagAddr, (1<<MTMR_CSU_INSERT));	// clear int flag
				gRxOffCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+79), gRxOffCnt); // 0x13C
				if (6 > gPP1sFlag)
				{
				    debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (2<<30))); // 0xD0
				    gPP1sFlag++;
				}

                set_jesd_all_rf_state(1, GPIO_OFF);
				//set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF);
				//set_jesd_rf_state(JESD_RF_RX, GPIO_OFF);
				//set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF);
			}
			if (tEventFlag & (1<<MTMR_JESD_TXON)) 		// tx on int
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_TXON));
				do_write(tFlagAddr, (1<<MTMR_JESD_TXON));	// clear int flag
				gTxOnCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+76), gTxOnCnt); // 0x130
				if (6 > gPP1sFlag)
				{
				    debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (3<<30))); // 0xD0
				    gPP1sFlag++;
				}
				
				uint32_t startTick = 0; 
				uint32_t cost = 0;
				startTick = GET_STC_CNT();
				set_jesd_all_rf_state(0, GPIO_ON);
				//set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON);
				//set_jesd_rf_state(JESD_RF_TX, GPIO_ON);
				//set_jesd_rf_state(JESD_ANT_TX, GPIO_ON);
				cost = GET_STC_CNT() - startTick;
				debug_write((DBG_DDR_IDX_DRV_BASE+120), cost);  // 0x1e0
				//jesd_csu_start();
#if 1
				uint8_t nTddTxId = 0;
				uint8_t nTddRxId = 0;
				if ((JESD_CSU_CTRL == gJesdIOMode) && (MTIMER_JESD_RX0_ID == nTmrId))
				{
					if (TDD_2500US_DOUBLE == pMtimerPara->frameType)
					{
						if (pMtimerInt->tddOffsetIntCnt & 0x1)
						{
							nTddTxId = 1;
							nTddRxId = 1;
						}
						else
						{
							nTddTxId = 0;
							nTddRxId = 0;
						}
						startTick = GET_STC_CNT();
						set_jesd_txoff_point(nTmrId, nTddTxId);
						cost = GET_STC_CNT() - startTick;
						debug_write((DBG_DDR_IDX_DRV_BASE+121), cost); // 0x1e0
						
						startTick = GET_STC_CNT();
						set_jesd_csuoff_point(MTIMER_JESD_TX0_ID, nTddTxId);
						cost = GET_STC_CNT() - startTick;
						debug_write((DBG_DDR_IDX_DRV_BASE+120), cost); // 0x1e0
						
						startTick = GET_STC_CNT();
						set_jesd_rxon_point(nTmrId, nTddRxId);
						cost = GET_STC_CNT() - startTick;
						debug_write((DBG_DDR_IDX_DRV_BASE+123), cost); // 0x1e0
						
						startTick = GET_STC_CNT();
						set_jesd_csuon_point(MTIMER_JESD_RX0_ID, nTddRxId);
						cost = GET_STC_CNT() - startTick;
						debug_write((DBG_DDR_IDX_DRV_BASE+122), cost); // 0x1e0
					}
				}
#endif
			}
			if (tEventFlag & (1<<MTMR_JESD_TXOFF)) 		// tx off int
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_TXOFF));
				do_write(tFlagAddr, (1<<MTMR_JESD_TXOFF));	// clear int flag
				gTxOffCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+77), gTxOffCnt); // 0x134
				set_jesd_all_rf_state(0, GPIO_OFF);
			    //set_jesd_rf_state(JESD_TRANS_TX, GPIO_OFF);
			    //set_jesd_rf_state(JESD_RF_TX, GPIO_OFF);
			    //set_jesd_rf_state(JESD_ANT_TX, GPIO_OFF);
			}
			if (cEventFlag & (1<<MTMR_CEVENT_RXEN2CSU0))
			{
				do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_RXEN2CSU0));
				do_write(cFlagAddr, (1<<MTMR_CEVENT_RXEN2CSU0)); // clear int flag
				//do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT24)); // GPIO1B24, high
				gRxCsuOnCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+392), gRxCsuOnCnt);   // 0x620
				debug_write((DBG_DDR_IDX_DRV_BASE+393), GET_STC_CNT()); // 0x624
			}
			if (cEventFlag & (1<<MTMR_CEVENT_RXEN2CSU1))
			{
				do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_RXEN2CSU1));
				do_write(cFlagAddr, (1<<MTMR_CEVENT_RXEN2CSU1)); // clear int flag
				//do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT24)))); // GPIO1B24, high
				gRxCsuOffCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+394), gRxCsuOffCnt);  // 0x628
				debug_write((DBG_DDR_IDX_DRV_BASE+395), GET_STC_CNT()); // 0x62C
			}
			cEventFlag = do_read_volatile(cFlagAddr);
			tEventFlag = do_read_volatile(tFlagAddr);
		}
		do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET));			// clear int
	}
}

void isr_jesd_tdd_offset_rx0(void)
{
	uint32_t tmrId = MTIMER_JESD_RX0_ID;

	jesd_tdd_callback(tmrId);
}

extern uint32_t lastTxSlotCnt; // = 0;
extern uint32_t nowTxSlotCnt; // = 0;
extern uint32_t rfmSlotErrCnt; // = 0;
extern uint32_t rfmSlotErrMax; // = 0;
void jesd_slot_callback(uint8_t nTmrId)
{
	uint32_t tmrIntcFlag = 0;
	uint32_t tEventFlag = 0;
	uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
	//stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[nTmrId];
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
	int32_t apeId = get_core_id();
	stCoreInt* apeCoreIntInfo = (stCoreInt*)APE_INT_INFO_ADDR + APE_INT_MAXNUM*apeId;

	tmrIntcFlag = do_read_volatile(tmrBaseAddr+MTMR_INTC_REG);
	if ((tmrIntcFlag & (1 << MTMR_INT_SLOT_OFFSET)))  /* tmr int */
	{
		uint32_t tFlagAddr = tmrBaseAddr+MTMR_TINTF00_REG+6*(MTMR_INT_SLOT_OFFSET<<2);
		tEventFlag = do_read_volatile(tFlagAddr);
		if (tEventFlag & ((1<<MTMR_TXSLOT_OFFSET)|(1<<MTMR_RXSLOT_OFFSET)|(1<<MTMR_LTE_FAPI)))
		{
			if (tEventFlag & (1<<MTMR_TXSLOT_OFFSET)) // tx slot offset
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TXSLOT_OFFSET));
				do_write(tFlagAddr, (1<<MTMR_TXSLOT_OFFSET));	// clear int flag
//uint32_t start = GET_STC_CNT();
				if (5 == reCfgFlag)
				{
				 	reCfgFlag = 0;
				    disable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms);	// disable 10ms int
				}
				pMtimerSfn->txSlotTiming = GET_STC_CNT();
				pMtimerSfn->txSlotNum++;
				__ucps2_synch(0);
				if (pMtimerSfn->txSlotNum == pMtimerSfn->slotMaxNum)
				{
					pMtimerSfn->txSfnNum++;
					pMtimerSfn->txSfnNum &= 0x3FF;
					pMtimerSfn->txSlotNum = 0;
				}
				// test for trigger
				if (0 == pMtimerSfn->txSlotNum)
				{
					set_trigger_state(GPIO_ON);
				}
				else if ((pMtimerSfn->slotMaxNum >> 1) == pMtimerSfn->txSlotNum)
				{
					set_trigger_state(GPIO_OFF);
				}
				//__ucps2_synch(0);
#ifdef PALLADIUM_TEST
				if (8 > pMtimerInt->txSlotIntCnt)
				{
					debug_write((DBG_DDR_IDX_DRV_BASE+576+(5<<3)+pMtimerInt->txSlotIntCnt), (GET_STC_CNT())); // -gRfm0LastTxTiming)); // 0x900
				}
#endif
				pMtimerInt->txSlotIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+80), pMtimerInt->txSlotIntCnt);	// 0x140
#endif

				do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2), pMtimerSfn->txSfnNum);
				do_write(SLOT_NUM_DEBUG_ADDR+((1+(apeId<<2))<<2), pMtimerSfn->txSlotNum);
				// write sm
				do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intNum), APE_INT_TX_SLOT);
				do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intCnt), pMtimerInt->txSlotIntCnt);
				__ucps2_synch(f_SMW);
//debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
#if 0 // def PALLADIUM_TEST
				debug_write(((DBG_DDR_IDX_DRV_BASE+8192) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), gCpriTimerPara.txSlotIntCnt);		// 0x8000
				debug_write(((DBG_DDR_IDX_DRV_BASE+8704) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), get_tx_nr_slot(1)); 		// 0x8800
				nowTxSlotStcCnt = GET_STC_CNT();
				debug_write(((DBG_DDR_IDX_DRV_BASE+9216) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), nowTxSlotStcCnt); 			// 0x9000
				debug_write(((DBG_DDR_IDX_DRV_BASE+9728) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), (nowTxSlotStcCnt-lastTxSlotStcCnt)); 	// 0x9800
				lastTxSlotStcCnt = nowTxSlotStcCnt;
#endif
#if 1
				nowTxSlotCnt = GET_STC_CNT();
				if ((nowTxSlotCnt > lastTxSlotCnt) && (2 < pMtimerInt->txSlotIntCnt))
				{
					uint32_t cost = nowTxSlotCnt - lastTxSlotCnt;
					if ((505000 < cost) || (495000 > cost))
					{
						rfmSlotErrCnt++;
						debug_write((DBG_DDR_IDX_DRV_BASE+108), rfmSlotErrCnt);	// 0x1b0
						debug_write((DBG_DDR_IDX_DRV_BASE+109), cost);			// 0x1b4
					}
					if (cost > rfmSlotErrMax)
					{
						rfmSlotErrMax = cost;
					}
					debug_write((DBG_DDR_IDX_DRV_BASE+110), rfmSlotErrMax); // 0x1b8
				}
				lastTxSlotCnt = nowTxSlotCnt;
#endif
			}
			if (tEventFlag & (1<<MTMR_RXSLOT_OFFSET)) // rx slot offset
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_RXSLOT_OFFSET));
				do_write(tFlagAddr, (1<<MTMR_RXSLOT_OFFSET));	// clear int flag
//uint32_t start = GET_STC_CNT();
				pMtimerSfn->rxSlotNum++;
				__ucps2_synch(0);
				if (pMtimerSfn->rxSlotNum == pMtimerSfn->slotMaxNum)
				{
					pMtimerSfn->rxSfnNum++;
					pMtimerSfn->rxSfnNum &= 0x3FF;
					pMtimerSfn->rxSlotNum = 0;
				}
				//__ucps2_synch(0);

#ifdef PALLADIUM_TEST
				if (8 > pMtimerInt->rxSlotIntCnt)
				{
					debug_write((DBG_DDR_IDX_DRV_BASE+624+(5<<3)+pMtimerInt->rxSlotIntCnt), (GET_STC_CNT())); // -gRfm0LastTxTiming)); // 0x900
				}
#endif

				pMtimerInt->rxSlotIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+81), pMtimerInt->rxSlotIntCnt);	// 0x144
#endif

				do_write(SLOT_NUM_DEBUG_ADDR+((2+(apeId<<2))<<2), pMtimerSfn->rxSfnNum);
				do_write(SLOT_NUM_DEBUG_ADDR+((3+(apeId<<2))<<2), pMtimerSfn->rxSlotNum);
				// write sm
				do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intNum), APE_INT_RX_SLOT);
				do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intCnt), pMtimerInt->rxSlotIntCnt);
				__ucps2_synch(f_SMW);
//debug_write((DBG_DDR_IDX_DRV_BASE+291), (GET_STC_CNT()-start)); // 0x48c
			}
			if (tEventFlag & (1<<MTMR_LTE_FAPI))				// LTE FAPI
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_LTE_FAPI));
				do_write(tFlagAddr, (1<<MTMR_LTE_FAPI)); // clear int flag
				pMtimerInt->lteFapiIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+64+14), pMtimerInt->lteFapiIntCnt);	// 0x138
				debug_write((DBG_DDR_IDX_DRV_BASE+672+(pMtimerInt->lteFapiIntCnt&0x1f)), (GET_STC_CNT()-pMtimerSfn->txSlotTiming)); //get_tx_nr_slot(1)); // 0xb7e06a80
#endif
				rfm1_fapi_callback();
			}
			tEventFlag = do_read_volatile(tFlagAddr);
		}
		do_write((tmrBaseAddr+MTMR_INTC_REG), (1<<MTMR_INT_SLOT_OFFSET));			// clear int
	}
}

void isr_jesd_slot_rx0(void)
{
	uint32_t tmrId = MTIMER_JESD_RX0_ID;

	jesd_slot_callback(tmrId);
}

void isr_jesd_slot_rx1(void)
{
	uint32_t tmrId = MTIMER_JESD_RX1_ID;

	jesd_slot_callback(tmrId);
}


