// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : cpri_test_case34.c
// Author        : xinxin.li
// Created On    : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#include "typedef.h"
#include "ucp_utility.h"
//#include "cpri_csu_lte_fdd.h"
#include "cpri_csu_api.h"

#include "cpri_test_case61.h"
#include "cpri_timer.h"
#include "ape_csu.h"
#include "cpri_test.h"
#include "ucp_printf.h"
#include "HeaderRam.h"
#include "cpri_driver.h"
#include "lte_mem_def.h"
#include "phy_para.h"
#include "hw_cpri.h"

#include <malloc.h>
//uint32_t srcImData[4*1024] = {0};	// 16KB
extern uint32_t 		gCpriTestMode;
extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];

extern uint32_t         gCpriTestMode;
//extern uint32_t         CPRI_OPTION;
extern uint32_t			gCpriCsuDummyFlag;
extern volatile uint32_t gVendorFlag;

extern uint32_t Nr_CompressData[1920];
extern uint32_t Lte_compressData[960];
extern uint32_t Nr_antData01[122880];
extern uint32_t Nr_antData23[122880];
extern uint32_t Lte_antData[30720];
extern uint32_t Agc_Data[2280];

#define HeaderTestCnt   10

int32_t fh_data_init(void)
{
	gCpriTestMode = CPRI_TEST_MODE;
	gCpriCsuDummyFlag  = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300

//	Get_Cpri_OptionId();//get cpri option value
//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
		
	Axc_data_init();//init axc data
	UCP_PRINT_EMPTY("Axc data init.\r\n");
	HeaderTxRam_data_init();
	//HeaderTxRam_init();
	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
	return 0;
}

int32_t fh_drv_init(void)
{
	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);

	return 0;
}

int32_t fh_csu_test_init(void)
{
	Config_Cpri_Csu_Lte();
	return 0;
}

void fh_test_case()
{
	UCP_API_CPRI_CSU_START();
}


void HeaderTxRam_data_init()
{
	for(int i=0;i<16*HeaderTestCnt;i++)
	{
		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
	}
#if 0
	for(int i=0;i<16*HeaderTestCnt;i++)
	{
		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
	}
#endif
}

void Axc_data_init()
{
	uint8_t idID = 0;
	uint8_t idSlot = 0;			// even slot, odd slot
//	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
//	uint8_t idSymbol = 0;
//	uint16_t idBF = 0;
//	uint16_t idWord = 0;

//	uint32_t* pSrcAddr = 0;
	uint32_t  srcAddr = 0;
	uint32_t  dstAddr = 0;
	uint32_t  dataLen = 0;
	uint16_t  bfByteCnt = 0;
	//uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;//1920
	uint32_t  slotBfCnt = 256*15;//3840,1ms是一个时隙
//	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//961
//	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//959
//	uint32_t  symbolBfCnt = 0;
//	uint32_t  idSlotBf = 0;
//	uint32_t  val = 0;
	
	//uint32_t* srcImData = dmalloc(10240, DM0);
	
	//debug_write((DBG_DDR_IDX_DRV_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
	//debug_write((DBG_DDR_IDX_DRV_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304

	uint32_t cpyCnt = 0;
	//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
	//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
	cpyCnt++;

	// valid data
	/******* compress factor********/
	//NR
	for (idSlot = 0; idSlot <= 1; idSlot++)
	{
		bfByteCnt = 2;//NR:2B	
		dataLen = (bfByteCnt*slotBfCnt); 
		//pSrcAddr = srcImData;
		if (0 == idSlot)	// even slot
		{
			dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
			
		}
		else				// odd slot
		{
			dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
			
		}
		srcAddr =  (uint32_t)(&Nr_CompressData[0]);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//		cpyCnt++;
		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
//		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
	}
	//LTE
	for (idSlot = 0; idSlot <= 1; idSlot++)
		{
			bfByteCnt = 1;//LTE:1B	
			dataLen = (bfByteCnt*slotBfCnt); 
		//	pSrcAddr = srcImData;
			if (0 == idSlot)	// even slot
			{
				dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR;
				
			}
			else				// odd slot
			{
				dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR;
				
			}
			
			srcAddr = (uint32_t)(&Lte_compressData[0]);//Lte_compressData;
	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
	//		cpyCnt++;
			memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
		//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
		}

	// IQ data	
//	for (idID = 1; idID < (CPRI_LTEFDD_AXCID_NUM-1); idID++)//NR:4AXC;LTE:2AXC
	for (idID = 2; idID < 5; idID++)//NR:4AXC;LTE:2AXC
	{
		if(idID < 4)//nr
		{
			bfByteCnt = 64*2;//2个天线合并
		}
		else//lte
		{
			bfByteCnt = 16*2;//2个天线合并
		}
		dataLen = slotBfCnt*bfByteCnt;
		for (idSlot = 0; idSlot <= 1; idSlot++)
		{
//			idSlotBf = 0;
			if (1 == idSlot) //奇时隙
			{
				if(2 == idID) //NR :2条天线数据交织:64*2B
				{
					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0;
					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
				}
				else if(3 == idID)//NR :2条天线数据交织:64*2B
				{
					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1;
					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
				}
				else //LTE :2条天线数据交织:16*2B 
				{
					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI;
					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
				}
				
			}
			else//偶时隙
			{	
				if(2 == idID) //NR :2条天线数据交织:64*2B
				{
					
					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0;
					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
				}
				else if(3 == idID)//NR :2条天线数据交织:64*2B
				{
					
					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1;
					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
				}
				else //LTE :2条天线数据交织:16*2B 
				{
					
					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI;
					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
				}
				
			}
		//	for (idSymbol = 0; idSymbol < 7; idSymbol++)
			{
				
				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//					cpyCnt++;
			//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
			//	dstAddr += dataLen;
			}
		}
	}
	
	// agc factor
	//NR	
	for (idSlot = 0; idSlot <= 1; idSlot++)
	{
		bfByteCnt = 3;
	//	pSrcAddr = srcImData;
		dataLen = (bfByteCnt*slotBfCnt); 
		if (0 == idSlot)	// even slot
		{
			dstAddr = SM0_LTE_CELL0_EVEN_COM_AGC_ADDR;
			
		}
		else				// odd slot
		{
			dstAddr = SM0_LTE_CELL0_ODD_COM_AGC_ADDR;
			
		}
		srcAddr = (uint32_t)(&Agc_Data[0]);//srcAddr = Agc_Data;	
		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//		cpyCnt++;
		
	//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	}

}

uint32_t Txdata[48] ={0};
uint32_t Rxdata0[48] ={0};

uint32_t Header_error0=0;
uint32_t Header_error1 = 0;
//uint32_t HeaderRxtimes = 0;
extern uint32_t HeaderTxtimes;

void Cpri_Header_Rx(void)
{
	uint32_t j= 0;
	if(OTIC_MAP_FIGURE12 == gVendorFlag)
	{
//		HeaderRxtimes++;
#if 1
		while(1)
		{
			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
			{
				break;
			}
		}
#endif
		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));

		for(j=0;j<4;j++)
		{
			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);

		}
		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
		for(j=0;j<48;j++)
		{
			if (Rxdata0[j] != Txdata[j])//vendor
			{
				Header_error0++;
				Header_error1++;
			}
		}

		
		if(Header_error1!=0)
		{
			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
			Header_error1 =0;
		}
		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
		}
}


uint32_t gCompWordCnt = 0;
uint32_t gErrSlotIdCnt = 0;
uint32_t gCompSlotIdCnt = 0;
uint32_t gBfStartErr = 0;
uint32_t cnt = 0;
void fh_data_check(uint32_t times)
{
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
	if (4 <= pMtimerInt->csuEnCnt)
	{
		gCompWordCnt = 0;
		for (int32_t i = 0; i < (CPRI_CASE61_SLOT_NUM>>1); i++)
		{
			cpri_check_slot_data(i);
		}
		#if 0
		if(24000 <= pMtimerInt->csuEnCnt)
		{ 
			
			//if(0 == cnt)
			{
				if(0 == gErrSlotIdCnt)
				{ 
					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
					UCP_PRINT_WARN("cpri test pass!\r\n");
				}
				else
				{
					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
				}
				cnt++;				
			}			
		}
		#endif
		Cpri_Header_Rx();
	}
}

void cpri_check_slot_data(uint32_t slotNum)
{
	// move data from sm to ddr
	uint32_t slotId = 0;
	uint32_t srcAddr = 0;
//	uint32_t srcAddr1 = 0;
	uint32_t realSrcAddr = 0;
//	uint32_t dataLen = 0;
//	uint8_t bitOffset = 0;
//	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
	uint32_t slotBfCnt = 3840;//1ms：1个slot，基本帧数
	uint8_t	bfWordCnt = 0;

	uint8_t slotVal = 0;
	uint8_t idVal = 0;
	int32_t bfStart = 0;

	uint32_t compVal = 0;
	uint32_t recvVal = 0;
	uint32_t recvAddr = 0;
	
	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
//	__ucps2_synch(0);
	for (uint32_t i = 0; i < 6; i++)
	{
		gCompSlotIdCnt++;
		idVal = i;
		bfStart = 0;
//		__ucps2_synch(0);
		
		if((slotId & 0x1) == 1) //奇时隙
		{
			slotVal = 1;
			if(0 == i)//NR :压缩因子和AGC:2B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
			}		
			else if(1 == i) //LTE :压缩因子:1B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR;
			}
			else if(2 == i) //NR :2条天线数据交织:64*2B
			{
				bfWordCnt = (128>>2);
				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0;
			}
			else if(3 == i)//NR :2条天线数据交织:64*2B
			{
				bfWordCnt = (128>>2);
				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1;
			}
			else if(4 == i)//LTE :2条天线数据交织:16*2B 
			{
				bfWordCnt = (32>>2);
				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI;
			}
			else// if(5 == i)//NR :AGC:2B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
			}
			/********
			else//LTE :AGC:1B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
			}
			***********/
		}
		else//偶时隙
		{
			slotVal = 0;
			if(0 == i)//NR :压缩因子和AGC:2B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
			}		
			else if(1 == i) //LTE :压缩因子:1B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR;
			}
			else if(2 == i) //NR :2条天线数据交织:64*2B
			{
				bfWordCnt = (128>>2);
				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0;
			}
			else if(3 == i)//NR :2条天线数据交织:64*2B
			{
				bfWordCnt = (128>>2);
				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1;
			}
			else if(4 == i)//LTE :2条天线数据交织:16*2B 
			{
				bfWordCnt = (32>>2);
				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI;
			}
			else// if(5 == i)//NR :AGC:2B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
			}
			/******
			else//LTE :AGC:1B
			{
				bfWordCnt = 1;
				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
			}
			*********/
		}
					
		if (0 == i)	// compress factor:NR
		{
			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
				//	compVal = (slotVal<<28) | (0<<24) | ((idBf<<1)<<8) | (idWord);
					compVal = do_read_volatile(Nr_CompressData+idBf*bfWordCnt + idWord);//Nr_CompressData[idBf*bfWordCnt + idWord];
					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;
					
					__ucps2_synch(0);
					#if 0
					if ((7 == slotId) && (686 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
						if (0 > (idBf-(bfStart>>1)))
						{
							gBfStartErr++;
							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
						}
						realSrcAddr = srcAddr1;
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
					#endif
					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
					realSrcAddr = srcAddr;
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						if (gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
						}
						gErrSlotIdCnt++;
//						break;
//						break;
					}
//					__ucps2_synch(0);
				}
			}
		}
		else if(1 == i)// compress factor:lte
		{
			for (int32_t idBf = 0; idBf < (slotBfCnt>>2); idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
				//	compVal = (slotVal<<28) | (1<<24) | ((idBf<<2)<<8) | (idWord);
					compVal =do_read_volatile(Lte_compressData+idBf*bfWordCnt + idWord);// Lte_compressData[idBf*bfWordCnt + idWord];
				
					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;
					__ucps2_synch(0);
					#if 0
					if ((7 == slotId) && (686 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
						if (0 > (idBf-(bfStart>>1)))
						{
							gBfStartErr++;
							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
						}
						realSrcAddr = srcAddr1;
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
					#endif
					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
					realSrcAddr = srcAddr;
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						if (gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
						}
						gErrSlotIdCnt++;
//						break;
//						break;
					}
//					__ucps2_synch(0);
				}
			}
		}
		else if((1 < i) && (5 > i))		// axc data
		{
			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
					if(4 == i)//LTE
					{
					// 	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<3)+idWord)<<8) | (idWord);
					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
						compVal = do_read_volatile(Lte_antData+idBf*bfWordCnt + idWord);//Lte_antData[idBf*bfWordCnt + idWord];
					}
					else if(3 == i)
					{
					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
						compVal = do_read_volatile(Nr_antData23+idBf*bfWordCnt + idWord);//Nr_antData23[idBf*bfWordCnt + idWord];
					}
					else //if (2 == i)
					{
					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
						compVal = do_read_volatile(Nr_antData01+idBf*bfWordCnt + idWord);//Nr_antData01[idBf*bfWordCnt + idWord];
					}
					
//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;					
					__ucps2_synch(0);
					#if 0
					if ((7 == slotId) && (1372 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
						realSrcAddr = srcAddr1;
						if (0 > (idBf-bfStart))
						{
							gBfStartErr++;
							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
						}
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
					#endif
					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
					realSrcAddr = srcAddr;
//					__ucps2_synch(0);					
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						if (gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
						}
						gErrSlotIdCnt++;
//						break;
//						break;
					}
				}
			}
		}
		else// if(5 == i) //NR:AGC
		{
		   	for (int32_t idBf = 0; idBf <((slotBfCnt*3) >> 2); idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<1)<<8) | (idWord);
				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<2)<<8) | (idWord);
					compVal = do_read_volatile(Agc_Data + idBf*bfWordCnt + idWord);//Agc_Data[idBf*bfWordCnt + idWord];
					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;
					
					__ucps2_synch(0);
					#if 0
					if ((7 == slotId) && (686 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
						if (0 > (idBf-(bfStart>>1)))
						{
							gBfStartErr++;
							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
						}
						realSrcAddr = srcAddr1;
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
					#endif
					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
					realSrcAddr = srcAddr;
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						if (gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
						}
						gErrSlotIdCnt++;
	//						break;
	//						break;
					}
	//					__ucps2_synch(0);
				}
			}
		}
	
		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
	}
}

