// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : phy_queue_proc.c
// Author        : xianfeng.du
// Created On    : 2023-02-06
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#include "rfm1_drv.h"
#include "app_interface.h"
#include "phy_queue_proc.h"
#include "ecs_rfm_spu1_oam.h"

void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size);

uint8_t phy_check_msg_type(uint32_t u32msg_addr)
{
    uint8_t u8msg_type       = 0;
    uint32_t u32check_addr   = 0;

    u32check_addr = u32msg_addr - (uint32_t)ECS_MSG_HEAD_LEN;
    u8msg_type    = do_read_byte(u32check_addr + 5); //padding1

    return u8msg_type;
}

void phy_queue_polling(void)
{
    uint32_t u32msg_addr = 0;
    uint32_t u32msg_size = 0;
    uint8_t u8msg_type    = 0;
    uint8_t  u8que_id = (uint8_t)get_core_id();

    uint8_t u8ret = ecs_hw_que_get_info(u8que_id, &u32msg_addr, &u32msg_size);
    if (0 == u8ret)
    {
        u8msg_type = phy_check_msg_type(u32msg_addr);
        debug_write(DBG_DDR_COMMON_IDX(u8que_id, 35), u8msg_type);/*0xB7E0168C*/

        if(SPU_OAM_MSG_TYPE == u8msg_type)/* OAM MSG */
        {
            #ifdef PCIE_BACKHAUL
                oam_msg_proc_test(u32msg_addr, u32msg_size);
            #else
                oam_msg_proc(u32msg_addr, u32msg_size);
            #endif
        }
        else
        {
            phy_msg_proc(u32msg_addr, u32msg_size);//phy application func
            //check_phy_cell();
        }
    }

    return;
}



