
#include "typedef.h"
#include "ucp_utility.h"
#include "cpri_csu_nr_7ds2u.h"
#include "mtimer_drv.h"
#include "cpri_timer.h"
#include "ape_csu.h"
#include "mem_sections.h"

#include "ucp_printf.h"
#include "HeaderRam.h"
#include "cpri_driver.h"
#include "cpri_test_mode.h"
#include "spu_shell.h"
#include "mtimer_com.h"

#include <malloc.h>


//uint32_t* TEST_MODE = (uint32_t *)ENTER_TEST_MODE_ADDR;

DDR0 uint32_t test_srcImData[4*1024] = {0};
// uint32_t test_srcImData[4*1024] = {0};

extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
extern volatile uint32_t    CsuStopFlag ;
extern uint32_t gCpriCsuCmdCnt;


uint32_t NormalToTest = 0;
uint32_t TestToNormal = 0;

void spu_shell_cpri_cmd()
{
	spu_insert_cmd_ext("ct_ape", (OSP_FUNCPTR)cpri_test_mode, "cpri test mode", 1);
}

void Axc_data_test_init()
{
	uint8_t idID = 0;
	uint8_t idSlot = 0;			// even slot, odd slot
	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
	uint8_t idSymbol = 0;
	uint16_t idBF = 0;
	uint16_t idWord = 0;

	uint32_t* pSrcAddr = 0;
	uint32_t  srcAddr = 0;
	uint32_t  dstAddr = 0;
	uint32_t  dataLen = 0;
	uint16_t  bfByteCnt = 0;
	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;
	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;
	uint32_t  symbolBfCnt = 0;
	uint32_t  idSlotBf = 0;
	uint32_t  val = 0;
	
	//uint32_t* srcImData = dmalloc(10240, DM0);
	
	//debug_write((DBG_DDR_IDX_CPRI_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
	//debug_write((DBG_DDR_IDX_CPRI_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304

	uint32_t cpyCnt = 0;
	debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)test_srcImData); // 0x310
	debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
	cpyCnt++;

	// valid data
	// compress factor
	for (idSlot = 0; idSlot <= 1; idSlot++)
	{
		bfByteCnt = 2;
		
		//pSrcAddr = test_srcImData;
		if (0 == idSlot)	// even slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
		}
		else				// odd slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
		}
		pSrcAddr = ((uint32_t*)dstAddr);
		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
		{
			val = (idSlot<<28) | ((idBF<<1)<<8) | (0);
			//*pSrcAddr = val;
			do_write(((uint32_t)pSrcAddr), val);
			pSrcAddr++;
		}
		dataLen = (bfByteCnt*slotBfCnt); 
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//		cpyCnt++;
		
		//memcpy_ucp((void*)dstAddr,(void*)test_srcImData, dataLen);
		//memcpy((void*)dstAddr,(void*)test_srcImData, dataLen);

	}

	// IQ data	
	for (idID = 1; idID < 5; idID++)
	{
		bfByteCnt = 64;
		for (idSlot = 0; idSlot <= 1; idSlot++)
		{
			idSlotBf = 0;
			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
			{
				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
				}
				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
				}
				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
				}
				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
				}
				pSrcAddr = ((uint32_t*)dstAddr);
				for (idSymbol = 0; idSymbol < 7; idSymbol++)
				{
					//pSrcAddr = test_srcImData;
					if ((0 == idSymbol) && (0 == idSymbolBlock))
					{
						symbolBfCnt = LONGCP_BF_CNT;
					}
					else
					{
						symbolBfCnt = SHORTCP_BF_CNT;
					}
					for (idBF = 0; idBF < symbolBfCnt; idBF++)	// basic frame
			 		{
						for (idWord = 0; idWord < (bfByteCnt>>2); idWord++)
						{
								val = (idSlot<<28) | (idID<<24) | ((idSlotBf++)<<8) | (idWord);
								//*pSrcAddr = val;
								do_write(((uint32_t)pSrcAddr), val);
								pSrcAddr++;
						}
			 		}
					dataLen = symbolBfCnt*bfByteCnt;
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//					cpyCnt++;
					//memcpy_ucp((void*)dstAddr,(void*)test_srcImData, dataLen);
				//	memcpy((void*)dstAddr,(void*)test_srcImData, dataLen);

					dstAddr += dataLen;
				}
			}
		}
	}

	// agc factor
	for (idSlot = 0; idSlot <= 1; idSlot++)
	{
		bfByteCnt = 2;
		
	//	pSrcAddr = test_srcImData;
		if (0 == idSlot)	// even slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_AGC_ADDR;
		}
		else				// odd slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR;
		}
		pSrcAddr = ((uint32_t*)dstAddr);
		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
		{
			val = (idSlot<<28) | (5<<24) | ((idBF<<1)<<8) | (0);
			//*pSrcAddr = val;
			do_write(((uint32_t)pSrcAddr), val);
			pSrcAddr++;
		}
		dataLen = (bfByteCnt*slotBfCnt); 
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//		cpyCnt++;
		
		//memcpy_ucp((void*)dstAddr,(void*)test_srcImData, dataLen);
	//	memcpy((void*)dstAddr,(void*)test_srcImData, dataLen);

//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	}

	// dummy data
	// compress factor
	uint8_t bitOffset = 1; // one bf, 2B
	uint8_t tag = 0;
	// S slot, symbol6~13, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
	dstAddr = CPRI_NR7DS2U_TX_DUMMY_COMPRESS_ADDR;
	dataLen = (SHORTCP_BF_CNT*8)<<bitOffset;
	ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	// slot8, even slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	// slot9, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);

	// axc data
	bitOffset = 6;		// one bf, 64B
	for (uint8_t antId = 0; antId < 4; antId++)
	{
		// S slot, symbol6, odd slot
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (antId*(f7BfCnt<<bitOffset)) + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
		dstAddr = CPRI_NR7DS2U_TX_DUMMY_AXC1DATA_ADDR + antId*CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN;
		dataLen = (SHORTCP_BF_CNT)<<bitOffset;
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		// S slot, symbol7~13
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (antId*(b7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = b7BfCnt<<bitOffset;
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		// slot8, even slot, symbol0~6
		srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + (antId*(f7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = f7BfCnt<<bitOffset;
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		// slot8, even slot, symbol7~13
		srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + (antId*(b7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = b7BfCnt<<bitOffset;
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		// slot9, odd slot, symbol0~6
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (antId*(f7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = f7BfCnt<<bitOffset;
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		// slot9, odd slot, symbol7~13
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (antId*(b7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = b7BfCnt<<bitOffset;
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		debug_write((DBG_DDR_IDX_CPRI_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	}

	// AGC factor
	bitOffset = 1; // one bf, 2B
	// S slot, symbol6~13, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
	dstAddr = CPRI_NR7DS2U_TX_DUMMY_AGC_ADDR;
	dataLen = (SHORTCP_BF_CNT*8)<<bitOffset;
	ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	// slot8, even slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_AGC_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	// slot9, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
}

uint32_t test_gCompWordCnt = 0;
uint32_t test_gErrSlotIdCnt = 0;
uint32_t test_gCompSlotIdCnt = 0;
uint32_t test_gBfStartErr = 0;
uint32_t test_cnt = 0;

void cpri_test_check_slot_data(uint32_t slotNum)
{
	// move data from sm to ddr
	uint32_t slotId = 0;
	uint32_t srcAddr = 0;
	uint32_t srcAddr1 = 0;
	uint32_t realSrcAddr = 0;
	uint32_t dataLen = 0;
	uint8_t bitOffset = 0;
	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
	uint8_t	bfWordCnt = 0;

	uint8_t slotVal = 0;
	uint8_t idVal = 0;
	int32_t bfStart = 0;

	uint32_t compVal = 0;
	uint32_t recvVal = 0;
	uint32_t recvAddr = 0;
	
	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
//	__ucps2_synch(0);
	for (uint32_t i = 0; i < 5; i++)
	{
		test_gCompSlotIdCnt++;
		idVal = i;
		bfStart = 0;
//		__ucps2_synch(0);
		if ((slotId >=0) && (slotId <= 6))
		{
			slotVal = slotId & 0x1;
			
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = 64>>2;
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
			}
			dataLen = slotBfCnt << bitOffset;
		}
		else if (7 == slotId)		// compare S slot, odd slot
		{
			bfStart = (LONGCP_BF_CNT+SHORTCP_BF_CNT*9);
			slotVal = 1;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset);
				srcAddr1 = CPRI_NR7DS2U_RX_SLOTS_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = (64>>2);
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(slotBfCnt<<bitOffset);
				srcAddr1 = CPRI_NR7DS2U_RX_SLOTS_AXCDATA_ADDR + (i-1)*((SHORTCP_BF_CNT*4)<<bitOffset);
			}
			dataLen = slotBfCnt << bitOffset;
		}
		else if (8 == slotId)		// current slot is odd slot, compare even slot, slot8
		{
			slotVal = 0;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = (64>>2);
				srcAddr = CPRI_NR7DS2U_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)*(slotBfCnt<<bitOffset));
			}
			dataLen = slotBfCnt << bitOffset;
		}
		else if (9 == slotId)	// compare odd slot, slot9
		{
			slotVal = 1;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_SLOT_ODD_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = (64>>2);
				srcAddr = CPRI_NR7DS2U_RX_SLOT_ODD_AXCDATA_ADDR + ((i-1)*(slotBfCnt<<bitOffset));
			}
			dataLen = slotBfCnt << bitOffset;
		}

		if (0 == i)	// compress factor
		{
#if 1
			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
					compVal = (slotVal<<28) | (idVal<<24) | ((idBf<<1)<<8) | (idWord);
					
					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_CPRI_BASE+1034), test_gCompWordCnt); 
					test_gCompWordCnt++;
					__ucps2_synch(0);
					
					if ((7 == slotId) && (686 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
						if (0 > (idBf-(bfStart>>1)))
						{
							test_gBfStartErr++;
							debug_write((DBG_DDR_IDX_CPRI_BASE+1035), test_gBfStartErr); 
						}
						realSrcAddr = srcAddr1;
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						//if (test_gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_CPRI_BASE+1036+((test_gErrSlotIdCnt<<3)&0xFF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_CPRI_BASE+1037+((test_gErrSlotIdCnt<<3)&0xFF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_CPRI_BASE+1038+((test_gErrSlotIdCnt<<3)&0xFF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_CPRI_BASE+1039+((test_gErrSlotIdCnt<<3)&0xFF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_CPRI_BASE+1040+((test_gErrSlotIdCnt<<3)&0xFF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
							debug_write((DBG_DDR_IDX_CPRI_BASE+1041+((test_gErrSlotIdCnt<<3)&0xFF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_CPRI_BASE+1042+((test_gErrSlotIdCnt<<3)&0xFF)), slotBfCnt);		// 0x328
						}
						test_gErrSlotIdCnt++;
//						break;
//						break;
					}
//					__ucps2_synch(0);
				}
			}
#endif
		}
#if 1
		else		// axc data
		{
			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
					compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<4)+idWord)<<8) | (idWord);
					
//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_CPRI_BASE+1034), test_gCompWordCnt); 
					test_gCompWordCnt++;
					__ucps2_synch(0);
					
					if ((7 == slotId) && (1372 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
						realSrcAddr = srcAddr1;
						if (0 > (idBf-bfStart))
						{
							test_gBfStartErr++;
							debug_write((DBG_DDR_IDX_CPRI_BASE+1035), test_gBfStartErr); 
						}
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
//					__ucps2_synch(0);
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						//if (test_gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_CPRI_BASE+1036+((test_gErrSlotIdCnt<<3)&0x1FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_CPRI_BASE+1037+((test_gErrSlotIdCnt<<3)&0x1FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_CPRI_BASE+1038+((test_gErrSlotIdCnt<<3)&0x1FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_CPRI_BASE+1039+((test_gErrSlotIdCnt<<3)&0x1FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_CPRI_BASE+1040+((test_gErrSlotIdCnt<<3)&0x1FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
							debug_write((DBG_DDR_IDX_CPRI_BASE+1041+((test_gErrSlotIdCnt<<3)&0x1FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_CPRI_BASE+1042+((test_gErrSlotIdCnt<<3)&0x1FF)), slotBfCnt); 	// 0x328
						}
						test_gErrSlotIdCnt++;
//						break;
//						break;
					}
				}
			}
		}
#endif
		debug_write((DBG_DDR_IDX_CPRI_BASE+1032), test_gCompSlotIdCnt);	// 0x1000
		debug_write((DBG_DDR_IDX_CPRI_BASE+1033), test_gErrSlotIdCnt);	// 0x1004
	}
}

void AxC_data_test_check(void)
{
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
	if (4 <= pMtimerInt->csuEnCnt)
	{
		test_gCompWordCnt = 0;
		for (int32_t i = 0; i < (CPRI_TEST_SLOT_NUM>>1); i++)
		{
			cpri_test_check_slot_data(i);
		}
#if 0
		if(24000 <= gCpriTimerPara.csuEnCnt)
		{ 		
			//if(0 == cnt)
			{
				if(0 == gErrSlotIdCnt)
				{ 
					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
					UCP_PRINT_WARN("cpri test pass!\r\n");
				}
				else
				{
					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
				}
				cnt++;				
			}	
		}
#endif
	}
}

uint32_t CsuStopFlagCnt = 0;
uint32_t ResetSyncCnt0 = 0;
uint32_t ResetSyncCnt1 = 0;
uint32_t GetslotId = 0;

uint32_t test_cnt1 = 0;
uint32_t test_mode_cnt = 0;
uint32_t test_mode_switch = 0;
//#define   cpri_test_cnt   0xFFFFFFFFFFFFFFFF
void cpri_test_mode(uint32_t testmode)
{
	//int64_t i;

    UCP_PRINT_ERROR("testmode:%u\n", testmode);
	debug_write((DBG_DDR_IDX_CPRI_BASE+1029), testmode);
	if(1 == testmode)
	{
		do_write(ENTER_TEST_MODE_ADDR, 1);
	}
	else if(2 == testmode)
	{
		do_write(ENTER_TEST_MODE_ADDR, 2);
	}
	else
	{
	
	}
	
#if 0
	
	for(i=0;i<cpri_test_cnt;i++)
	{	   
		test_mode_cnt++;
		debug_write((DBG_DDR_IDX_CPRI_BASE+1026), test_mode_cnt);
		
		if((do_read_volatile(&CPRI_FRAME_RX_STAT))!= 0x1e)//失步
		{			
			jecspma_recrx_reset();
			ResetSyncCnt1++;
			debug_write((DBG_DDR_IDX_CPRI_BASE+1030), ResetSyncCnt1);	
		}
		if(1 == testmode)//进入测试模式
		{
			if( 1 == test_mode_cnt)
			{
				Axc_data_test_init();
				cpri_csu_axc_link_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR);//修改csu链表为测试模式
				NormalToTest = 1;
			}
			if(( 5000 < test_mode_cnt) && (NormalToTest == 1))
			{		
				AxC_data_test_check();
			}		
		}
		if(0 == testmode)//退出测试模式
		{
			TestToNormal = 1;
			NormalToTest = 0;
			cpri_csu_axc_link_init_nr_7ds2u(CPRI_DUMMY_USE_DUMMY_ADDR);//修改csu链表为正式模式
			debug_write((DBG_DDR_IDX_CPRI_BASE+1028), 0x66666666);
			test_mode_cnt = 0;
			break;
		}

#if 0	
		if( 1 == test_mode_cnt)
		{
			Axc_data_test_init();
			cpri_csu_axc_link_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR);//修改csu链表为测试模式
			NormalToTest = 1;
		}
		if(( 100000 < test_mode_cnt) && (NormalToTest == 1))
		{		
			if(101000 > test_mode_cnt)
			{
				AxC_data_test_check();
			}		
			else if(101000 == test_mode_cnt)//test 1000次后，退出test模式
			{	
				TestToNormal = 1;
				NormalToTest = 0;
				cpri_csu_axc_link_init_nr_7ds2u(CPRI_DUMMY_USE_DUMMY_ADDR);//修改csu链表为正式模式
				debug_write((DBG_DDR_IDX_CPRI_BASE+1028), 0x66666666);
			}
		}	
#endif
	}	
#endif
}


void check_cpri(void)
{
	test_cnt1++;

	if(1 == test_cnt1)
	{
		do_write(ENTER_TEST_MODE_ADDR, 0);//初始化默认0，正式模式
	}
	
    #if 0
	if(0 == do_read_volatile(ENTER_TEST_MODE_ADDR))//Normal mode

    {
	   	if((do_read_volatile(&CPRI_FRAME_RX_STAT))!= 0x1e)//失步
		{
			gCpriIntStatus.cpriSyncFlag = 0;				// cpri sync flag = 0
			UCP_API_CPRI_CSU_STOP();
			
			jecspma_recrx_reset();
			ResetSyncCnt0++;
			debug_write((DBG_DDR_IDX_CPRI_BASE+1027), ResetSyncCnt0);

			set_cpri_tmr_ctrl();
		}	
	}
	#endif

	if(1 == do_read_volatile(ENTER_TEST_MODE_ADDR)) //进入测试模式
	{
	    test_mode_cnt++;
		debug_write((DBG_DDR_IDX_CPRI_BASE+1026), test_mode_cnt);
		debug_write((DBG_DDR_IDX_CPRI_BASE+1028), 0);

        #if 0
		if((do_read_volatile(&CPRI_FRAME_RX_STAT))!= 0x1e)//失步
		{			
			gCpriIntStatus.cpriSyncFlag = 0;				// cpri sync flag = 0
			UCP_API_CPRI_CSU_STOP();
			
			jecspma_recrx_reset();
			ResetSyncCnt1++;
			debug_write((DBG_DDR_IDX_CPRI_BASE+1030), ResetSyncCnt1);	

			set_cpri_tmr_ctrl();
		}
        #endif

		if( 1 == test_mode_cnt)
		{
			Axc_data_test_init();
			cpri_csu_axc_link_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR);//修改csu链表为测试模式
			NormalToTest = 1;
		}
		if(( 10000 < test_mode_cnt) && (NormalToTest == 1))
		{		
			AxC_data_test_check();
		}		
	}
	else if(2 == do_read_volatile(ENTER_TEST_MODE_ADDR))//退出测试模式
	{
		TestToNormal = 1;
		NormalToTest = 0;
		cpri_csu_axc_link_init_nr_7ds2u(CPRI_DUMMY_USE_DUMMY_ADDR);//修改csu链表为正式模式
		debug_write((DBG_DDR_IDX_CPRI_BASE+1028), 0x66666666);
		test_mode_cnt = 0;
	}
	else
	{
	}
	debug_write((DBG_DDR_IDX_CPRI_BASE+1025), test_cnt1); // 0xb7e29004

}

