#ifndef _JESD_CSU_NR_7DS2U_H_
#define _JESD_CSU_NR_7DS2U_H_

#include "typedef.h"

// 4 ant, 7DS2U
#define JESD_NR7DS2U_ANT_NUM						4
#define JESD_NR7DS2U_MARGIN							2
#define JESD_NR7DS2U_SLOT_NUM						10

#define JESD_NR7DS2U_TX_NODENUM						15
#define JESD_NR7DS2U_RX_NODENUM						3

#define JESD_2500US_DOUBLE_TX_NODENUM1				7			
#define JESD_2500US_DOUBLE_TX_NODENUM2				5
#define JESD_2500US_DOUBLE_RX_NODENUM1				2
#define JESD_2500US_DOUBLE_RX_NODENUM2				3


#define LONGCP_SAM_CNT								4448
#define SHORTCP_SAM_CNT								4384
#define SLOT_SAM_CNT								(LONGCP_SAM_CNT+13*SHORTCP_SAM_CNT)

#define JESD_TX_LIST_ADDR							0x8A000000
#define JESD_RX_LIST_ADDR							0x8A008000
#define JESD_TX_LIST2_ADDR							0x8A004000
#define JESD_RX_LIST2_ADDR							0x8A00C000

#define JESD_NR7DS2U_TX_DUMMY_AXCDATA_LEN			0x9A400 // 0x22400+0x78000
#define JESD_NR7DS2U_TX_DUMMY_AXC1DATA_ADDR			0xB4200000
#define JESD_NR7DS2U_TX_DUMMY_AXC2DATA_ADDR			(JESD_NR7DS2U_TX_DUMMY_AXC1DATA_ADDR+JESD_NR7DS2U_TX_DUMMY_AXCDATA_LEN)	//0xB429A400	// 0x9A400
#define JESD_NR7DS2U_TX_DUMMY_AXC3DATA_ADDR			(JESD_NR7DS2U_TX_DUMMY_AXC2DATA_ADDR+JESD_NR7DS2U_TX_DUMMY_AXCDATA_LEN)	//0xB4334800	// 0x9A400
#define JESD_NR7DS2U_TX_DUMMY_AXC4DATA_ADDR			(JESD_NR7DS2U_TX_DUMMY_AXC3DATA_ADDR+JESD_NR7DS2U_TX_DUMMY_AXCDATA_LEN)	//0xB43CEC00	// 0x9A400

#define JESD_NR7DS2U_RX_DUMMY_AXCDATA_LEN			0x1CEE00	// 0x1A4000+0x2AE00
#define JESD_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR			0xB4469000
#define JESD_NR7DS2U_RX_DUMMY_AXC2DATA_ADDR			(JESD_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+JESD_NR7DS2U_RX_DUMMY_AXCDATA_LEN)	//0xB4637E00	// 0x1CEE00
#define JESD_NR7DS2U_RX_DUMMY_AXC3DATA_ADDR			(JESD_NR7DS2U_RX_DUMMY_AXC2DATA_ADDR+JESD_NR7DS2U_RX_DUMMY_AXCDATA_LEN)	//0xB4806C00	// 0x1CEE00
#define JESD_NR7DS2U_RX_DUMMY_AXC4DATA_ADDR			(JESD_NR7DS2U_RX_DUMMY_AXC3DATA_ADDR+JESD_NR7DS2U_RX_DUMMY_AXCDATA_LEN)	//0xB49D5A00	// 0x1CEE00	// B4BA4800

#if 1
#define JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x9F00000	// SM2
#define JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR		0x9FF0400	// SM2
#define JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR		0xA380000	// SM5
#define JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR		0xA290400	// SM4
#else
#define JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x60F00000	// SM2
#define JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR		0x60FF0400	// SM2
#define JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR		0x61380000	// SM5
#define JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR		0x61290400	// SM4
#endif

#define JESD_NR7DS2U_RX_SLOTS_DATA_ADDR				0x6BC00000
#define JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR			0x6BC44800	// 0x6BC00000
#define JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR			0x6BD34800	// 0x6BC78200

#define JESD_98_NR7DS2U_MARGIN							3

#define JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x60F00000	// SM2
#define JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR		0x60FF0400	// SM2
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR		0x61380000	// SM5
#define JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR		0x61290400	// SM4

#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR				0x6BC00000  // 0x89000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR			0x6BC89000	// 0x1E0000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR			0x6BE69000	// 0x1E0000 // 0x6c049000

#define JESD_ORX_DATA_ADDR							0x60000000
#define JESD_ORX_DATA_LEN							12288000 // (24576000*5) // 125ms

int32_t jesd_csu_init_nr_7ds2u();
int32_t jesd_csu_init_nr_7d2u_slot0();
int32_t jesd_csu_init_nr_7ds2u_iomode();
int32_t jesd_csu_init_nr_7ds2u_8t8r();
int32_t jesd_csu_init_nr_7ds2u_4t4r_98();
// 4t4r, 245.76M
int32_t jesd_csu_init_nr_2500us_double();
// 4t4r, 245.76M, slot0
int32_t jesd_csu_init_nr_2500us_double_slot0();
int32_t jesd_sniffer_orx_csu_init();

int32_t jesd_csu_start_nr_7ds2u();
//int32_t jesd_csu_start_nr_7ds2u_8t8r();

#endif

