//******************** (C) COPYRIGHT 2019 SmartLogic*******************************
// FileName           : a72_ctrl.h
// Author             : lijian, jian.li@smartlogictech.com
// Date First Issued  : 2019-03-29 04:00:13 PM
// Last Modified      : 2022-06-09 10:57:12 PM
// Description        :
// ------------------------------------------------------------
// Modification History:
// Version    Date       Author    Modification Description
//
//**********************************************************************************
#ifndef __A72_CTRL_H__
#define __A72_CTRL_H__

#define A72_CTRL_BASE    0x02150000


#define A72_CLK0_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 0  *4 )))
#define CS_CLK_CFG_EN                        (*((volatile uint32_t *)(A72_CTRL_BASE + 1  *4 )))
#define A72CORE_POR_CFG0                     (*((volatile uint32_t *)(A72_CTRL_BASE + 2  *4 )))
#define A72CORE_CORERST_CFG0                 (*((volatile uint32_t *)(A72_CTRL_BASE + 3  *4 )))
#define A72_CTRL0                            (*((volatile uint32_t *)(A72_CTRL_BASE + 4  *4 )))
#define A72CORE0_POR_RST_TIMING_REG0         (*((volatile uint32_t *)(A72_CTRL_BASE + 5  *4 )))
#define A72CORE1_POR_RST_TIMING_REG0         (*((volatile uint32_t *)(A72_CTRL_BASE + 6  *4 )))
#define A72CORE2_POR_RST_TIMING_REG0         (*((volatile uint32_t *)(A72_CTRL_BASE + 7  *4 )))
#define A72CORE3_POR_RST_TIMING_REG0         (*((volatile uint32_t *)(A72_CTRL_BASE + 8  *4 )))
#define A72CORE0_RST_TIMING_REG0             (*((volatile uint32_t *)(A72_CTRL_BASE + 9  *4 )))
#define A72CORE1_RST_TIMING_REG0             (*((volatile uint32_t *)(A72_CTRL_BASE + 10 *4 )))
#define A72CORE2_RST_TIMING_REG0             (*((volatile uint32_t *)(A72_CTRL_BASE + 11 *4 )))
#define A72CORE3_RST_TIMING_REG0             (*((volatile uint32_t *)(A72_CTRL_BASE + 12 *4 )))
#define A72_L2_RST_TIMING_REG0               (*((volatile uint32_t *)(A72_CTRL_BASE + 13 *4 )))
#define CORESIGHT_RST_CFG                    (*((volatile uint32_t *)(A72_CTRL_BASE + 14 *4 )))
#define CORESIGHT_RST_TIMING_REG             (*((volatile uint32_t *)(A72_CTRL_BASE + 15 *4 )))
#define A72CORE0_RVBARADDR_L_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 16 *4 )))
#define A72CORE0_RVBARADDR_H_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 17 *4 )))
#define A72CORE1_RVBARADDR_L_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 18 *4 )))
#define A72CORE1_RVBARADDR_H_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 19 *4 )))
#define A72CORE2_RVBARADDR_L_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 20 *4 )))
#define A72CORE2_RVBARADDR_H_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 21 *4 )))
#define A72CORE3_RVBARADDR_L_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 22 *4 )))
#define A72CORE3_RVBARADDR_H_CFG0            (*((volatile uint32_t *)(A72_CTRL_BASE + 23 *4 )))
#define GIC_ACLK_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 24 *4 )))
#define DAP_ACLK_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 25 *4 )))
#define STM_ACLK_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 26 *4 )))
#define CS_PCLK_CFG_EN                       (*((volatile uint32_t *)(A72_CTRL_BASE + 27 *4 )))
#define ACLK_A72SUB_CFG_EN                   (*((volatile uint32_t *)(A72_CTRL_BASE + 28 *4 )))
#define GIC_ACLK_RST_CFG_EN                  (*((volatile uint32_t *)(A72_CTRL_BASE + 29 *4 )))
#define GIC_ACLK_RST_TIMINGCFG_EN            (*((volatile uint32_t *)(A72_CTRL_BASE + 30 *4 )))
#define DAP_ACLK_RST_CFG_EN                  (*((volatile uint32_t *)(A72_CTRL_BASE + 31 *4 )))
#define DAP_ACLK_RST_TIMING_CFG_EN           (*((volatile uint32_t *)(A72_CTRL_BASE + 32 *4 )))
#define STM_ACLK_RST_CFG_EN                  (*((volatile uint32_t *)(A72_CTRL_BASE + 33 *4 )))
#define STM_ACLK_RST_TIMING_CFG_EN           (*((volatile uint32_t *)(A72_CTRL_BASE + 34 *4 )))
#define CS_PCLK_RST_CFG_EN                   (*((volatile uint32_t *)(A72_CTRL_BASE + 35 *4 )))
#define CS_PCLK_RST_TIMING_CFG_EN            (*((volatile uint32_t *)(A72_CTRL_BASE + 36 *4 )))
#define ACP_ADDR0                            (*((volatile uint32_t *)(A72_CTRL_BASE + 37 *4 )))
#define DAP_ADDR_CFG                         (*((volatile uint32_t *)(A72_CTRL_BASE + 38 *4 )))
#define GIC_AXIERR                           (*((volatile uint32_t *)(A72_CTRL_BASE + 39 *4 )))
#define GIC_ECCFATAL                         (*((volatile uint32_t *)(A72_CTRL_BASE + 40 *4 )))
#define SDIO_HCLK_CFG                        (*((volatile uint32_t *)(A72_CTRL_BASE + 41 *4 )))
#define GMAC_ACLK_CFG                        (*((volatile uint32_t *)(A72_CTRL_BASE + 42 *4 )))
#define GMAC_RST_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 43 *4 )))
#define SDIO_RST_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 44 *4 )))
#define A72_DBG0_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 45 *4 )))
#define A72_DBG_RST0_CFG_EN                  (*((volatile uint32_t *)(A72_CTRL_BASE + 46 *4 )))
#define A72_DBG_RST0_TIMINGCFG_EN            (*((volatile uint32_t *)(A72_CTRL_BASE + 47 *4 )))
#define ACLK_A72SUB_RST_CFG_EN               (*((volatile uint32_t *)(A72_CTRL_BASE + 48 *4 )))
#define ACLK_A72SUB_RST_TIMINGCFG_EN         (*((volatile uint32_t *)(A72_CTRL_BASE + 49 *4 )))
#define SYSCNT_CLK_CFG_EN                    (*((volatile uint32_t *)(A72_CTRL_BASE + 50 *4 )))
#define SYSCNT_RST_CFG_EN                    (*((volatile uint32_t *)(A72_CTRL_BASE + 51 *4 )))
#define SYSCNT_RST_TIMINGCFG_EN              (*((volatile uint32_t *)(A72_CTRL_BASE + 52 *4 )))
#define A72_DBG_RST1_CFG_EN                  (*((volatile uint32_t *)(A72_CTRL_BASE + 56 *4 )))
#define A72_DBG_RST1_TIMINGCFG_EN            (*((volatile uint32_t *)(A72_CTRL_BASE + 57 *4 )))
#define A72_CLK1_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 58 *4 )))
#define A72_DBG1_CFG_EN                      (*((volatile uint32_t *)(A72_CTRL_BASE + 59 *4 )))
#define A72_CTRL1                            (*((volatile uint32_t *)(A72_CTRL_BASE + 60 *4 )))
#define A72CORE0_RVBARADDR_L_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 61 *4 )))
#define A72CORE0_RVBARADDR_H_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 62 *4 )))
#define A72CORE1_RVBARADDR_L_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 63 *4 )))
#define A72CORE1_RVBARADDR_H_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 64 *4 )))
#define A72CORE2_RVBARADDR_L_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 65 *4 )))
#define A72CORE2_RVBARADDR_H_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 66 *4 )))
#define A72CORE3_RVBARADDR_L_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 67 *4 )))
#define A72CORE3_RVBARADDR_H_CFG1            (*((volatile uint32_t *)(A72_CTRL_BASE + 68 *4 )))
#define A72CORE_CORERST_CFG1                 (*((volatile uint32_t *)(A72_CTRL_BASE + 69 *4 )))
#define ACP_ADDR1                            (*((volatile uint32_t *)(A72_CTRL_BASE + 70 *4 )))
#define A72CORE_POR_CFG1                     (*((volatile uint32_t *)(A72_CTRL_BASE + 71 *4 )))
#define A72CORE0_POR_RST_TIMING_REG1         (*((volatile uint32_t *)(A72_CTRL_BASE + 72 *4 )))
#define A72CORE1_POR_RST_TIMING_REG1         (*((volatile uint32_t *)(A72_CTRL_BASE + 73 *4 )))
#define A72CORE2_POR_RST_TIMING_REG1         (*((volatile uint32_t *)(A72_CTRL_BASE + 74 *4 )))
#define A72CORE3_POR_RST_TIMING_REG1         (*((volatile uint32_t *)(A72_CTRL_BASE + 75 *4 )))
#define A72CORE0_RST_TIMING_REG1             (*((volatile uint32_t *)(A72_CTRL_BASE + 76 *4 )))
#define A72CORE1_RST_TIMING_REG1             (*((volatile uint32_t *)(A72_CTRL_BASE + 77 *4 )))
#define A72CORE2_RST_TIMING_REG1             (*((volatile uint32_t *)(A72_CTRL_BASE + 78 *4 )))
#define A72CORE3_RST_TIMING_REG1             (*((volatile uint32_t *)(A72_CTRL_BASE + 79 *4 )))
#define A72_L2_RST_TIMING_REG1               (*((volatile uint32_t *)(A72_CTRL_BASE + 80 *4 )))
#define SDIO_TUNING_REG                      (*((volatile uint32_t *)(A72_CTRL_BASE + 81 *4 )))
#define A72_0_EVENT                          (*((volatile uint32_t *)(A72_CTRL_BASE + 82 *4 )))
#define A72_1_EVENT                          (*((volatile uint32_t *)(A72_CTRL_BASE + 83 *4 )))

#endif
