/*********************************************************************
 *
 *        Filename:  cpri_csu.h
 *
 *         Created:  2022-04-29 07:19:34 PM
 *   Last Modified:  2022-04-29 07:19:34 PM
 *          Author:  xinxin.li
 *    Organization:  Beijing Smart Logic Technology Co., Ltd.
 *
 *     Description:
 *
 *
 ********************************************************************/

#ifndef __CPRI_CSU_H__
#define __CPRI_CSU_H__

#include "typedef.h"
#include "hw_cpri.h"

//#define CPRI_TEST_NOTIMING
//#define CPRI_TEST_TIMING


#define CSU_DUMMY0    			0x08651000
#define CSU_DUMMY1    			0x08653000
#define CSU_RESERVED  			0x08655000

#define CSU_AXC_BASE_ADDR    	0xB4200000
#define CSU_TX_AXC_ADDR			CSU_AXC_BASE_ADDR//0xB3E00000//0x50000000 // tx ddr addr
#define CSU_RX_AXC_ADDR			(CSU_AXC_BASE_ADDR+0xE10000)//0xB4C10000//0x60000000 // rx ddr addr
#define CSU_TX_DESC_ADDR		(CSU_AXC_BASE_ADDR+0x3840000)//0xB7640000//0x80000000 // link desc ddr addr
#define CSU_RX_DESC_ADDR		(CSU_AXC_BASE_ADDR+0x3840400)//0xB7640400//0x88000000 // link desc ddr addr

#define CSU_TX_CTRL_ADDR		(CSU_AXC_BASE_ADDR+0x3840800)//0xB7640800//0x70000000 // tx ctrl ddr addr
#define CSU_RX_CTRL_ADDR		(CSU_AXC_BASE_ADDR+0x3849E00)//0xB7649E00//0x78000000 // rx ctrl ddr addr

//#define CSU_TX_DUMMY_ADDR		0x90000000
//#define CSU_RX_DUMMY_ADDR		0x98000000

#if 0
#ifdef CPRI_TIMING_7D2U_TEST
#ifdef CPRI_10G_TEST//option8
#define ID_NUM        6
#define ID0_SIZE      1
#define ID1_SIZE      8
#define ID2_SIZE      8
#define ID3_SIZE      8
#define ID4_SIZE      8
#define ID5_SIZE      1
#define ID6_SIZE      0
#define ID7_SIZE      0
#define ID8_SIZE      0
#define ID9_SIZE      0
#define ID10_SIZE     0
#define ID11_SIZE     0
#define ID12_SIZE     0
#define ID13_SIZE     0
#define ID14_SIZE     0
#define ID15_SIZE     0
#define ID_NUM_TIMING	5
#define HYPER_FRAME_NUM 150 // 10 //15
#endif

#ifdef CPRI_24G_TEST //option 10
#define ID_NUM        11//11
#define ID0_SIZE      1
#define ID1_SIZE      1
#define ID2_SIZE      8
#define ID3_SIZE      8
#define ID4_SIZE      8
#define ID5_SIZE      8
#define ID6_SIZE      8
#define ID7_SIZE      8
#define ID8_SIZE      8//8
#define ID9_SIZE      8//8
#define ID10_SIZE     1//1
#define ID11_SIZE     0
#define ID12_SIZE     0
#define ID13_SIZE     0
#define ID14_SIZE     0
#define ID15_SIZE     0
#define ID_NUM_TIMING	9//11
#define HYPER_FRAME_NUM 150 // 10 //15
#endif
#endif
#ifdef CPRI_TIMING_LTE_FDD_TEST
//#if 1

#define ID_NUM        9//10//6
#define ID0_SIZE      1
#define ID1_SIZE      1//8
#define ID2_SIZE      8
#define ID3_SIZE      8
#define ID4_SIZE      8
#define ID5_SIZE      8//1
#define ID6_SIZE      2//0
#define ID7_SIZE      2//0
#define ID8_SIZE      1//0
#define ID9_SIZE      0//1//0
#define ID10_SIZE     0
#define ID11_SIZE     0
#define ID12_SIZE     0
#define ID13_SIZE     0
#define ID14_SIZE     0
#define ID15_SIZE     0
#define ID_NUM_TIMING	9
#define HYPER_FRAME_NUM 150 // 10 //15

#endif
#endif
#define ID_DATA_STEP	0x12C000 // 0x258000  // 0x3C000

//void cpri_csu_init(void);

//void cpri_csu_axcctrl_init(void);

void cpri_csu_init(void);

int32_t cpri_csu_task_lookup(uint8_t task_tag);

void cpri_csu_axc_init_notiming(void);
void cpri_csu_start_notiming(void);
void cpri_csu_axcctrl_init_notiming();

void cpri_csu_axc_init_timing(void);
void cpri_csu_axc_link_init_timing();
void cpri_csu_axcctrl_init_timing();
void cpri_csu_start_timing(void);

void cpri_csu_axc_init_timing_7d2u(void);
void cpri_csu_axc_link_init_timing_7d2u();
void cpri_csu_axcctrl_init_timing_7d2u();
void cpri_csu_start_timing_7d2u(void);


#endif

