/******************************************************************
 * @file  Fphy_Timer_Csu_Config.s.c
 * @brief:    [file description] 
 * @author: guicheng.liu
 * @Date 2022年7月7日
 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
 * Change_date         Owner         Change_content
 * 2022年7月7日        guicheng.liu       create file

*****************************************************************/

/**************************include******************************/
//#include "type_define.h"
//#include "lte_common.h"
//#include "log_interface.h"
//#include "phy_timer_csu_config.h"
//#include "ecs_common.h"
#include "nr_mem_def.h"
#include "cpri_csu_api.h"
//#include "cpri_csu_nr_7ds2u.h"
#include "phy_timer_csu_config.h"


//#include "rfm_interface.h"


 /**************************function******************************/
 phy_csu_link_info_t g_phy_csu_link;
 
#define CPRI_RX_FRAME_DATA_OFFSET_LEN 10000 //单位ns, RX帧头和数据之间的偏移量
#define CPRI_BF_NUM_PER_SLOT  (61440/32)       //单slot, 共61440点, 每个基本帧32个点, 共1920个基本帧
#define CPRI_BF_DATA_PER_SLOT (61440*2)       //单slot, 共61440点, 压缩后数据61440*2
 
#define CPRI_BF_NUM_TX_F7_SYM  ((4384*6+4448)/32)       //TX前7个符号的基本帧的个数
#define CPRI_BF_NUM_TX_B7_SYM  ((4384*7)/32)            //TX后7个符号的基本帧的个数
#define CPRI_BF_NUM_TX_B3_SYM  ((4384*3)/32)            //TX后3个符号的基本帧的个数(1D3U S slot 10个符号分前7个符号,和后3个符号)
#define CPRI_BF_NUM_TX_F6_SYM  ((4384*5+4448)/32)       //TX后6个符号的基本帧的个数
 
#define CPRI_BF_NUM_RX_B4_SYM  ((4384*4)/32)            //RX后4个符号的基本帧的个数
#define CPRI_BF_NUM_RX_B2_SYM  ((4384*2)/32)            //RX后2个符号的基本帧的个数
 
#define CPRI_BF_NUM_TX_DUMMY_7D2U  (61440*2 + 4384*8)/32         //7D2U TX dummy(2 ul slot + 8 symbol (4 guard + 4 ul symbol))基本帧的个数
#define CPRI_BF_NUM_RX_DUMMY_7D2U  (61440*7 + 4448 + 4384*9)/32  //7D2U RX dummy(7 dl slot + 10 symbol (6 dl symbol + 4 guard))基本帧的个数
 
#define CPRI_BF_NUM_TX_DUMMY_1D3U  (61440*3 + 4384*4)/32         //1D3U TX dummy(3 ul slot + 4 symbol (2 guard + 2 ul symbol))基本帧的个数
#define CPRI_BF_NUM_RX_DUMMY_1D3U  (61440*1 + 4448 + 4384*11)/32 //1D3U RX dummy(1 dl slot + 12 symbol (10 dl symbol + 2 guard))基本帧的个数
 
#define CPRI_FDD_15KHZ_BF_NUM_PER_SLOT   (61440/32)*2               //单slot, 共61440点, 每个基本帧32个点, 共1920个基本帧
#define CPRI_FDD_15KHZ_BF_DATA_PER_SLOT  (61440*2)*2                //单slot, 共61440点, 压缩后数据61440*2
#define CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM  ((4384*6+4448)/32)*2       //TX前7个符号的基本帧的个数
#define CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM  ((4384*7)/32)*2            //TX后7个符号的基本帧的个数
#define CPRI_FDD_15KHZ_BF_NUM_TX_B3_SYM  ((4384*3)/32)*2            //TX后3个符号的基本帧的个数(1D3U S slot 10个符号分前7个符号,和后3个符号)
#define CPRI_FDD_15KHZ_BF_NUM_TX_F6_SYM  ((4384*5+4448)/32)*2       //TX后6个符号的基本帧的个数

 /*!   
 * @brief:  参数的初始化
 * @author:  shibo.weng
 * @Date:  2022年11月15日
 */
 //#define CPRI_NR_FDD_LINK_START_ADDR    0x721E800
void Phy_Timer_Csu_Init()
{
    memset(&g_phy_csu_link, 0, sizeof(phy_csu_link_info_t));

    //tx的链表地址
    g_phy_csu_link.tx0_even_f7_link_addr     = CPRI_NR_FDD_LINK_START_ADDR;
    g_phy_csu_link.tx0_even_b7_link_addr     = CPRI_NR_FDD_LINK_START_ADDR + 1*0x200;
    g_phy_csu_link.tx0_odd_f7_link_addr      = CPRI_NR_FDD_LINK_START_ADDR + 2*0x200;
    g_phy_csu_link.tx0_odd_b7_link_addr      = CPRI_NR_FDD_LINK_START_ADDR + 3*0x200;
    g_phy_csu_link.tx0_s_link_addr           = CPRI_NR_FDD_LINK_START_ADDR + 4*0x200;
    g_phy_csu_link.tx0_1st_dummy_link_addr   = CPRI_NR_FDD_LINK_START_ADDR + 5*0x200;
    g_phy_csu_link.tx0_2nd_dummy_link_addr   = CPRI_NR_FDD_LINK_START_ADDR + 6*0x200;

    //rx的链表地址
    g_phy_csu_link.rx0_first_link_addr       = CPRI_NR_FDD_LINK_START_ADDR + 7*0x200;
    g_phy_csu_link.rx0_dummy_link_addr       = CPRI_NR_FDD_LINK_START_ADDR + 8*0x200;
    g_phy_csu_link.rx0_s_link_addr           = CPRI_NR_FDD_LINK_START_ADDR + 9*0x200;
    g_phy_csu_link.rx0_normal0_link_addr     = CPRI_NR_FDD_LINK_START_ADDR + 10*0x200;
    g_phy_csu_link.rx0_normal1_link_addr     = CPRI_NR_FDD_LINK_START_ADDR + 11*0x200;
    g_phy_csu_link.rx0_last_link_addr        = CPRI_NR_FDD_LINK_START_ADDR + 12*0x200;
}

/*!   
* @brief:  CPRI CSU初始化
* @author:  guicheng.liu
* @Date:  2023年2月2日
*/
void Cpri_Csu_Init()
{
    uint32_t fifo_num = 4;//初始化4个FIFO通道(RX_AXC_DATA:CmdFIFO0, RX_AXC_CTRL:CmdFIFO2, TX_AXC_DATA:CmdFIFO1, TX_AXC_CTRL:CmdFIFO3)
    uint32_t dma_reg_group_num = 32;//清空CPRI的32组DMA参数寄存器
    uint32_t tag_mask = 0xFFFFFFFF;//DMA TAG全部不屏蔽

    UCP_API_CPRI_CSU_Init(fifo_num, dma_reg_group_num, tag_mask);
}

 /*!   
 * @brief:  
 * @author:  guicheng.liu
 * @Date:  2023年3月16日
 * @param: axc_id_num :       [param description ]
 * @param: rx_cycle_num :     [param description ]
 */
void Cpri_Csu_Latch_Init(uint32_t axc_id_num, uint32_t out_latch_num, uint32_t in_latch_num, uint32_t rx_cycle_num)
{
    uint32_t index = 0;
    //uint32_t axc_id_num = 5; //1个指数因子,4个天线(暂时不支持AGC因子)
    uint32_t tx0_rfp_set= 0;//[18:16]TX_AXC_DATA 通道开始工作后，提前发送的 Base Frame 的个数[8] 0:上升沿敏感 1: 高电平敏感
                            //[7:0]CSU捕捉到CPRI 端接口信号TX_AUX_CNT_POS 第一次为此数值后,延迟2个CSU                   的主时钟周期再次启动发送数据的工作
    uint32_t tx0_port_info[64] = {0};//共64个port, 
                        			//[31:26] CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的 ID 值
                        			//[25:20]CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的每拍有效比特数
                        			//[19:1]CPRI 模式 CSU 的 TX_AXC_DATA通道一个Basic Frame 中端口x的总比特数
                        			//[0]0:比特反序未使能 1:比特反序使能
    uint32_t tx0_latch_info_l[8] = {0}; //8个latch info配置，[24]bit_revert_enable 
                                        //[19:0]CPRI模式CSU的TX_AXC_DATA通道的OutLatch参数,     值为一个Basic Frame中在此OutLatch中缓存的所有端口的总比特数

    uint32_t tx0_latch_info_m[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*3  
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N
    uint32_t tx0_latch_info_h[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*7
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*5

    uint32_t rx0_port_info[64] = {0};//共64个port, [27:22]bit_number_one_cyclex [20:1]bit_number_one_basic_framex [0]bit_revert_enable
    uint32_t rx0_latch_info_l[8] = {0};//8个latch info配置，[24]bit_revert_enable  [19:0]bit_number_one_basic_frame
    uint32_t rx0_latch_info_h[8] = {0};//8个latch info配置，
                            			//[31]cpri_latch_n_7_times_bigger_than_128 =0： CPRI_LATCH_N*7 不大于 128, =1： CPRI_LATCH_N*7 大于 128
                            			//[30:24]cpri_latch_n_7_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*7
                            			//[23]cpri_latch_n_5_times_bigger_than_128  0： CPRI_LATCH_N*5 不大于 128, 1： CPRI_LATCH_N*5 大于 128
                            			//[22:16]cpri_latch_n_5_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*5
                            			//[15]cpri_latch_n_3_times_bigger_than_128  0： CPRI_LATCH_N*3 不大于 128, 1： CPRI_LATCH_N*3 大于 128
                            			//[14:8]cpri_latch_n_3_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*3
                            			//[6:0]cpri_latch_n
	uint32_t rx0_cycle_num[8] = {0};//8个latch info配置,
	                                //[7:0]CPRI模式CSU的RX_AXC_DATA通道的InLatch参数,值为该InLatch中连续接收的Basic Frame的个数减一
    uint32_t inlatch_index = 0;
    //uint32_t rx_cycle_num = 32;
	uint32_t bit_per_bf[6] = {16,512,512,512,512,16};  //压缩因子是2byte, 16bit, 数据是64byte,512bit
    uint32_t bit_per_cycle[6] = {16,0,0,0,0,16}; //0:表示64, 非0:有效比特数为数值本身

    uint32_t bit_per_bf_for_latch[6] = {16,512,512,512,512,16}; //0:表示64, 非0:有效比特数为数值本身
    for (index = 0; index < axc_id_num; index++)
    {
        //tx0_port_info[index] = ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));     
		tx0_port_info[index] = 0x1 | ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));//bit反序使能
    }

    for (index = 0; index < out_latch_num; index++)
    {
	    tx0_latch_info_l[index] = (0x1<<24ul) | bit_per_bf_for_latch[index];//bit反序使能
	    tx0_latch_info_m[index] = 0x180008;//CPRI_LATCH_N??bit反序??
	    tx0_latch_info_h[index] = 0x380028;
    }
    tx0_rfp_set = 0x40001;//RfpPoint=0x1 can send 4//push 4 basic frame at 1st tx_axc_rfp

    UCP_API_CPRI_CSU_TxOutLatch_Cfg(axc_id_num, 
                                    tx0_rfp_set, 
                                    tx0_port_info, 
                                    out_latch_num,
                                    tx0_latch_info_l, 
                                    tx0_latch_info_m, 
                                    tx0_latch_info_h);

    for (index = 0; index < axc_id_num; index++)
    {
        rx0_port_info[index] =  0x1 | ((bit_per_bf[index]<<1)|(bit_per_cycle[index]<<22));//bit反序使能
    }

    for (index = 0; index < in_latch_num; index++)
    {
        rx0_latch_info_l[index] =  (0x1<<24ul) | bit_per_bf_for_latch[index];
        rx0_latch_info_h[index] =  0x38281808;
        rx0_cycle_num[index] = rx_cycle_num - 1;
    }

    UCP_API_CPRI_CSU_RxInLatch_Cfg(axc_id_num,
                                    rx0_port_info,
                                    in_latch_num,
                                    rx0_latch_info_l,
                                    rx0_latch_info_h,
                                    rx0_cycle_num);

    UCP_API_CPRI_CSU_RxInLatchThres_Cfg(inlatch_index,
                                        1,//w_r_flag,
                                        0x0,//send_threshold,
                                        0x10);//almostfull_threshold);

    //先去使能
	UCP_API_CPRI_CSU_TXAxcData_ChannelCtrl(0, axc_id_num, out_latch_num);
	UCP_API_CPRI_CSU_RXAxcData_ChannelCtrl(0, axc_id_num);
}


void Cpri_Csu_Link_Fdd_Init(uint32_t out_latch_num, uint32_t in_latch_num, uint32_t rx_cycle_num, uint32_t tx_cycle_num)
{
    uint32_t CGran = 0;

 //   uint32_t rx_first_dma_flag = 0;

    uint32_t axc_id = 0;
    uint32_t latch_id = 0;
    uint32_t xnum = 0;
    uint32_t allnum = 0;
    uint32_t size = 0;
    uint32_t tx_src_addr = 0;
    uint32_t rx_dst_addr = 0;
    uint32_t cell0_comp_facter_addr_offset = 0;
    uint32_t cell0_agc_facter_addr_offset = 0;
    uint32_t cell0_rx_addr_offset = 0;

//    uint32_t bf_num_per_slot = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT;
    //一个基本帧的长度是1Tc=1/fc=1/3.84MHz
  //  uint32_t rx_bf_num_offset = (LOAD_EX_W((char*)0x0A4D7234)*384)/100000;//首先计算出基本帧的个数，帧头和数据偏移的基本帧个数
	uint32_t rx_bf_num_offset = 0;//首先计算出基本帧的个数，帧头和数据偏移的基本帧个数

    //第一种情况:如果RRU到BBU的帧头和数据偏移是0,为了适配所有场景,第一个链表的数据长度不能为0,故置为rx_cycle_num个基本帧的长度
    //第二种情况:如果偏移不为0
    //rx_cycle_num=4
    uint32_t rx_last_bf_num = (0 == rx_bf_num_offset) ? rx_cycle_num : ((rx_bf_num_offset/rx_cycle_num)*rx_cycle_num);
    uint32_t rx_first_bf_num = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT - rx_last_bf_num;

    uint32_t nr_cell0_rx0_ddr_addr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//SM3_NR_CELL0_ODD_RX_DATA_ADDR; //sm 7D2U:slot7/17, 1D3U:slot1/6/11/16, FDD:slot0/2/4/6/8
    uint32_t nr_cell0_rx1_ddr_addr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;//SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//sm 7D2U:slot8/18, 1D3U:slot2/7/12/17, FDD:slot1/3/5/7/9
  //  uint32_t nr_cell0_rx2_ddr_addr = SM3_NR_CELL0_ODD_RX_DATA_ADDR; //sm 7D2U:slot9/19, 1D3U:slot3/8/13/18
 //   uint32_t nr_cell0_rx3_ddr_addr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//sm 1D3U:slot4/9/14/19

    uint32_t nr_cell0_even_f7_tx_addr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR;//NR cell TX 偶时隙的前7个符号,sm
    uint32_t nr_cell0_even_b7_tx_addr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR;//NR cell TX 偶时隙的后7个符号,sm
    uint32_t nr_cell0_odd_f7_tx_addr  = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR;//NR cell TX 奇时隙的前7个符号,sm
    uint32_t nr_cell0_odd_b7_tx_addr  = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR;//NR cell TX 奇时隙的后7个符号,sm

    uint32_t nr_cell0_even_tx_compress_factor = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;
    uint32_t nr_cell0_odd_tx_compress_factor  = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
    uint32_t nr_cell0_even_tx_agc_factor      = SM1_NR_CELL0_EVNE_TX_AGC_ADDR;
    uint32_t nr_cell0_odd_tx_agc_factor       = SM1_NR_CELL0_ODD_TX_AGC_ADDR;

    uint32_t nr_cell_even_rx_agc_factor      = SM1_NR_CELL0_EVNE_RX_AGC_ADDR;
    uint32_t nr_cell_odd_rx_agc_factor       = SM1_NR_CELL0_ODD_RX_AGC_ADDR;

    uint32_t i = 0;

    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=5个节点的链表
    //tx的链表地址
    phy_csu_link_info_t* link = &g_phy_csu_link;

    uint32_t tx0_even_f7_link_addr     = link->tx0_even_f7_link_addr;//slot0
    uint32_t tx0_even_b7_link_addr     = link->tx0_even_b7_link_addr;//slot0
    uint32_t tx0_odd_f7_link_addr      = link->tx0_odd_f7_link_addr;//slot1
    uint32_t tx0_odd_b7_link_addr      = link->tx0_odd_b7_link_addr;//slot1 后3个符号
    uint32_t tx0_1st_dummy_link_addr     = link->tx0_1st_dummy_link_addr ;//发送最后一个时隙的b7
 //   uint32_t tx0_2nd_dummy_link_addr   = link->tx0_2nd_dummy_link_addr;

    //rx的链表地址
    uint32_t rx0_first_link_addr       = link->rx0_first_link_addr;  //slot19 
 //   uint32_t rx0_dummy_link_addr       = link->rx0_dummy_link_addr;  //slot0-slot1
 //   uint32_t rx0_s_link_addr           = link->rx0_s_link_addr;      //(slot1/slot6/slot11/slot16)2个符号
    uint32_t rx0_normal0_link_addr     = link->rx0_normal0_link_addr;//(slot2/slot7/slot12/slot17)(slot4/slot9/slot14)
    uint32_t rx0_normal1_link_addr     = link->rx0_normal1_link_addr;//(slot3/slot8/slot13/slot18)
    uint32_t rx0_last_link_addr        = link->rx0_last_link_addr;   //(slot4/9/14)前半部分数据的链表,在每个2.5ms的链表的尾部

	//TX:偶时隙前7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_even_tx_compress_factor;
            cell0_comp_facter_addr_offset = allnum;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_even_f7_tx_addr + allnum*(i - 1);
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
    	}
        else if (5 == i)
        {
            size = 2;//AGC因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_even_tx_agc_factor;
            cell0_agc_facter_addr_offset = allnum;
        }

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_f7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_f7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
    }

	//TX:偶时隙后7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_even_tx_compress_factor + cell0_comp_facter_addr_offset;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = nr_cell0_even_b7_tx_addr + allnum*(i - 1);
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
    	}
		else if (5 == i)
    	{
            size = 2;//AGC因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = nr_cell0_even_tx_agc_factor + cell0_agc_facter_addr_offset;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_b7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_b7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
    }

    cell0_comp_facter_addr_offset = 0;
    cell0_agc_facter_addr_offset = 0;
	//TX:奇时隙前7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = nr_cell0_odd_tx_compress_factor;
            cell0_comp_facter_addr_offset += allnum;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_odd_f7_tx_addr + allnum*(i - 1);
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
    	}
    	else if (5 == i)
    	{
            size = 2;//AGC，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_F7_SYM*size;
            tx_src_addr = nr_cell0_odd_tx_agc_factor;
            cell0_agc_facter_addr_offset = allnum;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_f7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_f7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
    }

	//TX:奇时隙后7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_odd_tx_compress_factor + cell0_comp_facter_addr_offset;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_odd_b7_tx_addr + allnum*(i - 1);
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
    	}
    	else if (5 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = nr_cell0_odd_tx_agc_factor + cell0_agc_facter_addr_offset;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_b7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_b7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
    }
	//TX:最后一个时隙后7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
		CGran = 0;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_odd_tx_compress_factor + cell0_comp_facter_addr_offset;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = (uint32_t)nr_cell0_odd_b7_tx_addr + allnum*(i - 1);
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
    	}
    	else if (5 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            CGran = 1;
            allnum = CPRI_FDD_15KHZ_BF_NUM_TX_B7_SYM*size;
            tx_src_addr = nr_cell0_odd_tx_agc_factor + cell0_agc_facter_addr_offset;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_1st_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,//TX CGran
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_1st_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,//TX CGran
                                            0);
    }

	//RX slot9时隙后一部分数据的链表
	#if 1
	for (i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
        CGran = 1;//当 DMA 为 RX_AXC_RFP信号之后的第一个DMA 时，此 DMA 的参数 GRAN[3]需置为1
                  //[36]节点信息命令字里的first_dma要置1
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = rx_last_bf_num*size;
            rx_dst_addr = nr_cell0_rx1_ddr_addr + rx_first_bf_num*size;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = rx_last_bf_num*size;
            rx_dst_addr = nr_cell0_rx1_ddr_addr + CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*2 + rx_first_bf_num*size + CPRI_FDD_15KHZ_BF_DATA_PER_SLOT*(i - 1);
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = rx_last_bf_num*size;
            rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
    	}
    	else if (5 == i)
        {
            size = 2;//AGC，一个BF 2B
            allnum = rx_last_bf_num*size;
            rx_dst_addr = nr_cell_odd_rx_agc_factor + rx_first_bf_num*size;
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_first_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,//RX CGran
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_first_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,//RX CGran
                                            0,
                                            0);
    }
#else
	for (i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
		CGran = 1;//当 DMA 为 RX_AXC_RFP信号之后的第一个DMA 时，此 DMA 的参数 GRAN[3]需置为1
                  //[36]节点信息命令字里的first_dma要置1
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = nr_cell0_rx0_ddr_addr;
            cell0_rx_addr_offset += allnum;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = nr_cell0_rx0_ddr_addr + cell0_rx_addr_offset;
            cell0_rx_addr_offset += allnum;
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
    	}
        else if (5 == i)
        {
            size = 2;//agc因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = (uint32_t)nr_cell_even_rx_agc_factor; 
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_first_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,//RX CGran
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_first_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,//RX CGran
                                            0,
                                            0);
    }
#endif

    cell0_rx_addr_offset = 0;

	//RX 第一个normal时隙的链表(slot0/2/4/6/8)
	for (i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = nr_cell0_rx0_ddr_addr;
            cell0_rx_addr_offset += allnum;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = nr_cell0_rx0_ddr_addr + cell0_rx_addr_offset;
            cell0_rx_addr_offset += allnum;
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
    	}
        else if (5 == i)
        {
            size = 2;//agc因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = (uint32_t)nr_cell_even_rx_agc_factor; 
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal0_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,//RX CGran
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal0_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,//RX CGran
                                            0,
                                            0);
    }

    cell0_rx_addr_offset = 0;

	//RX 第二个normal时隙的链表(slot1/3/5/7/9)
	for (i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = nr_cell0_rx1_ddr_addr;
            cell0_rx_addr_offset += allnum;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = nr_cell0_rx1_ddr_addr + cell0_rx_addr_offset;
            cell0_rx_addr_offset += allnum;
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
    	}
        else if (5 == i)
        {
            size = 2;//AGC，一个BF 2B
            allnum = CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*size;
            rx_dst_addr = nr_cell_odd_rx_agc_factor;
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal1_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,//RX CGran
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal1_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,//RX CGran
                                            0,
                                            0);
    }

	//RX slot9 时隙前一部分的的链表
	for (i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = rx_first_bf_num*size;
            rx_dst_addr = nr_cell0_rx1_ddr_addr;
    	}
    	else if ((1 <= i) && (2 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = rx_first_bf_num*size;
            rx_dst_addr = nr_cell0_rx1_ddr_addr + CPRI_FDD_15KHZ_BF_NUM_PER_SLOT*2 + CPRI_FDD_15KHZ_BF_DATA_PER_SLOT*(i - 1);
    	}
    	else if ((3 <= i) && (4 >= i))
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = rx_first_bf_num*size;
            rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
    	}
        else if (5 == i)
        {
            size = 2;//AGC，一个BF 2B
            allnum = rx_first_bf_num*size;
            rx_dst_addr = nr_cell_odd_rx_agc_factor;
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_last_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,//RX CGran
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_last_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,//RX CGran
                                            0,
                                            0);
    }
}

void Cpri_Csu_Reg_Fdd_Init(uint32_t axc_id_num)
{
    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=5个节点的链表
    //tx的链表地址
    phy_csu_link_info_t* link = &g_phy_csu_link;

    uint32_t tx0_even_f7_link_addr     = link->tx0_even_f7_link_addr;
    uint32_t tx0_even_b7_link_addr     = link->tx0_even_b7_link_addr;
    uint32_t tx0_odd_f7_link_addr      = link->tx0_odd_f7_link_addr;
    uint32_t tx0_odd_b7_link_addr      = link->tx0_odd_b7_link_addr;
	uint32_t tx0_1st_dummy_link_addr   = link->tx0_1st_dummy_link_addr;

    //rx的链表地址
    uint32_t rx0_first_link_addr       = link->rx0_first_link_addr;   //slot19 
    uint32_t rx0_normal0_link_addr     = link->rx0_normal0_link_addr; //slot8 slot18
    uint32_t rx0_normal1_link_addr     = link->rx0_normal1_link_addr; //slot9
    uint32_t rx0_last_link_addr        = link->rx0_last_link_addr;    //slot19 

    UCP_API_CPRI_CSU_DmaParamReg_Cfg(0,  //第0组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_even_f7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(1,  //第1组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_even_b7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(2,  //第2组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_odd_f7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(3,  //第3组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_odd_b7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
	 UCP_API_CPRI_CSU_DmaParamReg_Cfg(4,  //第3组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_1st_dummy_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);

     //rx
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(5,  //第4组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_first_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(6,  //第5组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_normal0_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(7,  //第6组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_normal1_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(8,  //第7组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_last_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
}


void Cpri_Csu_Cmd_Gen_Fdd(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo)
{
    uint32_t tx_even_f7_cmd_14_h = 0;
    uint32_t tx_even_f7_cmd_32_l = 0;
    uint32_t tx_even_b7_cmd_14_h = 0;
    uint32_t tx_even_b7_cmd_32_l = 0;
    uint32_t tx_odd_f7_cmd_14_h = 0;
    uint32_t tx_odd_f7_cmd_32_l = 0;
    uint32_t tx_odd_b7_cmd_14_h = 0;
    uint32_t tx_odd_b7_cmd_32_l = 0;
	uint32_t tx_last_b7_cmd_14_h = 0;
    uint32_t tx_last_b7_cmd_32_l = 0;

    //rx的链表地址
    uint32_t rx_first_cmd_14_h = 0;
    uint32_t rx_first_cmd_32_l = 0;
    uint32_t rx_normal0_cmd_14_h = 0;
    uint32_t rx_normal0_cmd_32_l = 0;
    uint32_t rx_normal1_cmd_14_h = 0;
    uint32_t rx_normal1_cmd_32_l = 0;
    uint32_t rx_last_cmd_14_h = 0;
    uint32_t rx_last_cmd_32_l = 0;


    //FIFO1 用于TX发送数据
    //[1:0]dma_mode_s, 1:一级链表模式 DMA
    //[3:2]dma_mode_d, 1:一级链表模式 DMA
    //[4]dma_dimension, 1:多维 DMA
    //[5]axi4_master_sel 非APE模式,0:访问 DDR 和 Share Memory 选择 AXI4 Master0（经过非 CCI 总线）
    //[6]continue_next_dma 1:下一个 DMA 源端数据的读取无需等待当前 DMA目的端数据写完
    //[7]continue_last_dma 1:下一个 DMA 源端数据的读取无需等待上一个 DMA目的端数据写完
    //[12:8]dma_buffer_id_s 存放源端 DMA 参数的寄存器 ID
    //[17:13]dma_buffer_id_d 存放目的端 DMA 参数的寄存器 ID
    //[22:18]cmd_tag
    //[23]clear非APE模式,0:当前DMA之前,不清空CSU内部缓存
    tx_even_f7_cmd_32_l = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(0<<8) |(0<<13)|(0<<18); 
    tx_even_f7_cmd_14_h = 0;

    tx_even_b7_cmd_32_l = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(1<<8) |(1<<13)|(1<<18);
    tx_even_b7_cmd_14_h = 0;

    tx_odd_f7_cmd_32_l = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(2<<8) |(2<<13)|(2<<18);
    tx_odd_f7_cmd_14_h = 0;

    tx_odd_b7_cmd_32_l = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(3<<8) |(3<<13)|(3<<18);
    tx_odd_b7_cmd_14_h = 0; 

	tx_last_b7_cmd_32_l = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(4<<8) |(4<<13)|(4<<18);
	tx_last_b7_cmd_14_h = 0; 

    pTxCmdFifo->cmdFifo_num = 4;
    pTxCmdFifo->cmdFifo[0].cmd_num = 6;
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd32l = tx_even_f7_cmd_32_l;//slot0
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd32l = tx_odd_f7_cmd_32_l;//slot1
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[3].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[3].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[4].cmd32l = tx_even_f7_cmd_32_l;//slot2
    pTxCmdFifo->cmdFifo[0].cmd[4].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[5].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[5].cmd14h = tx_even_b7_cmd_14_h;

    pTxCmdFifo->cmdFifo[1].cmd_num = 4;
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd32l = tx_odd_f7_cmd_32_l;//slot3
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[2].cmd32l = tx_even_f7_cmd_32_l;//slot4
    pTxCmdFifo->cmdFifo[1].cmd[2].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[3].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[3].cmd14h = tx_even_b7_cmd_14_h;

    pTxCmdFifo->cmdFifo[2].cmd_num = 6;
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd32l = tx_odd_f7_cmd_32_l;//slot5
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd32l = tx_even_f7_cmd_32_l;//slot6
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[3].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[3].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[4].cmd32l = tx_odd_f7_cmd_32_l;//slot7
    pTxCmdFifo->cmdFifo[2].cmd[4].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[5].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[5].cmd14h = tx_odd_b7_cmd_14_h;

    pTxCmdFifo->cmdFifo[3].cmd_num = 4;
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd32l = tx_even_f7_cmd_32_l;//slot8
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[2].cmd32l = tx_odd_f7_cmd_32_l;//slot9
    pTxCmdFifo->cmdFifo[3].cmd[2].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[3].cmd32l = tx_last_b7_cmd_32_l;//tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[3].cmd14h = tx_last_b7_cmd_14_h;//tx_odd_b7_cmd_14_h;

    //FIFO0 用于RX接收数据
    //[1:0]dma_mode_s, 1:一级链表模式 DMA
    //[3:2]dma_mode_d, 1:一级链表模式 DMA
    //[4]dma_dimension, 1:多维 DMA
    //[5]axi4_master_sel 非APE模式,0:访问 DDR 和 Share Memory 选择 AXI4 Master0（经过非 CCI 总线）
    //[6]continue_next_dma 1:下一个 DMA 源端数据的读取无需等待当前 DMA目的端数据写完
    //[7]continue_last_dma 1:下一个 DMA 源端数据的读取无需等待上一个 DMA目的端数据写完
    //[12:8]dma_buffer_id_s 
    //[17:13]dma_buffer_id_d
    //[22:18]cmd_tag
    //[23]clear非APE模式,0:当前DMA之前,不清空CSU内部缓存
    rx_first_cmd_32_l       = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(5<<8) |(5<<13)|(5<<18);
    rx_first_cmd_14_h       = (1 << 4);

    rx_normal0_cmd_32_l     = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(6<<8) |(6<<13)|(6<<18);
    rx_normal0_cmd_14_h     = 0;

    rx_normal1_cmd_32_l     = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(7<<8) |(7<<13)|(7<<18);
    rx_normal1_cmd_14_h     = 0;

    rx_last_cmd_32_l        = 1 | (1<<2) |(1<<4)|(1 <<5) |(3<<6) |(8<<8) |(8<<13)|(8<<18);
    rx_last_cmd_14_h        = 0;

#if 1
    pRxCmdFifo->cmdFifo_num = 4;
    pRxCmdFifo->cmdFifo[0].cmd_num = 4;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd32l = rx_first_cmd_32_l;//slot9 后部分
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd14h = rx_first_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd32l = rx_normal0_cmd_32_l;//slot0
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd32l = rx_normal1_cmd_32_l;//slot1
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd14h = rx_normal1_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[3].cmd32l = rx_normal0_cmd_32_l;//slot2
    pRxCmdFifo->cmdFifo[0].cmd[3].cmd14h = rx_normal0_cmd_14_h;

    pRxCmdFifo->cmdFifo[1].cmd_num = 2;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd32l = rx_normal1_cmd_32_l;//slot3
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd14h = rx_normal1_cmd_14_h;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd32l = rx_normal0_cmd_32_l;//slot4
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd14h = rx_normal0_cmd_14_h;

    pRxCmdFifo->cmdFifo[2].cmd_num = 3;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd32l = rx_normal1_cmd_32_l;//slot5
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd14h = rx_normal1_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd32l = rx_normal0_cmd_32_l;//slot6
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd32l = rx_normal1_cmd_32_l;//slot7
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd14h = rx_normal1_cmd_14_h;

    pRxCmdFifo->cmdFifo[3].cmd_num = 2;//3;
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd32l = rx_normal0_cmd_32_l;//slot8
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd14h = rx_normal0_cmd_14_h;
 //   pRxCmdFifo->cmdFifo[3].cmd[2].cmd32l = rx_normal1_cmd_32_l;//slot9
  //  pRxCmdFifo->cmdFifo[3].cmd[2].cmd14h = rx_normal1_cmd_14_h;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd32l = rx_last_cmd_32_l;   //slot9前部分
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd14h = rx_last_cmd_14_h;
#else

   pRxCmdFifo->cmdFifo_num = 4;
    pRxCmdFifo->cmdFifo[0].cmd_num = 3;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd32l = rx_first_cmd_32_l;//slot9 后部分
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd14h = rx_first_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd32l = rx_normal1_cmd_32_l;//slot0
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd14h = rx_normal1_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd32l = rx_normal0_cmd_32_l;//slot1
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd14h = rx_normal0_cmd_14_h;
 //   pRxCmdFifo->cmdFifo[0].cmd[3].cmd32l = rx_normal0_cmd_32_l;//slot2
 //   pRxCmdFifo->cmdFifo[0].cmd[3].cmd14h = rx_normal0_cmd_14_h;

    pRxCmdFifo->cmdFifo[1].cmd_num = 2;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd32l = rx_normal1_cmd_32_l;//slot3
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd14h = rx_normal1_cmd_14_h;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd32l = rx_normal0_cmd_32_l;//slot4
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd14h = rx_normal0_cmd_14_h;

    pRxCmdFifo->cmdFifo[2].cmd_num = 3;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd32l = rx_normal1_cmd_32_l;//slot5
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd14h = rx_normal1_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd32l = rx_normal0_cmd_32_l;//slot6
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd32l = rx_normal1_cmd_32_l;//slot7
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd14h = rx_normal1_cmd_14_h;

    pRxCmdFifo->cmdFifo[3].cmd_num = 2;//3;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd32l = rx_normal0_cmd_32_l;//slot8
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[3].cmd[2].cmd32l = rx_normal1_cmd_32_l;//slot9
    pRxCmdFifo->cmdFifo[3].cmd[2].cmd14h = rx_normal1_cmd_14_h;
  //  pRxCmdFifo->cmdFifo[3].cmd[2].cmd32l = rx_last_cmd_32_l;   //slot9前部分
  //  pRxCmdFifo->cmdFifo[3].cmd[2].cmd14h = rx_last_cmd_14_h;
#endif
}

 /*!   
 * @brief:  配置NR小区的CPRI CSU链表
 * @author:  guicheng.liu
 * @Date:  2023年1月15日
 * @param: cell :             [NR 小区参数]
 */
void Config_Cpri_Csu_Nr(uint8_t slot_format)
{
    uint32_t rx_cycle_num = (0 == slot_format) ? 4 : 2;//1D3U场景下,dummy和特殊时隙2个符号的长度不是4的整数倍,是2的整数倍
    uint32_t tx_cycle_num = (0 == slot_format) ? 4 : 2;//1D3U场景下,特殊时隙后3个符号的长度不是4的整数倍,是2的整数倍;
    uint32_t axc_id_num = 6; //1个指数因子,4个天线, 1个AGC因子(暂时不支持AGC因子,但是平台目前要求必须要配)
    uint32_t in_latch_num = 6;
    uint32_t out_latch_num = 6;

  //  uint32_t send_threshold = 0;
  //  uint32_t almostfull_threshold = 0;
    stCpriCsuCmdFifoInfo tx_cmdfifo;
    stCpriCsuCmdFifoInfo rx_cmdfifo;

    if (1 == g_phy_csu_link.state)
    {
        //多小区的场景,只配置一次CSU就行
   //     return;
    }

    g_phy_csu_link.state = 1;

    memset(&tx_cmdfifo, 0, sizeof(stCpriCsuCmdFifoInfo));
    memset(&rx_cmdfifo, 0, sizeof(stCpriCsuCmdFifoInfo));

    UCP_API_CPRI_CSU_Set_AxcIdNum(axc_id_num);
    UCP_API_CPRI_CSU_Set_LatchNum(in_latch_num);
	Phy_Timer_Csu_Init();

    //! step1 初始化所有的必要的寄存器
    Cpri_Csu_Init();

    //!step2 配置TX&RX data outlatch
    Cpri_Csu_Latch_Init(axc_id_num, out_latch_num, in_latch_num, rx_cycle_num);

    {
    	//!step3: RX 和TX 的链表节点的配置
        Cpri_Csu_Link_Fdd_Init(out_latch_num, in_latch_num, rx_cycle_num, tx_cycle_num);

    	//!step4: RX和TX参数寄存器的配置
        Cpri_Csu_Reg_Fdd_Init(axc_id_num);

    	//!step5: 根据配置生成cmd fifo命令
        Cpri_Csu_Cmd_Gen_Fdd(&tx_cmdfifo, &rx_cmdfifo);
    }

    //!step6：把生成好的FIFO命令配置给驱动
    UCP_API_CPRI_CSU_Get_CmdFIFO(&tx_cmdfifo, &rx_cmdfifo);

}

#if 0
/*!   
* @brief:  根据NR配置 Timer和JESD/CPRI CSU Timer&DMA链表
* @author:  guicheng.liu
* @Date:  2022年7月8日
* @param: cell :             [NR 小区参数]
*/
void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell)
{
   // Config_Cpri_Csu_Nr(3);
	Config_Cpri_Csu_Nr(0);
}
#endif



