#include "rfm0_jesd_timer.h"
#include "ucp_drv_common.h"
#include "jesd204.h"
#include "ucp_param.h"
#include "mtimer_com.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "inter_vector.h"

#if 0
extern stPhyScsPara* phyPara;
extern stSfnPara gCellSfnPara[2];
extern int ecs_rfm0_cal_sfn(void);

void set_jesd_timer_rfm0_int(int32_t nTmrId)
{
    int32_t apeId = get_core_id();
    uint32_t intNum = 0;
    irq_handler pfunc = NULL;
    if (MTIMER_JESD_RX_ID == nTmrId)
    {
        intNum = APC_JESD_RX0_SBU0_TMR_INTR0 + MTMR_INT_RFM0_SLOT;
        pfunc = isr_jesd_rx_rfm0_slot;
    }
    else if (MTIMER_JESD_TX_ID == nTmrId)
    {
        intNum = APC_JESD_TX0_SBU0_TMR_INTR0 + MTMR_INT_RFM0_SLOT;
        //pfunc = isr_jesd_tx_rfm0_slot;
    }
    else
    {
        return;
    }
    int32_t ret = smart_irq_request(intNum, pfunc);
    if (0 != ret)
    {
        UCP_PRINT_EMPTY("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
        // debug write
        debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
    }
}

void isr_jesd_rx_rfm0_slot(void)
{
	uint32_t tmrIntcFlag = 0;
	uint32_t tEventFlag = 0;
	int32_t eventId = MTMR_INT_RFM0_SLOT;
	uint32_t tmrBaseAddr = JS_RX0_TMR_BASE;
	int32_t apeId = get_core_id();
	stCoreInt* apeCoreIntInfo = (stCoreInt*)APE_INT_INFO_ADDR + APE_INT_MAXNUM*apeId;

	tmrIntcFlag = do_read_volatile(tmrBaseAddr + JS_TMR_INTC_REG);
	if (tmrIntcFlag & (1 << eventId))  /* tmr int */
	{
		uint32_t flagAddr = tmrBaseAddr + JS_TMR_TINTF00_REG + 6*(MTMR_INT_RFM0_SLOT<<2);
		int32_t txSlotTmrId = MTMR_RFM0_TXSLOT;
		int32_t rxSlotTmrId = MTMR_RFM0_RXSLOT;
		tEventFlag = do_read_volatile(flagAddr);
		if (tEventFlag & ((1<<txSlotTmrId) | (1<<rxSlotTmrId)))
		{
			if (tEventFlag & (1<<txSlotTmrId)) // tx slot offset
			{
				uint32_t crVal = (1<<txSlotTmrId);
				do_write((tmrBaseAddr + JS_TMR_TEVENT0_REG), crVal);
				do_write(flagAddr, crVal);

				// sfn calibration
				ecs_rfm0_cal_sfn();
				gCellSfnPara[MTIMER_JESD_RX_ID].txSlotNum++;
				__ucps2_synch(0);
				if (gCellSfnPara[MTIMER_JESD_RX_ID].txSlotNum == gCellSfnPara[MTIMER_JESD_RX_ID].slotMaxNum)
				{
					gCellSfnPara[MTIMER_JESD_RX_ID].txSfnNum++;
					gCellSfnPara[MTIMER_JESD_RX_ID].txSfnNum &= 0x3FF;
					gCellSfnPara[MTIMER_JESD_RX_ID].txSlotNum = 0;
				}
				gCellSfnPara[MTIMER_JESD_RX_ID].txSlotTiming = GET_STC_CNT();

				do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2), gCellSfnPara[MTIMER_JESD_RX_ID].txSfnNum);
				do_write(SLOT_NUM_DEBUG_ADDR+((1+(apeId<<2))<<2), gCellSfnPara[MTIMER_JESD_RX_ID].txSlotNum);
				
				gCellSfnPara[MTIMER_JESD_RX_ID].txSlotIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+82), gCellSfnPara[MTIMER_JESD_RX_ID].txSlotIntCnt);	// 0x148
#endif
				// write sm
				do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intNum), APE_INT_TX_SLOT);
				do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intCnt), gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt);
			}
			if (tEventFlag & (1<<rxSlotTmrId)) // rx slot offset
			{
				uint32_t crVal = ((1<<rxSlotTmrId));
				do_write((tmrBaseAddr + JS_TMR_TEVENT0_REG), crVal);
				do_write(flagAddr, crVal);

				gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotNum++;
				__ucps2_synch(0);
				if (gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotNum == gCellSfnPara[MTIMER_JESD_RX_ID].slotMaxNum)
				{
					gCellSfnPara[MTIMER_JESD_RX_ID].rxSfnNum++;
					gCellSfnPara[MTIMER_JESD_RX_ID].rxSfnNum &= 0x3FF;
					gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotNum = 0;
				}
				gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotTiming = GET_STC_CNT();
				do_write(SLOT_NUM_DEBUG_ADDR+((2+(apeId<<2))<<2), gCellSfnPara[MTIMER_JESD_RX_ID].rxSfnNum);
				do_write(SLOT_NUM_DEBUG_ADDR+((3+(apeId<<2))<<2), gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotNum);

				gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+83), gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotIntCnt);	// 0x14c
#endif
				// write sm
				do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intNum), APE_INT_RX_SLOT);
				do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intCnt), gCellSfnPara[MTIMER_JESD_RX_ID].rxSlotIntCnt);
			}
			tEventFlag = do_read_volatile(flagAddr);
		}
		do_write((tmrBaseAddr + JS_TMR_INTC_REG), (1 << eventId));			// clear int
	}
}

#if 0
void isr_jesd_tx_rfm0_slot(void)
{
	uint32_t tmrIntcFlag = 0;
	uint32_t tEventFlag = 0;
	int32_t eventId = MTMR_INT_RFM0_SLOT;
	uint32_t tmrBaseAddr = JS_TX0_TMR_BASE;

	tmrIntcFlag = do_read_volatile(tmrBaseAddr + JS_TMR_INTC_REG);
	if (tmrIntcFlag & (1 << eventId))  /* tmr int */
	{
		uint32_t flagAddr = tmrBaseAddr + JS_TMR_TINTF00_REG + 6*(MTMR_INT_RFM0_SLOT<<2);
		int32_t txSlotTmrId = MTMR_RFM0_TXSLOT;
		int32_t rxSlotTmrId = MTMR_RFM0_RXSLOT;
		tEventFlag = do_read_volatile(flagAddr);
		if (tEventFlag & ((1<<txSlotTmrId) | (1<<rxSlotTmrId)))
		{
			if (tEventFlag & (1<<txSlotTmrId)) // tx slot offset
			{
				uint32_t crVal = (1<<txSlotTmrId);
				do_write((tmrBaseAddr + JS_TMR_TEVENT0_REG), crVal);
				do_write(flagAddr, crVal);

				gCellSfnPara[MTIMER_JESD_TX_ID].txSlotNum++;
				__ucps2_synch(0);
				if (gCellSfnPara[MTIMER_JESD_TX_ID].txSlotNum == gCellSfnPara[MTIMER_JESD_TX_ID].slotMaxNum)
				{
					gCellSfnPara[MTIMER_JESD_TX_ID].txSfnNum++;
					gCellSfnPara[MTIMER_JESD_TX_ID].txSfnNum &= 0x3FF;
					gCellSfnPara[MTIMER_JESD_TX_ID].txSlotNum = 0;
				}
				gCellSfnPara[MTIMER_JESD_TX_ID].txSlotTiming = GET_STC_CNT();

				gCellSfnPara[MTIMER_JESD_TX_ID].txSlotIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+290), gCellSfnPara[MTIMER_JESD_TX_ID].txSlotIntCnt);	// 0x488
#endif
			}
			if (tEventFlag & (1<<rxSlotTmrId)) // rx slot offset
			{
				uint32_t crVal = ((1<<rxSlotTmrId));
				do_write((tmrBaseAddr + JS_TMR_TEVENT0_REG), crVal);
				do_write(flagAddr, crVal);

				gCellSfnPara[MTIMER_JESD_TX_ID].rxSlotNum++;
				__ucps2_synch(0);
				if (gCellSfnPara[MTIMER_JESD_TX_ID].rxSlotNum == gCellSfnPara[MTIMER_JESD_TX_ID].slotMaxNum)
				{
					gCellSfnPara[MTIMER_JESD_TX_ID].rxSfnNum++;
					gCellSfnPara[MTIMER_JESD_TX_ID].rxSfnNum &= 0x3FF;
					gCellSfnPara[MTIMER_JESD_TX_ID].rxSlotNum = 0;
				}
				gCellSfnPara[MTIMER_JESD_TX_ID].rxSlotTiming = GET_STC_CNT();

				gCellSfnPara[MTIMER_JESD_TX_ID].rxSlotIntCnt++;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+291), gCellSfnPara[MTIMER_JESD_TX_ID].rxSlotIntCnt);	// 0x48c
#endif
			}
			tEventFlag = do_read_volatile(flagAddr);
		}
		do_write((tmrBaseAddr + JS_TMR_INTC_REG), (1 << eventId));			// clear int
	}
}
#endif
#endif

