#include "inter_vector.h"
#include "ucp_printf.h"
#include "rfm0_drv.h"
#include "spu_hw_queue.h"

#include "phy_para.h"
#include "rfm0_mtimer.h"
#include "ape_csu.h"
#include "hwque.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ctc_intr.h"
#include "spu_log.h"
#include "app_interface.h"

#include "ecpri_que.h"
#include "ecpri_csu.h"
#include "ecpri_irq.h"

#ifdef TEST_ENABLE
#include "fh_test.h"
#endif


/*****************************************************/
void ecs_rfm0_drv_init(void)
{
    int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
    int32_t flag = 1;
    debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag);   // 0xA0
#endif

    int32_t ret = 0;
    ret = smart_irq_init(apeId);
    if (0 != ret)
    {
        debug_write(DBG_DDR_ERR_IDX(apeId, 14), ret);
    }
    UCP_PRINT_EMPTY("smart inter init. \r\n");
#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag);   // 0xA0
#endif

    ape_csu_init();
    UCP_PRINT_EMPTY("ape csu init. \r\n");
#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag);   // 0xA0
#endif

    sfn_para_init();
    UCP_PRINT_EMPTY("sfn para init.\r\n");
#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag);   // 0xA0
#endif

	ctc_cal_intr_init();
	UCP_PRINT_EMPTY("ctc cal intr init.\r\n");
#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag);   // 0xA0
#endif

    /* wait protocol type config finished */
    while (PROTOCOL_NULL == get_protocol_sel());

    if (PROTOCOL_ECPRI == get_protocol_sel())
    {
        /* wait ecpri serdes clk init finished */
        while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR)));

        rfm0_mtimer_int_init();

        /* eCPRI queue init */
        (void)ecpri_que_init();

        /* eCPRI CSU init */
        (void)ecpri_csu_init();

        /* eCPRI symbol interrupt init */
        ecpri_sym_irq_init();

#ifdef TEST_ENABLE
        fh_test_init();
#endif

        UCP_PRINT_EMPTY("eCPRI mtimer&queue&CSU init.\r\n");
#ifdef PALLADIUM_TEST
        flag++;
        debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag);   // 0xA0
#endif
    }

    ecs_hw_que_init(apeId);
    //ecs_hw_que_init_withirq(apeId, apeId);
    //ecs_msg_que_init(apeId);
    //ecs_hw_que_init_noirq(apeId, ECS_RFM_SPU0_HW_QUEUE);
    spu_log_init(LOG_ERROR);
    UCP_PRINT_EMPTY("[rfm0_drv_init]: OK \r\n");
#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag);   // 0xA0
#endif
}

