//******************** (C) COPYRIGHT 2019 SmartLogic*******************************
// FileName           : dw_gmac.h
// Author             : lijian
// Date First Issued  : 2019-03-29 02:46:53 PM
// Last Modified      : 2022-02-19 10:11:08 AM
// Description        :
// ------------------------------------------------------------
// Modification History:
// Version    Date       Author    Modification Description
//
//**********************************************************************************
#ifndef __GMAC_H__
#define __GMAC_H__

#define  GMAC0_BASE                      0x01A40000
#define  GMAC0_DWC_EQOS_MAC_BASE         GMAC0_BASE + 0x0
#define  GMAC0_DWC_EQOS_MTL_BASE         GMAC0_BASE + 0xc00
#define  GMAC0_DWC_EQOS_MTL_Q0_BASE      GMAC0_BASE + 0xd00
#define  GMAC0_DWC_EQOS_MTL_Q1_BASE      GMAC0_BASE + 0xd40
#define  GMAC0_DWC_EQOS_MTL_Q2_BASE      GMAC0_BASE + 0xd80
#define  GMAC0_DWC_EQOS_MTL_Q3_BASE      GMAC0_BASE + 0xdc0
#define  GMAC0_DWC_EQOS_DMA_BASE         GMAC0_BASE + 0x1000
#define  GMAC0_DWC_EQOS_DMA_CH0_BASE     GMAC0_BASE + 0x1100
#define  GMAC0_DWC_EQOS_DMA_CH1_BASE     GMAC0_BASE + 0x1180
#define  GMAC0_DWC_EQOS_DMA_CH2_BASE     GMAC0_BASE + 0x1200
#define  GMAC0_DWC_EQOS_DMA_CH3_BASE     GMAC0_BASE + 0x1280
#define  GMAC0_CTRL_BASE                 GMAC0_BASE + 0x2000

#define  GMAC1_BASE                      0x01A50000
#define  GMAC1_DWC_EQOS_MAC_BASE         GMAC1_BASE + 0x0
#define  GMAC1_DWC_EQOS_MTL_BASE         GMAC1_BASE + 0xc00
#define  GMAC1_DWC_EQOS_MTL_Q0_BASE      GMAC1_BASE + 0xd00
#define  GMAC1_DWC_EQOS_MTL_Q1_BASE      GMAC1_BASE + 0xd40
#define  GMAC1_DWC_EQOS_MTL_Q2_BASE      GMAC1_BASE + 0xd80
#define  GMAC1_DWC_EQOS_MTL_Q3_BASE      GMAC1_BASE + 0xdc0
#define  GMAC1_DWC_EQOS_DMA_BASE         GMAC1_BASE + 0x1000
#define  GMAC1_DWC_EQOS_DMA_CH0_BASE     GMAC1_BASE + 0x1100
#define  GMAC1_DWC_EQOS_DMA_CH1_BASE     GMAC1_BASE + 0x1180
#define  GMAC1_DWC_EQOS_DMA_CH2_BASE     GMAC1_BASE + 0x1200
#define  GMAC1_DWC_EQOS_DMA_CH3_BASE     GMAC1_BASE + 0x1280
#define  GMAC1_CTRL_BASE                 GMAC1_BASE + 0x2000

#define  GMAC2_BASE                      0x08524000
#define  GMAC2_DWC_EQOS_MAC_BASE         GMAC2_BASE + 0x0
#define  GMAC2_DWC_EQOS_MTL_BASE         GMAC2_BASE + 0xc00
#define  GMAC2_DWC_EQOS_MTL_Q0_BASE      GMAC2_BASE + 0xd00
#define  GMAC2_DWC_EQOS_MTL_Q1_BASE      GMAC2_BASE + 0xd40
#define  GMAC2_DWC_EQOS_MTL_Q2_BASE      GMAC2_BASE + 0xd80
#define  GMAC2_DWC_EQOS_MTL_Q3_BASE      GMAC2_BASE + 0xdc0
#define  GMAC2_DWC_EQOS_DMA_BASE         GMAC2_BASE + 0x1000
#define  GMAC2_DWC_EQOS_DMA_CH0_BASE     GMAC2_BASE + 0x1100
#define  GMAC2_DWC_EQOS_DMA_CH1_BASE     GMAC2_BASE + 0x1180
#define  GMAC2_DWC_EQOS_DMA_CH2_BASE     GMAC2_BASE + 0x1200
#define  GMAC2_DWC_EQOS_DMA_CH3_BASE     GMAC2_BASE + 0x1280



#define  GMAC0_SUB_MODE                              (*((volatile uint32_t *)(GMAC0_CTRL_BASE         +0x0 )))
#define  GMAC0_SPEED                                 (*((volatile uint32_t *)(GMAC0_CTRL_BASE         +0x4 )))
#define  GMAC0_TEIMESTAMPL                           (*((volatile uint32_t *)(GMAC0_CTRL_BASE         +0x8 )))
#define  GMAC0_TEIMESTAMPH                           (*((volatile uint32_t *)(GMAC0_CTRL_BASE         +0xC )))
#define  GMAC0_CLKCTRL                               (*((volatile uint32_t *)(GMAC0_CTRL_BASE         +0x10)))
#define  GMAC0_PPS                                   (*((volatile uint32_t *)(GMAC0_CTRL_BASE         +0x14)))
#define  GMAC0_CTRL_MODE                             (*((volatile uint32_t *)(GMAC0_CTRL_BASE         +0x18)))

#define  GMAC0_MAC_Configuration                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x0 )))
#define  GMAC0_MAC_Ext_Configuration                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4 )))
#define  GMAC0_MAC_Packet_Filter                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x8 )))
#define  GMAC0_MAC_Watchdog_Timeout                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc )))
#define  GMAC0_MAC_Hash_Table_Reg0                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x10 )))
#define  GMAC0_MAC_Hash_Table_Reg1                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x14 )))
#define  GMAC0_MAC_VLAN_Tag                          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x50 )))
#define  GMAC0_MAC_Q0_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x70 )))
#define  GMAC0_MAC_Q1_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x74 )))
#define  GMAC0_MAC_Q2_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x78 )))
#define  GMAC0_MAC_Q3_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x7c )))
#define  GMAC0_MAC_Rx_Flow_Ctrl                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x90 )))
#define  GMAC0_MAC_RxQ_Ctrl4                         (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x94 )))
#define  GMAC0_MAC_TxQ_Prty_Map0                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x98 )))
#define  GMAC0_MAC_RxQ_Ctrl0                         (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xa0 )))
#define  GMAC0_MAC_RxQ_Ctrl1                         (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xa4 )))
#define  GMAC0_MAC_RxQ_Ctrl2                         (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xa8 )))
#define  GMAC0_MAC_Interrupt_Status                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb0 )))
#define  GMAC0_MAC_Interrupt_Enable                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb4 )))
#define  GMAC0_MAC_Rx_Tx_Status                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb8 )))
#define  GMAC0_MAC_PMT_Control_Status                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc0 )))
#define  GMAC0_MAC_RWK_Packet_Filter                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter0123_Command                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter0123_Offset                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter01_CRC                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter0_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter1_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter23_CRC                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter2_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter3_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter4567_Command                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter4567_Offset                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter45_CRC                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter4_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter5_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter67_CRC                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter6_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_RWK_Filter7_Byte_Mask                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC0_MAC_LPI_Control_Status                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xd0 )))
#define  GMAC0_MAC_LPI_Timers_Control                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xd4 )))
#define  GMAC0_MAC_LPI_Entry_Timer                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xd8 )))
#define  GMAC0_MAC_1US_Tic_Counter                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xdc )))
#define  GMAC0_MAC_PHYIF_Control_Status              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xf8 )))
#define  GMAC0_MAC_Version                           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x110 )))
#define  GMAC0_MAC_Debug                             (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x114 )))
#define  GMAC0_MAC_HW_Feature0                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x11c )))
#define  GMAC0_MAC_HW_Feature1                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x120 )))
#define  GMAC0_MAC_HW_Feature2                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x124 )))
#define  GMAC0_MAC_HW_Feature3                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x128 )))
#define  GMAC0_MAC_MDIO_Address                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x200 )))
#define  GMAC0_MAC_MDIO_Data                         (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x204 )))
#define  GMAC0_MAC_ARP_Address                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x210 )))
#define  GMAC0_MAC_CSR_SW_Ctrl                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x230 )))
#define  GMAC0_MAC_FPE_CTRL_STS                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x234 )))
#define  GMAC0_MAC_Ext_Cfg1                          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x238 )))
#define  GMAC0_MAC_Address0_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x300 )))
#define  GMAC0_MAC_Address0_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x304 )))
#define  GMAC0_MAC_Address1_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x308 )))
#define  GMAC0_MAC_Address1_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x30c )))
#define  GMAC0_MAC_Address2_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x310 )))
#define  GMAC0_MAC_Address2_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x314 )))
#define  GMAC0_MAC_Address3_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x318 )))
#define  GMAC0_MAC_Address3_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x31c )))
#define  GMAC0_MAC_Address4_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x320 )))
#define  GMAC0_MAC_Address4_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x324 )))
#define  GMAC0_MAC_Address5_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x328 )))
#define  GMAC0_MAC_Address5_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x32c )))
#define  GMAC0_MAC_Address6_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x330 )))
#define  GMAC0_MAC_Address6_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x334 )))
#define  GMAC0_MAC_Address7_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x338 )))
#define  GMAC0_MAC_Address7_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x33c )))
#define  GMAC0_MAC_Address8_High                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x340 )))
#define  GMAC0_MAC_Address8_Low                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x344 )))
#define  GMAC0_MAC_Address32_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x400 )))
#define  GMAC0_MAC_Address32_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x404 )))
#define  GMAC0_MAC_Address33_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x408 )))
#define  GMAC0_MAC_Address33_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x40c )))
#define  GMAC0_MAC_Address34_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x410 )))
#define  GMAC0_MAC_Address34_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x414 )))
#define  GMAC0_MAC_Address35_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x418 )))
#define  GMAC0_MAC_Address35_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x41c )))
#define  GMAC0_MAC_Address36_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x420 )))
#define  GMAC0_MAC_Address36_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x424 )))
#define  GMAC0_MAC_Address37_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x428 )))
#define  GMAC0_MAC_Address37_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x42c )))
#define  GMAC0_MAC_Address38_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x430 )))
#define  GMAC0_MAC_Address38_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x434 )))
#define  GMAC0_MAC_Address39_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x438 )))
#define  GMAC0_MAC_Address39_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x43c )))
#define  GMAC0_MAC_Address40_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x440 )))
#define  GMAC0_MAC_Address40_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x444 )))
#define  GMAC0_MAC_Address41_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x448 )))
#define  GMAC0_MAC_Address41_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x44c )))
#define  GMAC0_MAC_Address42_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x450 )))
#define  GMAC0_MAC_Address42_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x454 )))
#define  GMAC0_MAC_Address43_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x458 )))
#define  GMAC0_MAC_Address43_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x45c )))
#define  GMAC0_MAC_Address44_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x460 )))
#define  GMAC0_MAC_Address44_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x464 )))
#define  GMAC0_MAC_Address45_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x468 )))
#define  GMAC0_MAC_Address45_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x46c )))
#define  GMAC0_MAC_Address46_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x470 )))
#define  GMAC0_MAC_Address46_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x474 )))
#define  GMAC0_MAC_Address47_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x478 )))
#define  GMAC0_MAC_Address47_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x47c )))
#define  GMAC0_MAC_Address48_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x480 )))
#define  GMAC0_MAC_Address48_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x484 )))
#define  GMAC0_MAC_Address49_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x488 )))
#define  GMAC0_MAC_Address49_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x48c )))
#define  GMAC0_MAC_Address50_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x490 )))
#define  GMAC0_MAC_Address50_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x494 )))
#define  GMAC0_MAC_Address51_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x498 )))
#define  GMAC0_MAC_Address51_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x49c )))
#define  GMAC0_MAC_Address52_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4a0 )))
#define  GMAC0_MAC_Address52_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4a4 )))
#define  GMAC0_MAC_Address53_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4a8 )))
#define  GMAC0_MAC_Address53_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4ac )))
#define  GMAC0_MAC_Address54_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4b0 )))
#define  GMAC0_MAC_Address54_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4b4 )))
#define  GMAC0_MAC_Address55_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4b8 )))
#define  GMAC0_MAC_Address55_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4bc )))
#define  GMAC0_MAC_Address56_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4c0 )))
#define  GMAC0_MAC_Address56_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4c4 )))
#define  GMAC0_MAC_Address57_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4c8 )))
#define  GMAC0_MAC_Address57_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4cc )))
#define  GMAC0_MAC_Address58_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4d0 )))
#define  GMAC0_MAC_Address58_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4d4 )))
#define  GMAC0_MAC_Address59_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4d8 )))
#define  GMAC0_MAC_Address59_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4dc )))
#define  GMAC0_MAC_Address60_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4e0 )))
#define  GMAC0_MAC_Address60_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4e4 )))
#define  GMAC0_MAC_Address61_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4e8 )))
#define  GMAC0_MAC_Address61_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4ec )))
#define  GMAC0_MAC_Address62_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4f0 )))
#define  GMAC0_MAC_Address62_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4f4 )))
#define  GMAC0_MAC_Address63_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4f8 )))
#define  GMAC0_MAC_Address63_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x4fc )))
#define  GMAC0_MAC_Address64_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x500 )))
#define  GMAC0_MAC_Address64_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x504 )))
#define  GMAC0_MAC_Address65_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x508 )))
#define  GMAC0_MAC_Address65_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x50c )))
#define  GMAC0_MAC_Address66_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x510 )))
#define  GMAC0_MAC_Address66_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x514 )))
#define  GMAC0_MAC_Address67_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x518 )))
#define  GMAC0_MAC_Address67_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x51c )))
#define  GMAC0_MAC_Address68_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x520 )))
#define  GMAC0_MAC_Address68_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x524 )))
#define  GMAC0_MAC_Address69_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x528 )))
#define  GMAC0_MAC_Address69_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x52c )))
#define  GMAC0_MAC_Address70_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x530 )))
#define  GMAC0_MAC_Address70_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x534 )))
#define  GMAC0_MAC_Address71_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x538 )))
#define  GMAC0_MAC_Address71_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x53c )))
#define  GMAC0_MAC_Address72_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x540 )))
#define  GMAC0_MAC_Address72_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x544 )))
#define  GMAC0_MAC_Address73_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x548 )))
#define  GMAC0_MAC_Address73_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x54c )))
#define  GMAC0_MAC_Address74_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x550 )))
#define  GMAC0_MAC_Address74_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x554 )))
#define  GMAC0_MAC_Address75_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x558 )))
#define  GMAC0_MAC_Address75_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x55c )))
#define  GMAC0_MAC_Address76_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x560 )))
#define  GMAC0_MAC_Address76_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x564 )))
#define  GMAC0_MAC_Address77_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x568 )))
#define  GMAC0_MAC_Address77_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x56c )))
#define  GMAC0_MAC_Address78_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x570 )))
#define  GMAC0_MAC_Address78_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x574 )))
#define  GMAC0_MAC_Address79_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x578 )))
#define  GMAC0_MAC_Address79_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x57c )))
#define  GMAC0_MAC_Address80_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x580 )))
#define  GMAC0_MAC_Address80_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x584 )))
#define  GMAC0_MAC_Address81_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x588 )))
#define  GMAC0_MAC_Address81_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x58c )))
#define  GMAC0_MAC_Address82_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x590 )))
#define  GMAC0_MAC_Address82_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x594 )))
#define  GMAC0_MAC_Address83_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x598 )))
#define  GMAC0_MAC_Address83_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x59c )))
#define  GMAC0_MAC_Address84_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5a0 )))
#define  GMAC0_MAC_Address84_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5a4 )))
#define  GMAC0_MAC_Address85_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5a8 )))
#define  GMAC0_MAC_Address85_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5ac )))
#define  GMAC0_MAC_Address86_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5b0 )))
#define  GMAC0_MAC_Address86_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5b4 )))
#define  GMAC0_MAC_Address87_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5b8 )))
#define  GMAC0_MAC_Address87_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5bc )))
#define  GMAC0_MAC_Address88_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5c0 )))
#define  GMAC0_MAC_Address88_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5c4 )))
#define  GMAC0_MAC_Address89_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5c8 )))
#define  GMAC0_MAC_Address89_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5cc )))
#define  GMAC0_MAC_Address90_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5d0 )))
#define  GMAC0_MAC_Address90_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5d4 )))
#define  GMAC0_MAC_Address91_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5d8 )))
#define  GMAC0_MAC_Address91_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5dc )))
#define  GMAC0_MAC_Address92_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5e0 )))
#define  GMAC0_MAC_Address92_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5e4 )))
#define  GMAC0_MAC_Address93_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5e8 )))
#define  GMAC0_MAC_Address93_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5ec )))
#define  GMAC0_MAC_Address94_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5f0 )))
#define  GMAC0_MAC_Address94_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5f4 )))
#define  GMAC0_MAC_Address95_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5f8 )))
#define  GMAC0_MAC_Address95_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x5fc )))
#define  GMAC0_MAC_Address96_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x600 )))
#define  GMAC0_MAC_Address96_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x604 )))
#define  GMAC0_MAC_Address97_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x608 )))
#define  GMAC0_MAC_Address97_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x60c )))
#define  GMAC0_MAC_Address98_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x610 )))
#define  GMAC0_MAC_Address98_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x614 )))
#define  GMAC0_MAC_Address99_High                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x618 )))
#define  GMAC0_MAC_Address99_Low                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x61c )))
#define  GMAC0_MAC_Address100_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x620 )))
#define  GMAC0_MAC_Address100_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x624 )))
#define  GMAC0_MAC_Address101_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x628 )))
#define  GMAC0_MAC_Address101_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x62c )))
#define  GMAC0_MAC_Address102_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x630 )))
#define  GMAC0_MAC_Address102_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x634 )))
#define  GMAC0_MAC_Address103_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x638 )))
#define  GMAC0_MAC_Address103_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x63c )))
#define  GMAC0_MAC_Address104_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x640 )))
#define  GMAC0_MAC_Address104_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x644 )))
#define  GMAC0_MAC_Address105_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x648 )))
#define  GMAC0_MAC_Address105_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x64c )))
#define  GMAC0_MAC_Address106_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x650 )))
#define  GMAC0_MAC_Address106_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x654 )))
#define  GMAC0_MAC_Address107_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x658 )))
#define  GMAC0_MAC_Address107_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x65c )))
#define  GMAC0_MAC_Address108_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x660 )))
#define  GMAC0_MAC_Address108_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x664 )))
#define  GMAC0_MAC_Address109_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x668 )))
#define  GMAC0_MAC_Address109_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x66c )))
#define  GMAC0_MAC_Address110_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x670 )))
#define  GMAC0_MAC_Address110_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x674 )))
#define  GMAC0_MAC_Address111_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x678 )))
#define  GMAC0_MAC_Address111_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x67c )))
#define  GMAC0_MAC_Address112_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x680 )))
#define  GMAC0_MAC_Address112_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x684 )))
#define  GMAC0_MAC_Address113_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x688 )))
#define  GMAC0_MAC_Address113_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x68c )))
#define  GMAC0_MAC_Address114_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x690 )))
#define  GMAC0_MAC_Address114_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x694 )))
#define  GMAC0_MAC_Address115_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x698 )))
#define  GMAC0_MAC_Address115_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x69c )))
#define  GMAC0_MAC_Address116_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6a0 )))
#define  GMAC0_MAC_Address116_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6a4 )))
#define  GMAC0_MAC_Address117_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6a8 )))
#define  GMAC0_MAC_Address117_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6ac )))
#define  GMAC0_MAC_Address118_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6b0 )))
#define  GMAC0_MAC_Address118_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6b4 )))
#define  GMAC0_MAC_Address119_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6b8 )))
#define  GMAC0_MAC_Address119_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6bc )))
#define  GMAC0_MAC_Address120_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6c0 )))
#define  GMAC0_MAC_Address120_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6c4 )))
#define  GMAC0_MAC_Address121_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6c8 )))
#define  GMAC0_MAC_Address121_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6cc )))
#define  GMAC0_MAC_Address122_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6d0 )))
#define  GMAC0_MAC_Address122_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6d4 )))
#define  GMAC0_MAC_Address123_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6d8 )))
#define  GMAC0_MAC_Address123_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6dc )))
#define  GMAC0_MAC_Address124_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6e0 )))
#define  GMAC0_MAC_Address124_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6e4 )))
#define  GMAC0_MAC_Address125_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6e8 )))
#define  GMAC0_MAC_Address125_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6ec )))
#define  GMAC0_MAC_Address126_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6f0 )))
#define  GMAC0_MAC_Address126_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6f4 )))
#define  GMAC0_MAC_Address127_High                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6f8 )))
#define  GMAC0_MAC_Address127_Low                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x6fc )))
#define  GMAC0_MAC_L3_L4_Control0                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x900 )))
#define  GMAC0_MAC_Layer4_Address0                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x904 )))
#define  GMAC0_MAC_Layer3_Addr0_Reg0                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x910 )))
#define  GMAC0_MAC_Layer3_Addr1_Reg0                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x914 )))
#define  GMAC0_MAC_Layer3_Addr2_Reg0                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x918 )))
#define  GMAC0_MAC_Layer3_Addr3_Reg0                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x91c )))
#define  GMAC0_MAC_L3_L4_Control1                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x930 )))
#define  GMAC0_MAC_Layer4_Address1                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x934 )))
#define  GMAC0_MAC_Layer3_Addr0_Reg1                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x940 )))
#define  GMAC0_MAC_Layer3_Addr1_Reg1                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x944 )))
#define  GMAC0_MAC_Layer3_Addr2_Reg1                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x948 )))
#define  GMAC0_MAC_Layer3_Addr3_Reg1                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x94c )))
#define  GMAC0_MAC_L3_L4_Control2                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x960 )))
#define  GMAC0_MAC_Layer4_Address2                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x964 )))
#define  GMAC0_MAC_Layer3_Addr0_Reg2                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x970 )))
#define  GMAC0_MAC_Layer3_Addr1_Reg2                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x974 )))
#define  GMAC0_MAC_Layer3_Addr2_Reg2                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x978 )))
#define  GMAC0_MAC_Layer3_Addr3_Reg2                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x97c )))
#define  GMAC0_MAC_L3_L4_Control3                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x990 )))
#define  GMAC0_MAC_Layer4_Address3                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x994 )))
#define  GMAC0_MAC_Layer3_Addr0_Reg3                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9a0 )))
#define  GMAC0_MAC_Layer3_Addr1_Reg3                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9a4 )))
#define  GMAC0_MAC_Layer3_Addr2_Reg3                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9a8 )))
#define  GMAC0_MAC_Layer3_Addr3_Reg3                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9ac )))
#define  GMAC0_MAC_L3_L4_Control4                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9c0 )))
#define  GMAC0_MAC_Layer4_Address4                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9c4 )))
#define  GMAC0_MAC_Layer3_Addr0_Reg4                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9d0 )))
#define  GMAC0_MAC_Layer3_Addr1_Reg4                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9d4 )))
#define  GMAC0_MAC_Layer3_Addr2_Reg4                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9d8 )))
#define  GMAC0_MAC_Layer3_Addr3_Reg4                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0x9dc )))
#define  GMAC0_MAC_Timestamp_Control                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb00 )))
#define  GMAC0_MAC_Sub_Second_Increment              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb04 )))
#define  GMAC0_MAC_System_Time_Seconds               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb08 )))
#define  GMAC0_MAC_System_Time_Nanoseconds           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb0c )))
#define  GMAC0_MAC_System_Time_Seconds_Update        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb10 )))
#define  GMAC0_MAC_System_Time_Nanoseconds_Update    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb14 )))
#define  GMAC0_MAC_Timestamp_Addend                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb18 )))
#define  GMAC0_MAC_Timestamp_Status                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb20 )))
#define  GMAC0_MAC_Tx_Timestamp_Status_Nanoseconds   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb30 )))
#define  GMAC0_MAC_Tx_Timestamp_Status_Seconds       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb34 )))
#define  GMAC0_MAC_Auxiliary_Control                 (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb40 )))
#define  GMAC0_MAC_Auxiliary_Timestamp_Nanoseconds   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb48 )))
#define  GMAC0_MAC_Auxiliary_Timestamp_Seconds       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb4c )))
#define  GMAC0_MAC_Timestamp_Ingress_Asym_Corr       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb50 )))
#define  GMAC0_MAC_Timestamp_Egress_Asym_Corr        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb54 )))
#define  GMAC0_MAC_Timestamp_Ingress_Corr_Nanosecond (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb58 )))
#define  GMAC0_MAC_Timestamp_Egress_Corr_Nanosecond  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb5c )))
#define  GMAC0_MAC_Timestamp_Ingress_Latency         (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb68 )))
#define  GMAC0_MAC_Timestamp_Egress_Latency          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb6c )))
#define  GMAC0_MAC_PPS_Control                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb70 )))
#define  GMAC0_MAC_PPS0_Target_Time_Seconds          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb80 )))
#define  GMAC0_MAC_PPS0_Target_Time_Nanoseconds      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MAC_BASE +0xb84 )))
#define  GMAC0_MTL_Operation_Mode                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x0 )))
#define  GMAC0_MTL_Interrupt_Status                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x20 )))
#define  GMAC0_MTL_RxQ_DMA_Map0                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x30 )))
#define  GMAC0_MTL_RxQ_DMA_Map1                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x34 )))
#define  GMAC0_MTL_TBS_CTRL                          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x40 )))
#define  GMAC0_MTL_EST_Control                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x50 )))
#define  GMAC0_MTL_EST_Status                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x58 )))
#define  GMAC0_MTL_EST_Sch_Error                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x60 )))
#define  GMAC0_MTL_EST_Frm_Size_Error                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x64 )))
#define  GMAC0_MTL_EST_Frm_Size_Capture              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x68 )))
#define  GMAC0_MTL_EST_Intr_Enable                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x70 )))
#define  GMAC0_MTL_EST_GCL_Control                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x80 )))
#define  GMAC0_MTL_EST_GCL_Data                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x84 )))
#define  GMAC0_MTL_FPE_CTRL_STS                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x90 )))
#define  GMAC0_MTL_FPE_Advance                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_BASE +0x94 )))
#define  GMAC0_MTL_TxQ0_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x0 )))
#define  GMAC0_MTL_TxQ0_Underflow                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x4 )))
#define  GMAC0_MTL_TxQ0_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x8 )))
#define  GMAC0_MTL_TxQ0_ETS_Status                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x14 )))
#define  GMAC0_MTL_TxQ0_Quantum_Weight               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x18 )))
#define  GMAC0_MTL_Q0_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x2c )))
#define  GMAC0_MTL_RxQ0_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x30 )))
#define  GMAC0_MTL_RxQ0_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x34 )))
#define  GMAC0_MTL_RxQ0_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x38 )))
#define  GMAC0_MTL_RxQ0_Control                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q0_BASE +0x3c )))
#define  GMAC0_MTL_TxQ1_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x0 )))
#define  GMAC0_MTL_TxQ1_Underflow                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x4 )))
#define  GMAC0_MTL_TxQ1_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x8 )))
#define  GMAC0_MTL_TxQ1_ETS_Status                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x14 )))
#define  GMAC0_MTL_TxQ1_Quantum_Weight               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x18 )))
#define  GMAC0_MTL_Q1_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x2c )))
#define  GMAC0_MTL_RxQ1_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x30 )))
#define  GMAC0_MTL_RxQ1_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x34 )))
#define  GMAC0_MTL_RxQ1_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x38 )))
#define  GMAC0_MTL_RxQ1_Control                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q1_BASE +0x3c )))
#define  GMAC0_MTL_TxQ2_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x0 )))
#define  GMAC0_MTL_TxQ2_Underflow                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x4 )))
#define  GMAC0_MTL_TxQ2_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x8 )))
#define  GMAC0_MTL_TxQ2_ETS_Status                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x14 )))
#define  GMAC0_MTL_TxQ2_Quantum_Weight               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x18 )))
#define  GMAC0_MTL_Q2_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x2c )))
#define  GMAC0_MTL_RxQ2_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x30 )))
#define  GMAC0_MTL_RxQ2_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x34 )))
#define  GMAC0_MTL_RxQ2_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x38 )))
#define  GMAC0_MTL_RxQ2_Control                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q2_BASE +0x3c )))
#define  GMAC0_MTL_TxQ3_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x0 )))
#define  GMAC0_MTL_TxQ3_Underflow                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x4 )))
#define  GMAC0_MTL_TxQ3_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x8 )))
#define  GMAC0_MTL_TxQ3_ETS_Control                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x10 )))
#define  GMAC0_MTL_TxQ3_ETS_Status                   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x14 )))
#define  GMAC0_MTL_TxQ3_Quantum_Weight               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x18 )))
#define  GMAC0_MTL_TxQ3_SendSlopeCredit              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x1c )))
#define  GMAC0_MTL_TxQ3_HiCredit                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x20 )))
#define  GMAC0_MTL_TxQ3_LoCredit                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x24 )))
#define  GMAC0_MTL_Q3_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x2c )))
#define  GMAC0_MTL_RxQ3_Operation_Mode               (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x30 )))
#define  GMAC0_MTL_RxQ3_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x34 )))
#define  GMAC0_MTL_RxQ3_Debug                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x38 )))
#define  GMAC0_MTL_RxQ3_Control                      (*((volatile uint32_t *)(GMAC0_DWC_EQOS_MTL_Q3_BASE +0x3c )))
#define  GMAC0_DMA_Mode                              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_BASE +0x0 )))
#define  GMAC0_DMA_SysBus_Mode                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_BASE +0x4 )))
#define  GMAC0_DMA_Interrupt_Status                  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_BASE +0x8 )))
#define  GMAC0_DMA_Debug_Status0                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_BASE +0xc )))
#define  GMAC0_DMA_Debug_Status1                     (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_BASE +0x10 )))
#define  GMAC0_AXI_LPI_Entry_Interval                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_BASE +0x40 )))
#define  GMAC0_DMA_TBS_CTRL                          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_BASE +0x50 )))
#define  GMAC0_DMA_CH0_Control                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x0 )))
#define  GMAC0_DMA_CH0_Tx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x4 )))
#define  GMAC0_DMA_CH0_Rx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x8 )))
#define  GMAC0_DMA_CH0_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x10 )))
#define  GMAC0_DMA_CH0_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x14 )))
#define  GMAC0_DMA_CH0_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x18 )))
#define  GMAC0_DMA_CH0_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x1c )))
#define  GMAC0_DMA_CH0_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x20 )))
#define  GMAC0_DMA_CH0_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x28 )))
#define  GMAC0_DMA_CH0_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x2c )))
#define  GMAC0_DMA_CH0_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x30 )))
#define  GMAC0_DMA_CH0_Interrupt_Enable              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x34 )))
#define  GMAC0_DMA_CH0_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x38 )))
#define  GMAC0_DMA_CH0_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x3c )))
#define  GMAC0_DMA_CH0_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x44 )))
#define  GMAC0_DMA_CH0_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x4c )))
#define  GMAC0_DMA_CH0_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x54 )))
#define  GMAC0_DMA_CH0_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x5c )))
#define  GMAC0_DMA_CH0_Status                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x60 )))
#define  GMAC0_DMA_CH0_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x64 )))
#define  GMAC0_DMA_CH0_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH0_BASE +0x6c )))
#define  GMAC0_DMA_CH1_Control                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x0 )))
#define  GMAC0_DMA_CH1_Tx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x4 )))
#define  GMAC0_DMA_CH1_Rx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x8 )))
#define  GMAC0_DMA_CH1_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x10 )))
#define  GMAC0_DMA_CH1_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x14 )))
#define  GMAC0_DMA_CH1_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x18 )))
#define  GMAC0_DMA_CH1_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x1c )))
#define  GMAC0_DMA_CH1_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x20 )))
#define  GMAC0_DMA_CH1_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x28 )))
#define  GMAC0_DMA_CH1_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x2c )))
#define  GMAC0_DMA_CH1_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x30 )))
#define  GMAC0_DMA_CH1_Interrupt_Enable              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x34 )))
#define  GMAC0_DMA_CH1_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x38 )))
#define  GMAC0_DMA_CH1_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x3c )))
#define  GMAC0_DMA_CH1_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x44 )))
#define  GMAC0_DMA_CH1_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x4c )))
#define  GMAC0_DMA_CH1_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x54 )))
#define  GMAC0_DMA_CH1_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x5c )))
#define  GMAC0_DMA_CH1_Status                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x60 )))
#define  GMAC0_DMA_CH1_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x64 )))
#define  GMAC0_DMA_CH1_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH1_BASE +0x6c )))
#define  GMAC0_DMA_CH2_Control                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x0 )))
#define  GMAC0_DMA_CH2_Tx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x4 )))
#define  GMAC0_DMA_CH2_Rx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x8 )))
#define  GMAC0_DMA_CH2_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x10 )))
#define  GMAC0_DMA_CH2_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x14 )))
#define  GMAC0_DMA_CH2_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x18 )))
#define  GMAC0_DMA_CH2_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x1c )))
#define  GMAC0_DMA_CH2_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x20 )))
#define  GMAC0_DMA_CH2_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x28 )))
#define  GMAC0_DMA_CH2_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x2c )))
#define  GMAC0_DMA_CH2_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x30 )))
#define  GMAC0_DMA_CH2_Interrupt_Enable              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x34 )))
#define  GMAC0_DMA_CH2_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x38 )))
#define  GMAC0_DMA_CH2_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x3c )))
#define  GMAC0_DMA_CH2_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x44 )))
#define  GMAC0_DMA_CH2_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x4c )))
#define  GMAC0_DMA_CH2_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x54 )))
#define  GMAC0_DMA_CH2_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x5c )))
#define  GMAC0_DMA_CH2_Status                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x60 )))
#define  GMAC0_DMA_CH2_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x64 )))
#define  GMAC0_DMA_CH2_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH2_BASE +0x6c )))
#define  GMAC0_DMA_CH3_Control                       (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x0 )))
#define  GMAC0_DMA_CH3_Tx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x4 )))
#define  GMAC0_DMA_CH3_Rx_Control                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x8 )))
#define  GMAC0_DMA_CH3_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x10 )))
#define  GMAC0_DMA_CH3_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x14 )))
#define  GMAC0_DMA_CH3_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x18 )))
#define  GMAC0_DMA_CH3_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x1c )))
#define  GMAC0_DMA_CH3_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x20 )))
#define  GMAC0_DMA_CH3_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x28 )))
#define  GMAC0_DMA_CH3_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x2c )))
#define  GMAC0_DMA_CH3_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x30 )))
#define  GMAC0_DMA_CH3_Interrupt_Enable              (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x34 )))
#define  GMAC0_DMA_CH3_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x38 )))
#define  GMAC0_DMA_CH3_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x3c )))
#define  GMAC0_DMA_CH3_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x44 )))
#define  GMAC0_DMA_CH3_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x4c )))
#define  GMAC0_DMA_CH3_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x54 )))
#define  GMAC0_DMA_CH3_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x5c )))
#define  GMAC0_DMA_CH3_Status                        (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x60 )))
#define  GMAC0_DMA_CH3_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x64 )))
#define  GMAC0_DMA_CH3_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC0_DWC_EQOS_DMA_CH3_BASE +0x6c )))


#define  GMAC1_SUB_MODE                              (*((volatile uint32_t *)(GMAC1_CTRL_BASE         +0x0 ))) 
#define  GMAC1_SPEED                                 (*((volatile uint32_t *)(GMAC1_CTRL_BASE         +0x4 )))
#define  GMAC1_TEIMESTAMPL                           (*((volatile uint32_t *)(GMAC1_CTRL_BASE         +0x8 )))
#define  GMAC1_TEIMESTAMPH                           (*((volatile uint32_t *)(GMAC1_CTRL_BASE         +0xC )))
#define  GMAC1_CLKCTRL                               (*((volatile uint32_t *)(GMAC1_CTRL_BASE         +0x10)))
#define  GMAC1_PPS                                   (*((volatile uint32_t *)(GMAC1_CTRL_BASE         +0x14)))
#define  GMAC1_CTRL_MODE                             (*((volatile uint32_t *)(GMAC1_CTRL_BASE         +0x18)))

#define  GMAC1_MAC_Configuration                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x0 )))
#define  GMAC1_MAC_Ext_Configuration                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4 )))
#define  GMAC1_MAC_Packet_Filter                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x8 )))
#define  GMAC1_MAC_Watchdog_Timeout                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc )))
#define  GMAC1_MAC_Hash_Table_Reg0                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x10 )))
#define  GMAC1_MAC_Hash_Table_Reg1                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x14 )))
#define  GMAC1_MAC_VLAN_Tag                          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x50 )))
#define  GMAC1_MAC_Q0_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x70 )))
#define  GMAC1_MAC_Q1_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x74 )))
#define  GMAC1_MAC_Q2_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x78 )))
#define  GMAC1_MAC_Q3_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x7c )))
#define  GMAC1_MAC_Rx_Flow_Ctrl                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x90 )))
#define  GMAC1_MAC_RxQ_Ctrl4                         (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x94 )))
#define  GMAC1_MAC_TxQ_Prty_Map0                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x98 )))
#define  GMAC1_MAC_RxQ_Ctrl0                         (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xa0 )))
#define  GMAC1_MAC_RxQ_Ctrl1                         (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xa4 )))
#define  GMAC1_MAC_RxQ_Ctrl2                         (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xa8 )))
#define  GMAC1_MAC_Interrupt_Status                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb0 )))
#define  GMAC1_MAC_Interrupt_Enable                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb4 )))
#define  GMAC1_MAC_Rx_Tx_Status                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb8 )))
#define  GMAC1_MAC_PMT_Control_Status                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc0 )))
#define  GMAC1_MAC_RWK_Packet_Filter                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter0123_Command                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter0123_Offset                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter01_CRC                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter0_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter1_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter23_CRC                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter2_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter3_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter4567_Command                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter4567_Offset                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter45_CRC                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter4_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter5_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter67_CRC                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter6_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_RWK_Filter7_Byte_Mask                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC1_MAC_LPI_Control_Status                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xd0 )))
#define  GMAC1_MAC_LPI_Timers_Control                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xd4 )))
#define  GMAC1_MAC_LPI_Entry_Timer                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xd8 )))
#define  GMAC1_MAC_1US_Tic_Counter                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xdc )))
#define  GMAC1_MAC_PHYIF_Control_Status              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xf8 )))
#define  GMAC1_MAC_Version                           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x110 )))
#define  GMAC1_MAC_Debug                             (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x114 )))
#define  GMAC1_MAC_HW_Feature0                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x11c )))
#define  GMAC1_MAC_HW_Feature1                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x120 )))
#define  GMAC1_MAC_HW_Feature2                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x124 )))
#define  GMAC1_MAC_HW_Feature3                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x128 )))
#define  GMAC1_MAC_MDIO_Address                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x200 )))
#define  GMAC1_MAC_MDIO_Data                         (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x204 )))
#define  GMAC1_MAC_ARP_Address                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x210 )))
#define  GMAC1_MAC_CSR_SW_Ctrl                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x230 )))
#define  GMAC1_MAC_FPE_CTRL_STS                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x234 )))
#define  GMAC1_MAC_Ext_Cfg1                          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x238 )))
#define  GMAC1_MAC_Address0_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x300 )))
#define  GMAC1_MAC_Address0_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x304 )))
#define  GMAC1_MAC_Address1_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x308 )))
#define  GMAC1_MAC_Address1_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x30c )))
#define  GMAC1_MAC_Address2_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x310 )))
#define  GMAC1_MAC_Address2_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x314 )))
#define  GMAC1_MAC_Address3_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x318 )))
#define  GMAC1_MAC_Address3_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x31c )))
#define  GMAC1_MAC_Address4_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x320 )))
#define  GMAC1_MAC_Address4_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x324 )))
#define  GMAC1_MAC_Address5_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x328 )))
#define  GMAC1_MAC_Address5_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x32c )))
#define  GMAC1_MAC_Address6_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x330 )))
#define  GMAC1_MAC_Address6_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x334 )))
#define  GMAC1_MAC_Address7_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x338 )))
#define  GMAC1_MAC_Address7_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x33c )))
#define  GMAC1_MAC_Address8_High                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x340 )))
#define  GMAC1_MAC_Address8_Low                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x344 )))
#define  GMAC1_MAC_Address32_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x400 )))
#define  GMAC1_MAC_Address32_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x404 )))
#define  GMAC1_MAC_Address33_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x408 )))
#define  GMAC1_MAC_Address33_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x40c )))
#define  GMAC1_MAC_Address34_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x410 )))
#define  GMAC1_MAC_Address34_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x414 )))
#define  GMAC1_MAC_Address35_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x418 )))
#define  GMAC1_MAC_Address35_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x41c )))
#define  GMAC1_MAC_Address36_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x420 )))
#define  GMAC1_MAC_Address36_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x424 )))
#define  GMAC1_MAC_Address37_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x428 )))
#define  GMAC1_MAC_Address37_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x42c )))
#define  GMAC1_MAC_Address38_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x430 )))
#define  GMAC1_MAC_Address38_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x434 )))
#define  GMAC1_MAC_Address39_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x438 )))
#define  GMAC1_MAC_Address39_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x43c )))
#define  GMAC1_MAC_Address40_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x440 )))
#define  GMAC1_MAC_Address40_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x444 )))
#define  GMAC1_MAC_Address41_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x448 )))
#define  GMAC1_MAC_Address41_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x44c )))
#define  GMAC1_MAC_Address42_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x450 )))
#define  GMAC1_MAC_Address42_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x454 )))
#define  GMAC1_MAC_Address43_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x458 )))
#define  GMAC1_MAC_Address43_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x45c )))
#define  GMAC1_MAC_Address44_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x460 )))
#define  GMAC1_MAC_Address44_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x464 )))
#define  GMAC1_MAC_Address45_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x468 )))
#define  GMAC1_MAC_Address45_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x46c )))
#define  GMAC1_MAC_Address46_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x470 )))
#define  GMAC1_MAC_Address46_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x474 )))
#define  GMAC1_MAC_Address47_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x478 )))
#define  GMAC1_MAC_Address47_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x47c )))
#define  GMAC1_MAC_Address48_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x480 )))
#define  GMAC1_MAC_Address48_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x484 )))
#define  GMAC1_MAC_Address49_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x488 )))
#define  GMAC1_MAC_Address49_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x48c )))
#define  GMAC1_MAC_Address50_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x490 )))
#define  GMAC1_MAC_Address50_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x494 )))
#define  GMAC1_MAC_Address51_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x498 )))
#define  GMAC1_MAC_Address51_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x49c )))
#define  GMAC1_MAC_Address52_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4a0 )))
#define  GMAC1_MAC_Address52_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4a4 )))
#define  GMAC1_MAC_Address53_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4a8 )))
#define  GMAC1_MAC_Address53_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4ac )))
#define  GMAC1_MAC_Address54_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4b0 )))
#define  GMAC1_MAC_Address54_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4b4 )))
#define  GMAC1_MAC_Address55_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4b8 )))
#define  GMAC1_MAC_Address55_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4bc )))
#define  GMAC1_MAC_Address56_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4c0 )))
#define  GMAC1_MAC_Address56_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4c4 )))
#define  GMAC1_MAC_Address57_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4c8 )))
#define  GMAC1_MAC_Address57_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4cc )))
#define  GMAC1_MAC_Address58_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4d0 )))
#define  GMAC1_MAC_Address58_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4d4 )))
#define  GMAC1_MAC_Address59_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4d8 )))
#define  GMAC1_MAC_Address59_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4dc )))
#define  GMAC1_MAC_Address60_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4e0 )))
#define  GMAC1_MAC_Address60_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4e4 )))
#define  GMAC1_MAC_Address61_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4e8 )))
#define  GMAC1_MAC_Address61_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4ec )))
#define  GMAC1_MAC_Address62_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4f0 )))
#define  GMAC1_MAC_Address62_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4f4 )))
#define  GMAC1_MAC_Address63_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4f8 )))
#define  GMAC1_MAC_Address63_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x4fc )))
#define  GMAC1_MAC_Address64_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x500 )))
#define  GMAC1_MAC_Address64_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x504 )))
#define  GMAC1_MAC_Address65_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x508 )))
#define  GMAC1_MAC_Address65_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x50c )))
#define  GMAC1_MAC_Address66_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x510 )))
#define  GMAC1_MAC_Address66_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x514 )))
#define  GMAC1_MAC_Address67_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x518 )))
#define  GMAC1_MAC_Address67_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x51c )))
#define  GMAC1_MAC_Address68_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x520 )))
#define  GMAC1_MAC_Address68_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x524 )))
#define  GMAC1_MAC_Address69_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x528 )))
#define  GMAC1_MAC_Address69_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x52c )))
#define  GMAC1_MAC_Address70_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x530 )))
#define  GMAC1_MAC_Address70_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x534 )))
#define  GMAC1_MAC_Address71_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x538 )))
#define  GMAC1_MAC_Address71_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x53c )))
#define  GMAC1_MAC_Address72_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x540 )))
#define  GMAC1_MAC_Address72_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x544 )))
#define  GMAC1_MAC_Address73_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x548 )))
#define  GMAC1_MAC_Address73_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x54c )))
#define  GMAC1_MAC_Address74_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x550 )))
#define  GMAC1_MAC_Address74_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x554 )))
#define  GMAC1_MAC_Address75_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x558 )))
#define  GMAC1_MAC_Address75_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x55c )))
#define  GMAC1_MAC_Address76_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x560 )))
#define  GMAC1_MAC_Address76_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x564 )))
#define  GMAC1_MAC_Address77_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x568 )))
#define  GMAC1_MAC_Address77_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x56c )))
#define  GMAC1_MAC_Address78_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x570 )))
#define  GMAC1_MAC_Address78_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x574 )))
#define  GMAC1_MAC_Address79_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x578 )))
#define  GMAC1_MAC_Address79_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x57c )))
#define  GMAC1_MAC_Address80_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x580 )))
#define  GMAC1_MAC_Address80_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x584 )))
#define  GMAC1_MAC_Address81_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x588 )))
#define  GMAC1_MAC_Address81_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x58c )))
#define  GMAC1_MAC_Address82_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x590 )))
#define  GMAC1_MAC_Address82_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x594 )))
#define  GMAC1_MAC_Address83_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x598 )))
#define  GMAC1_MAC_Address83_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x59c )))
#define  GMAC1_MAC_Address84_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5a0 )))
#define  GMAC1_MAC_Address84_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5a4 )))
#define  GMAC1_MAC_Address85_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5a8 )))
#define  GMAC1_MAC_Address85_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5ac )))
#define  GMAC1_MAC_Address86_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5b0 )))
#define  GMAC1_MAC_Address86_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5b4 )))
#define  GMAC1_MAC_Address87_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5b8 )))
#define  GMAC1_MAC_Address87_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5bc )))
#define  GMAC1_MAC_Address88_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5c0 )))
#define  GMAC1_MAC_Address88_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5c4 )))
#define  GMAC1_MAC_Address89_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5c8 )))
#define  GMAC1_MAC_Address89_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5cc )))
#define  GMAC1_MAC_Address90_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5d0 )))
#define  GMAC1_MAC_Address90_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5d4 )))
#define  GMAC1_MAC_Address91_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5d8 )))
#define  GMAC1_MAC_Address91_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5dc )))
#define  GMAC1_MAC_Address92_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5e0 )))
#define  GMAC1_MAC_Address92_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5e4 )))
#define  GMAC1_MAC_Address93_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5e8 )))
#define  GMAC1_MAC_Address93_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5ec )))
#define  GMAC1_MAC_Address94_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5f0 )))
#define  GMAC1_MAC_Address94_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5f4 )))
#define  GMAC1_MAC_Address95_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5f8 )))
#define  GMAC1_MAC_Address95_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x5fc )))
#define  GMAC1_MAC_Address96_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x600 )))
#define  GMAC1_MAC_Address96_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x604 )))
#define  GMAC1_MAC_Address97_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x608 )))
#define  GMAC1_MAC_Address97_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x60c )))
#define  GMAC1_MAC_Address98_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x610 )))
#define  GMAC1_MAC_Address98_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x614 )))
#define  GMAC1_MAC_Address99_High                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x618 )))
#define  GMAC1_MAC_Address99_Low                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x61c )))
#define  GMAC1_MAC_Address100_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x620 )))
#define  GMAC1_MAC_Address100_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x624 )))
#define  GMAC1_MAC_Address101_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x628 )))
#define  GMAC1_MAC_Address101_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x62c )))
#define  GMAC1_MAC_Address102_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x630 )))
#define  GMAC1_MAC_Address102_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x634 )))
#define  GMAC1_MAC_Address103_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x638 )))
#define  GMAC1_MAC_Address103_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x63c )))
#define  GMAC1_MAC_Address104_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x640 )))
#define  GMAC1_MAC_Address104_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x644 )))
#define  GMAC1_MAC_Address105_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x648 )))
#define  GMAC1_MAC_Address105_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x64c )))
#define  GMAC1_MAC_Address106_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x650 )))
#define  GMAC1_MAC_Address106_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x654 )))
#define  GMAC1_MAC_Address107_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x658 )))
#define  GMAC1_MAC_Address107_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x65c )))
#define  GMAC1_MAC_Address108_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x660 )))
#define  GMAC1_MAC_Address108_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x664 )))
#define  GMAC1_MAC_Address109_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x668 )))
#define  GMAC1_MAC_Address109_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x66c )))
#define  GMAC1_MAC_Address110_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x670 )))
#define  GMAC1_MAC_Address110_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x674 )))
#define  GMAC1_MAC_Address111_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x678 )))
#define  GMAC1_MAC_Address111_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x67c )))
#define  GMAC1_MAC_Address112_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x680 )))
#define  GMAC1_MAC_Address112_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x684 )))
#define  GMAC1_MAC_Address113_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x688 )))
#define  GMAC1_MAC_Address113_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x68c )))
#define  GMAC1_MAC_Address114_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x690 )))
#define  GMAC1_MAC_Address114_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x694 )))
#define  GMAC1_MAC_Address115_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x698 )))
#define  GMAC1_MAC_Address115_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x69c )))
#define  GMAC1_MAC_Address116_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6a0 )))
#define  GMAC1_MAC_Address116_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6a4 )))
#define  GMAC1_MAC_Address117_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6a8 )))
#define  GMAC1_MAC_Address117_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6ac )))
#define  GMAC1_MAC_Address118_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6b0 )))
#define  GMAC1_MAC_Address118_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6b4 )))
#define  GMAC1_MAC_Address119_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6b8 )))
#define  GMAC1_MAC_Address119_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6bc )))
#define  GMAC1_MAC_Address120_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6c0 )))
#define  GMAC1_MAC_Address120_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6c4 )))
#define  GMAC1_MAC_Address121_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6c8 )))
#define  GMAC1_MAC_Address121_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6cc )))
#define  GMAC1_MAC_Address122_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6d0 )))
#define  GMAC1_MAC_Address122_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6d4 )))
#define  GMAC1_MAC_Address123_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6d8 )))
#define  GMAC1_MAC_Address123_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6dc )))
#define  GMAC1_MAC_Address124_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6e0 )))
#define  GMAC1_MAC_Address124_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6e4 )))
#define  GMAC1_MAC_Address125_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6e8 )))
#define  GMAC1_MAC_Address125_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6ec )))
#define  GMAC1_MAC_Address126_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6f0 )))
#define  GMAC1_MAC_Address126_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6f4 )))
#define  GMAC1_MAC_Address127_High                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6f8 )))
#define  GMAC1_MAC_Address127_Low                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x6fc )))
#define  GMAC1_MAC_L3_L4_Control0                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x900 )))
#define  GMAC1_MAC_Layer4_Address0                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x904 )))
#define  GMAC1_MAC_Layer3_Addr0_Reg0                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x910 )))
#define  GMAC1_MAC_Layer3_Addr1_Reg0                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x914 )))
#define  GMAC1_MAC_Layer3_Addr2_Reg0                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x918 )))
#define  GMAC1_MAC_Layer3_Addr3_Reg0                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x91c )))
#define  GMAC1_MAC_L3_L4_Control1                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x930 )))
#define  GMAC1_MAC_Layer4_Address1                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x934 )))
#define  GMAC1_MAC_Layer3_Addr0_Reg1                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x940 )))
#define  GMAC1_MAC_Layer3_Addr1_Reg1                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x944 )))
#define  GMAC1_MAC_Layer3_Addr2_Reg1                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x948 )))
#define  GMAC1_MAC_Layer3_Addr3_Reg1                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x94c )))
#define  GMAC1_MAC_L3_L4_Control2                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x960 )))
#define  GMAC1_MAC_Layer4_Address2                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x964 )))
#define  GMAC1_MAC_Layer3_Addr0_Reg2                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x970 )))
#define  GMAC1_MAC_Layer3_Addr1_Reg2                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x974 )))
#define  GMAC1_MAC_Layer3_Addr2_Reg2                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x978 )))
#define  GMAC1_MAC_Layer3_Addr3_Reg2                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x97c )))
#define  GMAC1_MAC_L3_L4_Control3                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x990 )))
#define  GMAC1_MAC_Layer4_Address3                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x994 )))
#define  GMAC1_MAC_Layer3_Addr0_Reg3                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9a0 )))
#define  GMAC1_MAC_Layer3_Addr1_Reg3                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9a4 )))
#define  GMAC1_MAC_Layer3_Addr2_Reg3                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9a8 )))
#define  GMAC1_MAC_Layer3_Addr3_Reg3                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9ac )))
#define  GMAC1_MAC_L3_L4_Control4                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9c0 )))
#define  GMAC1_MAC_Layer4_Address4                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9c4 )))
#define  GMAC1_MAC_Layer3_Addr0_Reg4                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9d0 )))
#define  GMAC1_MAC_Layer3_Addr1_Reg4                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9d4 )))
#define  GMAC1_MAC_Layer3_Addr2_Reg4                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9d8 )))
#define  GMAC1_MAC_Layer3_Addr3_Reg4                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0x9dc )))
#define  GMAC1_MAC_Timestamp_Control                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb00 )))
#define  GMAC1_MAC_Sub_Second_Increment              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb04 )))
#define  GMAC1_MAC_System_Time_Seconds               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb08 )))
#define  GMAC1_MAC_System_Time_Nanoseconds           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb0c )))
#define  GMAC1_MAC_System_Time_Seconds_Update        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb10 )))
#define  GMAC1_MAC_System_Time_Nanoseconds_Update    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb14 )))
#define  GMAC1_MAC_Timestamp_Addend                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb18 )))
#define  GMAC1_MAC_Timestamp_Status                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb20 )))
#define  GMAC1_MAC_Tx_Timestamp_Status_Nanoseconds   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb30 )))
#define  GMAC1_MAC_Tx_Timestamp_Status_Seconds       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb34 )))
#define  GMAC1_MAC_Auxiliary_Control                 (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb40 )))
#define  GMAC1_MAC_Auxiliary_Timestamp_Nanoseconds   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb48 )))
#define  GMAC1_MAC_Auxiliary_Timestamp_Seconds       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb4c )))
#define  GMAC1_MAC_Timestamp_Ingress_Asym_Corr       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb50 )))
#define  GMAC1_MAC_Timestamp_Egress_Asym_Corr        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb54 )))
#define  GMAC1_MAC_Timestamp_Ingress_Corr_Nanosecond (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb58 )))
#define  GMAC1_MAC_Timestamp_Egress_Corr_Nanosecond  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb5c )))
#define  GMAC1_MAC_Timestamp_Ingress_Latency         (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb68 )))
#define  GMAC1_MAC_Timestamp_Egress_Latency          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb6c )))
#define  GMAC1_MAC_PPS_Control                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb70 )))
#define  GMAC1_MAC_PPS0_Target_Time_Seconds          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb80 )))
#define  GMAC1_MAC_PPS0_Target_Time_Nanoseconds      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MAC_BASE +0xb84 )))
#define  GMAC1_MTL_Operation_Mode                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x0 )))
#define  GMAC1_MTL_Interrupt_Status                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x20 )))
#define  GMAC1_MTL_RxQ_DMA_Map0                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x30 )))
#define  GMAC1_MTL_RxQ_DMA_Map1                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x34 )))
#define  GMAC1_MTL_TBS_CTRL                          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x40 )))
#define  GMAC1_MTL_EST_Control                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x50 )))
#define  GMAC1_MTL_EST_Status                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x58 )))
#define  GMAC1_MTL_EST_Sch_Error                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x60 )))
#define  GMAC1_MTL_EST_Frm_Size_Error                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x64 )))
#define  GMAC1_MTL_EST_Frm_Size_Capture              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x68 )))
#define  GMAC1_MTL_EST_Intr_Enable                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x70 )))
#define  GMAC1_MTL_EST_GCL_Control                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x80 )))
#define  GMAC1_MTL_EST_GCL_Data                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x84 )))
#define  GMAC1_MTL_FPE_CTRL_STS                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x90 )))
#define  GMAC1_MTL_FPE_Advance                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_BASE +0x94 )))
#define  GMAC1_MTL_TxQ0_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x0 )))
#define  GMAC1_MTL_TxQ0_Underflow                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x4 )))
#define  GMAC1_MTL_TxQ0_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x8 )))
#define  GMAC1_MTL_TxQ0_ETS_Status                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x14 )))
#define  GMAC1_MTL_TxQ0_Quantum_Weight               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x18 )))
#define  GMAC1_MTL_Q0_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x2c )))
#define  GMAC1_MTL_RxQ0_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x30 )))
#define  GMAC1_MTL_RxQ0_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x34 )))
#define  GMAC1_MTL_RxQ0_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x38 )))
#define  GMAC1_MTL_RxQ0_Control                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q0_BASE +0x3c )))
#define  GMAC1_MTL_TxQ1_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x0 )))
#define  GMAC1_MTL_TxQ1_Underflow                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x4 )))
#define  GMAC1_MTL_TxQ1_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x8 )))
#define  GMAC1_MTL_TxQ1_ETS_Status                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x14 )))
#define  GMAC1_MTL_TxQ1_Quantum_Weight               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x18 )))
#define  GMAC1_MTL_Q1_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x2c )))
#define  GMAC1_MTL_RxQ1_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x30 )))
#define  GMAC1_MTL_RxQ1_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x34 )))
#define  GMAC1_MTL_RxQ1_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x38 )))
#define  GMAC1_MTL_RxQ1_Control                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q1_BASE +0x3c )))
#define  GMAC1_MTL_TxQ2_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x0 )))
#define  GMAC1_MTL_TxQ2_Underflow                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x4 )))
#define  GMAC1_MTL_TxQ2_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x8 )))
#define  GMAC1_MTL_TxQ2_ETS_Status                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x14 )))
#define  GMAC1_MTL_TxQ2_Quantum_Weight               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x18 )))
#define  GMAC1_MTL_Q2_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x2c )))
#define  GMAC1_MTL_RxQ2_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x30 )))
#define  GMAC1_MTL_RxQ2_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x34 )))
#define  GMAC1_MTL_RxQ2_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x38 )))
#define  GMAC1_MTL_RxQ2_Control                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q2_BASE +0x3c )))
#define  GMAC1_MTL_TxQ3_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x0 )))
#define  GMAC1_MTL_TxQ3_Underflow                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x4 )))
#define  GMAC1_MTL_TxQ3_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x8 )))
#define  GMAC1_MTL_TxQ3_ETS_Control                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x10 )))
#define  GMAC1_MTL_TxQ3_ETS_Status                   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x14 )))
#define  GMAC1_MTL_TxQ3_Quantum_Weight               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x18 )))
#define  GMAC1_MTL_TxQ3_SendSlopeCredit              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x1c )))
#define  GMAC1_MTL_TxQ3_HiCredit                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x20 )))
#define  GMAC1_MTL_TxQ3_LoCredit                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x24 )))
#define  GMAC1_MTL_Q3_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x2c )))
#define  GMAC1_MTL_RxQ3_Operation_Mode               (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x30 )))
#define  GMAC1_MTL_RxQ3_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x34 )))
#define  GMAC1_MTL_RxQ3_Debug                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x38 )))
#define  GMAC1_MTL_RxQ3_Control                      (*((volatile uint32_t *)(GMAC1_DWC_EQOS_MTL_Q3_BASE +0x3c )))
#define  GMAC1_DMA_Mode                              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_BASE +0x0 )))
#define  GMAC1_DMA_SysBus_Mode                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_BASE +0x4 )))
#define  GMAC1_DMA_Interrupt_Status                  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_BASE +0x8 )))
#define  GMAC1_DMA_Debug_Status0                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_BASE +0xc )))
#define  GMAC1_DMA_Debug_Status1                     (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_BASE +0x10 )))
#define  GMAC1_AXI_LPI_Entry_Interval                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_BASE +0x40 )))
#define  GMAC1_DMA_TBS_CTRL                          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_BASE +0x50 )))
#define  GMAC1_DMA_CH0_Control                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x0 )))
#define  GMAC1_DMA_CH0_Tx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x4 )))
#define  GMAC1_DMA_CH0_Rx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x8 )))
#define  GMAC1_DMA_CH0_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x10 )))
#define  GMAC1_DMA_CH0_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x14 )))
#define  GMAC1_DMA_CH0_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x18 )))
#define  GMAC1_DMA_CH0_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x1c )))
#define  GMAC1_DMA_CH0_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x20 )))
#define  GMAC1_DMA_CH0_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x28 )))
#define  GMAC1_DMA_CH0_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x2c )))
#define  GMAC1_DMA_CH0_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x30 )))
#define  GMAC1_DMA_CH0_Interrupt_Enable              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x34 )))
#define  GMAC1_DMA_CH0_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x38 )))
#define  GMAC1_DMA_CH0_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x3c )))
#define  GMAC1_DMA_CH0_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x44 )))
#define  GMAC1_DMA_CH0_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x4c )))
#define  GMAC1_DMA_CH0_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x54 )))
#define  GMAC1_DMA_CH0_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x5c )))
#define  GMAC1_DMA_CH0_Status                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x60 )))
#define  GMAC1_DMA_CH0_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x64 )))
#define  GMAC1_DMA_CH0_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH0_BASE +0x6c )))
#define  GMAC1_DMA_CH1_Control                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x0 )))
#define  GMAC1_DMA_CH1_Tx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x4 )))
#define  GMAC1_DMA_CH1_Rx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x8 )))
#define  GMAC1_DMA_CH1_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x10 )))
#define  GMAC1_DMA_CH1_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x14 )))
#define  GMAC1_DMA_CH1_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x18 )))
#define  GMAC1_DMA_CH1_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x1c )))
#define  GMAC1_DMA_CH1_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x20 )))
#define  GMAC1_DMA_CH1_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x28 )))
#define  GMAC1_DMA_CH1_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x2c )))
#define  GMAC1_DMA_CH1_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x30 )))
#define  GMAC1_DMA_CH1_Interrupt_Enable              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x34 )))
#define  GMAC1_DMA_CH1_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x38 )))
#define  GMAC1_DMA_CH1_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x3c )))
#define  GMAC1_DMA_CH1_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x44 )))
#define  GMAC1_DMA_CH1_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x4c )))
#define  GMAC1_DMA_CH1_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x54 )))
#define  GMAC1_DMA_CH1_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x5c )))
#define  GMAC1_DMA_CH1_Status                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x60 )))
#define  GMAC1_DMA_CH1_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x64 )))
#define  GMAC1_DMA_CH1_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH1_BASE +0x6c )))
#define  GMAC1_DMA_CH2_Control                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x0 )))
#define  GMAC1_DMA_CH2_Tx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x4 )))
#define  GMAC1_DMA_CH2_Rx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x8 )))
#define  GMAC1_DMA_CH2_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x10 )))
#define  GMAC1_DMA_CH2_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x14 )))
#define  GMAC1_DMA_CH2_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x18 )))
#define  GMAC1_DMA_CH2_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x1c )))
#define  GMAC1_DMA_CH2_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x20 )))
#define  GMAC1_DMA_CH2_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x28 )))
#define  GMAC1_DMA_CH2_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x2c )))
#define  GMAC1_DMA_CH2_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x30 )))
#define  GMAC1_DMA_CH2_Interrupt_Enable              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x34 )))
#define  GMAC1_DMA_CH2_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x38 )))
#define  GMAC1_DMA_CH2_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x3c )))
#define  GMAC1_DMA_CH2_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x44 )))
#define  GMAC1_DMA_CH2_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x4c )))
#define  GMAC1_DMA_CH2_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x54 )))
#define  GMAC1_DMA_CH2_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x5c )))
#define  GMAC1_DMA_CH2_Status                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x60 )))
#define  GMAC1_DMA_CH2_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x64 )))
#define  GMAC1_DMA_CH2_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH2_BASE +0x6c )))
#define  GMAC1_DMA_CH3_Control                       (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x0 )))
#define  GMAC1_DMA_CH3_Tx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x4 )))
#define  GMAC1_DMA_CH3_Rx_Control                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x8 )))
#define  GMAC1_DMA_CH3_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x10 )))
#define  GMAC1_DMA_CH3_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x14 )))
#define  GMAC1_DMA_CH3_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x18 )))
#define  GMAC1_DMA_CH3_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x1c )))
#define  GMAC1_DMA_CH3_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x20 )))
#define  GMAC1_DMA_CH3_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x28 )))
#define  GMAC1_DMA_CH3_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x2c )))
#define  GMAC1_DMA_CH3_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x30 )))
#define  GMAC1_DMA_CH3_Interrupt_Enable              (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x34 )))
#define  GMAC1_DMA_CH3_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x38 )))
#define  GMAC1_DMA_CH3_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x3c )))
#define  GMAC1_DMA_CH3_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x44 )))
#define  GMAC1_DMA_CH3_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x4c )))
#define  GMAC1_DMA_CH3_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x54 )))
#define  GMAC1_DMA_CH3_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x5c )))
#define  GMAC1_DMA_CH3_Status                        (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x60 )))
#define  GMAC1_DMA_CH3_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x64 )))
#define  GMAC1_DMA_CH3_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC1_DWC_EQOS_DMA_CH3_BASE +0x6c )))

#define  GMAC2_CTRL_MODE                             (*((volatile uint32_t *)(GMAC2_CTRL_BASE         +0x0 )))
#define  GMAC2_SPEED                                 (*((volatile uint32_t *)(GMAC2_CTRL_BASE         +0x4 )))
#define  GMAC2_TEIMESTAMPL                           (*((volatile uint32_t *)(GMAC2_CTRL_BASE         +0x8 )))
#define  GMAC2_TEIMESTAMPH                           (*((volatile uint32_t *)(GMAC2_CTRL_BASE         +0xC )))
#define  GMAC2_CLKCTRL                               (*((volatile uint32_t *)(GMAC2_CTRL_BASE         +0x10)))
#define  GMAC2_MAC_Configuration                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x0 )))
#define  GMAC2_MAC_Ext_Configuration                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4 )))
#define  GMAC2_MAC_Packet_Filter                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x8 )))
#define  GMAC2_MAC_Watchdog_Timeout                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc )))
#define  GMAC2_MAC_Hash_Table_Reg0                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x10 )))
#define  GMAC2_MAC_Hash_Table_Reg1                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x14 )))
#define  GMAC2_MAC_VLAN_Tag                          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x50 )))
#define  GMAC2_MAC_Q0_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x70 )))
#define  GMAC2_MAC_Q1_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x74 )))
#define  GMAC2_MAC_Q2_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x78 )))
#define  GMAC2_MAC_Q3_Tx_Flow_Ctrl                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x7c )))
#define  GMAC2_MAC_Rx_Flow_Ctrl                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x90 )))
#define  GMAC2_MAC_RxQ_Ctrl4                         (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x94 )))
#define  GMAC2_MAC_TxQ_Prty_Map0                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x98 )))
#define  GMAC2_MAC_RxQ_Ctrl0                         (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xa0 )))
#define  GMAC2_MAC_RxQ_Ctrl1                         (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xa4 )))
#define  GMAC2_MAC_RxQ_Ctrl2                         (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xa8 )))
#define  GMAC2_MAC_Interrupt_Status                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb0 )))
#define  GMAC2_MAC_Interrupt_Enable                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb4 )))
#define  GMAC2_MAC_Rx_Tx_Status                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb8 )))
#define  GMAC2_MAC_PMT_Control_Status                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc0 )))
#define  GMAC2_MAC_RWK_Packet_Filter                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter0123_Command                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter0123_Offset                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter01_CRC                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter0_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter1_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter23_CRC                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter2_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter3_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter4567_Command                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter4567_Offset                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter45_CRC                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter4_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter5_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter67_CRC                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter6_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_RWK_Filter7_Byte_Mask                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xc4 )))
#define  GMAC2_MAC_LPI_Control_Status                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xd0 )))
#define  GMAC2_MAC_LPI_Timers_Control                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xd4 )))
#define  GMAC2_MAC_LPI_Entry_Timer                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xd8 )))
#define  GMAC2_MAC_1US_Tic_Counter                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xdc )))
#define  GMAC2_MAC_PHYIF_Control_Status              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xf8 )))
#define  GMAC2_MAC_Version                           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x110 )))
#define  GMAC2_MAC_Debug                             (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x114 )))
#define  GMAC2_MAC_HW_Feature0                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x11c )))
#define  GMAC2_MAC_HW_Feature1                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x120 )))
#define  GMAC2_MAC_HW_Feature2                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x124 )))
#define  GMAC2_MAC_HW_Feature3                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x128 )))
#define  GMAC2_MAC_MDIO_Address                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x200 )))
#define  GMAC2_MAC_MDIO_Data                         (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x204 )))
#define  GMAC2_MAC_ARP_Address                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x210 )))
#define  GMAC2_MAC_CSR_SW_Ctrl                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x230 )))
#define  GMAC2_MAC_FPE_CTRL_STS                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x234 )))
#define  GMAC2_MAC_Ext_Cfg1                          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x238 )))
#define  GMAC2_MAC_Address0_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x300 )))
#define  GMAC2_MAC_Address0_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x304 )))
#define  GMAC2_MAC_Address1_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x308 )))
#define  GMAC2_MAC_Address1_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x30c )))
#define  GMAC2_MAC_Address2_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x310 )))
#define  GMAC2_MAC_Address2_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x314 )))
#define  GMAC2_MAC_Address3_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x318 )))
#define  GMAC2_MAC_Address3_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x31c )))
#define  GMAC2_MAC_Address4_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x320 )))
#define  GMAC2_MAC_Address4_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x324 )))
#define  GMAC2_MAC_Address5_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x328 )))
#define  GMAC2_MAC_Address5_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x32c )))
#define  GMAC2_MAC_Address6_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x330 )))
#define  GMAC2_MAC_Address6_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x334 )))
#define  GMAC2_MAC_Address7_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x338 )))
#define  GMAC2_MAC_Address7_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x33c )))
#define  GMAC2_MAC_Address8_High                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x340 )))
#define  GMAC2_MAC_Address8_Low                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x344 )))
#define  GMAC2_MAC_Address32_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x400 )))
#define  GMAC2_MAC_Address32_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x404 )))
#define  GMAC2_MAC_Address33_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x408 )))
#define  GMAC2_MAC_Address33_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x40c )))
#define  GMAC2_MAC_Address34_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x410 )))
#define  GMAC2_MAC_Address34_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x414 )))
#define  GMAC2_MAC_Address35_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x418 )))
#define  GMAC2_MAC_Address35_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x41c )))
#define  GMAC2_MAC_Address36_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x420 )))
#define  GMAC2_MAC_Address36_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x424 )))
#define  GMAC2_MAC_Address37_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x428 )))
#define  GMAC2_MAC_Address37_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x42c )))
#define  GMAC2_MAC_Address38_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x430 )))
#define  GMAC2_MAC_Address38_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x434 )))
#define  GMAC2_MAC_Address39_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x438 )))
#define  GMAC2_MAC_Address39_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x43c )))
#define  GMAC2_MAC_Address40_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x440 )))
#define  GMAC2_MAC_Address40_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x444 )))
#define  GMAC2_MAC_Address41_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x448 )))
#define  GMAC2_MAC_Address41_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x44c )))
#define  GMAC2_MAC_Address42_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x450 )))
#define  GMAC2_MAC_Address42_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x454 )))
#define  GMAC2_MAC_Address43_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x458 )))
#define  GMAC2_MAC_Address43_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x45c )))
#define  GMAC2_MAC_Address44_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x460 )))
#define  GMAC2_MAC_Address44_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x464 )))
#define  GMAC2_MAC_Address45_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x468 )))
#define  GMAC2_MAC_Address45_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x46c )))
#define  GMAC2_MAC_Address46_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x470 )))
#define  GMAC2_MAC_Address46_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x474 )))
#define  GMAC2_MAC_Address47_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x478 )))
#define  GMAC2_MAC_Address47_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x47c )))
#define  GMAC2_MAC_Address48_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x480 )))
#define  GMAC2_MAC_Address48_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x484 )))
#define  GMAC2_MAC_Address49_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x488 )))
#define  GMAC2_MAC_Address49_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x48c )))
#define  GMAC2_MAC_Address50_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x490 )))
#define  GMAC2_MAC_Address50_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x494 )))
#define  GMAC2_MAC_Address51_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x498 )))
#define  GMAC2_MAC_Address51_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x49c )))
#define  GMAC2_MAC_Address52_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4a0 )))
#define  GMAC2_MAC_Address52_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4a4 )))
#define  GMAC2_MAC_Address53_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4a8 )))
#define  GMAC2_MAC_Address53_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4ac )))
#define  GMAC2_MAC_Address54_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4b0 )))
#define  GMAC2_MAC_Address54_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4b4 )))
#define  GMAC2_MAC_Address55_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4b8 )))
#define  GMAC2_MAC_Address55_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4bc )))
#define  GMAC2_MAC_Address56_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4c0 )))
#define  GMAC2_MAC_Address56_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4c4 )))
#define  GMAC2_MAC_Address57_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4c8 )))
#define  GMAC2_MAC_Address57_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4cc )))
#define  GMAC2_MAC_Address58_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4d0 )))
#define  GMAC2_MAC_Address58_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4d4 )))
#define  GMAC2_MAC_Address59_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4d8 )))
#define  GMAC2_MAC_Address59_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4dc )))
#define  GMAC2_MAC_Address60_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4e0 )))
#define  GMAC2_MAC_Address60_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4e4 )))
#define  GMAC2_MAC_Address61_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4e8 )))
#define  GMAC2_MAC_Address61_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4ec )))
#define  GMAC2_MAC_Address62_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4f0 )))
#define  GMAC2_MAC_Address62_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4f4 )))
#define  GMAC2_MAC_Address63_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4f8 )))
#define  GMAC2_MAC_Address63_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x4fc )))
#define  GMAC2_MAC_Address64_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x500 )))
#define  GMAC2_MAC_Address64_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x504 )))
#define  GMAC2_MAC_Address65_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x508 )))
#define  GMAC2_MAC_Address65_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x50c )))
#define  GMAC2_MAC_Address66_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x510 )))
#define  GMAC2_MAC_Address66_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x514 )))
#define  GMAC2_MAC_Address67_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x518 )))
#define  GMAC2_MAC_Address67_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x51c )))
#define  GMAC2_MAC_Address68_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x520 )))
#define  GMAC2_MAC_Address68_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x524 )))
#define  GMAC2_MAC_Address69_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x528 )))
#define  GMAC2_MAC_Address69_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x52c )))
#define  GMAC2_MAC_Address70_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x530 )))
#define  GMAC2_MAC_Address70_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x534 )))
#define  GMAC2_MAC_Address71_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x538 )))
#define  GMAC2_MAC_Address71_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x53c )))
#define  GMAC2_MAC_Address72_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x540 )))
#define  GMAC2_MAC_Address72_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x544 )))
#define  GMAC2_MAC_Address73_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x548 )))
#define  GMAC2_MAC_Address73_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x54c )))
#define  GMAC2_MAC_Address74_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x550 )))
#define  GMAC2_MAC_Address74_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x554 )))
#define  GMAC2_MAC_Address75_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x558 )))
#define  GMAC2_MAC_Address75_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x55c )))
#define  GMAC2_MAC_Address76_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x560 )))
#define  GMAC2_MAC_Address76_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x564 )))
#define  GMAC2_MAC_Address77_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x568 )))
#define  GMAC2_MAC_Address77_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x56c )))
#define  GMAC2_MAC_Address78_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x570 )))
#define  GMAC2_MAC_Address78_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x574 )))
#define  GMAC2_MAC_Address79_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x578 )))
#define  GMAC2_MAC_Address79_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x57c )))
#define  GMAC2_MAC_Address80_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x580 )))
#define  GMAC2_MAC_Address80_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x584 )))
#define  GMAC2_MAC_Address81_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x588 )))
#define  GMAC2_MAC_Address81_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x58c )))
#define  GMAC2_MAC_Address82_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x590 )))
#define  GMAC2_MAC_Address82_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x594 )))
#define  GMAC2_MAC_Address83_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x598 )))
#define  GMAC2_MAC_Address83_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x59c )))
#define  GMAC2_MAC_Address84_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5a0 )))
#define  GMAC2_MAC_Address84_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5a4 )))
#define  GMAC2_MAC_Address85_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5a8 )))
#define  GMAC2_MAC_Address85_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5ac )))
#define  GMAC2_MAC_Address86_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5b0 )))
#define  GMAC2_MAC_Address86_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5b4 )))
#define  GMAC2_MAC_Address87_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5b8 )))
#define  GMAC2_MAC_Address87_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5bc )))
#define  GMAC2_MAC_Address88_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5c0 )))
#define  GMAC2_MAC_Address88_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5c4 )))
#define  GMAC2_MAC_Address89_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5c8 )))
#define  GMAC2_MAC_Address89_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5cc )))
#define  GMAC2_MAC_Address90_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5d0 )))
#define  GMAC2_MAC_Address90_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5d4 )))
#define  GMAC2_MAC_Address91_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5d8 )))
#define  GMAC2_MAC_Address91_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5dc )))
#define  GMAC2_MAC_Address92_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5e0 )))
#define  GMAC2_MAC_Address92_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5e4 )))
#define  GMAC2_MAC_Address93_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5e8 )))
#define  GMAC2_MAC_Address93_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5ec )))
#define  GMAC2_MAC_Address94_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5f0 )))
#define  GMAC2_MAC_Address94_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5f4 )))
#define  GMAC2_MAC_Address95_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5f8 )))
#define  GMAC2_MAC_Address95_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x5fc )))
#define  GMAC2_MAC_Address96_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x600 )))
#define  GMAC2_MAC_Address96_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x604 )))
#define  GMAC2_MAC_Address97_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x608 )))
#define  GMAC2_MAC_Address97_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x60c )))
#define  GMAC2_MAC_Address98_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x610 )))
#define  GMAC2_MAC_Address98_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x614 )))
#define  GMAC2_MAC_Address99_High                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x618 )))
#define  GMAC2_MAC_Address99_Low                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x61c )))
#define  GMAC2_MAC_Address100_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x620 )))
#define  GMAC2_MAC_Address100_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x624 )))
#define  GMAC2_MAC_Address101_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x628 )))
#define  GMAC2_MAC_Address101_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x62c )))
#define  GMAC2_MAC_Address102_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x630 )))
#define  GMAC2_MAC_Address102_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x634 )))
#define  GMAC2_MAC_Address103_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x638 )))
#define  GMAC2_MAC_Address103_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x63c )))
#define  GMAC2_MAC_Address104_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x640 )))
#define  GMAC2_MAC_Address104_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x644 )))
#define  GMAC2_MAC_Address105_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x648 )))
#define  GMAC2_MAC_Address105_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x64c )))
#define  GMAC2_MAC_Address106_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x650 )))
#define  GMAC2_MAC_Address106_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x654 )))
#define  GMAC2_MAC_Address107_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x658 )))
#define  GMAC2_MAC_Address107_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x65c )))
#define  GMAC2_MAC_Address108_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x660 )))
#define  GMAC2_MAC_Address108_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x664 )))
#define  GMAC2_MAC_Address109_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x668 )))
#define  GMAC2_MAC_Address109_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x66c )))
#define  GMAC2_MAC_Address110_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x670 )))
#define  GMAC2_MAC_Address110_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x674 )))
#define  GMAC2_MAC_Address111_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x678 )))
#define  GMAC2_MAC_Address111_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x67c )))
#define  GMAC2_MAC_Address112_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x680 )))
#define  GMAC2_MAC_Address112_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x684 )))
#define  GMAC2_MAC_Address113_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x688 )))
#define  GMAC2_MAC_Address113_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x68c )))
#define  GMAC2_MAC_Address114_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x690 )))
#define  GMAC2_MAC_Address114_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x694 )))
#define  GMAC2_MAC_Address115_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x698 )))
#define  GMAC2_MAC_Address115_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x69c )))
#define  GMAC2_MAC_Address116_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6a0 )))
#define  GMAC2_MAC_Address116_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6a4 )))
#define  GMAC2_MAC_Address117_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6a8 )))
#define  GMAC2_MAC_Address117_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6ac )))
#define  GMAC2_MAC_Address118_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6b0 )))
#define  GMAC2_MAC_Address118_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6b4 )))
#define  GMAC2_MAC_Address119_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6b8 )))
#define  GMAC2_MAC_Address119_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6bc )))
#define  GMAC2_MAC_Address120_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6c0 )))
#define  GMAC2_MAC_Address120_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6c4 )))
#define  GMAC2_MAC_Address121_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6c8 )))
#define  GMAC2_MAC_Address121_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6cc )))
#define  GMAC2_MAC_Address122_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6d0 )))
#define  GMAC2_MAC_Address122_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6d4 )))
#define  GMAC2_MAC_Address123_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6d8 )))
#define  GMAC2_MAC_Address123_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6dc )))
#define  GMAC2_MAC_Address124_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6e0 )))
#define  GMAC2_MAC_Address124_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6e4 )))
#define  GMAC2_MAC_Address125_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6e8 )))
#define  GMAC2_MAC_Address125_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6ec )))
#define  GMAC2_MAC_Address126_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6f0 )))
#define  GMAC2_MAC_Address126_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6f4 )))
#define  GMAC2_MAC_Address127_High                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6f8 )))
#define  GMAC2_MAC_Address127_Low                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x6fc )))
#define  GMAC2_MAC_L3_L4_Control0                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x900 )))
#define  GMAC2_MAC_Layer4_Address0                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x904 )))
#define  GMAC2_MAC_Layer3_Addr0_Reg0                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x910 )))
#define  GMAC2_MAC_Layer3_Addr1_Reg0                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x914 )))
#define  GMAC2_MAC_Layer3_Addr2_Reg0                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x918 )))
#define  GMAC2_MAC_Layer3_Addr3_Reg0                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x91c )))
#define  GMAC2_MAC_L3_L4_Control1                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x930 )))
#define  GMAC2_MAC_Layer4_Address1                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x934 )))
#define  GMAC2_MAC_Layer3_Addr0_Reg1                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x940 )))
#define  GMAC2_MAC_Layer3_Addr1_Reg1                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x944 )))
#define  GMAC2_MAC_Layer3_Addr2_Reg1                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x948 )))
#define  GMAC2_MAC_Layer3_Addr3_Reg1                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x94c )))
#define  GMAC2_MAC_L3_L4_Control2                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x960 )))
#define  GMAC2_MAC_Layer4_Address2                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x964 )))
#define  GMAC2_MAC_Layer3_Addr0_Reg2                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x970 )))
#define  GMAC2_MAC_Layer3_Addr1_Reg2                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x974 )))
#define  GMAC2_MAC_Layer3_Addr2_Reg2                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x978 )))
#define  GMAC2_MAC_Layer3_Addr3_Reg2                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x97c )))
#define  GMAC2_MAC_L3_L4_Control3                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x990 )))
#define  GMAC2_MAC_Layer4_Address3                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x994 )))
#define  GMAC2_MAC_Layer3_Addr0_Reg3                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9a0 )))
#define  GMAC2_MAC_Layer3_Addr1_Reg3                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9a4 )))
#define  GMAC2_MAC_Layer3_Addr2_Reg3                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9a8 )))
#define  GMAC2_MAC_Layer3_Addr3_Reg3                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9ac )))
#define  GMAC2_MAC_L3_L4_Control4                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9c0 )))
#define  GMAC2_MAC_Layer4_Address4                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9c4 )))
#define  GMAC2_MAC_Layer3_Addr0_Reg4                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9d0 )))
#define  GMAC2_MAC_Layer3_Addr1_Reg4                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9d4 )))
#define  GMAC2_MAC_Layer3_Addr2_Reg4                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9d8 )))
#define  GMAC2_MAC_Layer3_Addr3_Reg4                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0x9dc )))
#define  GMAC2_MAC_Timestamp_Control                 (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb00 )))
#define  GMAC2_MAC_Sub_Second_Increment              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb04 )))
#define  GMAC2_MAC_System_Time_Seconds               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb08 )))
#define  GMAC2_MAC_System_Time_Nanoseconds           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb0c )))
#define  GMAC2_MAC_System_Time_Seconds_Update        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb10 )))
#define  GMAC2_MAC_System_Time_Nanoseconds_Update    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb14 )))
#define  GMAC2_MAC_Timestamp_Addend                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb18 )))
#define  GMAC2_MAC_Timestamp_Status                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb20 )))
#define  GMAC2_MAC_Tx_Timestamp_Status_Nanoseconds   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb30 )))
#define  GMAC2_MAC_Tx_Timestamp_Status_Seconds       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb34 )))
#define  GMAC2_MAC_Timestamp_Ingress_Asym_Corr       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb50 )))
#define  GMAC2_MAC_Timestamp_Egress_Asym_Corr        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb54 )))
#define  GMAC2_MAC_Timestamp_Ingress_Corr_Nanosecond (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb58 )))
#define  GMAC2_MAC_Timestamp_Egress_Corr_Nanosecond  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb5c )))
#define  GMAC2_MAC_Timestamp_Ingress_Latency         (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb68 )))
#define  GMAC2_MAC_Timestamp_Egress_Latency          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb6c )))
#define  GMAC2_MAC_PPS_Control                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb70 )))
#define  GMAC2_MAC_PPS0_Target_Time_Seconds          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb80 )))
#define  GMAC2_MAC_PPS0_Target_Time_Nanoseconds      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MAC_BASE +0xb84 )))
#define  GMAC2_MTL_Operation_Mode                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x0 )))
#define  GMAC2_MTL_Interrupt_Status                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x20 )))
#define  GMAC2_MTL_RxQ_DMA_Map0                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x30 )))
#define  GMAC2_MTL_RxQ_DMA_Map1                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x34 )))
#define  GMAC2_MTL_TBS_CTRL                          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x40 )))
#define  GMAC2_MTL_EST_Control                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x50 )))
#define  GMAC2_MTL_EST_Status                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x58 )))
#define  GMAC2_MTL_EST_Sch_Error                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x60 )))
#define  GMAC2_MTL_EST_Frm_Size_Error                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x64 )))
#define  GMAC2_MTL_EST_Frm_Size_Capture              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x68 )))
#define  GMAC2_MTL_EST_Intr_Enable                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x70 )))
#define  GMAC2_MTL_EST_GCL_Control                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x80 )))
#define  GMAC2_MTL_EST_GCL_Data                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x84 )))
#define  GMAC2_MTL_FPE_CTRL_STS                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x90 )))
#define  GMAC2_MTL_FPE_Advance                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_BASE +0x94 )))
#define  GMAC2_MTL_TxQ0_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x0 )))
#define  GMAC2_MTL_TxQ0_Underflow                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x4 )))
#define  GMAC2_MTL_TxQ0_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x8 )))
#define  GMAC2_MTL_TxQ0_ETS_Status                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x14 )))
#define  GMAC2_MTL_TxQ0_Quantum_Weight               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x18 )))
#define  GMAC2_MTL_Q0_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x2c )))
#define  GMAC2_MTL_RxQ0_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x30 )))
#define  GMAC2_MTL_RxQ0_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x34 )))
#define  GMAC2_MTL_RxQ0_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x38 )))
#define  GMAC2_MTL_RxQ0_Control                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q0_BASE +0x3c )))
#define  GMAC2_MTL_TxQ1_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x0 )))
#define  GMAC2_MTL_TxQ1_Underflow                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x4 )))
#define  GMAC2_MTL_TxQ1_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x8 )))
#define  GMAC2_MTL_TxQ1_ETS_Status                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x14 )))
#define  GMAC2_MTL_TxQ1_Quantum_Weight               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x18 )))
#define  GMAC2_MTL_Q1_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x2c )))
#define  GMAC2_MTL_RxQ1_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x30 )))
#define  GMAC2_MTL_RxQ1_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x34 )))
#define  GMAC2_MTL_RxQ1_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x38 )))
#define  GMAC2_MTL_RxQ1_Control                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q1_BASE +0x3c )))
#define  GMAC2_MTL_TxQ2_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x0 )))
#define  GMAC2_MTL_TxQ2_Underflow                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x4 )))
#define  GMAC2_MTL_TxQ2_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x8 )))
#define  GMAC2_MTL_TxQ2_ETS_Status                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x14 )))
#define  GMAC2_MTL_TxQ2_Quantum_Weight               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x18 )))
#define  GMAC2_MTL_Q2_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x2c )))
#define  GMAC2_MTL_RxQ2_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x30 )))
#define  GMAC2_MTL_RxQ2_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x34 )))
#define  GMAC2_MTL_RxQ2_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x38 )))
#define  GMAC2_MTL_RxQ2_Control                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q2_BASE +0x3c )))
#define  GMAC2_MTL_TxQ3_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x0 )))
#define  GMAC2_MTL_TxQ3_Underflow                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x4 )))
#define  GMAC2_MTL_TxQ3_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x8 )))
#define  GMAC2_MTL_TxQ3_ETS_Control                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x10 )))
#define  GMAC2_MTL_TxQ3_ETS_Status                   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x14 )))
#define  GMAC2_MTL_TxQ3_Quantum_Weight               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x18 )))
#define  GMAC2_MTL_TxQ3_SendSlopeCredit              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x1c )))
#define  GMAC2_MTL_TxQ3_HiCredit                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x20 )))
#define  GMAC2_MTL_TxQ3_LoCredit                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x24 )))
#define  GMAC2_MTL_Q3_Interrupt_Control_Status       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x2c )))
#define  GMAC2_MTL_RxQ3_Operation_Mode               (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x30 )))
#define  GMAC2_MTL_RxQ3_Missed_Packet_Overflow_Cnt   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x34 )))
#define  GMAC2_MTL_RxQ3_Debug                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x38 )))
#define  GMAC2_MTL_RxQ3_Control                      (*((volatile uint32_t *)(GMAC2_DWC_EQOS_MTL_Q3_BASE +0x3c )))
#define  GMAC2_DMA_Mode                              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_BASE +0x0 )))
#define  GMAC2_DMA_SysBus_Mode                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_BASE +0x4 )))
#define  GMAC2_DMA_Interrupt_Status                  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_BASE +0x8 )))
#define  GMAC2_DMA_Debug_Status0                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_BASE +0xc )))
#define  GMAC2_DMA_Debug_Status1                     (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_BASE +0x10 )))
#define  GMAC2_AXI_LPI_Entry_Interval                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_BASE +0x40 )))
#define  GMAC2_DMA_TBS_CTRL                          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_BASE +0x50 )))
#define  GMAC2_DMA_CH0_Control                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x0 )))
#define  GMAC2_DMA_CH0_Tx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x4 )))
#define  GMAC2_DMA_CH0_Rx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x8 )))
#define  GMAC2_DMA_CH0_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x10 )))
#define  GMAC2_DMA_CH0_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x14 )))
#define  GMAC2_DMA_CH0_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x18 )))
#define  GMAC2_DMA_CH0_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x1c )))
#define  GMAC2_DMA_CH0_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x20 )))
#define  GMAC2_DMA_CH0_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x28 )))
#define  GMAC2_DMA_CH0_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x2c )))
#define  GMAC2_DMA_CH0_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x30 )))
#define  GMAC2_DMA_CH0_Interrupt_Enable              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x34 )))
#define  GMAC2_DMA_CH0_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x38 )))
#define  GMAC2_DMA_CH0_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x3c )))
#define  GMAC2_DMA_CH0_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x44 )))
#define  GMAC2_DMA_CH0_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x4c )))
#define  GMAC2_DMA_CH0_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x54 )))
#define  GMAC2_DMA_CH0_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x5c )))
#define  GMAC2_DMA_CH0_Status                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x60 )))
#define  GMAC2_DMA_CH0_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x64 )))
#define  GMAC2_DMA_CH0_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH0_BASE +0x6c )))
#define  GMAC2_DMA_CH1_Control                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x0 )))
#define  GMAC2_DMA_CH1_Tx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x4 )))
#define  GMAC2_DMA_CH1_Rx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x8 )))
#define  GMAC2_DMA_CH1_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x10 )))
#define  GMAC2_DMA_CH1_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x14 )))
#define  GMAC2_DMA_CH1_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x18 )))
#define  GMAC2_DMA_CH1_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x1c )))
#define  GMAC2_DMA_CH1_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x20 )))
#define  GMAC2_DMA_CH1_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x28 )))
#define  GMAC2_DMA_CH1_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x2c )))
#define  GMAC2_DMA_CH1_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x30 )))
#define  GMAC2_DMA_CH1_Interrupt_Enable              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x34 )))
#define  GMAC2_DMA_CH1_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x38 )))
#define  GMAC2_DMA_CH1_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x3c )))
#define  GMAC2_DMA_CH1_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x44 )))
#define  GMAC2_DMA_CH1_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x4c )))
#define  GMAC2_DMA_CH1_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x54 )))
#define  GMAC2_DMA_CH1_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x5c )))
#define  GMAC2_DMA_CH1_Status                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x60 )))
#define  GMAC2_DMA_CH1_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x64 )))
#define  GMAC2_DMA_CH1_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH1_BASE +0x6c )))
#define  GMAC2_DMA_CH2_Control                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x0 )))
#define  GMAC2_DMA_CH2_Tx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x4 )))
#define  GMAC2_DMA_CH2_Rx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x8 )))
#define  GMAC2_DMA_CH2_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x10 )))
#define  GMAC2_DMA_CH2_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x14 )))
#define  GMAC2_DMA_CH2_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x18 )))
#define  GMAC2_DMA_CH2_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x1c )))
#define  GMAC2_DMA_CH2_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x20 )))
#define  GMAC2_DMA_CH2_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x28 )))
#define  GMAC2_DMA_CH2_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x2c )))
#define  GMAC2_DMA_CH2_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x30 )))
#define  GMAC2_DMA_CH2_Interrupt_Enable              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x34 )))
#define  GMAC2_DMA_CH2_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x38 )))
#define  GMAC2_DMA_CH2_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x3c )))
#define  GMAC2_DMA_CH2_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x44 )))
#define  GMAC2_DMA_CH2_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x4c )))
#define  GMAC2_DMA_CH2_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x54 )))
#define  GMAC2_DMA_CH2_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x5c )))
#define  GMAC2_DMA_CH2_Status                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x60 )))
#define  GMAC2_DMA_CH2_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x64 )))
#define  GMAC2_DMA_CH2_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH2_BASE +0x6c )))
#define  GMAC2_DMA_CH3_Control                       (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x0 )))
#define  GMAC2_DMA_CH3_Tx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x4 )))
#define  GMAC2_DMA_CH3_Rx_Control                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x8 )))
#define  GMAC2_DMA_CH3_TxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x10 )))
#define  GMAC2_DMA_CH3_TxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x14 )))
#define  GMAC2_DMA_CH3_RxDesc_List_HAddress          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x18 )))
#define  GMAC2_DMA_CH3_RxDesc_List_Address           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x1c )))
#define  GMAC2_DMA_CH3_TxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x20 )))
#define  GMAC2_DMA_CH3_RxDesc_Tail_Pointer           (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x28 )))
#define  GMAC2_DMA_CH3_TxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x2c )))
#define  GMAC2_DMA_CH3_RxDesc_Ring_Length            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x30 )))
#define  GMAC2_DMA_CH3_Interrupt_Enable              (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x34 )))
#define  GMAC2_DMA_CH3_Rx_Interrupt_Watchdog_Timer   (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x38 )))
#define  GMAC2_DMA_CH3_Slot_Function_Control_Status  (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x3c )))
#define  GMAC2_DMA_CH3_Current_App_TxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x44 )))
#define  GMAC2_DMA_CH3_Current_App_RxDesc            (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x4c )))
#define  GMAC2_DMA_CH3_Current_App_TxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x54 )))
#define  GMAC2_DMA_CH3_Current_App_RxBuffer          (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x5c )))
#define  GMAC2_DMA_CH3_Status                        (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x60 )))
#define  GMAC2_DMA_CH3_Miss_Frame_Cnt                (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x64 )))
#define  GMAC2_DMA_CH3_RX_ERI_Cnt                    (*((volatile uint32_t *)(GMAC2_DWC_EQOS_DMA_CH3_BASE +0x6c )))



#endif
