//******************** (C) COPYRIGHT 2019 SmartLogic*******************************
// FileName           : dw_apb_gpio.h
// Author             : lijian, jian.li@smartlogictech.com
// Date First Issued  : 2019-03-29 03:39:50 PM
// Last Modified      : 2020-05-13 10:20:01 AM
// Description        :
// ------------------------------------------------------------
// Modification History:
// Version    Date       Author    Modification Description
//
//**********************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__

#define GPIO0_A29_PINMUX_REG_ADDR	0x04458180
#define PB14_CTRL_REG_ADDR			0x044580BC	// PB14_CTRL_REG

#define RF_LVDS_PMUX0_REG_ADDR      0x04DA0094
#define RF_LVDS_PMUX1_REG_ADDR		0x04DA0098

#define GPIO0A_DATA_REG_ADDR		0x04450000
#define GPIO0A_DIR_REG_ADDR			0x04450004

#define GPIO0B_DATA_REG_ADDR		0x0445000C
#define GPIO0B_DIR_REG_ADDR			0x04450010

#define GPIO1A_DATA_REG_ADDR		0x04D10000
#define GPIO1A_DIR_REG_ADDR			0x04D10004

#define GPIO1B_DATA_REG_ADDR		0x04D1000C
#define GPIO1B_DIR_REG_ADDR			0x04D10010
#define GPIO1B_EXT_REG_ADDR			0x04D10054

#define DW_APB_GPIO0_BASE 0x04450000
#define DW_APB_GPIO1_BASE 0x04d10000
#define GPIO_SWPORTA_DR_OFFSET    0x00
#define GPIO_SWPORTA_DDR_OFFSET   0x04
#define GPIO_SWPORTA_CTL_OFFSET   0x08
#define GPIO_SWPORTB_DR_OFFSET    0x0C
#define GPIO_SWPORTB_DDR_OFFSET   0x10
#define GPIO_SWPORTB_CTL_OFFSET   0x14
#define GPIO_SWPORTC_DR_OFFSET    0x18
#define GPIO_SWPORTC_DDR_OFFSET   0x1C
#define GPIO_SWPORTC_CTL_OFFSET   0x20
#define GPIO_SWPORTD_DR_OFFSET    0x24
#define GPIO_SWPORTD_DDR_OFFSET   0x28
#define GPIO_SWPORTD_CTL_OFFSET   0x2C
#define GPIO_INTEN_OFFSET         0x30
#define GPIO_INTMASK_OFFSET       0x34
#define GPIO_INTTYPE_LEVEL_OFFSET 0x38
#define GPIO_INT_POLARITY_OFFSET  0x3C
#define GPIO_INTSTATUS_OFFSET     0x40
#define GPIO_RAW_INTSTATUS_OFFSET 0x44
#define GPIO_DEBOUNCE_OFFSET      0x48
#define GPIO_PORTA_EOI_OFFSET     0x4C
#define GPIO_EXT_PORTA_OFFSET     0x50
#define GPIO_EXT_PORTB_OFFSET     0x54
#define GPIO_EXT_PORTC_OFFSET     0x58
#define GPIO_EXT_PORTD_OFFSET     0x5C
#define GPIO_LS_SYNC_OFFSET       0x60
#define GPIO_ID_CODE_OFFSET       0x64
#define GPIO_VER_ID_CODE_OFFSET   0x6C
#define GPIO_CONFIGID_REG2_OFFSET 0x70
#define GPIO_CONFIGID_REG1_OFFSET 0x74

#define GPIO0_SWPORTA_DR       (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTA_DR_OFFSET)))
#define GPIO0_SWPORTA_DDR      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTA_DDR_OFFSET)))
#define GPIO0_SWPORTA_CTL      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTA_CTL_OFFSET)))
#define GPIO0_SWPORTB_DR       (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTB_DR_OFFSET)))
#define GPIO0_SWPORTB_DDR      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTB_DDR_OFFSET)))
#define GPIO0_SWPORTB_CTL      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTB_CTL_OFFSET)))
#define GPIO0_SWPORTC_DR       (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTC_DR_OFFSET)))
#define GPIO0_SWPORTC_DDR      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTC_DDR_OFFSET)))
#define GPIO0_SWPORTC_CTL      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTC_CTL_OFFSET)))
#define GPIO0_SWPORTD_DR       (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTD_DR_OFFSET)))
#define GPIO0_SWPORTD_DDR      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTD_DDR_OFFSET)))
#define GPIO0_SWPORTD_CTL      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_SWPORTD_CTL_OFFSET)))
#define GPIO0_INTEN            (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_INTEN_OFFSET)))
#define GPIO0_INTMASK          (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_INTMASK_OFFSET)))
#define GPIO0_INTTYPE_LEVEL    (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_INTTYPE_LEVEL_OFFSET)))
#define GPIO0_INT_POLARITY     (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_INT_POLARITY_OFFSET)))
#define GPIO0_INTSTATUS        (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_INTSTATUS_OFFSET)))
#define GPIO0_RAW_INTSTATUS    (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_RAW_INTSTATUS_OFFSET)))
#define GPIO0_DEBOUNCE         (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_DEBOUNCE_OFFSET)))
#define GPIO0_PORTA_EOI        (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_PORTA_EOI_OFFSET)))
#define GPIO0_EXT_PORTA        (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_EXT_PORTA_OFFSET)))
#define GPIO0_EXT_PORTB        (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_EXT_PORTB_OFFSET)))
#define GPIO0_EXT_PORTC        (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_EXT_PORTC_OFFSET)))
#define GPIO0_EXT_PORTD        (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_EXT_PORTD_OFFSET)))
#define GPIO0_LS_SYNC          (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_LS_SYNC_OFFSET)))
#define GPIO0_ID_CODE          (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_ID_CODE_OFFSET)))
#define GPIO0_VER_ID_CODE      (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_VER_ID_CODE_OFFSET)))
#define GPIO0_CONFIGID_REG2    (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_CONFIGID_REG2_OFFSET)))
#define GPIO0_CONFIGID_REG1    (*((volatile UINT32 *)(DW_APB_GPIO0_BASE  + GPIO_CONFIGID_REG1_OFFSET)))
#define GPIO0PING_1BIT_WR      (GPIO0_SWPORTA_DR)
#define GPIO1_SWPORTA_DR       (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTA_DR_OFFSET)))
#define GPIO1_SWPORTA_DDR      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTA_DDR_OFFSET)))
#define GPIO1_SWPORTA_CTL      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTA_CTL_OFFSET)))
#define GPIO1_SWPORTB_DR       (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTB_DR_OFFSET)))
#define GPIO1_SWPORTB_DDR      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTB_DDR_OFFSET)))
#define GPIO1_SWPORTB_CTL      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTB_CTL_OFFSET)))
#define GPIO1_SWPORTC_DR       (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTC_DR_OFFSET)))
#define GPIO1_SWPORTC_DDR      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTC_DDR_OFFSET)))
#define GPIO1_SWPORTC_CTL      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTC_CTL_OFFSET)))
#define GPIO1_SWPORTD_DR       (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTD_DR_OFFSET)))
#define GPIO1_SWPORTD_DDR      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTD_DDR_OFFSET)))
#define GPIO1_SWPORTD_CTL      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_SWPORTD_CTL_OFFSET)))
#define GPIO1_INTEN            (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_INTEN_OFFSET)))
#define GPIO1_INTMASK          (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_INTMASK_OFFSET)))
#define GPIO1_INTTYPE_LEVEL    (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_INTTYPE_LEVEL_OFFSET)))
#define GPIO1_INT_POLARITY     (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_INT_POLARITY_OFFSET)))
#define GPIO1_INTSTATUS        (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_INTSTATUS_OFFSET)))
#define GPIO1_RAW_INTSTATUS    (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_RAW_INTSTATUS_OFFSET)))
#define GPIO1_DEBOUNCE         (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_DEBOUNCE_OFFSET)))
#define GPIO1_PORTA_EOI        (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_PORTA_EOI_OFFSET)))
#define GPIO1_EXT_PORTA        (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_EXT_PORTA_OFFSET)))
#define GPIO1_EXT_PORTB        (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_EXT_PORTB_OFFSET)))
#define GPIO1_EXT_PORTC        (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_EXT_PORTC_OFFSET)))
#define GPIO1_EXT_PORTD        (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_EXT_PORTD_OFFSET)))
#define GPIO1_LS_SYNC          (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_LS_SYNC_OFFSET)))
#define GPIO1_ID_CODE          (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_ID_CODE_OFFSET)))
#define GPIO1_VER_ID_CODE      (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_VER_ID_CODE_OFFSET)))
#define GPIO1_CONFIGID_REG2    (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_CONFIGID_REG2_OFFSET)))
#define GPIO1_CONFIGID_REG1    (*((volatile UINT32 *)(DW_APB_GPIO1_BASE  + GPIO_CONFIGID_REG1_OFFSET)))
#define GPIO1PING_1BIT_WR      (GPIO1_SWPORTA_DR)


#define CC_GPIO_ADD_ENCODED_PARAM            0x1
#define CC_GPIO_APB_DATA_WIDTH               32
#define CC_GPIO_NUM_PORTS                    4
#define CC_GPIO_ID                           0
#define CC_GPIO_DEBOUNCE                     0
#define CC_GPIO_ID_WIDTH                     32
#define CC_GPIO_ID_NUM                       0x0
#define CC_GPIO_REV_ID                       0
#define CC_GPIO_REV_ID_WIDTH                 32
#define CC_GPIO_REV_ID_NUM                   0x0
#define CC_GPIO_PWIDTH_A                     8
#define CC_GPIO_PORTA_SINGLE_CTL             1
#define CC_GPIO_SWPORTA_RESET                0x0
#define CC_GPIO_HW_PORTA                     1
#define CC_GPIO_DFLT_DIR_A                   0
#define CC_GPIO_DFLT_SRC_A                   0
#define CC_GPIO_PORTA_INTR                   1
#define CC_GPIO_INT_POL                      0
#define CC_GPIO_INTR_IO                      0
#define CC_GPIO_PA_SYNC_EXT_DATA             1
#define CC_GPIO_PA_SYNC_INTERRUPTS           1
#define CC_GPIO_PWIDTH_B                     32
#define CC_GPIO_PORTB_SINGLE_CTL             1
#define CC_GPIO_SWPORTB_RESET                0x0
#define CC_GPIO_HW_PORTB                     0
#define CC_GPIO_DFLT_DIR_B                   0
#define CC_GPIO_DFLT_SRC_B                   0
#define CC_GPIO_PB_SYNC_EXT_DATA             1
#define CC_GPIO_PWIDTH_C                     32
#define CC_GPIO_PORTC_SINGLE_CTL             1
#define CC_GPIO_SWPORTC_RESET                0x0
#define CC_GPIO_HW_PORTC                     0
#define CC_GPIO_DFLT_DIR_C                   1
#define CC_GPIO_DFLT_SRC_C                   0
#define CC_GPIO_PC_SYNC_EXT_DATA             0
#define CC_GPIO_PWIDTH_D                     8
#define CC_GPIO_PORTD_SINGLE_CTL             1
#define CC_GPIO_SWPORTD_RESET                0x0
#define CC_GPIO_HW_PORTD                     1
#define CC_GPIO_DFLT_DIR_D                   1
#define CC_GPIO_DFLT_SRC_D                   1
#define CC_GPIO_PD_SYNC_EXT_DATA             1

#define GPIO_Pin_0                 (0x00000001)  /*!< Pin 0 selected */
#define GPIO_Pin_1                 (0x00000002)  /*!< Pin 1 selected */
#define GPIO_Pin_2                 (0x00000004)  /*!< Pin 2 selected */
#define GPIO_Pin_3                 (0x00000008)  /*!< Pin 3 selected */
#define GPIO_Pin_4                 (0x00000010)  /*!< Pin 4 selected */
#define GPIO_Pin_5                 (0x00000020)  /*!< Pin 5 selected */
#define GPIO_Pin_6                 (0x00000040)  /*!< Pin 6 selected */
#define GPIO_Pin_7                 (0x00000080)  /*!< Pin 7 selected */
#define GPIO_Pin_8                 (0x00000100)  /*!< Pin 8 selected */
#define GPIO_Pin_9                 (0x00000200)  /*!< Pin 9 selected */
#define GPIO_Pin_10                (0x00000400)  /*!< Pin 10 selected */
#define GPIO_Pin_11                (0x00000800)  /*!< Pin 11 selected */
#define GPIO_Pin_12                (0x00001000)  /*!< Pin 12 selected */
#define GPIO_Pin_13                (0x00002000)  /*!< Pin 13 selected */
#define GPIO_Pin_14                (0x00004000)  /*!< Pin 14 selected */
#define GPIO_Pin_15                (0x00008000)  /*!< Pin 15 selected */
#define GPIO_Pin_16                (0x00010000)  /*!< Pin 16 selected */
#define GPIO_Pin_17                (0x00020000)  /*!< Pin 17 selected */
#define GPIO_Pin_18                (0x00040000)  /*!< Pin 18 selected */
#define GPIO_Pin_19                (0x00080000)  /*!< Pin 19 selected */
#define GPIO_Pin_20                (0x00100000)  /*!< Pin 20 selected */
#define GPIO_Pin_21                (0x00200000)  /*!< Pin 21 selected */
#define GPIO_Pin_22                (0x00400000)  /*!< Pin 22 selected */
#define GPIO_Pin_23                (0x00800000)  /*!< Pin 23 selected */
#define GPIO_Pin_24                (0x01000000)  /*!< Pin 24 selected */
#define GPIO_Pin_25                (0x02000000)  /*!< Pin 25 selected */
#define GPIO_Pin_26                (0x04000000)  /*!< Pin 26 selected */
#define GPIO_Pin_27                (0x08000000)  /*!< Pin 27 selected */
#define GPIO_Pin_28                (0x10000000)  /*!< Pin 28 selected */
#define GPIO_Pin_29                (0x20000000)  /*!< Pin 29 selected */
#define GPIO_Pin_30                (0x40000000)  /*!< Pin 30 selected */
#define GPIO_Pin_31                (0x80000000)  /*!< Pin 31 selected */
#define GPIO_Pin_All               (0xFFFFFFFF)  /*!< All pins selected */


#endif
