/******************************************************************
 * @file  Fphy_Timer_Csu_Config.s.c
 * @brief:    [file description] 
 * @author: guicheng.liu
 * @Date 2022年7月7日
 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
 * Change_date         Owner         Change_content
 * 2022年7月7日        guicheng.liu       create file

*****************************************************************/

/**************************include******************************/
//#include "type_define.h"
//#include "lte_common.h"
//#include "log_interface.h"
//#include "phy_timer_csu_config.h"
//#include "ecs_common.h"
#include "nr_mem_def.h"
#include "phy_timer_csu_config.h"
#include "cpri_csu_api.h"
//#include "cpri_csu_nr_7ds2u.h"


//#include "rfm_interface.h"

/**************************function******************************/
phy_csu_link_info_t g_phy_csu_link;

/*!   
* @brief:  Jesd 参数的初始化
* @author:  guicheng.liu
* @Date:  2022年7月7日
*/
void Phy_Timer_Csu_Init()
{
    //tx的链表地址
    g_phy_csu_link.tx0_even_f7_link_addr     = CPRI_LINK_START_ADDR; // 0x721E800;
    g_phy_csu_link.tx0_even_b7_link_addr     = CPRI_LINK_START_ADDR + 1*0x200; // 0x721EA00;
    g_phy_csu_link.tx0_odd_f7_link_addr      = CPRI_LINK_START_ADDR + 2*0x200; // 0x721EC00;
    g_phy_csu_link.tx0_odd_b7_link_addr      = CPRI_LINK_START_ADDR + 3*0x200; // 0x721EE00;
    g_phy_csu_link.tx0_s_link_addr           = CPRI_LINK_START_ADDR + 4*0x200; // 0x721F000;
    g_phy_csu_link.tx0_1st_dummy_link_addr   = CPRI_LINK_START_ADDR + 5*0x200; // 0x721F200;
    g_phy_csu_link.tx0_2nd_dummy_link_addr   = CPRI_LINK_START_ADDR + 6*0x200; // 0x721F400;

    //rx的链表地址
    g_phy_csu_link.rx0_1st_dummy_link_addr   = CPRI_LINK_START_ADDR + 7*0x200; // 0x721F600;
    g_phy_csu_link.rx0_2nd_dummy_link_addr   = CPRI_LINK_START_ADDR + 8*0x200; // 0x721F800;
    g_phy_csu_link.rx0_s_link_addr           = CPRI_LINK_START_ADDR + 9*0x200; // 0x721FA00;
    g_phy_csu_link.rx0_normal0_link_addr     = CPRI_LINK_START_ADDR + 10*0x200; // 0x721FC00;
    g_phy_csu_link.rx0_normal1_link_addr     = CPRI_LINK_START_ADDR + 11*0x200; // 0x721FE00;
    g_phy_csu_link.rx0_normal2_link_addr     = CPRI_LINK_START_ADDR + 12*0x200; // 0x7220000;
}

/*!   
* @brief:  CPRI CSU初始化
* @author:  guicheng.liu
* @Date:  2023年2月2日
*/
void Cpri_Csu_Init()
{
    uint32_t fifo_num = 4;//初始化4个FIFO通道(RX_AXC_DATA:CmdFIFO0, RX_AXC_CTRL:CmdFIFO2, TX_AXC_DATA:CmdFIFO1, TX_AXC_CTRL:CmdFIFO3)
    uint32_t dma_reg_group_num = 32;//清空CPRI的32组DMA参数寄存器
    uint32_t tag_mask = 0xFFFFFFFF;//DMA TAG全部不屏蔽

    UCP_API_CPRI_CSU_Init(fifo_num, dma_reg_group_num, tag_mask);
}

 /*!   
 * @brief:  
 * @author:  guicheng.liu
 * @Date:  2023年3月16日
 * @param: axc_id_num :       [param description ]
 * @param: rx_cycle_num :     [param description ]
 */
void Cpri_Csu_Latch_Init(uint32_t axc_id_num, uint32_t in_latch_num, uint32_t out_latch_num, uint32_t rx_cycle_num)
{
    uint32_t index = 0;
    //uint32_t axc_id_num = 5; //1个指数因子,4个天线(暂时不支持AGC因子)
    uint32_t tx0_rfp_set= 0;//[18:16]TX_AXC_DATA 通道开始工作后，提前发送的 Base Frame 的个数[8] 0:上升沿敏感 1: 高电平敏感
                            //[7:0]CSU捕捉到CPRI 端接口信号TX_AUX_CNT_POS 第一次为此数值后,延迟2个CSU                   的主时钟周期再次启动发送数据的工作
    uint32_t tx0_port_info[64] = {0};//共64个port, 
                        			//[31:26] CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的 ID 值
                        			//[25:20]CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的每拍有效比特数
                        			//[19:1]CPRI 模式 CSU 的 TX_AXC_DATA通道一个Basic Frame 中端口x的总比特数
                        			//[0]0:比特反序未使能 1:比特反序使能
    uint32_t tx0_latch_info_l[8] = {0}; //8个latch info配置，[24]bit_revert_enable 
                                        //[19:0]CPRI模式CSU的TX_AXC_DATA通道的OutLatch参数,     值为一个Basic Frame中在此OutLatch中缓存的所有端口的总比特数

    uint32_t tx0_latch_info_m[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*3  
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N
    uint32_t tx0_latch_info_h[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*7
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*5

    uint32_t rx0_port_info[64] = {0};//共64个port, [27:22]bit_number_one_cyclex [20:1]bit_number_one_basic_framex [0]bit_revert_enable
    uint32_t rx0_latch_info_l[8] = {0};//8个latch info配置，[24]bit_revert_enable  [19:0]bit_number_one_basic_frame
    uint32_t rx0_latch_info_h[8] = {0};//8个latch info配置，
                            			//[31]cpri_latch_n_7_times_bigger_than_128 =0： CPRI_LATCH_N*7 不大于 128, =1： CPRI_LATCH_N*7 大于 128
                            			//[30:24]cpri_latch_n_7_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*7
                            			//[23]cpri_latch_n_5_times_bigger_than_128  0： CPRI_LATCH_N*5 不大于 128, 1： CPRI_LATCH_N*5 大于 128
                            			//[22:16]cpri_latch_n_5_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*5
                            			//[15]cpri_latch_n_3_times_bigger_than_128  0： CPRI_LATCH_N*3 不大于 128, 1： CPRI_LATCH_N*3 大于 128
                            			//[14:8]cpri_latch_n_3_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*3
                            			//[6:0]cpri_latch_n
	uint32_t rx0_cycle_num[8] = {0};//8个latch info配置,
	                                //[7:0]CPRI模式CSU的RX_AXC_DATA通道的InLatch参数,值为该InLatch中连续接收的Basic Frame的个数减一
    uint32_t inlatch_index = 0;
    //uint32_t rx_cycle_num = 32;
	uint32_t bit_per_bf[11] = {16,16,512,512,512,512,512,512,512,512,32};  //压缩因子是2个2byte, 16bit, 数据是64byte*2(2天线交织),1024bit, 
                                                            // agc:2小区交织使用同一port,4byte,32bit
    uint32_t bit_per_cycle[11] = {16,16,0,0,0,0,0,0,0,0,32}; //0:表示64, 非0:有效比特数为数值本身

    uint32_t bit_per_bf_for_latch[7] = {16,16,1024,1024,1024,1024,32};  //压缩因子是2个2byte, 16bit, 数据是64byte*2(2天线交织),1024bit, 
                                                            // agc:2小区交织使用同一port,4byte,32bit

    for (index = 0; index < axc_id_num; index++)
    {
        //tx0_port_info[index] = ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));     
		tx0_port_info[index] = 0x1 | ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));//bit反序使能
    }

    for (index = 0; index < out_latch_num; index++)
    {
	    tx0_latch_info_l[index] = (0x1<<24ul) | bit_per_bf_for_latch[index];//bit反序使能
	    tx0_latch_info_m[index] = 0x180008;//CPRI_LATCH_N??bit反序??
	    tx0_latch_info_h[index] = 0x380028;
    }
    tx0_rfp_set = 0x40001;//RfpPoint=0x1 can send 4//push 4 basic frame at 1st tx_axc_rfp

    UCP_API_CPRI_CSU_TxOutLatch_Cfg(axc_id_num, 
                                    tx0_rfp_set, 
                                    tx0_port_info, 
                                    out_latch_num,
                                    tx0_latch_info_l, 
                                    tx0_latch_info_m, 
                                    tx0_latch_info_h);

    for (index = 0; index < axc_id_num; index++)
    {
        rx0_port_info[index] =  0x1 | ((bit_per_bf[index]<<1)|(bit_per_cycle[index]<<22));//bit反序使能
    }

    for (index = 0; index < in_latch_num; index++)
    {
        rx0_latch_info_l[index] =  (0x1<<24ul) | bit_per_bf_for_latch[index];
        rx0_latch_info_h[index] =  0x38281808;
        rx0_cycle_num[index] = rx_cycle_num - 1;
    }

    UCP_API_CPRI_CSU_RxInLatch_Cfg(axc_id_num,
                                    rx0_port_info,
                                    in_latch_num,
                                    rx0_latch_info_l,
                                    rx0_latch_info_h,
                                    rx0_cycle_num);

    UCP_API_CPRI_CSU_RxInLatchThres_Cfg(inlatch_index,
                                        1,//w_r_flag,
                                        0x10,//send_threshold,
                                        0x40);//almostfull_threshold);

    //先去使能
	UCP_API_CPRI_CSU_TXAxcData_ChannelCtrl(0, axc_id_num, out_latch_num);
	UCP_API_CPRI_CSU_RXAxcData_ChannelCtrl(0, in_latch_num);
}


 /*!   
 * @brief:  
 * @author:  guicheng.liu
 * @Date:  2023年3月16日
 * @param: cell :             [param description ]
 * @param: axc_id_num :       [param description ]
 * @param: rx_cycle_num :     [param description ]
 * @param: tx_cycle_num :     [param description ]
 */
void Cpri_Csu_Link_7d2u_Init(uint32_t axc_id_num, uint32_t in_latch_num, uint32_t out_latch_num, uint32_t rx_cycle_num, uint32_t tx_cycle_num)
{
    uint32_t CGran = 0;

//    uint32_t rx_first_dma_flag = 0;

    uint32_t axc_id = 0;
    uint32_t latch_id = 0;
    uint32_t xnum = 0;
    uint32_t allnum = 0;
    uint32_t size = 0;
    uint32_t tx_src_addr = 0;
    uint32_t rx_dst_addr = 0;
    uint32_t cell0_comp_facter_addr_offset = 0;
    uint32_t cell1_comp_facter_addr_offset = 0;
    uint32_t cell0_rx_addr_offset = 0;
    uint32_t cell1_rx_addr_offset = 0;

//#ifdef TESTMAC_TEST
//    uint32_t nr_cell_rx_ddr_addr = DDR_NR_CELL0_RX_ADDR;//ddr
//#else
//    uint32_t nr_cell_rx_ddr_addr = (uint32_t)LOAD_EX_W(&cell->nr_tasks_inf_ptr->nr_cell_rx_ddr_addr);//ddr
//#endif

    uint32_t i = 0;

    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=5个节点的链表
    //tx的链表地址
    phy_csu_link_info_t* link = &g_phy_csu_link;

    uint32_t tx0_even_f7_link_addr     = link->tx0_even_f7_link_addr; // 0x721E800;
    uint32_t tx0_even_b7_link_addr     = link->tx0_even_b7_link_addr; // 0x721EA00;
    uint32_t tx0_odd_f7_link_addr      = link->tx0_odd_f7_link_addr; // 0x721EC00;
    uint32_t tx0_odd_b7_link_addr      = link->tx0_odd_b7_link_addr; // 0x721EE00;
    uint32_t tx0_s_link_addr           = link->tx0_s_link_addr; // 0x721F000;
    uint32_t tx0_1st_dummy_link_addr   = link->tx0_1st_dummy_link_addr; // 0x721F200;
    uint32_t tx0_2nd_dummy_link_addr   = link->tx0_2nd_dummy_link_addr; // 0x721F400;

    //rx的链表地址
    uint32_t rx0_1st_dummy_link_addr   = link->rx0_1st_dummy_link_addr; // 0x721F600;
    uint32_t rx0_2nd_dummy_link_addr   = link->rx0_2nd_dummy_link_addr; // 0x721F800;
    uint32_t rx0_s_link_addr           = link->rx0_s_link_addr; // 0x721FA00;
    uint32_t rx0_normal0_link_addr     = link->rx0_normal0_link_addr; // 0x721FC00;
    uint32_t rx0_normal1_link_addr     = link->rx0_normal1_link_addr; // 0x721FE00;

//    uint32_t tx0_2nd_link_addr         = 0x7220E00;
//    uint32_t rx0_2nd_link_addr         = 0x7221000;

	//TX:偶时隙前7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
        CGran = 0;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = (uint32_t)SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;//0x09e2a100
            cell0_comp_facter_addr_offset = allnum;
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = (uint32_t)SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR;//0x0a0a2900
            cell1_comp_facter_addr_offset = allnum;
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
          //  allnum = (4384*6+4448)*2*2;//2天线交织
            allnum = size*(4384*6+4448)/32;//2天线交织
            tx_src_addr = (uint32_t)SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + allnum*(i - 2);//0x09dee000,0x09e0c080
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
          //  allnum = (4384*6+4448)*2*2;//2天线交织
            allnum = size*(4384*6+4448)/32;//2天线交织
            tx_src_addr = (uint32_t)SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + allnum*(i - 4);//0x0a066800,0x0a084880
    	}
    	else //if (6 == i)
        {
            size = 4;//AGC因子，一个BF 2B
            allnum = size*(4384*6+4448)/32;//2小区的AGC因子,需要交织在一起
            tx_src_addr = (uint32_t)SM5_RESERVED3_ADDR;
        }

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_f7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_f7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:偶时隙后7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
        CGran = 0;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = (uint32_t)SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + cell0_comp_facter_addr_offset;//0x09e2a882
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = (uint32_t)SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + cell1_comp_facter_addr_offset;//0x0a0a3082
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
        //    allnum = 4384*7*2*2;//2天线交织
            allnum = size*4384*7/32;//2天线交织
            tx_src_addr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + allnum*(i - 2);//0x0a2c0400,0x0a2de380
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = 4384*7*2*2;//2天线交织
            allnum = size*4384*7/32;//2天线交织
            tx_src_addr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + allnum*(i - 4);//0x0a466c00,0x0a484b80
    	}
		else// if (6 == i)
    	{
            size = 4;//AGC，一个BF 2B
            allnum = size*4384*7/32;//2小区的AGC因子,需要交织在一起
            tx_src_addr = SM5_RESERVED3_ADDR;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_b7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_b7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

    cell0_comp_facter_addr_offset = 0;
    cell1_comp_facter_addr_offset = 0;

	//TX:奇时隙前7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
        CGran = 0;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = (uint32_t)SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;//0x09e67100
            cell0_comp_facter_addr_offset += allnum;
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = (uint32_t)SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR;//0x0a0df900
            cell1_comp_facter_addr_offset += allnum;
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = (4384*6+4448)*2*2;//2天线交织
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = (uint32_t)SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + allnum*(i - 2);//0x09e2b000,0x09e49080
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
        //    allnum = (4384*6+4448)*2*2;//2天线交织
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = (uint32_t)SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + allnum*(i - 4);//0x0a0a3800,0x0a0c1880
    	}
    	else //if (6 == i)
    	{
            size = 4;//AGC，一个BF 2B
            allnum = size*(4384*6+4448)/32;//2小区的AGC因子,需要交织在一起
            tx_src_addr = SM5_RESERVED3_ADDR;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_f7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_f7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:奇时隙后7个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
        CGran = 0;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = (uint32_t)SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + cell0_comp_facter_addr_offset;//
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = (uint32_t)SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + cell1_comp_facter_addr_offset;
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = 4384*7*2*2;//2天线交织
            allnum = size*4384*7/32;
            tx_src_addr = (uint32_t)SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + allnum*(i - 2);
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
          //  allnum = 4384*7*2*2;//2天线交织
            allnum = size*4384*7/32;
            tx_src_addr = (uint32_t)SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + allnum*(i - 4);
    	}
    	else //if (6 == i)
    	{
            size = 4;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;//2小区的AGC因子,需要交织在一起
            tx_src_addr = SM5_RESERVED3_ADDR;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_b7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_b7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:特殊时隙6个符号
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
        CGran = 0;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*5+4448)/32;
            tx_src_addr = (uint32_t)SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*5+4448)/32;
            tx_src_addr = (uint32_t)SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR;
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
          //  allnum = (4384*5+4448)*2*2;//2天线交织
             allnum = size*(4384*5+4448)/32;
            //特殊使用奇时隙的内存,特殊时隙占用6个符号的长度,剩余1个符号的长度，所以地址偏移是7个符号(64*2*(4384*6+4448)/32)
            tx_src_addr = (uint32_t)SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + ((4384*6+4448)*4)*(i - 2);
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = (4384*5+4448)*2*2;//2天线交织
             allnum = size*(4384*5+4448)/32;
            //特殊使用奇时隙的内存,特殊时隙占用6个符号的长度,剩余1个符号的长度，所以地址偏移是7个符号((4384*6+4448)*2)
            tx_src_addr = (uint32_t)SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + ((4384*6+4448)*4)*(i - 4);
    	}
    	else //if (6 == i)
    	{
            size = 4;//AGC因子，一个BF 2B
            allnum = size*(4384*5+4448)/32;//2小区的AGC因子,需要交织在一起
            tx_src_addr = SM5_RESERVED3_ADDR;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_s_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_s_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:dummy, 10ms周期的第一个
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
        CGran = 0;

    	if (0 == i || 1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440*2 + 4384*8)/32;//4936 BF
			tx_src_addr = CPRI_NRCELL_TXDUMMY_SLOTS_COMPRESS_ADDR + (i*allnum);//CSU_TX_DUMMYBUFFER_ADDR;
    	}
    	else if ((2 <= i) && (5 >= i))
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
          //  allnum = (61440*2 + 4384*8)*2*2;//2天线交织
            allnum = size*(61440*2 + 4384*8)/32;
		  	tx_src_addr = CPRI_NRCELL_TXDUMMY_SLOTS_AXCDATA_ADDR + ((i-2)*allnum);//CSU_TX_DUMMYBUFFER_ADDR;
    	}
    	else// if (6 == i)
    	{
            size = 4;//AGC，一个BF 2B
            allnum = size*(61440*2 + 4384*8)/32;//2小区的AGC因子,需要交织在一起
    		tx_src_addr = CPRI_NRCELL_TXDUMMY_SLOTS_AGC_ADDR;//CSU_TX_DUMMYBUFFER_ADDR;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_1st_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_1st_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:dummy, 10ms周期的最后一个
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i || 1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440*2 + 4384*8)/32;
			tx_src_addr = CPRI_NRCELL_TXDUMMY_SLOTS_COMPRESS_ADDR + (i*allnum);//CSU_TX_DUMMYBUFFER_ADDR;
        	CGran = 0;
    	}
    	else if  ((2 <= i) && (5 >= i))
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = (61440*2 + 4384*8)*2*2;//2天线交织
            allnum = size*(61440*2 + 4384*8)/32;
		 	tx_src_addr = CPRI_NRCELL_TXDUMMY_SLOTS_AXCDATA_ADDR + ((i-2)*allnum);//CSU_TX_DUMMYBUFFER_ADDR;
        	CGran = 0;
    	}
    	else //if (6 == i)
    	{
            size = 4;//AGC，一个BF 2B
            allnum = size*(61440*2 + 4384*8)/32;//2小区的AGC因子,需要交织在一起
           tx_src_addr = CPRI_NRCELL_TXDUMMY_SLOTS_AGC_ADDR;//CSU_TX_DUMMYBUFFER_ADDR;
			CGran = 1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_2nd_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_2nd_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//RX:占用连续的DDR地址
	//RX dummy 前5ms的链表
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i || 1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440*7 + 4448 + 4384*9)/32;//bf：14812
			rx_dst_addr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+ (i*allnum);//CSU_RX_DUMMYBUFFER_ADDR;
    	}
    	else if  ((2 <= i) && (5 >= i))
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
      //      allnum = (61440*7 + 4448 + 4384*9)*2*2;//2天线交织
            allnum = size*(61440*7 + 4448 + 4384*9)/32;//
	  		 rx_dst_addr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+ ((i-2)*allnum);
     	}
    	else// if (6 == i)
    	{
            size = 4;//agc，一个BF 2B
            allnum = size*(61440*7 + 4448 + 4384*9)/32;//2小区的AGC因子,需要交织在一起
            rx_dst_addr = CPRI_NRCELL_RXDUMMY_SLOTS_AGC_ADDR;
    	}

        xnum = size*rx_cycle_num;
        CGran = 1;//当 DMA 为 RX_AXC_RFP信号之后的第一个DMA 时，此 DMA 的参数 GRAN[3]需置为1
                  //[36]节点信息命令字里的first_dma要置1

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_1st_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_1st_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
    }

	//RX dummy 后5ms周期的链表
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i || 1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440*7 + 4448 + 4384*9)/32;
			rx_dst_addr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+ (i*allnum);//CSU_RX_DUMMYBUFFER_ADDR;
    	}
    	else if  ((2 <= i) && (5 >= i))
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = (61440*7 + 4448 + 4384*9)*2*2;//2天线交织
            allnum = size*(61440*7 + 4448 + 4384*9)/32;
		 	rx_dst_addr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+ ((i-2)*allnum);
     	}
    	else// if (6 == i)
    	{
            size = 4;//AGC因子，一个BF 2B
            allnum = size*(61440*7 + 4448 + 4384*9)/32;//2小区的AGC因子,需要交织在一起
            rx_dst_addr = CPRI_NRCELL_RXDUMMY_SLOTS_AGC_ADDR;
    	}

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_2nd_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_2nd_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }

    cell0_rx_addr_offset = 0;
    cell1_rx_addr_offset = 0;

	//RX特殊时隙链表
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*4)/32;
            rx_dst_addr = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR;//SM3_NR_CELL0_ODD_RX_DATA_ADDR;   0xb4200000
            cell0_rx_addr_offset += allnum;
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*4)/32;
            rx_dst_addr = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR;//SM5_NR_CELL1_ODD_RX_DATA_ADDR;   0xb4800000
            cell1_rx_addr_offset += allnum;
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = (4384*4)*2*2;//2天线数据交织
            allnum = size*(4384*4)/32;
            rx_dst_addr = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR+ cell0_rx_addr_offset;//SM3_NR_CELL0_ODD_RX_DATA_ADDR + cell0_rx_addr_offset;  0xb4200448;0xb4211648
            cell0_rx_addr_offset += allnum;
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
        //    allnum = (4384*4)*2*2;//2天线数据交织
        	allnum = size*(4384*4)/32;
            rx_dst_addr = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR+ cell1_rx_addr_offset;//SM5_NR_CELL1_ODD_RX_DATA_ADDR + cell1_rx_addr_offset; 0xb4800448;0xb4811648
            cell1_rx_addr_offset += allnum;
    	}
        else //if (6 == i)
        {
            size = 4;//AGC，一个BF 2B
            allnum = size*(4384*4)/32;//2小区的AGC因子,需要交织在一起
            rx_dst_addr = DDR_NR_CELL0_RX_AGC_ADDR;
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_s_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_s_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }

    cell0_rx_addr_offset = 0;
    cell1_rx_addr_offset = 0;

	//RX 第一个normal时隙的链表
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//0x09e68000
            cell0_rx_addr_offset += allnum;
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR;//0x0a338400
            cell1_rx_addr_offset += allnum;
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = 61440*2*2;//2天线数据交织
            allnum = size*(61440)/32;
            rx_dst_addr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR + cell0_rx_addr_offset;//0x09e68f00,0x09ea4f00
            cell0_rx_addr_offset += allnum;
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = 61440*2*2;//2天线数据交织
            allnum = size*(61440)/32;
            rx_dst_addr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR + cell1_rx_addr_offset;//0x0a339300,0x0a375300
            cell1_rx_addr_offset += allnum;
    	}
        else// if (6 == i)
        {
            size = 4;//agc因子，一个BF 2B
            allnum = size*(61440)/32;//2小区的AGC因子,需要交织在一起
            rx_dst_addr = (uint32_t)DDR_NR_CELL0_RX_AGC_ADDR; 
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal0_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal0_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }

    cell0_rx_addr_offset = 0;
    cell1_rx_addr_offset = 0;

	//RX 第二个normal时隙的链表
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;//0x0a0e0800
            cell0_rx_addr_offset += allnum;
    	}
    	else if (1 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = SM5_NR_CELL1_ODD_RX_DATA_ADDR;//0x0a3b1800
            cell1_rx_addr_offset += allnum;
    	}
    	else if (2 == i || 3 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
        //    allnum = 61440*2*2;//2天线数据交织
            allnum = size*(61440)/32;
            rx_dst_addr = SM3_NR_CELL0_ODD_RX_DATA_ADDR + cell0_rx_addr_offset;//0x0a0e1700,0x0a11d700
            cell0_rx_addr_offset += allnum;
    	}
    	else if (4 == i || 5 == i)
    	{
            size = 64*2;//AxC数据，一个BF有4个AxC 64B
         //   allnum = 61440*2*2;//2天线数据交织
            allnum = size*(61440)/32;
            rx_dst_addr = SM5_NR_CELL1_ODD_RX_DATA_ADDR + cell1_rx_addr_offset;//0x0a3b2700,0x0a3ee700
            cell1_rx_addr_offset += allnum;
    	}
    	else// if (6 == i)
        {
            size = 4;//AGC，一个BF 2B
            allnum = size*(61440)/32;//2小区的AGC因子,需要交织在一起
            rx_dst_addr = DDR_NR_CELL0_RX_AGC_ADDR;
        }

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal1_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal1_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }
}

/*!   
* @brief:  
* @author:  guicheng.liu
* @Date:  2023年3月16日
* @param: axc_id_num :       [param description ]
*/
void Cpri_Csu_Reg_7d2u_Init(uint32_t axc_id_num)
{
    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=5个节点的链表
    //tx的链表地址
    phy_csu_link_info_t* link = &g_phy_csu_link;

    uint32_t tx0_even_f7_link_addr     = link->tx0_even_f7_link_addr; // 0x721E800;
    uint32_t tx0_even_b7_link_addr     = link->tx0_even_b7_link_addr; // 0x721EA00;
    uint32_t tx0_odd_f7_link_addr      = link->tx0_odd_f7_link_addr; // 0x721EC00;
    uint32_t tx0_odd_b7_link_addr      = link->tx0_odd_b7_link_addr; // 0x721EE00;
    uint32_t tx0_s_link_addr           = link->tx0_s_link_addr; // 0x721F000;
    uint32_t tx0_1st_dummy_link_addr   = link->tx0_1st_dummy_link_addr; // 0x721F200;
    uint32_t tx0_2nd_dummy_link_addr   = link->tx0_2nd_dummy_link_addr; // 0x721F400;

    //rx的链表地址
    uint32_t rx0_1st_dummy_link_addr   = link->rx0_1st_dummy_link_addr; // 0x721F600;
    uint32_t rx0_2nd_dummy_link_addr   = link->rx0_2nd_dummy_link_addr; // 0x721F800;
    uint32_t rx0_s_link_addr           = link->rx0_s_link_addr; // 0x721FA00;
    uint32_t rx0_normal0_link_addr     = link->rx0_normal0_link_addr; // 0x721FC00;
    uint32_t rx0_normal1_link_addr     = link->rx0_normal1_link_addr; // 0x721FE00;

    UCP_API_CPRI_CSU_DmaParamReg_Cfg(0,  //第0组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_even_f7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(1,  //第1组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_even_b7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(2,  //第2组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_odd_f7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(3,  //第3组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_odd_b7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(4,  //第4组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_s_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(5,  //第5组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_1st_dummy_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(6,  //第6组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_2nd_dummy_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);

     //rx
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(7,  //第7组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_1st_dummy_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(8,  //第8组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_2nd_dummy_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(9,  //第9组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_s_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(10,  //第10组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_normal0_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(11,  //第11组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_normal1_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
}

/*!   
* @brief:  
* @author:  guicheng.liu
* @Date:  2023年3月16日
* @param: pTxCmdFifo :       [param description ]
* @param: pRxCmdFifo :       [param description ]
*/
void Cpri_Csu_Cmd_Gen_7d2u(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo)
{
    uint32_t tx_even_f7_cmd_14_h = 0;
    uint32_t tx_even_f7_cmd_32_l = 0;
    uint32_t tx_even_b7_cmd_14_h = 0;
    uint32_t tx_even_b7_cmd_32_l = 0;
    uint32_t tx_odd_f7_cmd_14_h = 0;
    uint32_t tx_odd_f7_cmd_32_l = 0;
    uint32_t tx_odd_b7_cmd_14_h = 0;
    uint32_t tx_odd_b7_cmd_32_l = 0;
    uint32_t tx_s_cmd_14_h = 0;
    uint32_t tx_s_cmd_32_l = 0;
    uint32_t tx_1st_dummy_cmd_14_h = 0;
    uint32_t tx_1st_dummy_cmd_32_l = 0;
    uint32_t tx_2nd_dummy_cmd_14_h = 0;
    uint32_t tx_2nd_dummy_cmd_32_l = 0;

    uint32_t rx_1st_dummy_cmd_14_h = 0;
    uint32_t rx_1st_dummy_cmd_32_l = 0;
    uint32_t rx_2nd_dummy_cmd_14_h = 0;
    uint32_t rx_2nd_dummy_cmd_32_l = 0;
    uint32_t rx_s_cmd_14_h = 0;
    uint32_t rx_s_cmd_32_l = 0;
    uint32_t rx_normal0_cmd_14_h = 0;
    uint32_t rx_normal0_cmd_32_l = 0;
    uint32_t rx_normal1_cmd_14_h = 0;
    uint32_t rx_normal1_cmd_32_l = 0;


    //FIFO1 用于TX发送数据
    //[1:0]dma_mode_s, 1:一级链表模式 DMA
    //[3:2]dma_mode_d, 1:一级链表模式 DMA
    //[4]dma_dimension, 1:多维 DMA
    //[5]axi4_master_sel 非APE模式,0:访问 DDR 和 Share Memory 选择 AXI4 Master0（经过非 CCI 总线）
    //[6]continue_next_dma 1:下一个 DMA 源端数据的读取无需等待当前 DMA目的端数据写完
    //[7]continue_last_dma 1:下一个 DMA 源端数据的读取无需等待上一个 DMA目的端数据写完
    //[12:8]dma_buffer_id_s 存放源端 DMA 参数的寄存器 ID
    //[17:13]dma_buffer_id_d 存放目的端 DMA 参数的寄存器 ID
    //[22:18]cmd_tag
    //[23]clear非APE模式,0:当前DMA之前,不清空CSU内部缓存
    tx_even_f7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(0<<8) |(0<<13)|(0<<18); 
    tx_even_f7_cmd_14_h = 0;

    tx_even_b7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(1<<8) |(1<<13)|(1<<18);
    tx_even_b7_cmd_14_h = 0;

    tx_odd_f7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(2<<8) |(2<<13)|(2<<18);
    tx_odd_f7_cmd_14_h = 0;

    tx_odd_b7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(3<<8) |(3<<13)|(3<<18);
    tx_odd_b7_cmd_14_h = 0;

    tx_s_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(4<<8) |(4<<13)|(4<<18);
    tx_s_cmd_14_h = 0;

    tx_1st_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(5<<8) |(5<<13)|(5<<18);
    tx_1st_dummy_cmd_14_h = 0;

    tx_2nd_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(6<<8) |(6<<13)|(6<<18);
    tx_2nd_dummy_cmd_14_h = 0;
    //UCP_API_CPRI_CSU_TxAxcData_Fifo1Cmd(tx_cmd_14_h,tx_cmd_32_l);


    pTxCmdFifo->cmdFifo_num = 4;
    pTxCmdFifo->cmdFifo[0].cmd_num = 10;
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[3].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[3].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[4].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[4].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[5].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[5].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[6].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[6].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[7].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[7].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[8].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[8].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[9].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[9].cmd14h = tx_even_b7_cmd_14_h;

    pTxCmdFifo->cmdFifo[1].cmd_num = 6;
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[2].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[2].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[3].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[3].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[4].cmd32l = tx_s_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[4].cmd14h = tx_s_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[5].cmd32l = tx_1st_dummy_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[5].cmd14h = tx_1st_dummy_cmd_14_h;

    pTxCmdFifo->cmdFifo[2].cmd_num = 10;
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[3].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[3].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[4].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[4].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[5].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[5].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[6].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[6].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[7].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[7].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[8].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[8].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[9].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[9].cmd14h = tx_even_b7_cmd_14_h;

    pTxCmdFifo->cmdFifo[3].cmd_num = 6;
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[2].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[2].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[3].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[3].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[4].cmd32l = tx_s_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[4].cmd14h = tx_s_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[5].cmd32l = tx_2nd_dummy_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[5].cmd14h = tx_2nd_dummy_cmd_14_h;


    //FIFO0 用于RX接收数据
    rx_1st_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(7<<8) |(7<<13)|(7<<18);
//  rx_1st_dummy_cmd_14_h  = 0;
	rx_1st_dummy_cmd_14_h  =  (1 << 4);

	rx_2nd_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(8<<8) |(8<<13)|(8<<18);
	rx_2nd_dummy_cmd_14_h = 0;

    rx_s_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(9<<8) |(9<<13)|(9<<18);
    rx_s_cmd_14_h = 0;

    rx_normal0_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(10<<8) |(10<<13)|(10<<18);
    rx_normal0_cmd_14_h = 0;

    rx_normal1_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(11<<8) |(11<<13)|(11<<18);
    rx_normal1_cmd_14_h = 0;
    //UCP_API_CPRI_CSU_RxAxcData_Fifo0Cmd(rx_cmd_14_h, rx_cmd_32_l); 


    pRxCmdFifo->cmdFifo_num = 4;
    pRxCmdFifo->cmdFifo[0].cmd_num = 1;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd32l = rx_1st_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd14h = rx_1st_dummy_cmd_14_h;

    pRxCmdFifo->cmdFifo[1].cmd_num = 3;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd32l = rx_s_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd14h = rx_s_cmd_14_h;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd32l = rx_normal0_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[1].cmd[2].cmd32l = rx_normal1_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[2].cmd14h = rx_normal1_cmd_14_h;

    pRxCmdFifo->cmdFifo[2].cmd_num = 1;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd32l = rx_2nd_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd14h = rx_2nd_dummy_cmd_14_h;

    pRxCmdFifo->cmdFifo[3].cmd_num = 3;
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd32l = rx_s_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd14h = rx_s_cmd_14_h;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd32l = rx_normal0_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[3].cmd[2].cmd32l = rx_normal1_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[2].cmd14h = rx_normal1_cmd_14_h;

}

 /*!   
 * @brief:  配置NR小区的CPRI CSU链表
 * @author:  guicheng.liu
 * @Date:  2023年1月15日
 * @param: cell :             [NR 小区参数]
 */
void Config_Cpri_Csu_Nr()
{
    uint32_t rx_cycle_num = 4;
    uint32_t tx_cycle_num = 4;
    uint32_t axc_id_num = 11; //2个指数因子,8个天线, 1个AGC因子(暂时不支持AGC因子,但是平台目前要求必须要配)
    uint32_t in_latch_num = 7;
	uint32_t out_latch_num = 7;

//    uint32_t w_r_flag = 0;//0:w, 1:r
//    uint32_t send_threshold = 0;
//    uint32_t almostfull_threshold = 0;
    stCpriCsuCmdFifoInfo tx_cmdfifo;
    stCpriCsuCmdFifoInfo rx_cmdfifo;

    memset(&tx_cmdfifo, 0, sizeof(stCpriCsuCmdFifoInfo));
    memset(&rx_cmdfifo, 0, sizeof(stCpriCsuCmdFifoInfo));

    UCP_API_CPRI_CSU_Set_AxcIdNum(axc_id_num);
    UCP_API_CPRI_CSU_Set_LatchNum(in_latch_num);

    //! step1 初始化所有的必要的寄存器
    Cpri_Csu_Init();
	
	//!step3: RX 和TX 的链表节点的配置
	Cpri_Csu_Link_7d2u_Init(axc_id_num, in_latch_num, out_latch_num, rx_cycle_num, tx_cycle_num);

    //!step2 配置TX&RX data outlatch
    Cpri_Csu_Latch_Init(axc_id_num, in_latch_num,out_latch_num, rx_cycle_num);

	//!step4: RX和TX参数寄存器的配置
    Cpri_Csu_Reg_7d2u_Init(in_latch_num);

	//!step5: 根据配置生成cmd fifo命令
    Cpri_Csu_Cmd_Gen_7d2u(&tx_cmdfifo, &rx_cmdfifo);

    //!step6：把生成好的FIFO命令配置给驱动
    UCP_API_CPRI_CSU_Get_CmdFIFO(&tx_cmdfifo, &rx_cmdfifo);

}


/*!   
* @brief:  根据NR配置 Timer和JESD/CPRI CSU Timer&DMA链表
* @author:  guicheng.liu
* @Date:  2022年7月8日
* @param: cell :             [NR 小区参数]
*/
void Phy_Timer_Csu_Config_Nr()
{
    Phy_Timer_Csu_Init();
    Config_Cpri_Csu_Nr();
}

