#ifndef _CPRI_CSU_NR_7DS2U_H_
#define _CPRI_CSU_NR_7DS2U_H_

#include "typedef.h"
#include "cpri_csu_api.h"

#define CPRI_NR7DS2U_ID_NUM							6

#define CPRI_LINK_START_ADDR						0x721E800
#define CPRI_NR7DS2U_TX_DUMMY_COMPRESS_LEN			0x2690
#define CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN			0x4D200
#define CPRI_NR7DS2U_TX_DUMMY_COMPRESS_ADDR			0xB4200000 // 0xB3E00000	// 0x2690
#define CPRI_NR7DS2U_TX_DUMMY_AXC1DATA_ADDR			(CPRI_NR7DS2U_TX_DUMMY_COMPRESS_ADDR+CPRI_NR7DS2U_TX_DUMMY_COMPRESS_LEN)	//0xB4202690	// 0x4D200
#define CPRI_NR7DS2U_TX_DUMMY_AXC2DATA_ADDR			(CPRI_NR7DS2U_TX_DUMMY_AXC1DATA_ADDR+CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN)	//0xB424F890	// 0x4D200
#define CPRI_NR7DS2U_TX_DUMMY_AXC3DATA_ADDR			(CPRI_NR7DS2U_TX_DUMMY_AXC2DATA_ADDR+CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN)	//0xB429CA90	// 0x4D200
#define CPRI_NR7DS2U_TX_DUMMY_AXC4DATA_ADDR			(CPRI_NR7DS2U_TX_DUMMY_AXC3DATA_ADDR+CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN)	//0xB42E9C90	// 0x4D200
#define CPRI_NR7DS2U_TX_DUMMY_AGC_ADDR				(CPRI_NR7DS2U_TX_DUMMY_AXC4DATA_ADDR+CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN)	//0xB4336E90	// 0x2690

#define CPRI_NR7DS2U_RX_DUMMY_COMPRESS_LEN			0x73B8
#define CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN			0xE7700
#define CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR			0xB4339520 // 0xB3F39520	// 0x73B8
#define CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR			(CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+CPRI_NR7DS2U_RX_DUMMY_COMPRESS_LEN)	//0xB43408D8	// 0xE7700
#define CPRI_NR7DS2U_RX_DUMMY_AXC2DATA_ADDR			(CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)	//0xB4427FD8 //	// 0xE7700
#define CPRI_NR7DS2U_RX_DUMMY_AXC3DATA_ADDR			(CPRI_NR7DS2U_RX_DUMMY_AXC2DATA_ADDR+CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)	//0xB450F6D8	// 0xE7700
#define CPRI_NR7DS2U_RX_DUMMY_AXC4DATA_ADDR			(CPRI_NR7DS2U_RX_DUMMY_AXC3DATA_ADDR+CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)	//0xB45F6DD8	// 0xE7700
#define CPRI_NR7DS2U_RX_DUMMY_AGC_ADDR				(CPRI_NR7DS2U_RX_DUMMY_AXC4DATA_ADDR+CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)	//0xB46DE4D8	// 0x73B8		// B46E5890


#if 1
#define CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x9F00000	// SM2
#define CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR		0x9FF0400	// SM2
#define CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR		0xA380000	// SM5
#define CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR		0xA290400	// SM4
#define CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR		0x9F3C100
#define CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR		0xA02C500
#else
#define CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x60F00000	// SM2
#define CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR		0x61380000	// SM5
#define CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR		0x60FF0400	// SM2
#define CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR		0x61290400	// SM4
#define CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR		0x60F3C100
#define CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR		0x6102C500
#endif
#define CPRI_NR7DS2U_TX_SLOT_EVEN_AGC_ADDR			0xB533D800
#define CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR			0xB533E700

#define CPRI_NR7DS2U_RX_SLOTS_COMPRESS_ADDR			0x6BC00000	// 0x448
#define CPRI_NR7DS2U_RX_SLOTS_AXCDATA_ADDR			0x6BC00448	// 0x22400
#define CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR		0x6BC22848	// 0xF00
#define CPRI_NR7DS2U_RX_SLOT_EVEN_AXCDATA_ADDR		0x6BC23748	// 0x78000
#define CPRI_NR7DS2U_RX_SLOT_ODD_COMPRESS_ADDR		0x6BC9B748	// 0xF00
#define CPRI_NR7DS2U_RX_SLOT_ODD_AXCDATA_ADDR		0x6BC9C648	// 0x78000

#define CPRI_NR7DS2U_RX_SLOTS_AGC_ADDR				0xB533F600
#define CPRI_NR7DS2U_RX_SLOT_EVEN_AGC_ADDR			0xB533FA48
#define CPRI_NR7DS2U_RX_SLOT_ODD_AGC_ADDR			0xB5340948


void cpri_csu_axc_init_nr_7ds2u(uint32_t nDummyFlag, stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo);
void cpri_csu_axc_latch_init_nr_7ds2u(void);
void cpri_csu_axc_link_init_nr_7ds2u(int32_t testMode);
void cpri_csu_axc_paramreg_init_nr_7ds2u();
void cpri_csu_axc_cmd_gen_7ds2u(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo);
void cpri_csu_start_nr_7ds2u(stCpriCsuCmdFifoInfo tx_cmdfifo, stCpriCsuCmdFifoInfo rx_cmdfifo);

#endif

