//#include "ucp_cpri.h"
#include "ucp_param.h"
#include "ucp_csu.h"
//#include "ucp_js_ctrl.h"
#include "ucp_mtimer.h"
#include "mtimer_com.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "phy_para.h"
#include "ctc_intr.h"
#include "inter_vector.h"
#include "HeaderRam.h"
#include "dw_apb_gpio.h"
#include "ecs_rfm_dm_mgt.h"
#include "mtimer_drv.h"

extern stPhyScsPara*	phyPara;

stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];

int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	uint8_t nBsType = get_protocol_sel(); 
    uint32_t coreClk = 0;

	memset(pMtimerPara, 0, sizeof(stMtimerPara));
	
    if (PROTOCOL_CPRI == nBsType) 
	{
		coreClk = pEcsDmLocalMgt->pCpriPara->core_clk;
	}
	else if (PROTOCOL_JESD == nBsType)
	{
	    uint32_t sample_clk = do_read_volatile(JESD_RX_SAMPLE_RATE+(nTmrId<<5));
		uint32_t sam_clk_ratio = do_read_volatile(JESD_RX_CLK_RATIO+(nTmrId<<5)) & 0xFF;
	    coreClk = sample_clk * sam_clk_ratio;
	}
    else if (PROTOCOL_ECPRI == nBsType)
	{
	    uint32_t rateOpt = get_protocol_opt();
		if (ECPRI_OPTION_10G == rateOpt)
		{
		    coreClk = 156240000; // 161132000; // 402832000;
		}
		else if (ECPRI_OPTION_25G == rateOpt)
		{
		    coreClk = 402832000;
		}
		else
		{
		    return -1;
		}
	}
	else
	{
	    return -1;
	}
	if (0 == coreClk)
	{
		return -1;
	}

	pMtimerPara->tmrClk = coreClk;
	pMtimerPara->tmrMsPeriod = coreClk / 1000;
    pMtimerPara->tmr100UsPeriod = pMtimerPara->tmrMsPeriod / 10;
    pMtimerPara->tmrUsPeriod = pMtimerPara->tmrMsPeriod / 1000;

    // init slot, tdd value, and config timer period
    pMtimerPara->scsId = nScsId;
    pMtimerPara->slotPeriod = do_read_volatile_short(&(phyPara[nScsId].slotPeriod));
    pMtimerPara->tddSlotNum = nTddSlotNum;
    pMtimerPara->tddPeriod = pMtimerPara->slotPeriod * nTddSlotNum;

	debug_write((DBG_DDR_IDX_DRV_BASE+42), pMtimerPara->tmrClk);		// 0xb7e060A8
	debug_write((DBG_DDR_IDX_DRV_BASE+43), pMtimerPara->slotPeriod);	// 0xb7e060Ac
	
	return 0;
}

uint32_t mtimer_get_baseaddr(uint8_t nTmrId)
{
	uint8_t nBsType = get_protocol_sel(); 
	uint8_t nRateOption = get_protocol_opt();
	uint32_t tmrBaseAddr = 0;

    if (PROTOCOL_JESD == nBsType)
	{
		if (nTmrId >= MTIMER_INTEGRATED_MAX_NUM)
		{
			return 0;
		}
	    if (JESD_OPTION_204B == nRateOption)
    	{
		    tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
    	}
		else if (JESD_OPTION_204C == nRateOption)
		{
			if (MTIMER_JESD_RX0_ID == nTmrId)
			{
			    tmrBaseAddr = JS_RX1_TMR_BASE;
			}
			else if (MTIMER_JESD_RX1_ID == nTmrId)
			{
			    tmrBaseAddr = JS_RX0_TMR_BASE;
			}
		    else if (MTIMER_JESD_TX0_ID == nTmrId)
		    {
			    tmrBaseAddr = JS_TX1_TMR_BASE;
		    }
		    else if (MTIMER_JESD_TX1_ID == nTmrId)
		    {
			    tmrBaseAddr = JS_TX0_TMR_BASE;
		    }
		}
		else
		{
		    return 0;
		}
	}
	else
	{
		if (MTIMER_CPRI_ID == nTmrId)
		{
			tmrBaseAddr = CPRI_TMR_BASE;
		}
		else if (MTIMER_ECPRI_ID == nTmrId)
		{
			tmrBaseAddr = ECPRI_TMR_BASE;
		}
		else
		{
			return 0;
		}
	}

	return tmrBaseAddr;
}

int32_t mtimer_clear_all_event(uint8_t nTmrId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}
	
	// 配置MTimer
	do_write(tmrBaseAddr + MTMR_CTRL_REG, 0x0);// 计时清零
	// T-EVENT
	do_write(tmrBaseAddr + MTMR_TEVENT0_REG, 0xFFFFFFFF);	  // 清除96个定时点事件
	do_write(tmrBaseAddr + MTMR_TEVENT1_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TEVENT2_REG, 0xFFFFFFFF);
	// clear TINT
	do_write(tmrBaseAddr + MTMR_TINTF00_REG, 0xFFFFFFFF);     /* INT0 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF01_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF02_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF10_REG, 0xFFFFFFFF);     /* INT1 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF11_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF12_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF20_REG, 0xFFFFFFFF);     /* INT2 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF21_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF22_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF30_REG, 0xFFFFFFFF);     /* INT3 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF31_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF32_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF40_REG, 0xFFFFFFFF);     /* INT4 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF41_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF42_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF50_REG, 0xFFFFFFFF);     /* INT5 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF51_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF52_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF60_REG, 0xFFFFFFFF);     /* INT6 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF61_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF62_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF70_REG, 0xFFFFFFFF);     /* INT7 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF71_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF72_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF80_REG, 0xFFFFFFFF);     /* INT8 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF81_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF82_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF90_REG, 0xFFFFFFFF);     /* INT9 flag clear */
	do_write(tmrBaseAddr + MTMR_TINTF91_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTF92_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTFA0_REG, 0xFFFFFFFF);     /* INTA flag clear */
	do_write(tmrBaseAddr + MTMR_TINTFA1_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTFA2_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTFB0_REG, 0xFFFFFFFF);     /* INTB flag clear */
	do_write(tmrBaseAddr + MTMR_TINTFB1_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_TINTFB2_REG, 0xFFFFFFFF);

	// C-EVENT
	do_write(tmrBaseAddr + MTMR_CEVENT_REG, 0xFFFFFFFF);
	// clear CINT
	do_write(tmrBaseAddr + MTMR_CINTF0_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF1_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF2_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF3_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF4_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF5_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF6_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF7_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF8_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTF9_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTFA_REG, 0xFFFFFFFF);
	do_write(tmrBaseAddr + MTMR_CINTFB_REG, 0xFFFFFFFF);
	__ucps2_synch(0);

	return 0;
}

int32_t set_mtimer_period(uint8_t nTmrId, uint32_t nTmrL, uint32_t nTmrM, uint32_t nTmrH)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}
	
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	// 设置计数器溢出值
	uint32_t tempL = nTmrL;
	uint32_t tempM = nTmrM;
	uint32_t tempH = nTmrH;
	tempL = (tempL > 0) ? (tempL - 1) : (0);
	tempM = (tempM > 0) ? (tempM - 1) : (0);
	tempH = (tempH > 0) ? (tempH - 1) : (0);
	pMtimerPara->tempL_max = tempL;
	pMtimerPara->tempM_max = tempM;
	pMtimerPara->tempH_max = tempH;

#ifdef PALLADIUM_TEST
	debug_write((DBG_DDR_IDX_DRV_BASE+128+(nTmrId<<7)), tempL);	// 0x200
	debug_write((DBG_DDR_IDX_DRV_BASE+128+1+(nTmrId<<7)), tempM);	// 0x204
	debug_write((DBG_DDR_IDX_DRV_BASE+128+2+(nTmrId<<7)), tempH);	// 0x208
#endif

	do_write(tmrBaseAddr + MTMR_OVFL_REG, tempL);
	do_write(tmrBaseAddr + MTMR_OVFH_REG, ((0x1<<31) + (tempH<<16) + tempM)); // WREQ, 10ms, all slot
	__ucps2_synch(0);
	while(do_read_volatile(tmrBaseAddr + MTMR_OVFH_REG) & BIT31); 	        			// RWC reg, wait until the OVF value set finished

	return 0;
}

int32_t set_mtimer_1pps_scratch(uint8_t nTmrId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

	uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
	uint32_t val = do_read_volatile(addr);
	do_write(addr, (val|BIT1));		// 1pps抓取使能

	//addr = tmrBaseAddr + MTMR_CINTE0_REG + 2*(MTMR_INT_10ms<<2);
	//val = do_read_volatile(addr);
	//do_write(addr, (val|BIT17));	// int enable
	enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_1PPS, MTMR_INT_10ms);	// int enable

	return 0;
}

// nTmrPoint: us as unit
int32_t set_mtimer_tmrpoint(uint8_t nTmrId, uint8_t nPointId, int32_t nTmrPoint, uint8_t mask)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	//uint32_t periodL = pMtimerPara->tempL_max + 1;
	uint32_t periodM = pMtimerPara->tempM_max + 1;
	//uint32_t periodH = pMtimerPara->tempH_max + 1;

	if (nTmrPoint < 0)
	{
		nTmrPoint += SFN_PERIOD;
	}

	uint32_t tempL = pMtimerPara->tmrMsPeriod * (nTmrPoint % pMtimerPara->slotPeriod) / 1000;
	uint32_t tempM = (nTmrPoint / pMtimerPara->slotPeriod) % periodM;
	uint32_t tempH = (nTmrPoint / pMtimerPara->slotPeriod) / periodM;
	if ((0 == tempM) && (0 == tempL))
	{
		tempH = (tempH > 0) ? (tempH - 1) : (pMtimerPara->tempH_max);
		tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
	}
	else if (0 == tempL)
	{
		tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
	}
	tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);

	if (MTIMER_MASK_32BIT == mask)
	{
		tempH = 0;
		tempM = 0;
	}
	else if (MTIMER_MASK_48BIT == mask)
	{
		tempH = 0;
	}
#ifdef PALLADIUM_TEST
	debug_write((DBG_DDR_IDX_DRV_BASE+128+4+(nPointId<<2)+(nTmrId<<7)), nTmrPoint);	// 0x210
	debug_write((DBG_DDR_IDX_DRV_BASE+128+5+(nPointId<<2)+(nTmrId<<7)), tempL);	// 0x214
	debug_write((DBG_DDR_IDX_DRV_BASE+128+6+(nPointId<<2)+(nTmrId<<7)), tempM);	// 0x218
	debug_write((DBG_DDR_IDX_DRV_BASE+128+7+(nPointId<<2)+(nTmrId<<7)), tempH);	// 0x21c
#endif

	do_write((tmrBaseAddr + MTMR_TnL_REG0 + (nPointId<<3)), tempL);
	do_write((tmrBaseAddr + MTMR_TnH_REG0 + (nPointId<<3)), ((mask<<30) + (tempH<<16) + tempM));
	do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)), (1<<(nPointId&0x1F)));
	__ucps2_synch(0);
	while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)) & (1<<(nPointId&0x1F)));			// REQ reg, wait until the T0L and T0H set finished

	return 0;
}

// nTmrPoint: ns as unit
int32_t set_mtimer_tmrpoint_ns(uint8_t nTmrId, uint8_t nPointId, int32_t nTmrPoint, uint8_t mask)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	//uint32_t periodL = pMtimerPara->tempL_max + 1;
	uint32_t periodM = pMtimerPara->tempM_max + 1;
	//uint32_t periodH = pMtimerPara->tempH_max + 1;

	if (nTmrPoint < 0)
	{
		nTmrPoint += (SFN_PERIOD*1000);
	}

	uint32_t tempL = (uint64_t)pMtimerPara->tmrMsPeriod * (nTmrPoint % (pMtimerPara->slotPeriod*1000)) / 1000000;
	uint32_t tempM = (nTmrPoint / (pMtimerPara->slotPeriod*1000)) % periodM;
	uint32_t tempH = (nTmrPoint / (pMtimerPara->slotPeriod*1000)) / periodM;
	if ((0 == tempM) && (0 == tempL))
	{
		tempH = (tempH > 0) ? (tempH - 1) : (pMtimerPara->tempH_max);
		tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
	}
	else if (0 == tempL)
	{
		tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
	}
	tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);

	if (MTIMER_MASK_32BIT == mask)
	{
		tempH = 0;
		tempM = 0;
	}
	else if (MTIMER_MASK_48BIT == mask)
	{
		tempH = 0;
	}
#ifdef PALLADIUM_TEST
	debug_write((DBG_DDR_IDX_DRV_BASE+128+4+(nPointId<<2)+(nTmrId<<7)), nTmrPoint);	// 0x210
	debug_write((DBG_DDR_IDX_DRV_BASE+128+5+(nPointId<<2)+(nTmrId<<7)), tempL);	// 0x214
	debug_write((DBG_DDR_IDX_DRV_BASE+128+6+(nPointId<<2)+(nTmrId<<7)), tempM);	// 0x218
	debug_write((DBG_DDR_IDX_DRV_BASE+128+7+(nPointId<<2)+(nTmrId<<7)), tempH);	// 0x21c
#endif

	do_write((tmrBaseAddr + MTMR_TnL_REG0 + (nPointId<<3)), tempL);
	do_write((tmrBaseAddr + MTMR_TnH_REG0 + (nPointId<<3)), ((mask<<30) + (tempH<<16) + tempM));
	do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)), (1<<(nPointId&0x1F)));
	__ucps2_synch(0);
	while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)) & (1<<(nPointId&0x1F)));			// REQ reg, wait until the T0L and T0H set finished

	return 0;
}

int32_t enable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nIntcId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

	uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
	do_write(addr, (do_read_volatile(addr) | (1 << (nPointId&0x1F))));

	return 0;
}

int32_t disable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nIntcId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

	uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
	do_write(addr, (do_read_volatile(addr) & (~(1 << (nPointId&0x1F)))));

	return 0;
}

int32_t enable_mtimer_cevent_int(uint8_t nTmrId, uint8_t nCEvtId, uint8_t nIntcId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

	uint32_t addr = tmrBaseAddr + MTMR_CINTE0_REG + (nIntcId<<3);
	uint32_t val = do_read_volatile(addr);
	val |= (1 << nCEvtId);
	do_write(addr, val);

	return 0;
}

int32_t disable_mtimer_cevent_int(uint8_t nTmrId, uint8_t nCEvtId, uint8_t nIntcId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

	uint32_t addr = tmrBaseAddr + MTMR_CINTE0_REG + (nIntcId<<3);
	uint32_t val = do_read_volatile(addr);
	val &= (~(1 << nCEvtId));
	do_write(addr, val);

	return 0;
}

int32_t set_cpri_tmr_ctrl()
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

	do_write((tmrBaseAddr + MTMR_CPRI_10MS_CLR), 0x1); // count clear
	do_write((tmrBaseAddr + MTMR_CPRI_10MS_CTRL), ((0x1<<9) + (MTMR_10ms_OFFSET<<2) + (0x0<<1) + 0x1 + (MTMR_CSU_CH << 10)));
	return 0;
}

int32_t start_mtimer(uint8_t nTmrId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	pMtimerPara->tmrScrCnt = 0;
	
	uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
    do_write(addr, ((do_read_volatile(addr))|BIT0)); // start timer
    
	return 0;
}

int32_t stop_mtimer(uint8_t nTmrId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}

	uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
    do_write(addr, ((do_read_volatile(addr))&(~BIT0))); // stop timer and clear the count
    
	return 0;
}

uint64_t get_mtimer_rt_scr_value(uint8_t nTmrId)
{
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
	if (0 == tmrBaseAddr)
	{
		return -1;
	}
	
	uint64_t scrval = 0;
	uint64_t hval = 0;
	uint32_t addr = tmrBaseAddr + MTMR_SCR_CTRL_REG;
	do_write(addr, ((do_read_volatile(addr)) | BIT31));
	while (do_read_volatile(addr) & BIT31) // 抓取完成
	{
		ucp_nop(1);
	}

    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
	pMtimerPara->tmrScrCnt++;
	if (pMtimerPara->tmrScrCnt & 0x1)
	{
		hval = do_read_volatile(tmrBaseAddr + MTMR_SCRATH0H_REG);
		scrval = (hval<<32) | do_read_volatile(tmrBaseAddr + MTMR_SCRATH0L_REG);
	}
	else
	{
		hval = do_read_volatile(tmrBaseAddr + MTMR_SCRATH1H_REG);
		scrval = (hval<<32) | do_read_volatile(tmrBaseAddr + MTMR_SCRATH1L_REG);
	}

	return scrval;
}


