#include "cpri_csu_nr_2period.h"
#include "typedef.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "cpri_driver.h"
#include "ucp_drv_common.h"

extern uint32_t 				gCpriCsuDummyFlag;

void cpri_csu_axc_init_nr_2period(uint32_t nDummyFlag, stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo)
{
	UCP_API_CPRI_CSU_Set_AxcIdNum(CPRI_NR2PERIOD_ID_NUM);
	UCP_API_CPRI_CSU_Set_LatchNum(CPRI_NR2PERIOD_ID_NUM);
	cpri_csu_axc_link_init_nr_2period(nDummyFlag);
	cpri_csu_axc_latch_init_nr_2period();
	cpri_csu_axc_paramreg_init_nr_2period();
	cpri_csu_axc_cmd_gen_2period(pTxCmdFifo, pRxCmdFifo);
}

void cpri_csu_axc_latch_init_nr_2period(void)
{
    uint32_t fifo_num = 4;//初始化4个FIFO通道(RX_AXC_DATA:CmdFIFO0, RX_AXC_CTRL:CmdFIFO2, TX_AXC_DATA:CmdFIFO1, TX_AXC_CTRL:CmdFIFO3)
    uint32_t dma_reg_group_num = 32;//清空CPRI的32组DMA参数寄存器
    uint32_t tag_mask = 0xFFFFFFFF;//DMA TAG全部不屏蔽

    uint32_t axc_id_num = CPRI_NR2PERIOD_ID_NUM; //1个指数因子,4个天线，1个AGC因子
    uint32_t tx0_rfp_set= 0;//[18:16]TX_AXC_DATA 通道开始工作后，提前发送的 Base Frame 的个数[8] 0:上升沿敏感 1: 高电平敏感
                            //[7:0]CSU捕捉到CPRI 端接口信号TX_AUX_CNT_POS 第一次为此数值后,延迟2个CSU                   的主时钟周期再次启动发送数据的工作
    uint32_t tx0_port_info[64] = {0};//共64个port, 
                        			//[31:26] CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的 ID 值
                        			//[25:20]CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的每拍有效比特数
                        			//[19:1]CPRI 模式 CSU 的 TX_AXC_DATA通道一个Basic Frame 中端口x的总比特数
                        			//[0]0:比特反序未使能 1:比特反序使能
    uint32_t out_latch_num = CPRI_NR2PERIOD_ID_NUM;//
    uint32_t tx0_latch_info_l[8] = {0}; //8个latch info配置，[24]bit_revert_enable 
                                        //[19:0]CPRI模式CSU的TX_AXC_DATA通道的OutLatch参数,     值为一个Basic Frame中在此OutLatch中缓存的所有端口的总比特数

    uint32_t tx0_latch_info_m[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*3  
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N
    uint32_t tx0_latch_info_h[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*7
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*5

    uint32_t rx0_port_info[64] = {0};//共64个port, [27:22]bit_number_one_cyclex [20:1]bit_number_one_basic_framex [0]bit_revert_enable
    uint32_t in_latch_num = CPRI_NR2PERIOD_ID_NUM;//
    uint32_t rx0_latch_info_l[8] = {0};//8个latch info配置，[24]bit_revert_enable  [19:0]bit_number_one_basic_frame
    uint32_t rx0_latch_info_h[8] = {0};//8个latch info配置，
                            			//[31]cpri_latch_n_7_times_bigger_than_128 =0： CPRI_LATCH_N*7 不大于 128, =1： CPRI_LATCH_N*7 大于 128
                            			//[30:24]cpri_latch_n_7_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*7
                            			//[23]cpri_latch_n_5_times_bigger_than_128  0： CPRI_LATCH_N*5 不大于 128, 1： CPRI_LATCH_N*5 大于 128
                            			//[22:16]cpri_latch_n_5_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*5
                            			//[15]cpri_latch_n_3_times_bigger_than_128  0： CPRI_LATCH_N*3 不大于 128, 1： CPRI_LATCH_N*3 大于 128
                            			//[14:8]cpri_latch_n_3_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*3
                            			//[6:0]cpri_latch_n
	uint32_t rx0_cycle_num[8] = {0};//8个latch info配置,
	                                //[7:0]CPRI模式CSU的RX_AXC_DATA通道的InLatch参数,值为该InLatch中连续接收的Basic Frame的个数减一

    uint32_t inlatch_index = 0;
//    uint32_t w_r_flag = 0;//0:w, 1:r
//    uint32_t send_threshold = 0;
//    uint32_t almostfull_threshold = 0;
//    uint32_t tx_cycle_num = 32;
    uint32_t rx_cycle_num = 2;

    uint32_t index = 0;
//    uint32_t i = 0;

	uint32_t bit_per_bf[CPRI_NR2PERIOD_ID_NUM] = {16,512,512,512,512,16};  //压缩因子是2byte, 16bit, 数据是64byte,512bit
    uint32_t bit_per_cycle[CPRI_NR2PERIOD_ID_NUM] = {16,0,0,0,0,16}; //0:表示64, 非0:有效比特数为数值本身

    //! step1 初始化所有的必要的寄存器
    UCP_API_CPRI_CSU_Init(fifo_num, dma_reg_group_num, tag_mask);

    //!step2 配置TX&RX data outlatch
    for (index = 0; index < axc_id_num; index++)
    {
//        tx0_port_info[index] = ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));     
		tx0_port_info[index] = 0x1 | ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));	   
    }

    for (index = 0; index < out_latch_num; index++)
    {
//	    tx0_latch_info_l[index] = 	bit_per_bf[index]; 
	    tx0_latch_info_l[index] = BIT24 |bit_per_bf[index]; 
	    tx0_latch_info_m[index] = 0x180008;//CPRI_LATCH_N??bit反序??
	    tx0_latch_info_h[index] = 0x380028; 
    }
    tx0_rfp_set = 0x40001;//RfpPoint=0x1 can send 4//push 4 basic frame at 1st tx_axc_rfp

    UCP_API_CPRI_CSU_TxOutLatch_Cfg(axc_id_num, 
                                    tx0_rfp_set, 
                                    tx0_port_info, 
                                    out_latch_num,
                                    tx0_latch_info_l, 
                                    tx0_latch_info_m, 
                                    tx0_latch_info_h);

    for (index = 0; index < axc_id_num; index++)
    {
//        rx0_port_info[index] =  ((bit_per_bf[index]<<1)|(bit_per_cycle[index]<<22));     
		rx0_port_info[index] =	0x1 | ((bit_per_bf[index]<<1)|(bit_per_cycle[index]<<22));	 
    }

    for (index = 0; index < in_latch_num; index++)
    {
//        rx0_latch_info_l[index] =  bit_per_bf[index];  
        rx0_latch_info_l[index] =  BIT24 | bit_per_bf[index];  
        rx0_latch_info_h[index] =  0x38281808; 
        rx0_cycle_num[index] = rx_cycle_num - 1; 
    }

    UCP_API_CPRI_CSU_RxInLatch_Cfg(axc_id_num,
                                    rx0_port_info,
                                    in_latch_num,
                                    rx0_latch_info_l,
                                    rx0_latch_info_h,
                                    rx0_cycle_num);

    UCP_API_CPRI_CSU_RxInLatchThres_Cfg(inlatch_index,
                                        1,//w_r_flag,
                                        0x0,//send_threshold,
                                        0x10);//almostfull_threshold);

	UCP_API_CPRI_CSU_TXAxcData_ChannelCtrl(0, axc_id_num, axc_id_num);
	UCP_API_CPRI_CSU_RXAxcData_ChannelCtrl(0, axc_id_num);
}

void cpri_csu_axc_link_init_nr_2period(int32_t testMode)
{
    uint32_t axc_id = 0;
    uint32_t latch_id = 0;
    uint32_t xnum = 0;
    uint32_t allnum = 0;
    uint32_t size = 0;
    uint32_t tx_cycle_num = 2;
    uint32_t rx_cycle_num = 2;
    uint32_t tx_src_addr = 0;
    uint32_t rx_dst_addr = 0;
    uint32_t comp_facter_addr_offset = 0;
//    uint32_t rx_addr_offset = 0;
    uint32_t CGran = 0;

//    uint32_t index = 0;
    uint32_t i = 0;
    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=6个节点的链表
#if 0
    //tx的链表地址
    uint32_t tx0_even_f7_link_addr     = CPRI_LINK_START_ADDR; // 0x721E800;
    uint32_t tx0_even_b7_link_addr     = CPRI_LINK_START_ADDR + 1*0x200; // 0x721EA00;
    uint32_t tx0_odd_f7_link_addr      = CPRI_LINK_START_ADDR + 2*0x200; // 0x721EC00;
    uint32_t tx0_odd_b7_link_addr      = CPRI_LINK_START_ADDR + 3*0x200; // 0x721EE00;
    uint32_t tx0_s_link_addr           = CPRI_LINK_START_ADDR + 4*0x200; // 0x721F000;
    uint32_t tx0_1st_dummy_link_addr   = CPRI_LINK_START_ADDR + 5*0x200; // 0x721F200;
    uint32_t tx0_2nd_dummy_link_addr   = CPRI_LINK_START_ADDR + 6*0x200; // 0x721F400;

    //rx的链表地址
    uint32_t rx0_1st_dummy_link_addr   = CPRI_LINK_START_ADDR + 7*0x200;  // 0x721F600;
    uint32_t rx0_2nd_dummy_link_addr   = CPRI_LINK_START_ADDR + 8*0x200;  // 0x721F800;
    uint32_t rx0_s_link_addr           = CPRI_LINK_START_ADDR + 9*0x200;  // 0x721FA00;
    uint32_t rx0_normal0_link_addr     = CPRI_LINK_START_ADDR + 10*0x200; // 0x721FC00;
    uint32_t rx0_normal1_link_addr     = CPRI_LINK_START_ADDR + 11*0x200; // 0x721FE00;
#else
	//tx的链表地址
	uint32_t tx0_even_f7_link_addr	   = 0x6821F800;
	uint32_t tx0_even_b7_link_addr	   = 0x6821FA00;
	uint32_t tx0_odd_f7_link_addr	   = 0x6821FC00;
	uint32_t tx0_odd_b7_link_addr	   = 0x6821FE00;
	uint32_t tx0_s_link_addr		   = 0x68220000;
	uint32_t tx0_1st_dummy_link_addr   = 0x68220200;
	uint32_t tx0_2nd_dummy_link_addr   = 0x68220400;
    uint32_t tx0_3nd_dummy_link_addr   = 0x68220600;

	//rx的链表地址
	uint32_t rx0_1st_dummy_link_addr   = 0x68220800;
	uint32_t rx0_2nd_dummy_link_addr   = 0x68220A00;
	uint32_t rx0_3nd_dummy_link_addr   = 0x68220C00;
	uint32_t rx0_s_link_addr		   = 0x68220E00;
	uint32_t rx0_normal0_link_addr	   = 0x68221000;
	uint32_t rx0_normal1_link_addr	   = 0x68221200;
#endif

	//step3: 进行RX 和TX 的链表节点的配置
	//TX:偶时隙前7个符号
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_EVEN_COMPRESS_ADDR;
            comp_facter_addr_offset = allnum;
            CGran = 0;
    	}
		else if (5 == i)
		{
			size = 2;//压缩因子，一个BF 2B
			allnum = size*(4384*6+4448)/32;
			tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_EVEN_AGC_ADDR;
			comp_facter_addr_offset = allnum;
			CGran = 0; //1; //TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1，表示是该基本帧的最后一个节点，防止基本帧数据不完整，latch中有数据残留
		}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (4384*6+4448)*2;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_EVEN_F7SYMBOL_ADDR + allnum*(i - 1);
            CGran = 0;
    	}


        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_f7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_f7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:偶时隙后7个符号
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_EVEN_COMPRESS_ADDR + comp_facter_addr_offset;
            CGran = 0;
    	}
		else if (5 == i)
    	{
            size = 1*2;//AGC，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_EVEN_AGC_ADDR + comp_facter_addr_offset;
            CGran = 0; // 1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = 4384*7*2;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_EVEN_B7SYMBOL_ADDR + allnum*(i - 1);
            CGran = 0;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_b7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_even_b7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

    comp_facter_addr_offset = 0;

	//TX:奇时隙前7个符号
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_COMPRESS_ADDR;
            comp_facter_addr_offset = allnum;
        	CGran = 0;
    	}
    	else if (5 == i)
    	{
            size = 1*2;//AGC，一个BF 2B
            allnum = size*(4384*6+4448)/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_AGC_ADDR;
            comp_facter_addr_offset = allnum;
        	CGran = 0; //1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (4384*6+4448)*2;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_F7SYMBOL_ADDR + allnum*(i - 1);
            CGran = 0;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_f7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_f7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:奇时隙后7个符号
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_COMPRESS_ADDR + comp_facter_addr_offset;
        	CGran = 0;
    	}
    	else if (5 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*4384*7/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_AGC_ADDR + comp_facter_addr_offset;
        	CGran = 0; //1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = 4384*7*2;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_B7SYMBOL_ADDR + allnum*(i - 1);
            CGran = 0;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_b7_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_odd_b7_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:特殊时隙后3个符号
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(4384*3)/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_COMPRESS_ADDR;
        	CGran = 0;
    	}
    	else if (5 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(4384*3)/32;
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_AGC_ADDR;
			CGran = 0; //1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (4384*3)*2;
            //特殊使用奇时隙的内存,特殊时隙占用6个符号的长度,剩余1个符号的长度，所以地址偏移是7个符号((4384*6+4448)*2)
            tx_src_addr = CPRI_NR2PERIOD_TX_SLOT_ODD_B7SYMBOL_ADDR + ((4384*7)*2)*(i - 1);
        	CGran = 0;
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_s_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_s_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:dummy, 10ms周期的第一个
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440*1 + 4384*4)/32;
        	CGran = 0;
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY1_COMPRESS_ADDR;
			}
    	}
    	else if (5 == i)
    	{
            size = 1*2;//AGC，一个BF 2B
            allnum = size*(61440*1 + 4384*4)/32;
			CGran = 0; //1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY1_AGC_ADDR;
			}
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (61440*1 + 4384*4)*2;
        	CGran = 0;
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY1_AXC1DATA_ADDR + (i-1)*CPRI_NR2PERIOD_TX_DUMMY1_AXCDATA_LEN;
			}
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_1st_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_1st_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:dummy, 5ms周期的第二个
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440*2 + 4384*4)/32;
        	CGran = 0;
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY2_COMPRESS_ADDR;
			}
    	}
    	else if (5 == i)
    	{
            size = 1*2;//AGC，一个BF 2B
            allnum = size*(61440*2 + 4384*4)/32;
			CGran = 0;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY2_AGC_ADDR;
			}
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2 + 4384*4)*2;
			CGran = 0;
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY2_AXC1DATA_ADDR + (i-1)*CPRI_NR2PERIOD_TX_DUMMY2_AXCDATA_LEN;
			}
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_2nd_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_2nd_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }
#if 1
	//TX:dummy, 10ms周期的最后一个
	for (i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i)
    	{
            size = 2;//压缩因子，一个BF 2B
            allnum = size*(61440*2 + 4384*4)/32;
        	CGran = 0;
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY2_COMPRESS_ADDR;
			}
    	}
    	else if (5 == i)
    	{
            size = 1*2;//AGC，一个BF 2B
            allnum = size*(61440*2 + 4384*4)/32;
			CGran = 1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY2_AGC_ADDR;
			}
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2 + 4384*4)*2;
			CGran = 0;
			if (0 == testMode)
			{
				tx_src_addr = CSU_TX_DUMMYBUFFER_ADDR;
			}
			else
			{
				tx_src_addr = CPRI_NR2PERIOD_TX_DUMMY2_AXC1DATA_ADDR + (i-1)*CPRI_NR2PERIOD_TX_DUMMY2_AXCDATA_LEN;
			}
    	}

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_3nd_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx0_3nd_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }
#endif

	//RX:占用连续的DDR地址
	//RX dummy 10ms的第一个链表
	for(i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440*3 + 4448 + 4384*11)/32;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY1_COMPRESS_ADDR;
			}
    	}
    	else if (5 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440*3 + 4448 + 4384*11)/32;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY1_AGC_ADDR;
			}
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (61440*3 + 4448 + 4384*11)*2;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY1_AXC1DATA_ADDR + (i-1)*CPRI_NR2PERIOD_RX_DUMMY1_AXCDATA_LEN;
			}
     	}

        xnum = size*rx_cycle_num;
        CGran = 1;//当 DMA 为 RX_AXC_RFP信号之后的第一个DMA 时，此 DMA 的参数 GRAN[3]需置为1
                  //[36]节点信息命令字里的first_dma要置1

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_1st_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_1st_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran, // 0,
                                            0,
                                            0);
    }

	//RX dummy 10ms的第二个链表
	for(i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440*2 + 4448 + 4384*11)/32;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY1_COMPRESS_ADDR;
			}
    	}
    	else if (5 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440*2 + 4448 + 4384*11)/32;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY1_AGC_ADDR;
			}
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2 + 4448 + 4384*11)*2;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY1_AXC1DATA_ADDR + (i-1)*CPRI_NR2PERIOD_RX_DUMMY1_AXCDATA_LEN;
			}
     	}

        xnum = size*rx_cycle_num;
        CGran = 0;//当 DMA 为 RX_AXC_RFP信号之后的第一个DMA 时，此 DMA 的参数 GRAN[3]需置为1
                  //[36]节点信息命令字里的first_dma要置1

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_2nd_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_2nd_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran, // 0,
                                            0,
                                            0);
    }
	//RX dummy 10ms周期的第三个链表
	for(i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;

    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440*3 + 4448 + 4384*11)/32;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY2_COMPRESS_ADDR;
			}
    	}
    	else if (5 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440*3 + 4448 + 4384*11)/32;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY2_AGC_ADDR;
			}
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (61440*3 + 4448 + 4384*11)*2;
			if (0 == testMode)
			{
				rx_dst_addr = CSU_RX_DUMMYBUFFER_ADDR;
			}
			else
			{
				rx_dst_addr = CPRI_NR2PERIOD_RX_DUMMY2_AXC1DATA_ADDR + (i-1)*CPRI_NR2PERIOD_RX_DUMMY2_AXCDATA_LEN;
			}
     	}

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_3nd_dummy_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_3nd_dummy_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }
#if 0
    rx_addr_offset = 0;
	uint32_t rxCnt = 0;
	debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)), (uint32_t)rx_addr_offset);	// 0x310
	debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)+1), (uint32_t)rx_dst_addr);	// 0x310
#endif
	//RX特殊时隙链表
	for(i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(4384*2)/32;
            rx_dst_addr = CPRI_NR2PERIOD_RX_SLOTS_COMPRESS_ADDR; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
    	else if (5 == i)
    	{
            size = 1*2;//AGC，一个BF 2B
            allnum = size*(4384*2)/32;
            rx_dst_addr = CPRI_NR2PERIOD_RX_SLOTS_AGC_ADDR; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = (4384*2)*2;
            rx_dst_addr = CPRI_NR2PERIOD_RX_SLOTS_AXCDATA_ADDR + (i-1)*allnum; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
#if 0
		rxCnt++;
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)), (uint32_t)rx_addr_offset); // 0x310
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)+1), (uint32_t)rx_dst_addr); // 0x310
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)+2), (uint32_t)allnum); // 0x310
#endif
        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_s_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_s_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }

	//RX 第一个normal时隙的链表
	for(i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = (uint32_t)CPRI_NR2PERIOD_RX_SLOT_EVEN_COMPRESS_ADDR; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
    	else if (5 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = (uint32_t)CPRI_NR2PERIOD_RX_SLOT_EVEN_AGC_ADDR; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = 61440*2;
            rx_dst_addr = CPRI_NR2PERIOD_RX_SLOT_EVEN_AXCDATA_ADDR + (i-1)*allnum; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
#if 0
		rxCnt++;
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)), (uint32_t)rx_addr_offset);	// 0x310
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)+1), (uint32_t)rx_dst_addr);	// 0x310
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)+2), (uint32_t)allnum);			// 0x310
#endif
        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal0_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal0_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }

	//RX 第二个normal时隙的链表
	for(i = 0; i < CPRI_NR2PERIOD_ID_NUM; i++)
	{
    	axc_id = i;
    	latch_id = i;
    	if (0 == i)
    	{
            size = 1*2;//压缩因子，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = CPRI_NR2PERIOD_RX_SLOT_ODD_COMPRESS_ADDR; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
    	else if (5 == i)
    	{
            size = 1*2;//AGC，一个BF 2B
            allnum = size*(61440)/32;
            rx_dst_addr = CPRI_NR2PERIOD_RX_SLOT_ODD_AGC_ADDR; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
    	else
    	{
            size = 64;//AxC数据，一个BF有4个AxC 64B
            allnum = 61440*2;
            rx_dst_addr = CPRI_NR2PERIOD_RX_SLOT_ODD_AXCDATA_ADDR + (i-1)*allnum; // + rx_addr_offset;
//            rx_addr_offset += allnum;
    	}
#if 0
		rxCnt++;
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)), (uint32_t)rx_addr_offset); // 0x310
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)+1), (uint32_t)rx_dst_addr); // 0x310
		debug_write((DBG_DDR_IDX_DRV_BASE+196+(rxCnt<<2)+2), (uint32_t)allnum); // 0x310
#endif
        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal1_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx0_normal1_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
    }
}

void cpri_csu_axc_paramreg_init_nr_2period()
{
    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=6个节点的链表
    uint32_t axc_id_num = CPRI_NR2PERIOD_ID_NUM; //1个指数因子,4个天线, 1个AGC因子
#if 0
    //tx的链表地址
    uint32_t tx0_even_f7_link_addr     = CPRI_LINK_START_ADDR; // 0x721E800;
    uint32_t tx0_even_b7_link_addr     = CPRI_LINK_START_ADDR + 1*0x200; // 0x721EA00;
    uint32_t tx0_odd_f7_link_addr      = CPRI_LINK_START_ADDR + 2*0x200; // 0x721EC00;
    uint32_t tx0_odd_b7_link_addr      = CPRI_LINK_START_ADDR + 3*0x200; // 0x721EE00;
    uint32_t tx0_s_link_addr           = CPRI_LINK_START_ADDR + 4*0x200; // 0x721F000;
    uint32_t tx0_1st_dummy_link_addr   = CPRI_LINK_START_ADDR + 5*0x200; // 0x721F200;
    uint32_t tx0_2nd_dummy_link_addr   = CPRI_LINK_START_ADDR + 6*0x200; // 0x721F400;

    //rx的链表地址
    uint32_t rx0_1st_dummy_link_addr   = CPRI_LINK_START_ADDR + 7*0x200; // 0x721F600;
    uint32_t rx0_2nd_dummy_link_addr   = CPRI_LINK_START_ADDR + 8*0x200; // 0x721F800;
    uint32_t rx0_s_link_addr           = CPRI_LINK_START_ADDR + 9*0x200; // 0x721FA00;
    uint32_t rx0_normal0_link_addr     = CPRI_LINK_START_ADDR + 10*0x200; // 0x721FC00;
    uint32_t rx0_normal1_link_addr     = CPRI_LINK_START_ADDR + 11*0x200; // 0x721FE00;
#else
	//tx的链表地址
	uint32_t tx0_even_f7_link_addr	   = 0x6821F800;
	uint32_t tx0_even_b7_link_addr	   = 0x6821FA00;
	uint32_t tx0_odd_f7_link_addr	   = 0x6821FC00;
	uint32_t tx0_odd_b7_link_addr	   = 0x6821FE00;
	uint32_t tx0_s_link_addr		   = 0x68220000;
	uint32_t tx0_1st_dummy_link_addr   = 0x68220200;
	uint32_t tx0_2nd_dummy_link_addr   = 0x68220400;
    uint32_t tx0_3nd_dummy_link_addr   = 0x68220600;

	//rx的链表地址
	uint32_t rx0_1st_dummy_link_addr   = 0x68220800;
	uint32_t rx0_2nd_dummy_link_addr   = 0x68220A00;
	uint32_t rx0_3nd_dummy_link_addr   = 0x68220C00;
	uint32_t rx0_s_link_addr		   = 0x68220E00;
	uint32_t rx0_normal0_link_addr	   = 0x68221000;
	uint32_t rx0_normal1_link_addr	   = 0x68221200;
#endif

    //step4：进行DMA 参数寄存器的配置 
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(0,  //第0组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_even_f7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(1,  //第1组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_even_b7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(2,  //第2组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_odd_f7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(3,  //第3组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_odd_b7_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(4,  //第4组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_s_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(5,  //第5组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_1st_dummy_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
#if 1
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(6,  //第6组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx0_2nd_dummy_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
#endif
	 UCP_API_CPRI_CSU_DmaParamReg_Cfg(7,  //第7组寄存器
									  DMA_PARAM_MODE_LINKLIST,
									  tx0_3nd_dummy_link_addr, 
									  0,
									  0,
									  0,
									  0,
									  axc_id_num);
     //rx
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(8,  //第8组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_1st_dummy_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(9,  //第9组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_2nd_dummy_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(10,  //第10组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_3nd_dummy_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(11,  //第11组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_s_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(12,  //第12组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_normal0_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
     UCP_API_CPRI_CSU_DmaParamReg_Cfg(13,  //第13组寄存器
                                      DMA_PARAM_MODE_LINKLIST,
                                      rx0_normal1_link_addr, 
                                      0,
                                      0,
                                      0,
                                      0,
                                      axc_id_num);
}

void cpri_csu_axc_cmd_gen_2period(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo)
{
    uint32_t tx_even_f7_cmd_14_h = 0;
    uint32_t tx_even_f7_cmd_32_l = 0;
    uint32_t tx_even_b7_cmd_14_h = 0;
    uint32_t tx_even_b7_cmd_32_l = 0;
    uint32_t tx_odd_f7_cmd_14_h = 0;
    uint32_t tx_odd_f7_cmd_32_l = 0;
    uint32_t tx_odd_b7_cmd_14_h = 0;
    uint32_t tx_odd_b7_cmd_32_l = 0;
    uint32_t tx_s_cmd_14_h = 0;
    uint32_t tx_s_cmd_32_l = 0;
    uint32_t tx_1st_dummy_cmd_14_h = 0;
    uint32_t tx_1st_dummy_cmd_32_l = 0;
    uint32_t tx_2nd_dummy_cmd_14_h = 0;
    uint32_t tx_2nd_dummy_cmd_32_l = 0;
    uint32_t tx_3nd_dummy_cmd_14_h = 0;
    uint32_t tx_3nd_dummy_cmd_32_l = 0;

    uint32_t rx_1st_dummy_cmd_14_h = 0;
    uint32_t rx_1st_dummy_cmd_32_l = 0;
    uint32_t rx_2nd_dummy_cmd_14_h = 0;
    uint32_t rx_2nd_dummy_cmd_32_l = 0;
    uint32_t rx_3nd_dummy_cmd_14_h = 0;
    uint32_t rx_3nd_dummy_cmd_32_l = 0;
    uint32_t rx_s_cmd_14_h = 0;
    uint32_t rx_s_cmd_32_l = 0;
    uint32_t rx_normal0_cmd_14_h = 0;
    uint32_t rx_normal0_cmd_32_l = 0;
    uint32_t rx_normal1_cmd_14_h = 0;
    uint32_t rx_normal1_cmd_32_l = 0;

    //FIFO1 用于TX发送数据
    //[1:0]dma_mode_s, 3:二级链表模式 DMA
    //[3:2]dma_mode_d, 3:二级链表模式 DMA
    //[4]dma_dimension, 1:多维 DMA
    //[5]axi4_master_sel 非APE模式,0： 访问 DDR 和 Share Memory 选择 AXI4 Master0（经过非 CCI 总线）
    //[6]continue_next_dma 1:下一个 DMA 源端数据的读取无需等待当前 DMA目的端数据写完
    //[7]continue_last_dma 1:下一个 DMA 源端数据的读取无需等待上一个 DMA目的端数据写完
    //[12:8]dma_buffer_id_s 
    //[17:13]dma_buffer_id_d
    //[22:18]cmd_tag
    //[23]clear 非 APE 模式,0：当前 DMA 之前， 不清空 CSU 内部缓存
    tx_even_f7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(0<<8) |(0<<13)|(0<<18); 
    tx_even_f7_cmd_14_h = 0;

    tx_even_b7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(1<<8) |(1<<13)|(1<<18);
    tx_even_b7_cmd_14_h = 0;

    tx_odd_f7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(2<<8) |(2<<13)|(2<<18);
    tx_odd_f7_cmd_14_h = 0;

    tx_odd_b7_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(3<<8) |(3<<13)|(3<<18);
    tx_odd_b7_cmd_14_h = 0;

    tx_s_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(4<<8) |(4<<13)|(4<<18);
    tx_s_cmd_14_h = 0;

    tx_1st_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(5<<8) |(5<<13)|(5<<18);
    tx_1st_dummy_cmd_14_h = 0;

    tx_2nd_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(6<<8) |(6<<13)|(6<<18);
    tx_2nd_dummy_cmd_14_h = 0;

    tx_3nd_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(7<<8) |(7<<13)|(7<<18);
    tx_3nd_dummy_cmd_14_h = 0;

    pTxCmdFifo->cmdFifo_num = 4; 
    pTxCmdFifo->cmdFifo[0].cmd_num = 9;
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[3].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[3].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[4].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[4].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[5].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[5].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[6].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[6].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[7].cmd32l = tx_s_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[7].cmd14h = tx_s_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[8].cmd32l = tx_1st_dummy_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[8].cmd14h = tx_1st_dummy_cmd_14_h;

    pTxCmdFifo->cmdFifo[1].cmd_num = 7;
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[2].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[2].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[3].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[3].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[4].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[4].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[5].cmd32l = tx_s_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[5].cmd14h = tx_s_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[6].cmd32l = tx_2nd_dummy_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[6].cmd14h = tx_2nd_dummy_cmd_14_h;

    pTxCmdFifo->cmdFifo[2].cmd_num = 9;
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[3].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[3].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[4].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[4].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[5].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[5].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[6].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[6].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[7].cmd32l = tx_s_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[7].cmd14h = tx_s_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[8].cmd32l = tx_1st_dummy_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[8].cmd14h = tx_1st_dummy_cmd_14_h;

    pTxCmdFifo->cmdFifo[3].cmd_num = 7;
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd32l = tx_odd_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd14h = tx_odd_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[2].cmd32l = tx_even_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[2].cmd14h = tx_even_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[3].cmd32l = tx_even_b7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[3].cmd14h = tx_even_b7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[4].cmd32l = tx_odd_f7_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[4].cmd14h = tx_odd_f7_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[5].cmd32l = tx_s_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[5].cmd14h = tx_s_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[6].cmd32l = tx_3nd_dummy_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[6].cmd14h = tx_3nd_dummy_cmd_14_h;


    //FIFO0 用于RX接收数据
    rx_1st_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(8<<8) |(8<<13)|(8<<18);
    rx_1st_dummy_cmd_14_h = (1 << 4);

    rx_2nd_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(9<<8) |(9<<13)|(9<<18);
    rx_2nd_dummy_cmd_14_h = 0;

    rx_3nd_dummy_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(10<<8) |(10<<13)|(10<<18);
    rx_3nd_dummy_cmd_14_h = 0;

    rx_s_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(11<<8) |(11<<13)|(11<<18);
    rx_s_cmd_14_h = 0;

    rx_normal0_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(12<<8) |(12<<13)|(12<<18);
    rx_normal0_cmd_14_h = 0;

    rx_normal1_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(13<<8) |(13<<13)|(13<<18);
    rx_normal1_cmd_14_h = 0;

    pRxCmdFifo->cmdFifo_num = 4;
    pRxCmdFifo->cmdFifo[0].cmd_num = 3;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd32l = rx_1st_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd14h = rx_1st_dummy_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd32l = rx_s_cmd_32_l;
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd14h = rx_s_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd32l = rx_normal0_cmd_32_l;
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd14h = rx_normal0_cmd_14_h;

    pRxCmdFifo->cmdFifo[1].cmd_num = 4;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd32l = rx_2nd_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd14h = rx_2nd_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd32l = rx_s_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd14h = rx_s_cmd_14_h;
    pRxCmdFifo->cmdFifo[1].cmd[2].cmd32l = rx_normal0_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[2].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[1].cmd[3].cmd32l = rx_normal1_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[3].cmd14h = rx_normal1_cmd_14_h;

    pRxCmdFifo->cmdFifo[2].cmd_num = 3;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd32l = rx_3nd_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd14h = rx_3nd_dummy_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd32l = rx_s_cmd_32_l;
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd14h = rx_s_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd32l = rx_normal0_cmd_32_l;
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd14h = rx_normal0_cmd_14_h;

    pRxCmdFifo->cmdFifo[3].cmd_num = 4;
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd32l = rx_2nd_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd14h = rx_2nd_dummy_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd32l = rx_s_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd14h = rx_s_cmd_14_h;
    pRxCmdFifo->cmdFifo[3].cmd[2].cmd32l = rx_normal0_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[2].cmd14h = rx_normal0_cmd_14_h;
    pRxCmdFifo->cmdFifo[3].cmd[3].cmd32l = rx_normal1_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[3].cmd14h = rx_normal1_cmd_14_h;
}


