#ifndef _CPRI_CSU_NR_2PERIOD_H_
#define _CPRI_CSU_NR_2PERIOD_H_

#include "typedef.h"
#include "cpri_csu_api.h"

#define CPRI_NR2PERIOD_ID_NUM						6

//#define CPRI_LINK_START_ADDR						0x721E800
#define CPRI_NR2PERIOD_TX_DUMMY1_COMPRESS_LEN			0x1348
#define CPRI_NR2PERIOD_TX_DUMMY1_AXCDATA_LEN			0x26900
#define CPRI_NR2PERIOD_TX_DUMMY1_COMPRESS_ADDR			0xB4200000 // 0x1348
#define CPRI_NR2PERIOD_TX_DUMMY1_AXC1DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY1_COMPRESS_ADDR+CPRI_NR2PERIOD_TX_DUMMY1_COMPRESS_LEN)//0xB4201348	// 0x26900
#define CPRI_NR2PERIOD_TX_DUMMY1_AXC2DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY1_AXC1DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY1_AXCDATA_LEN)	//0xB4227C48	// 0x26900
#define CPRI_NR2PERIOD_TX_DUMMY1_AXC3DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY1_AXC2DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY1_AXCDATA_LEN)	//0xB424E548	// 0x26900
#define CPRI_NR2PERIOD_TX_DUMMY1_AXC4DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY1_AXC3DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY1_AXCDATA_LEN)	//0xB4274E48	// 0x26900
#define CPRI_NR2PERIOD_TX_DUMMY1_AGC_ADDR				(CPRI_NR2PERIOD_TX_DUMMY1_AXC4DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY1_AXCDATA_LEN)	//0xB429B748	// 0x1348

#define CPRI_NR2PERIOD_TX_DUMMY2_COMPRESS_LEN			0x2248
#define CPRI_NR2PERIOD_TX_DUMMY2_AXCDATA_LEN			0x44900
#define CPRI_NR2PERIOD_TX_DUMMY2_COMPRESS_ADDR			0xB429CA90 // 0x2248
#define CPRI_NR2PERIOD_TX_DUMMY2_AXC1DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY2_COMPRESS_ADDR+CPRI_NR2PERIOD_TX_DUMMY2_COMPRESS_LEN)//0xB429ECD8	// 0x44900
#define CPRI_NR2PERIOD_TX_DUMMY2_AXC2DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY2_AXC1DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY2_AXCDATA_LEN)	//0xB42E35D8	// 0x44900
#define CPRI_NR2PERIOD_TX_DUMMY2_AXC3DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY2_AXC2DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY2_AXCDATA_LEN)	//0xB4327ED8	// 0x44900
#define CPRI_NR2PERIOD_TX_DUMMY2_AXC4DATA_ADDR			(CPRI_NR2PERIOD_TX_DUMMY2_AXC3DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY2_AXCDATA_LEN)	//0xB436C7D8	// 0x44900
#define CPRI_NR2PERIOD_TX_DUMMY2_AGC_ADDR				(CPRI_NR2PERIOD_TX_DUMMY2_AXC4DATA_ADDR+CPRI_NR2PERIOD_TX_DUMMY2_AXCDATA_LEN)	//0xB43B10D8	// 0x2248

#define CPRI_NR2PERIOD_RX_DUMMY1_COMPRESS_LEN			0x39DC
#define CPRI_NR2PERIOD_RX_DUMMY1_AXCDATA_LEN			0x73B80
#define CPRI_NR2PERIOD_RX_DUMMY1_COMPRESS_ADDR			0xB43B3320 // 0x39DC
#define CPRI_NR2PERIOD_RX_DUMMY1_AXC1DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY1_COMPRESS_ADDR+CPRI_NR2PERIOD_RX_DUMMY1_COMPRESS_LEN)//0xB43B6CFC	// 0x73B80
#define CPRI_NR2PERIOD_RX_DUMMY1_AXC2DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY1_AXC1DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY1_AXCDATA_LEN)	//0xB442A87C //	// 0x73B80
#define CPRI_NR2PERIOD_RX_DUMMY1_AXC3DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY1_AXC2DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY1_AXCDATA_LEN)	//0xB449E3FC	// 0x73B80
#define CPRI_NR2PERIOD_RX_DUMMY1_AXC4DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY1_AXC3DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY1_AXCDATA_LEN)	//0xB4511F7C	// 0x73B80
#define CPRI_NR2PERIOD_RX_DUMMY1_AGC_ADDR				(CPRI_NR2PERIOD_RX_DUMMY1_AXC4DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY1_AXCDATA_LEN)	//0xB4585AFC	// 0x39DC		

#define CPRI_NR2PERIOD_RX_DUMMY2_COMPRESS_LEN			0x2ADC
#define CPRI_NR2PERIOD_RX_DUMMY2_AXCDATA_LEN			0x55B80
#define CPRI_NR2PERIOD_RX_DUMMY2_COMPRESS_ADDR			0xB45894D8 	// 0x73B8
#define CPRI_NR2PERIOD_RX_DUMMY2_AXC1DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY2_COMPRESS_ADDR+CPRI_NR2PERIOD_RX_DUMMY2_COMPRESS_LEN)//0xB458BFB4	// 0x55B80
#define CPRI_NR2PERIOD_RX_DUMMY2_AXC2DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY2_AXC1DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY2_AXCDATA_LEN)	//0xB45E1B34‬   // 0x55B80
#define CPRI_NR2PERIOD_RX_DUMMY2_AXC3DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY2_AXC2DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY2_AXCDATA_LEN)	//0xB46376B4	// 0x55B80
#define CPRI_NR2PERIOD_RX_DUMMY2_AXC4DATA_ADDR			(CPRI_NR2PERIOD_RX_DUMMY2_AXC3DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY2_AXCDATA_LEN)	//0xB468D234	// 0x55B80
#define CPRI_NR2PERIOD_RX_DUMMY2_AGC_ADDR				(CPRI_NR2PERIOD_RX_DUMMY2_AXC4DATA_ADDR+CPRI_NR2PERIOD_RX_DUMMY2_AXCDATA_LEN)	//0xB46E2DB4	// 0x2ADC		


#if 0
#define CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x9F00000	// SM2
#define CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR		0x9FF0400	// SM2
#define CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR		0xA380000	// SM5
#define CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR		0xA290400	// SM4
#define CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR		0x9F3C100
#define CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR		0xA02C500
#else
#define CPRI_NR2PERIOD_TX_SLOT_EVEN_F7SYMBOL_ADDR		0x60F00000	
#define CPRI_NR2PERIOD_TX_SLOT_EVEN_B7SYMBOL_ADDR		0x61380000	
#define CPRI_NR2PERIOD_TX_SLOT_ODD_F7SYMBOL_ADDR		0x60FF0400	
#define CPRI_NR2PERIOD_TX_SLOT_ODD_B7SYMBOL_ADDR		0x61290400	
#define CPRI_NR2PERIOD_TX_SLOT_EVEN_COMPRESS_ADDR		0x60F3C100
#define CPRI_NR2PERIOD_TX_SLOT_ODD_COMPRESS_ADDR		0x6102C500
#endif
#define CPRI_NR2PERIOD_TX_SLOT_EVEN_AGC_ADDR			0xB533D800
#define CPRI_NR2PERIOD_TX_SLOT_ODD_AGC_ADDR			    0xB533E700

#define CPRI_NR2PERIOD_RX_SLOTS_COMPRESS_ADDR			0x6BC00000	// 0x448
#define CPRI_NR2PERIOD_RX_SLOTS_AXCDATA_ADDR			0x6BC00448	// 0x22400
#define CPRI_NR2PERIOD_RX_SLOT_EVEN_COMPRESS_ADDR		0x6BC22848	// 0xF00
#define CPRI_NR2PERIOD_RX_SLOT_EVEN_AXCDATA_ADDR		0x6BC23748	// 0x78000
#define CPRI_NR2PERIOD_RX_SLOT_ODD_COMPRESS_ADDR		0x6BC9B748	// 0xF00
#define CPRI_NR2PERIOD_RX_SLOT_ODD_AXCDATA_ADDR		    0x6BC9C648	// 0x78000

#define CPRI_NR2PERIOD_RX_SLOTS_AGC_ADDR				0xB533F600
#define CPRI_NR2PERIOD_RX_SLOT_EVEN_AGC_ADDR			0xB533FA48
#define CPRI_NR2PERIOD_RX_SLOT_ODD_AGC_ADDR			    0xB5340948


void cpri_csu_axc_init_nr_2period(uint32_t nDummyFlag, stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo);
void cpri_csu_axc_latch_init_nr_2period(void);
void cpri_csu_axc_link_init_nr_2period(int32_t testMode);
void cpri_csu_axc_paramreg_init_nr_2period();
void cpri_csu_axc_cmd_gen_2period(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo);
void cpri_csu_start_nr_2period(stCpriCsuCmdFifoInfo tx_cmdfifo, stCpriCsuCmdFifoInfo rx_cmdfifo);

#endif

