#include "ucp_drv_common.h"
#include "typedef.h"
#include "dw_apb_timers.h"
#include <ucps2-intrin.h>
#include "a72_ctrl.h"
#include "apcs.h"
#include "cci550.h"
#include "ucp_sfr_c.h"
#include "ucp_js_subcrg.h"
#include "ucp_js_ctrl.h"
#include "ucp_csu.h"
#include "ucp_drv_common.h"
#include "phy_para.h"
//#include "ape_cnt.h"
#include "osp_io.h"
#include "ucp_utility.h"

void delay_us(uint32_t num)
{
    uint32_t start = GET_STC_CNT();
    uint32_t waitCycle = num * 1000;
    uint32_t limitVal = do_read_volatile(STC_RT_ADDR);
    while (((GET_STC_CNT() - start + limitVal)%limitVal) <= waitCycle);
}

void SET_CLK_CFG_EMU(void)
{
    //EN CCI
//    SLV0_SNOOP_CTRL = 0x3;
    //SLV1_SNOOP_CTRL = 0x3;
    //SLV2_SNOOP_CTRL = 0x3;
//    SLV5_SNOOP_CTRL = 0x3;
//    SLV6_SNOOP_CTRL = 0x3;

//    A72_CLK0_CFG_EN       =   0x520000|BIT24;
//    A72_CLK1_CFG_EN       =   0x520000|BIT24;
//    CS_CLK_CFG_EN         =   0x521000;//900
//    MAIN_HI_CLK_CFG_REG   =   0x520000;
//    MAIN_LO_CLK_CFG_REG   =   0x521000;
//    MAINP_CLK_CFG_REG     =   0x523000;
//    MAINH_CLK_CFG_REG     =   0x523000;
    JS_HI_CLK_CFG_REG     =   0x520000;
    ES_HI_CLK_CFG_REG     =   0x520000;
    PET_HI_CLK_CFG_REG    =   0x520000;
    JS_LO_CLK_CFG_REG     =   0x521000;
    ES_LO_CLK_CFG_REG     =   0x521000;
    PET_LO_CLK_CFG_REG    =   0x521000;
    JSP_CLK_CFG_REG       =   0x523000;
    ESP_CLK_CFG_REG       =   0x523000;
    PETP_CLK_CFG_REG      =   0x523000;
    JS_PMA_CLK_CFG_REG    =   0x529000;
    ES_PMA_CLK_CFG_REG    =   0x529000;
    PET_PMA_CLK_CFG_REG   =   0x529000;
    ESH_CLK_CFG_REG       =   0x523000;
    JSH_CLK_CFG_REG       =   0x523000;
    PETH_CLK_CFG_REG      =   0x523000;

//    DMAS0_CLK_CFG_REG     =   0x523000;
//    DMAS1_CLK_CFG_REG     =   0x523000;
//    APC0_CLK_CFG_REG          =   0x520000;
//    APC1_CLK_CFG_REG          =   0x520000;
//    APC2_CLK_CFG_REG          =   0x520000;
//    APC3_CLK_CFG_REG          =   0x520000;
    APC0_SYSCNT_CLK_CFG_REG   =   0x520000;
//    APC1_SYSCNT_CLK_CFG_REG   =   0x520000;
//    APC2_SYSCNT_CLK_CFG_REG   =   0x520000;
//    APC3_SYSCNT_CLK_CFG_REG   =   0x520000;
//    SMMU_CLK_CFG_REG          =   0x520000;
    SPACC_CLK_CFG_REG         =   0x521000;
    EIP_CLK_CFG_REG           =   0x520000;
    ECPRI_ACLK_CFG_REG        =   0x520000;
    RFC_CLK_CFG_REG           =   0x521000;
//    M3_TPIU_CLK_CFG_REG       =   0x523000;
//    M3_DAP_CLK_CFG_REG        =   0x523000;
//    M3_AHB_CLK_CFG_REG        =   0x523000;

    SRIO0_CLK_CFG_REG         =   0x521000;
    SRIO1_CLK_CFG_REG         =   0x521000;
    SRIO2_CLK_CFG_REG         =   0x521000;

    TIMER20_CLK_CFG_REG   	=   0x529000;
	
    APC0_SUBCTRL_REG0 = 0x2;
  //APC1_SUBCTRL_REG0 = 0x2;
  //APC2_SUBCTRL_REG0 = 0x2;
  //APC3_SUBCTRL_REG0 = 0x2;

    APC0_SUBCTRL_REG1 = 0xAA;
  //APC1_SUBCTRL_REG1 = 0xAA;
  //APC2_SUBCTRL_REG1 = 0xAA;
  //APC3_SUBCTRL_REG1 = 0xAA;

  //SMMU_SHARE_CTRL = RNG_VALUE;
   // CLK_CTL_REG0 = (BIT11+BIT14);//select 20M

    JECS_CRG_PLLSEL &= (~BIT4); //ECPRI PLL3

    // temp, to be change
    /**********************************************************************/
	//JECS_CTRL_QOS_M3_SRIO_AXIM |= BIT19;
    //                             gnss_sel     stc_sel     cpri_sel
	//JECS_CTRL_CPRI_GMAC_PHY_INT = (0x0 << 4) | (0x5 << 7) | (0x5<<10);
    ECSRFM_CSU_ELEVELMASK = 0xFFFFFFFF;
    /**********************************************************************/
#if 0
    PLL0_CTL_REG1 = BIT18+(1<<15)+(1<<12)+90;//1.8G
    PLL1_CTL_REG1 = BIT18+(1<<15)+(2<<12)+140;//1.4G
    PLL2_CTL_REG1 = BIT18+(1<<15)+(2<<12)+100;//1.2G
    PLL3_CTL_REG1 = BIT18+(1<<15)+(2<<12)+100;//1G
    CLK_CTL_REG1 = 0x3;
    PLL4_CTL_REG1 = BIT18+(1<<15)+(2<<12)+93;
    PLL5_CTL_REG1 = BIT18+(1<<15)+(2<<12)+120;
    while(PLL_STATUS_REG  != 0x3f) ;
    CLK_CTL_REG1 = 0x3f;

    while((CCI_STATUS&BIT1));
#endif
}

