// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : spu_sw_queue.h
// Author        : lishuang.xie
// Created On    : 2023-01-11
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#ifndef __SPU_SW_QUEUE_H__
#define __SPU_SW_QUEUE_H__

#include "typedef.h"

#define SPU_APE_RFM_QUE_SIG_SIZE    (512)       /* 软件队列一个单位的长度为512字节 */
#define SPU_APE_RFM_SHELL_QUE_DEP   (8)         /* Shell软件队列的深度为8 */
#define SPU_APE_RFM_QUE_DEP         (256)
#define SPU_APE_RFM_MSG_QUE_DEP     (128)

typedef enum SPU_SW_QUEUE_INDEX
{
    SW_LOG_APE0 = 0,
    SW_LOG_APE1,
    SW_LOG_APE2,
    SW_LOG_APE3,
    SW_LOG_APE4,
    SW_LOG_APE5,
    SW_LOG_APE6,
    SW_LOG_APE7,
    SW_LOG_PET_RFM0,
    SW_LOG_PET_RFM1,
    SW_LOG_ECS_RFM0,
    SW_LOG_ECS_RFM1,

    SW_SHELL_APE0, //12
    SW_SHELL_APE1,
    SW_SHELL_APE2,
    SW_SHELL_APE3,
    SW_SHELL_APE4,
    SW_SHELL_APE5,
    SW_SHELL_APE6,
    SW_SHELL_APE7,
    SW_SHELL_PET_RFM0,
    SW_SHELL_PET_RFM1,
    SW_SHELL_ECS_RFM0,
    SW_SHELL_ECS_RFM1,

    SW_SHELL_ECHO_APE0, //24
    SW_SHELL_ECHO_APE1,
    SW_SHELL_ECHO_APE2,
    SW_SHELL_ECHO_APE3,
    SW_SHELL_ECHO_APE4,
    SW_SHELL_ECHO_APE5,
    SW_SHELL_ECHO_APE6,
    SW_SHELL_ECHO_APE7,
    SW_SHELL_ECHO_PET_RFM0,
    SW_SHELL_ECHO_PET_RFM1,
    SW_SHELL_ECHO_ECS_RFM0,
    SW_SHELL_ECHO_ECS_RFM1,

    SW_QUEUE_MAX_INDEX,
}spu_sw_queue_index_e;

typedef enum SPU_SW_QUEUE_TYPE
{
    SPU_SW_QUEUE_MSG,       /* MSG软件队列 */
    SPU_SW_QUEUE_SHELL,     /* Shell软件队列 */
    SPU_SW_QUEUE_MAX,       /* 软件队列最大类型 */
}spu_sw_queue_type_e;

typedef struct SPU_SW_QUEUE_MEM
{
    uint32_t u32addr;
    uint16_t u16queue_id;
    uint16_t u16queue_type;
    uint8_t  u8queue_offset;
    uint8_t  u8queue_padding;
    uint16_t u16queue_mem_idx;
    uint16_t u16queue_dep;
    uint16_t u16queue_mask;
    uint16_t u16queue_padding;
    uint32_t u32queue_full_count;
    uint32_t u32queue_empty_count;
}spu_sw_queue_mem_t;

typedef struct SPU_SW_QUEUE_SHARE_INFO
{
    uint16_t u16queue_deque_idx;
    uint16_t u16queue_enque_idx;
    uint16_t u16queue_alloc_idx;
    uint16_t u16queue_free_idx;
    //uint16_t u16queue_deque_count;
    //uint16_t u16queue_enque_count;
    uint16_t u16queue_msg[SPU_APE_RFM_QUE_DEP];
}spu_sw_queue_share_info_t;

#define SPU_SW_QUEUE_SHARE_INFO_SIZE    (sizeof(spu_sw_queue_share_info_t))

typedef struct SPU_SW_MSG_INFO
{
    uint8_t  u8Head[2];
    uint16_t u16DataLen;
    uint8_t  u8PktType;
    uint8_t  u8CoreId;
    uint16_t u16Tail;
    int8_t   i8Data[0];
}spu_sw_msg_info_t;

#define SPU_SW_MSG_INFO_HEAD1   (0xAB)
#define SPU_SW_MSG_INFO_HEAD2   (0xEF)
#define SPU_SW_MSG_INFO_SIZE    sizeof(spu_sw_msg_info_t)

//void* spu_sw_queue_share_get_info(void);

//uint8_t spu_sw_queue_spin_init(void);           /* 只需要调用一次，放在rfm0初始时调用 */
//int8_t *spu_sw_mem_malloc_by_ape(spu_sw_queue_index_e emqueue_idx);
//int8_t *spu_sw_mem_malloc_by_rfm(spu_sw_queue_index_e emqueue_idx);


//uint8_t spu_sw_queue_get(uint16_t u16queue_id, spu_sw_queue_type_e emqueue_type, spu_sw_queue_info_t* pqueue_info);
uint8_t spu_sw_enque(spu_sw_queue_index_e emqueue_idx, int8_t *pi8addr);
uint8_t spu_sw_deque(spu_sw_queue_index_e emqueue_idx, uint32_t **pu32value);
int8_t *spu_sw_mem_malloc(spu_sw_queue_index_e emqueue_idx);

/*
uint8_t spu_sw_enque_by_ape(spu_sw_queue_index_e emqueue_idx, int8_t *pi8addr);
uint8_t spu_sw_enque_by_rfm(spu_sw_queue_index_e emqueue_idx, int8_t *pi8addr);

uint8_t spu_sw_deque_by_ape(spu_sw_queue_index_e emqueue_idx, uint32_t *pu32value);
uint8_t spu_sw_deque_by_rfm(spu_sw_queue_index_e emqueue_idx, uint32_t *pu32value);


int8_t *spu_sw_msg_malloc(spu_sw_queue_index_e emqueue_idx);
void spu_sw_msg_enque(spu_sw_queue_index_e emqueue_idx, int8_t *pi8addr);
uint8_t spu_sw_msg_deque(spu_sw_queue_index_e emqueue_idx, uint32_t *pu32value);
*/
#endif  /* __SPU_SW_QUEUE_H__ */

