// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : main.c
// Author        : xianfeng.du
// Created On    : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#include "ucp_printf.h"
#include "rfm1_drv.h"
#include "ucp_heartbeat.h"
#include "ecs_rfm_spu1_top.h"
#include "msg_transfer_queue.h"
#include "log_server.h"
#include "ucp_utility.h"
#include "phy_queue_proc.h"
#include "cpri_test_mode.h"
#include "spu_shell.h"
#include "gtimer_drv.h"
#include "rfm1_gtimer2.h"
#include "ecs_rfm_spu1_oam.h"
#include "phy_para.h"
#include "hw_cpri.h"
#include "hwque.h"
#include "lib_debug_init.h"
#include "ecpri_driver.h"

#ifdef TEST_ENABLE
#include "fh_test.h"
#endif

extern void Mem_Init(void);

#ifdef DDR_MONITOR
void spu_ddr_monitor()
{
    if (1 == do_read_volatile(DDR_MONITOR_ENABLE))
    {
        clear_rfm1_gtimer2_1_intcnt();
        gtimer2_int_enable(0);
        do_write(DDR_MONITOR_ENABLE, 0);
    }
    volatile uint32_t nMonitorCnt = do_read_volatile(DDR_MONITOR_CNT);
    __ucps2_synch(0);
    if (nMonitorCnt < get_rfm1_gtimer2_1_intcnt())
    {
        gtimer2_int_disable(0);
        do_write(DDR_MONITOR_CNT, 0);
    }
}
#endif

extern uint32_t     gCpriCsuDummyFlag;

int32_t main(int32_t argc, char* argv[])
{
    int32_t core_id = 0;
    int32_t ret = 0;

    UCP_PRINT_EMPTY("Hello world from ECS RFM SPU1,coreId[0x%x]",  get_core_id());

    core_id = get_core_id();
    debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);

    ret = spu_lib_debug_init(core_id);
    debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);

#ifdef PALLADIUM_TEST
    int flag = 1;
    debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
#endif

    spu_log_client_init();

    spu_log_server_init();

#ifdef PALLADIUM_TEST
    debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
#endif

    Mem_Init();     /* call phy function to mem sm */

#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif

    ecs_rfm_spu1_drv_init();
#ifdef PALLADIUM_TEST
    flag++;
    debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif

    ecs_rfm_spu1_msg_transfer_init();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif

    spu_shell_init();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif

    spu_shell_cpri_cmd();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif

    oam_msg_init();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif

    while (1)
    {
        if (PROTOCOL_CPRI == get_protocol_sel())
        {
            check_cpri();

            check_10ms_offset();
        }

        if (PROTOCOL_ECPRI == get_protocol_sel())
        {
            /* eCPRI link status check */
            ecpri_link_status_check();
        }

#ifdef TEST_ENABLE
        //do_write(CSU_TX_ADVANCE_SAMPLE, 10000);     // 10us
        //do_write(CSU_RX_TD_SAMPLE, 10000);

        check_test_outcome(0);
#endif

        phy_queue_polling();

        spu_log_server_proc();

        /* check whether shell commands exist */
        spu_shell_task();

        /* update heartbeat count */
        heart_beat_write();

#ifdef DDR_MONITOR
        spu_ddr_monitor();
#endif
    }

    return 0;
}

