/******************************************************************
 * @file  ucp_mem_def.h
 * @brief:   两片UCP的内存分布头文件
 * @author: xuekun.zhang
 * @Date 2021年1月5日
 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
 * Change_date         Owner         Change_content
 * 2021年1月5日        xuekun.zhang       create file

*****************************************************************/

#ifndef     UCP_MEM_DEF_H
#define     UCP_MEM_DEF_H

//#include "interface_fapi_tasks.h"
//#include "interface_fapi_dl_lte.h"
//#include "interface_fapi_pusch.h"
//#include "interface_fapi_pucch.h"
//#include "interface_fapi_srs.h"
//#include "interface_fapi_dlctrl_lte.h"
//#include "interface_fapi_pbch_lte.h"
//#include "interface_pdcch_dl.h"
//#include "interface_fapi_prach.h"
#include "typedef.h"



//！命名宏定义时需要注意UCP使用的地址
/*********************************UCP************************************************/
//#define SM0_BASE                             (0x09D00000)//1M
//#define SM1_BASE                             (0x09E00000)//1M
//#define SM2_BASE                             (0x09F00000)//1.5M
//#define SM3_BASE                             (0x0A080000)//1.5M
//#define SM4_BASE                             (0x0A200000)//1.5M
//#define SM5_BASE                             (0x0A380000)//1.5M

/***************************************SM0-SM1--2M*********************************************/
//len define
//SM0
#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K

#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
#define SM0_RESERVED0_LEN                          0X00000400  //1K
#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
#define SM0_RESERVED1_LEN                          0x00000400  //1K
#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
#define SM0_RESERVED2_LEN                          0x00000400  //1K
#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
#define SM0_RESERVED3_LEN                          0x00000400  //1K
#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
#define SM0_RESERVED4_LEN                          0x00000400  //1K
#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
#define SM0_RESERVED5_LEN                          0x00005900  //22.25
#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
//SM1
#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00001E00//0x00000F00  //3.75k
#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00001E00//0x00000F00  //3.75k
#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
#define SM1_NR_CELL0_EVNE_RX_AGC_LEN               0x00001E00//0x00001400  //5k
#define SM1_NR_CELL0_ODD_RX_AGC_LEN                0x00001E00//0x00001400  //5k
#define SM1_NR_CELL1_EVNE_RX_AGC_LEN               0x00001400  //5k
#define SM1_NR_CELL1_ODD_RX_AGC_LEN                0x00001400  //5k
#define SM1_NR_CELL0_EVNE_TX_AGC_LEN               0x00001E00//0x00001400  //5k
#define SM1_NR_CELL0_ODD_TX_AGC_LEN                0x00001E00//0x00001400  //5k
#define SM1_NR_CELL1_EVNE_TX_AGC_LEN               0x00001400  //5k
#define SM1_NR_CELL1_ODD_TX_AGC_LEN                0x00001400  //5k
#define SM1_RESERVED0_LEN                          0x00014C00  //83k

#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE)
#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)

#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 

#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
//SM1
#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
#define SM1_NR_CELL0_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)  //5k
#define SM1_NR_CELL0_ODD_RX_AGC_ADDR               (SM1_NR_CELL0_EVNE_RX_AGC_ADDR+SM1_NR_CELL0_EVNE_RX_AGC_LEN)  //5k
#define SM1_NR_CELL1_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_ODD_RX_AGC_ADDR+SM1_NR_CELL0_ODD_RX_AGC_LEN)  //5k
#define SM1_NR_CELL1_ODD_RX_AGC_ADDR               (SM1_NR_CELL1_EVNE_RX_AGC_ADDR+SM1_NR_CELL1_EVNE_RX_AGC_LEN)  //5k
#define SM1_NR_CELL0_EVNE_TX_AGC_ADDR              (SM1_NR_CELL1_ODD_RX_AGC_ADDR+SM1_NR_CELL1_ODD_RX_AGC_LEN)  //5k
#define SM1_NR_CELL0_ODD_TX_AGC_ADDR               (SM1_NR_CELL0_EVNE_TX_AGC_ADDR+SM1_NR_CELL0_EVNE_TX_AGC_LEN)  //5k
#define SM1_NR_CELL1_EVNE_TX_AGC_ADDR              (SM1_NR_CELL0_ODD_TX_AGC_ADDR+SM1_NR_CELL0_ODD_TX_AGC_LEN)  //5k
#define SM1_NR_CELL1_ODD_TX_AGC_ADDR               (SM1_NR_CELL1_EVNE_TX_AGC_ADDR+SM1_NR_CELL1_EVNE_TX_AGC_LEN)  //5k
#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL1_ODD_TX_AGC_ADDR+SM1_NR_CELL1_ODD_TX_AGC_LEN)

/***************************************SM2-SM5--6M*********************************************/
//len define
#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
#define SM5_RESERVED0_LEN                          0x00034400  //209k
#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x0000E000  //56k
#define SM5_CPRI_CSU_LINK_TABLE_LEN                0x00002000  //8k

#define SM5_ERROR_RECORD_LEN                       0x00003000 //12k
#define SM5_NR_STATISTIC_LEN                       0x00000120 //288byte
#define SM5_STATE_RECORD_LEN                       0x000004E0 //1248byte
#define SM5_COMMON_DEBUG_LEN                       0x00000400 //1K
#define SM5_PDCCH_DEBUG_LEN                        0x00000400 //1K
#define SM5_PDSCH_DEBUG_LEN                        0x00000400 //1K
#define SM5_SSB_DEBUG_LEN                          0x00000400 //1K
#define SM5_CSIRS_DEBUG_LEN                        0x00000400 //1K
#define SM5_DEOFDM_DEBUG_LEN                       0x00000400 //1K
#define SM5_PUCCH_DEBUG_LEN                        0x00000400 //1K
#define SM5_PUSCH_DEBUG_LEN                        0x00000400 //1K
#define SM5_PRACH_DEBUG_LEN                        0x00000400 //1K
#define SM5_SRS_DEBUG_LEN                          0x00000400 //1K

#define SM5_ERROR_RECORD_CELL1_LEN                 SM5_ERROR_RECORD_LEN //12k
#define SM5_NR_STATISTIC_CELL1_LEN                 SM5_NR_STATISTIC_LEN //288byte
#define SM5_STATE_RECORD_CELL1_LEN                 SM5_STATE_RECORD_LEN //1248byte
#define SM5_COMMON_DEBUG_CELL1_LEN                 SM5_COMMON_DEBUG_LEN //1K
#define SM5_PDCCH_DEBUG_CELL1_LEN                  SM5_PDCCH_DEBUG_LEN  //1K
#define SM5_PDSCH_DEBUG_CELL1_LEN                  SM5_PDSCH_DEBUG_LEN  //1K
#define SM5_SSB_DEBUG_CELL1_LEN                    SM5_SSB_DEBUG_LEN    //1K
#define SM5_CSIRS_DEBUG_CELL1_LEN                  SM5_CSIRS_DEBUG_LEN  //1K
#define SM5_DEOFDM_DEBUG_CELL1_LEN                 SM5_DEOFDM_DEBUG_LEN //1K
#define SM5_PUCCH_DEBUG_CELL1_LEN                  SM5_PUCCH_DEBUG_LEN  //1K
#define SM5_PUSCH_DEBUG_CELL1_LEN                  SM5_PUSCH_DEBUG_LEN  //1K
#define SM5_PRACH_DEBUG_CELL1_LEN                  SM5_PRACH_DEBUG_LEN  //1K
#define SM5_SRS_DEBUG_CELL1_LEN                    SM5_SRS_DEBUG_LEN    //1K

#define SM5_RESERVED3_LEN                          0x0000D400 //53K

#define SM5_NR_CELL_TRACE_LEN \
    (SM5_ERROR_RECORD_LEN+SM5_NR_STATISTIC_LEN+SM5_STATE_RECORD_LEN+SM5_COMMON_DEBUG_LEN \
    +SM5_PDCCH_DEBUG_LEN+SM5_PDSCH_DEBUG_LEN+SM5_SSB_DEBUG_LEN+SM5_CSIRS_DEBUG_LEN+SM5_DEOFDM_DEBUG_LEN \
    +SM5_PUCCH_DEBUG_LEN+SM5_PUSCH_DEBUG_LEN+SM5_PRACH_DEBUG_LEN+SM5_SRS_DEBUG_LEN)

//addr define
#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE)
#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)

#define SM5_CPRI_CSU_LINK_TABLE_ADDR               (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)//0x0A4E5A00

#define SM5_ERROR_RECORD_ADDR                      (SM5_CPRI_CSU_LINK_TABLE_ADDR + SM5_CPRI_CSU_LINK_TABLE_LEN)
#define SM5_NR_STATISTIC_ADDR                      (SM5_ERROR_RECORD_ADDR + SM5_ERROR_RECORD_LEN)
#define SM5_STATE_RECORD_ADDR                      (SM5_NR_STATISTIC_ADDR + SM5_NR_STATISTIC_LEN)
#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_ADDR + SM5_STATE_RECORD_LEN)
#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)

#define SM5_ERROR_RECORD_CELL1_ADDR                (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
#define SM5_NR_STATISTIC_CELL1_ADDR                (SM5_ERROR_RECORD_CELL1_ADDR + SM5_ERROR_RECORD_CELL1_LEN)
#define SM5_STATE_RECORD_CELL1_ADDR                (SM5_NR_STATISTIC_CELL1_ADDR + SM5_NR_STATISTIC_CELL1_LEN)
#define SM5_COMMON_DEBUG_CELL1_ADDR                (SM5_STATE_RECORD_CELL1_ADDR + SM5_STATE_RECORD_CELL1_LEN)
#define SM5_PDCCH_DEBUG_CELL1_ADDR                 (SM5_COMMON_DEBUG_CELL1_ADDR + SM5_COMMON_DEBUG_CELL1_LEN)
#define SM5_PDSCH_DEBUG_CELL1_ADDR                 (SM5_PDCCH_DEBUG_CELL1_ADDR + SM5_PDCCH_DEBUG_CELL1_LEN)
#define SM5_SSB_DEBUG_CELL1_ADDR                   (SM5_PDSCH_DEBUG_CELL1_ADDR + SM5_PDSCH_DEBUG_CELL1_LEN)
#define SM5_CSIRS_DEBUG_CELL1_ADDR                 (SM5_SSB_DEBUG_CELL1_ADDR + SM5_SSB_DEBUG_CELL1_LEN)
#define SM5_DEOFDM_DEBUG_CELL1_ADDR                (SM5_CSIRS_DEBUG_CELL1_ADDR + SM5_CSIRS_DEBUG_CELL1_LEN)
#define SM5_PUCCH_DEBUG_CELL1_ADDR                 (SM5_DEOFDM_DEBUG_CELL1_ADDR + SM5_DEOFDM_DEBUG_CELL1_LEN)
#define SM5_PUSCH_DEBUG_CELL1_ADDR                 (SM5_PUCCH_DEBUG_CELL1_ADDR + SM5_PUCCH_DEBUG_CELL1_LEN)
#define SM5_PRACH_DEBUG_CELL1_ADDR                 (SM5_PUSCH_DEBUG_CELL1_ADDR + SM5_PUSCH_DEBUG_CELL1_LEN)
#define SM5_SRS_DEBUG_CELL1_ADDR                   (SM5_PRACH_DEBUG_CELL1_ADDR + SM5_PRACH_DEBUG_CELL1_LEN)

#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_CELL1_ADDR + SM5_SRS_DEBUG_CELL1_LEN)

#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
/**************************************DDR****************************************************/
/*******************************PUSCH HARQ 0x14400000-0x84C00000******************************/
#define DDR_NR_CELL0_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
#define DDR_NR_CELL0_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
#define DDR_NR_CELL0_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
#define DDR_NR_CELL0_SCRAMBLE_LEN           (0x14CB8) //(85176)
#define DDR_NR_CELL0_RNTI_LEN               (0x960)   //(2400)

#define DDR_NR_CELL0_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
#define DDR_NR_CELL0_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
#define DDR_NR_CELL0_DEOFDM_LEN             (0x7D000)   //(500*1024)

#define DDR_NR_CELL1_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
#define DDR_NR_CELL1_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
#define DDR_NR_CELL1_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
#define DDR_NR_CELL1_SCRAMBLE_LEN           (0x14CB8) //(85176)
#define DDR_NR_CELL1_RNTI_LEN               (0x960)   //(2400)

#define DDR_NR_CELL1_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
#define DDR_NR_CELL1_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
#define DDR_NR_CELL1_DEOFDM_LEN             (0x7D000)   //(500*1024)

//0x14400000-0x4C800000
#define DDR_NR_CELL0_SOFTBIT_PING_ADDR       (0x14400000) //(680*1024)
#define DDR_NR_CELL0_SOFTBIT_PANG_ADDR       (DDR_NR_CELL0_SOFTBIT_PING_ADDR+DDR_NR_CELL0_SOFTBIT_PING_LEN) //(680*1024)
#define DDR_NR_CELL0_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL0_SOFTBIT_PANG_ADDR+DDR_NR_CELL0_SOFTBIT_PANG_LEN)//(419328*14)
#define DDR_NR_CELL0_SCRAMBLE_ADDR           (DDR_NR_CELL0_MME_FREQ_CPTS_ADDR+DDR_NR_CELL0_MME_FREQ_CPTS_LEN) //(85176)
#define DDR_NR_CELL0_RNTI_ADDR               (DDR_NR_CELL0_SCRAMBLE_ADDR+DDR_NR_CELL0_SCRAMBLE_LEN)   //(2400)

#define DDR_NR_CELL0_HARQ_INFO_ADDR          (DDR_NR_CELL0_RNTI_ADDR+DDR_NR_CELL0_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
#define DDR_NR_CELL0_TB_DECODE_ADDR          (DDR_NR_CELL0_HARQ_INFO_ADDR+DDR_NR_CELL0_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
#define DDR_NR_CELL0_DEOFDM_ADDR             (DDR_NR_CELL0_TB_DECODE_ADDR+DDR_NR_CELL0_TB_DECODE_LEN)   //(500*1024)

//0x4C800000-0x84C00000
#define DDR_NR_CELL1_SOFTBIT_PING_ADDR       (0x4C800000) //(680*1024)
#define DDR_NR_CELL1_SOFTBIT_PANG_ADDR       (DDR_NR_CELL1_SOFTBIT_PING_ADDR+DDR_NR_CELL1_SOFTBIT_PING_LEN) //(680*1024)
#define DDR_NR_CELL1_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL1_SOFTBIT_PANG_ADDR+DDR_NR_CELL1_SOFTBIT_PANG_LEN)//(419328*14)
#define DDR_NR_CELL1_SCRAMBLE_ADDR           (DDR_NR_CELL1_MME_FREQ_CPTS_ADDR+DDR_NR_CELL1_MME_FREQ_CPTS_LEN) //(85176)
#define DDR_NR_CELL1_RNTI_ADDR               (DDR_NR_CELL1_SCRAMBLE_ADDR+DDR_NR_CELL1_SCRAMBLE_LEN)   //(2400)

#define DDR_NR_CELL1_HARQ_INFO_ADDR          (DDR_NR_CELL1_RNTI_ADDR+DDR_NR_CELL1_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
#define DDR_NR_CELL1_TB_DECODE_ADDR          (DDR_NR_CELL1_HARQ_INFO_ADDR+DDR_NR_CELL1_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
#define DDR_NR_CELL1_DEOFDM_ADDR             (DDR_NR_CELL1_TB_DECODE_ADDR+DDR_NR_CELL1_TB_DECODE_LEN)   //(500*1024)

/*******************************共180+192M可用0x84C00000-0x9C000000***************************/
//len
#define DDR_NR_CELL0_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
#define DDR_NR_CELL1_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
#define DDR_TEST_MAC_DL_DATA_BUF_LEN   (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
#define DDR_WRITE_MONITOR_LEN          (0x400000)//预留4M空间给写DDR检查功能
#define DDR_READ_MONITOR_LEN           (0X400000)//预留4M空间给读DDR检查功能

//addr
#define DDR_PHY_BASE                         (0x84C00000)
#define DDR_TEST_MAC_NR_CELL0_RX_DATA_ADDR   (0x84C00000)//0x84C00000 ~ 0x85100000 
#define DDR_TEST_MAC_NR_CELL1_RX_DATA_ADDR   (0x85100000)//0x85100000 ~ 0x85600000

#define DDR_PHY_RECORD_ADDR                  (0x85600000)//0x85600000 ~ 0x86000000
#define DDR_NR_DL_RECORD_ADDR                (0x85600000)//0x85600000 ~ 0x87600000 32M
#define DDR_NR_UL_RECORD_ADDR                (0x87600000)//0x87600000 ~ 0x89600000 32M
#define DDR_NR_DL1_RECORD_ADDR               (0x89600000)//0x89600000 ~ 0x8B600000 32M
#define DDR_NR_UL1_RECORD_ADDR               (0x8B600000)//0x8B600000 ~ 0x8D600000 32M

#define DDR_TEST_MAC_DL_DATA_BUF_ADDR        (0x8D600000)//testmac预留20M,缓存DL的IQ数据      		//0x8D600000 ~ 0x8EA00000

#define DDR_WRITE_MONITOR_ADDR               (0x8EA00000)//预留4M空间给写DDR检查功能					//0x8B400000 ~ 0X8EE00000
#define DDR_READ_MONITOR_ADDR                (0x8EE00000)//预留4M空间给读DDR检查功能

#define DDR_MAX_ADDR                         (0x90000000)

//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
//void Config_Cpri_Csu_Lte();
void Config_Cpri_Csu_Nr(uint8_t slot_format);


#endif

