/******************************************************************
 * @file  phy_timer_csu_config.h
 * @brief:    [file description] 
 * @author: guicheng.liu
 * @Date 2022年7月7日
 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
 * Change_date         Owner         Change_content
 * 2022年7月7日        guicheng.liu       create file

*****************************************************************/

#ifndef     FPHY_TIMER_CSU_CONFIG_H
#define     FPHY_TIMER_CSU_CONFIG_H
//#include <type_define.h>
//#include "phy_nr_context.h"
//#include "drv_rfm.h"


#include "typedef.h"
#include "nr_mem_def.h"
#include "phy_para.h"

//#define CPRI_LINK_START_ADDR						0x721E000 //ECS SM后8K 0x721E000- 0x7220000
#define CPRI_NR_FDD_LINK_START_ADDR                 SM5_CPRI_CSU_LINK_TABLE_ADDR//更换为SM的地址

#define NR_LONGCP_SAM_CNT								4448
#define NR_SHORTCP_SAM_CNT								4384

typedef struct
{
    uint16_t period;//=t_us*num_t;
    uint16_t rev;

    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
}timer_info_t;

typedef struct
{
    uint8_t flag;//0:default timer, 1:inuse timer
    uint8_t rev[3];

    timer_info_t default_timer;
    timer_info_t inuse_timer;
}phy_timer_t;

typedef struct
{
    uint8_t total_ants;
    uint8_t scs;
    uint8_t num_dl_symbols;
    uint8_t rev;

    uint16_t num_dl_tti;
    uint16_t rev1;

    phy_timer_config_ind_t jesd_timer;
    phy_timer_config_ind_t cpri_timer;
}phy_csu_timer_t;

typedef struct
{
    uint32_t state;//0:idle, 1:configured

    //tx的链表地址
    uint32_t tx0_even_f7_link_addr;
    uint32_t tx0_even_b7_link_addr;
    uint32_t tx0_odd_f7_link_addr;
    uint32_t tx0_odd_b7_link_addr;
    uint32_t tx0_s_link_addr;
    uint32_t tx0_1st_dummy_link_addr;
    uint32_t tx0_2nd_dummy_link_addr;

    //rx的链表地址
    uint32_t rx0_first_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot尾部的数据
    uint32_t rx0_dummy_link_addr;
    uint32_t rx0_s_link_addr;
    uint32_t rx0_normal0_link_addr;
    uint32_t rx0_normal1_link_addr;
    uint32_t rx0_last_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot头部的数据
}phy_csu_link_info_t;


void Phy_Timer_Csu_Init();

//void Csu_Dma_Init();
//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
//                                uint8_t num_tx0_ants, 
//                                uint16_t num_tx_tti);
//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
//                                uint8_t num_tx0_ants, 
//                                uint16_t num_tx_tti);
//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
//                                uint8_t num_rx0_ants, 
//                                uint16_t num_rx_tti);
//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
//                                uint8_t num_rx1_ants, 
//                                uint16_t num_rx_tti);
void Config_Csu_Timer(uint16_t dl_bw,
                            uint16_t num_tx_ants,
                            uint8_t nrOfSlots,
                            uint16_t num_dl_tti,

                            uint8_t num_dl_symbols,
                            uint8_t num_ul_symbols,
                            uint8_t scs,
                            uint32_t run_core_id_map);
//void Update_Phy_Timer(uint8_t tdd_period);

//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);


#endif
