/******************************************************************
 * @file  Fphy_Timer_Csu_Config.s.c
 * @brief:    [file description] 
 * @author: guicheng.liu
 * @Date 2022年7月7日
 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
 * Change_date         Owner         Change_content
 * 2022年7月7日        guicheng.liu       create file

*****************************************************************/

/**************************include******************************/
//#include "type_define.h"
//#include "lte_common.h"
//#include "log_interface.h"
//#include "phy_timer_csu_config.h"
//#include "ecs_common.h"
#include "lte_mem_def.h"
#include "cpri_csu_api.h"
#include "cpri_csu_nr_7ds2u.h"


//#include "rfm_interface.h"

/**************************function******************************/
//phy_csu_timer_t g_phy_csu_timer;
//phy_csu_dma_t g_phy_csu_dma;
//phy_timer_t g_phy_timer;
phy_csu_link_info_t g_phy_lte_csu_link;

 /*!   
 * @brief:  LTE Jesd 参数的初始化
 * @author:  shibo.weng
 * @Date:  2022年11月15日
 */
void Phy_Lte_Timer_Csu_Init()
{
#if 0
    uint16_t t_us = 1000;//物理层子帧定时长度1000us
    uint16_t num_t = 10;//timer周期内子帧个数

    memset(&g_phy_timer, 0, sizeof(phy_timer_t));
    memset(&g_phy_csu_timer, 0, sizeof(phy_csu_timer_t));
    memset(&g_phy_csu_dma, 0, sizeof(phy_csu_dma_t));
    memset(&g_phy_lte_csu_link, 0, sizeof(phy_csu_link_info_t));

    //初始默认,子帧个数10, 子帧长度1ms,Timer为10*1ms=10ms周期
    g_phy_timer.flag = 0;
    g_phy_timer.default_timer.period = t_us*num_t;
    g_phy_timer.default_timer.t_us = t_us;
    g_phy_timer.default_timer.num_t = num_t;
#endif
    //start_cpri_timer(t_us, num_t);
    //tx的链表地址
    g_phy_lte_csu_link.tx_even_link_addr  = CPRI_LINK_START_ADDR; // 0x721E800;
    g_phy_lte_csu_link.tx_odd_link_addr   = CPRI_LINK_START_ADDR + 1*0x200; // 0x721EA00;
    g_phy_lte_csu_link.tx_last_link_addr  = CPRI_LINK_START_ADDR + 2*0x200; // 0x721EC00;

    //rx的链表地址
    g_phy_lte_csu_link.rx_first_link_addr = CPRI_LINK_START_ADDR + 3*0x200; // 0x721EE00;
    g_phy_lte_csu_link.rx_even_link_addr  = CPRI_LINK_START_ADDR + 4*0x200; // 0x721F000;
    g_phy_lte_csu_link.rx_odd_link_addr   = CPRI_LINK_START_ADDR + 5*0x200; // 0x721F200;
}

#if 0

/*!   
* @brief:  获取slot/subframe长度
* @author:  guicheng.liu
* @Date:  2022年7月8日
* @param: scs :              [scs]
*/
uint16_t get_tti_us(uint8_t scs)
{
    uint16_t t_us = 0;

    switch(scs)
    {
        case 0: 
        {
            t_us = 1000;
            break;
        }
        case 1: 
        {
            t_us = 500;
            break;
        }
        case 2:
        {
            t_us = 250;
            break;
        }
        case 3:
        {
            t_us = 125;
            break;
        }
        default:
        {
            t_us = 500;
            break;
        }
    }	

    return t_us;
}

/*!   
* @brief:  根据带宽计算采样率
* @author:  guicheng.liu
* @Date:  2022年7月9日
* @param: dl_bw :            [带宽]
*/
uint32_t get_sampling_rate(uint16_t dl_bw)
{
    uint32_t sampling_rate = 0;

    switch(dl_bw)
    {
        case 100:
        {
            sampling_rate = 122880000;
            break;
        }
        case 80 :
        {
            sampling_rate = 122880000;
            break;
        }
        case 60:
        {
            sampling_rate = 122880000;
            break;
        }
        case 50:
        {
            sampling_rate = 122880000;
            break;
        }
        case 40:
        {
            sampling_rate = 122880000;
            break;
        }
        case 20:
        {
            sampling_rate =  30720000;
            break;
        }
        case 15:
        {
            sampling_rate = 23040000;
            break;
        }
        case 10:
        {
            sampling_rate = 15360000;
            break;
        }
        case 5:
        {
            sampling_rate = 7680000;
            break;
        }
        default:
        {
            sampling_rate = 122880000;
            break;
        }
    }

    return sampling_rate;
}
#endif
/*!   
* @brief:  CPRI CSU初始化
* @author:  guicheng.liu
* @Date:  2023年2月2日
*/
void Cpri_Csu_Init()
{
    uint32_t fifo_num = 4;//初始化4个FIFO通道(RX_AXC_DATA:CmdFIFO0, RX_AXC_CTRL:CmdFIFO2, TX_AXC_DATA:CmdFIFO1, TX_AXC_CTRL:CmdFIFO3)
    uint32_t dma_reg_group_num = 32;//清空CPRI的32组DMA参数寄存器
    uint32_t tag_mask = 0xFFFFFFFF;//DMA TAG全部不屏蔽

    UCP_API_CPRI_CSU_Init(fifo_num, dma_reg_group_num, tag_mask);
}

 /*!   
 * @brief:  
 * @author:  guicheng.liu
 * @Date:  2023年3月16日
 * @param: axc_id_num :       [param description ]
 * @param: rx_cycle_num :     [param description ]
 */
void Cpri_Csu_Latch_Init(uint32_t axc_id_num, uint32_t in_latch_num, uint32_t out_latch_num, uint32_t rx_cycle_num)
{
    uint32_t index = 0;
    uint32_t tx0_rfp_set= 0;//[18:16]TX_AXC_DATA 通道开始工作后，提前发送的 Base Frame 的个数[8] 0:上升沿敏感 1: 高电平敏感
                            //[7:0]CSU捕捉到CPRI 端接口信号TX_AUX_CNT_POS 第一次为此数值后,延迟2个CSU                   的主时钟周期再次启动发送数据的工作
    uint32_t tx0_port_info[64] = {0};//共64个port, 
                        			//[31:26] CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的 ID 值
                        			//[25:20]CPRI 模式 CSU 的 TX_AXC_DATA通道端口x的每拍有效比特数
                        			//[19:1]CPRI 模式 CSU 的 TX_AXC_DATA通道一个Basic Frame 中端口x的总比特数
                        			//[0]0:比特反序未使能 1:比特反序使能
    uint32_t tx0_latch_info_l[8] = {0}; //8个latch info配置，[24]bit_revert_enable 
                                        //[19:0]CPRI模式CSU的TX_AXC_DATA通道的OutLatch参数,     值为一个Basic Frame中在此OutLatch中缓存的所有端口的总比特数

    uint32_t tx0_latch_info_m[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*3  
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N
    uint32_t tx0_latch_info_h[8] = {0}; //8个latch info配置
                                        //[24:16]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*7
                                        //[8:0]CPRI 模式 CSU 的 TX_AXC_DATA 通道的OutLatch 参数，值为 CPRI_LATCH_N*5

    uint32_t rx0_port_info[64] = {0};//共64个port, [27:22]bit_number_one_cyclex [20:1]bit_number_one_basic_framex [0]bit_revert_enable
    uint32_t rx0_latch_info_l[8] = {0};//8个latch info配置，[24]bit_revert_enable  [19:0]bit_number_one_basic_frame
    uint32_t rx0_latch_info_h[8] = {0};//8个latch info配置，
                            			//[31]cpri_latch_n_7_times_bigger_than_128 =0： CPRI_LATCH_N*7 不大于 128, =1： CPRI_LATCH_N*7 大于128
                            			//[30:24]cpri_latch_n_7_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*7
                            			//[23]cpri_latch_n_5_times_bigger_than_128  0： CPRI_LATCH_N*5 不大于 128, 1： CPRI_LATCH_N*5 大于128
                            			//[22:16]cpri_latch_n_5_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*5
                            			//[15]cpri_latch_n_3_times_bigger_than_128  0： CPRI_LATCH_N*3 不大于 128, 1： CPRI_LATCH_N*3 大于128
                            			//[14:8]cpri_latch_n_3_times CPRI 模式 CSU 的 RX_AXC_DATA 通道的InLatch 参数，值为 CPRI_LATCH_N*3
                            			//[6:0]cpri_latch_n
	uint32_t rx0_cycle_num[8] = {0};//8个latch info配置,
	                                //[7:0]CPRI模式CSU的RX_AXC_DATA通道的InLatch参数,值为该InLatch中连续接收的Basic Frame的个数减一
    uint32_t inlatch_index = 0;
    //uint32_t rx_cycle_num = 32;
//	uint32_t bit_per_bf[10] = {16,8,512,512,512,512,128,128,16,8};  //压缩因子是NR:2byte, 16bit,LTE:1byte, 8bit
	uint32_t bit_per_bf[9] = {16,8,512,512,512,512,128,128,24};                                                                //数据是NR:4天线,每个64byte,512bit,LTE:2天线,每个16byte,128bit
	                                                                //AGC NR:2byte, 16bit,LTE:1byte, 8bit
//    uint32_t bit_per_cycle[10] = {16,8,0,0,0,0,0,0,16,8}; //0:表示64, 非0:有效比特数为数值本身
	uint32_t bit_per_cycle[9] = {16,8,0,0,0,0,0,0,24}; 

	
 //   uint32_t bit_per_bf_for_latch[7] = {16,8,1024,1024,256,16,8};  //压缩因子是NR:2byte, 16bit,LTE:1byte, 8bit
                                                                    //数据是NR:4天线,每个64byte,两个天线共用一个latch:512bit+512bit=1024,
                                                                    //LTE:2天线,每个16byte,两个天线共用一个latch:128bit+128bit=256bit
                                                                    //AGC NR:2byte, 16bit,LTE:1byte, 8bit
   uint32_t bit_per_bf_for_latch[6] = {16,8,1024,1024,256,24}; 

    for (index = 0; index < axc_id_num; index++)
    {
        //tx0_port_info[index] = ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));     
		tx0_port_info[index] = 0x1 | ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));//bit反序使能
#if 0
		if((index < 2) || (index == 8) )
		{
			tx0_port_info[index] = 0x1 | ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));//bit反序使能
		}
		else
		{
			tx0_port_info[index] = ((bit_per_bf[index]<<1) | (bit_per_cycle[index] <<20) | (index << 26));//bit未反序使能
		}
#endif

    }

 
    for (index = 0; index < out_latch_num; index++)
    {

#if 0//xin tong
		if(index < 2 )
		{
			tx0_latch_info_l[index] = (0x1<<24ul) | bit_per_bf_for_latch[index];//bit反序使能
		}
	    else
    	{
    		tx0_latch_info_l[index] =  bit_per_bf_for_latch[index];//bit反序使能
    	}
#endif
	    
#if 1//dian ge
		tx0_latch_info_l[index] = (0x1<<24ul) | bit_per_bf_for_latch[index];//bit反序使能
#endif   
	    tx0_latch_info_m[index] = 0x180008;//CPRI_LATCH_N??bit反序??
	    tx0_latch_info_h[index] = 0x380028;
    }

    //[7:0]CSU捕捉到CPRI端接口信号TX_AUX_CNT_POS第一次为此数值后，延迟2个CSU的主时钟周期再次启动发送数据的工作RfpPoint=0x1 can send 4
    //TX_AXC_DATA[18:16] 通道开始工作后，提前发送的Base Frame的个数push 4 basic frame at 1st tx_axc_rfp
    tx0_rfp_set = 0x40001;

    UCP_API_CPRI_CSU_TxOutLatch_Cfg(axc_id_num, 
                                    tx0_rfp_set, 
                                    tx0_port_info, 
                                    out_latch_num,
                                    tx0_latch_info_l, 
                                    tx0_latch_info_m, 
                                    tx0_latch_info_h);

#if 0
		JECS_CSU_LATCHALFULL = 0x2;
		JECS_CSU_LATCHALFULL = 0x80000040;
		JECS_CSU_EM_BS_SMSEL_PREDATANUM = (0x1<<14) | (0x3<<5) | 0x4;
		JECS_CSU_EM_BS_SMSEL_PREDATANUM = (0x3<<14) | (0x3<<5) | 0x4;
#endif


    for (index = 0; index < axc_id_num; index++)
    {
        rx0_port_info[index] =  0x1 | ((bit_per_bf[index]<<1)|(bit_per_cycle[index]<<22));
#if 0
		if((index < 2) || (index == 8) )
		{
			rx0_port_info[index] =  0x1 | ((bit_per_bf[index]<<1)|(bit_per_cycle[index]<<22));
		}
		else
		{
			rx0_port_info[index] =  ((bit_per_bf[index]<<1)|(bit_per_cycle[index]<<22));
		}
#endif


    }

    for (index = 0; index < in_latch_num; index++)
    {
#if 0//xin tong
     if(index < 2 )
 	{
		rx0_latch_info_l[index] =  (0x1<<24ul) | bit_per_bf_for_latch[index];
 	}
	 else
 	{
 		rx0_latch_info_l[index] =  bit_per_bf_for_latch[index];
 	}
#endif
#if 1//dian ge
		rx0_latch_info_l[index] =	(0x1<<24ul) | bit_per_bf_for_latch[index];
#endif
        rx0_latch_info_h[index] =  0x38281808;
        rx0_cycle_num[index] = rx_cycle_num - 1;
    }

    UCP_API_CPRI_CSU_RxInLatch_Cfg(axc_id_num,
                                    rx0_port_info,
                                    in_latch_num,
                                    rx0_latch_info_l,
                                    rx0_latch_info_h,
                                    rx0_cycle_num);

    UCP_API_CPRI_CSU_RxInLatchThres_Cfg(inlatch_index,
                                        1,//w_r_flag,
                                        0x10,//send_threshold,
                                        0x40);//almostfull_threshold);

    //先去使能
	UCP_API_CPRI_CSU_TXAxcData_ChannelCtrl(0, axc_id_num, out_latch_num);
	UCP_API_CPRI_CSU_RXAxcData_ChannelCtrl(0, in_latch_num);
}


 /*!   
 * @brief:  
 * @author:  guicheng.liu
 * @Date:  2023年3月16日
 * @param: cell :             [param description ]
 * @param: axc_id_num :       [param description ]
 * @param: rx_cycle_num :     [param description ]
 * @param: tx_cycle_num :     [param description ]
 */
//void Cpri_Csu_Link_Init(lte_cell_info_t* cell, 
//    uint32_t axc_id_num, 
//    uint32_t in_latch_num, 
//    uint32_t out_latch_num, 
//    uint32_t rx_cycle_num, 
//    uint32_t tx_cycle_num)
void Cpri_Csu_Link_Init(
	uint32_t axc_id_num, 
	uint32_t in_latch_num, 
	uint32_t out_latch_num, 
	uint32_t rx_cycle_num, 
	uint32_t tx_cycle_num)
{
    uint32_t CGran = 0;

//    uint32_t rx_first_dma_flag = 0;

    uint32_t axc_id = 0;
    uint32_t latch_id = 0;
    uint32_t xnum = 0;
    uint32_t allnum = 0;
    uint32_t size = 0;
    uint32_t tx_src_addr = 0;
    uint32_t rx_dst_addr = 0;
    uint32_t comp_facter_addr_offset = 0;
    uint32_t agc_facter_addr_offset = 0;
//    uint32_t rx_addr_offset = 0;

    uint32_t i = 0;
    uint32_t bf_num = 0;

    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=5个节点的链表
    phy_csu_link_info_t* link = &g_phy_lte_csu_link;

    //tx的链表地址
    uint32_t tx_even_link_addr  = link->tx_even_link_addr; // 0x721E800;
    uint32_t tx_odd_link_addr   = link->tx_odd_link_addr; // 0x721EA00;
    uint32_t tx_last_link_addr  = link->tx_last_link_addr; // 0x721EC00;

    //rx的链表地址
    uint32_t rx_first_link_addr = link->rx_first_link_addr; // 0x721EE00;
    uint32_t rx_even_link_addr  = link->rx_even_link_addr; // 0x721F000;
    uint32_t rx_odd_link_addr   = link->rx_odd_link_addr; // 0x721F200;

    /*
        驱动采用2.5ms周期压FIFO命令的方式,故5ms周期需要两个3+2的方式填写LTE链表
        目前配置只考虑LTE,NR数据采用dummy方式
    */

	//TX:偶时隙
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
        CGran = 0;
        latch_id = i;
    	if (0 == i)
    	{
            size = 2;//NR压缩因子，一个BF 2B
            bf_num = (61440*2*2)/64;//基本帧个数, 时长1ms, 2:slot长度, 2:一个样点压缩之后的数据长度
            allnum = size*bf_num;
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;//CSU_TX_DUMMYBUFFER_ADDR;//NR的源数据地址暂时填dummy,等确定双模的具体模式之后再填
            comp_facter_addr_offset = allnum;
    	}
    	else if (1 == i)
    	{
            size = 1;//LTE压缩因子，一个BF 1B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
//            tx_src_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_even_com_fact_tx_addr);
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_EVEN_COM_FACT_ADDR;
            latch_id = 1;
    	}
    	else if ((2 == i) || (3 == i))
    	{
            size = 64*2;//NR AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2*2*2);//1ms, 2:slot长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
            if(2 == i)
        	{
        		tx_src_addr = (uint32_t)SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0;//CSU_TX_DUMMYBUFFER_ADDR;
        	}
			else
			{
				tx_src_addr = (uint32_t)SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1;//CSU_TX_DUMMYBUFFER_ADDR;
			}         
    	}
    	else if (4 == i)
        {
            size = 16*2;//LTE AxC数据，一个BF有2个AxC 16B
            allnum = (30720*2*2);//1ms, 1:subframe长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
//            tx_src_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_even_tx_addr);
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI;
        }
    	else// if (5 == i)
        {
          //  size = 2;//NR AGC因子，一个BF 2B
            size = 3;//AGC因子，一个BF 3B
            bf_num = (61440*2*2)/64;
            allnum = size*bf_num;//1ms, 2 slot长度
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_EVEN_COM_AGC_ADDR;
            agc_facter_addr_offset = allnum;
        }
		/*******
    	else //if (6 == i)
        {
            size = 1;//LTE AGC因子，一个BF 2B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_EVEN_COM_AGC_ADDR;
            agc_facter_addr_offset = allnum;
        }
**********/
        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx_even_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx_even_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:奇时隙
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
        CGran = 0;
        latch_id = i;
    	if (0 == i)
    	{
            size = 2;//NR压缩因子，一个BF 2B
            bf_num = (61440*2*2)/64;//1ms, 2 slot长度
            allnum = size*bf_num;
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR;//CSU_TX_DUMMYBUFFER_ADDR;//NR的源数据地址暂时填dummy,等确定双模的具体模式之后再填
            comp_facter_addr_offset = allnum;
    	}
    	else if (1 == i)
    	{
            size = 1;//LTE压缩因子，一个BF 1B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
//            tx_src_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_odd_com_fact_tx_addr);
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_FACT_ADDR;
            comp_facter_addr_offset = allnum;
            latch_id = 1;
    	}
    	else if ((2 == i) || (3 == i))
    	{
            size = 64*2;//NR AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2*2*2);//1ms, 2:slot长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
            if(2 == i)
        	{
        		tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0;//CSU_TX_DUMMYBUFFER_ADDR;
        	}
			else
			{
				tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1;//CSU_TX_DUMMYBUFFER_ADDR;
			}
    	}
    	else if (4 == i)
        {
            size = 16*2;//LTE AxC数据，一个BF有2个AxC 16B
            allnum = (30720*2*2);//1ms, 1:subframe长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
//            tx_src_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_odd_tx_addr);
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_TX_ADDR_CPRI;
        }
    	else //if (5 == i)
        {
         //   size = 2;//NR AGC因子，一个BF 2B
            size = 3;//AGC因子，一个BF 3B
            bf_num = (61440*2*2)/64;
            allnum = size*bf_num;//1ms, 2 slot长度
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_AGC_ADDR;//CSU_TX_DUMMYBUFFER_ADDR;
            agc_facter_addr_offset = allnum;
        }
		/*******
    	else //if (6 == i)
        {
            size = 1;//LTE AGC因子，一个BF 2B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_AGC_ADDR;//CSU_TX_DUMMYBUFFER_ADDR;
            agc_facter_addr_offset = allnum;
        }
		*******/

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx_odd_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx_odd_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//TX:10ms最后一个链表
	for (i = 0; i < out_latch_num; i++)
	{
    	axc_id = i;
        CGran = 0;
        latch_id = i;
    	if (0 == i)
    	{
            size = 2;//NR压缩因子，一个BF 2B
            bf_num = (61440*2*2)/64;//1ms, 2 slot长度
            allnum = size*bf_num;
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR;//CSU_TX_DUMMYBUFFER_ADDR;//NR的源数据地址暂时填dummy,等确定双模的具体模式之后再填
            comp_facter_addr_offset = allnum;
    	}
    	else if (1 == i)
    	{
            size = 1;//LTE压缩因子，一个BF 1B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
//            tx_src_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_odd_com_fact_tx_addr);
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_FACT_ADDR;
            comp_facter_addr_offset = allnum;
            latch_id = 1;
    	}
    	else if ((2 == i) || (3 == i))
    	{
            size = 64*2;//NR AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2*2*2);//1ms, 2:slot长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
           if(2 == i)
        	{
        		tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0;//CSU_TX_DUMMYBUFFER_ADDR;
        	}
			else
			{
				tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1;//CSU_TX_DUMMYBUFFER_ADDR;
			}
    	}
    	else if (4 == i)
        {
            size = 16*2;//LTE AxC数据，一个BF有2个AxC 16B
            allnum = (30720*2*2);//1ms, 1:subframe长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
//            tx_src_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_odd_tx_addr);
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_TX_ADDR_CPRI;
        }
    	else //if (5 == i)
        {
         //   size = 2;//NR AGC因子，一个BF 2B
            size = 3;//AGC因子，一个BF 3B
            bf_num = (61440*2*2)/64;
            allnum = size*bf_num;//1ms, 2 slot长度
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_AGC_ADDR;//CSU_TX_DUMMYBUFFER_ADDR;
            agc_facter_addr_offset = allnum;
			CGran = 1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
        }
		/*******
    	else //if (6 == i)
        {
            size = 1;//LTE AGC因子，一个BF 2B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
            tx_src_addr = (uint32_t)SM0_LTE_CELL0_ODD_COM_AGC_ADDR;//CSU_TX_DUMMYBUFFER_ADDR;
            agc_facter_addr_offset = allnum;
			CGran = 1;//TX发送，每个循环链表中的最后一个节点中的GRAN[3]需要配置成1
        }
		*******/

        xnum = size*tx_cycle_num;

    	//TX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx_last_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            NONCPRIENDFLAG,
                                            tx_src_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            0,
                                            0);
       	//TX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)tx_last_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            0,
                                            CGran,
                                            0);
    }

	//RX:占用连续的DDR地址
	//RX:第一个子帧
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
        CGran = 1;//当 DMA 为 RX_AXC_RFP信号之后的第一个DMA 时，此 DMA 的参数 GRAN[3]需置为1
                  //[36]节点信息命令字里的first_dma要置1
        latch_id = i;
    	if (0 == i)
    	{
            size = 2;//NR压缩因子，一个BF 2B
            bf_num = (61440*2*2)/64;//1ms, 2:slot长度, 2:一个样点压缩之后的数据长度
            allnum = size*bf_num;
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;//CSU_RX_DUMMYBUFFER_ADDR;//NR的源数据地址暂时填dummy,等确定双模的具体模式之后再填
    	}
    	else if (1 == i)
    	{
            size = 1;//LTE压缩因子，一个BF 1B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
//            rx_dst_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_even_rx_com_fact_addr);
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_FACT_ADDR;
        }
    	else if ((2 == i) || (3 == i))
    	{
            size = 64*2;//NR AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2*2*2);//1ms, 2:slot长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
            if(2 == i)
        	{
        		rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0;//CSU_RX_DUMMYBUFFER_ADDR;
        	}
			else
			{
				rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1;//CSU_RX_DUMMYBUFFER_ADDR;
			}
    	}
    	else if (4 == i)
        {
            size = 16*2;//LTE AxC数据，一个BF有2个AxC 16B
            allnum = (30720*2*2);//1ms, 1:subframe长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
//            rx_dst_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_even_rx_addr);
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI;
        }
    	else// if (5 == i)
        {
         //   size = 2;//NR AGC因子，一个BF 2B
            size = 3;//AGC因子，一个BF 3B
            bf_num = (61440*2*2)/64;
            allnum = size*bf_num;//1ms, 2 slot长度
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;//CSU_RX_DUMMYBUFFER_ADDR;
        }
		/*******
    	else //if (6 == i)
        {
            size = 1;//LTE AGC因子，一个BF 2B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;//CSU_RX_DUMMYBUFFER_ADDR;
        }
		*******/

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx_first_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx_first_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
    }

	//RX:偶时隙
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
        CGran = 0;
        latch_id = i;
    	if (0 == i)
    	{
            size = 2;//NR压缩因子，一个BF 2B
            bf_num = (61440*2*2)/64;//1ms, 2:slot长度, 2:一个样点压缩之后的数据长度
            allnum = size*bf_num;
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;//CSU_RX_DUMMYBUFFER_ADDR;//NR的源数据地址暂时填dummy,等确定双模的具体模式之后再填
    	}
    	else if (1 == i)
    	{
            size = 1;//LTE压缩因子，一个BF 1B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
//            rx_dst_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_even_rx_com_fact_addr);
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_FACT_ADDR;
    	}
    	else if ((2 == i) || (3 == i))
    	{
            size = 64*2;//NR AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2*2*2);//1ms, 2:slot长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
           	if(2 == i)
        	{
        		rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0;//CSU_RX_DUMMYBUFFER_ADDR;
        	}
			else
			{
				rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1;//CSU_RX_DUMMYBUFFER_ADDR;
			}
    	}
    	else if (4 == i)
        {
            size = 16*2;//LTE AxC数据，一个BF有2个AxC 16B
            allnum = (30720*2*2);//1ms, 1:subframe长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
//            rx_dst_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_even_rx_addr);
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI;
        }
    	else //if (5 == i)
        {
         //   size = 2;//NR AGC因子，一个BF 2B
            size = 3;//AGC因子，一个BF 3B
            bf_num = (61440*2*2)/64;
            allnum = size*bf_num;//1ms, 2 slot长度
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;//CSU_RX_DUMMYBUFFER_ADDR;
        }
		/*******
    	else// if (6 == i)
        {
            size = 1;//LTE AGC因子，一个BF 2B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;//CSU_RX_DUMMYBUFFER_ADDR;
        }
		*******/

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx_even_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx_even_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
    }

	//RX:奇时隙
	for(i = 0; i < in_latch_num; i++)
	{
    	axc_id = i;
        CGran = 0;
        latch_id = i;
    	if (0 == i)
    	{
            size = 2;//NR压缩因子，一个BF 2B
            bf_num = (61440*2*2)/64;//1ms, 2:slot长度, 2:一个样点压缩之后的数据长度
            allnum = size*bf_num;
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR;//CSU_RX_DUMMYBUFFER_ADDR;//NR的源数据地址暂时填dummy,等确定双模的具体模式之后再填
    	}
    	else if (1 == i)
    	{
            size = 1;//LTE压缩因子，一个BF 1B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
//            rx_dst_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_odd_rx_com_fact_addr);
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_ODD_COM_FACT_ADDR;
    	}
    	else if ((2 == i) || (3 == i))
    	{
            size = 64*2;//NR AxC数据，一个BF有4个AxC 64B
            allnum = (61440*2*2*2);//1ms, 2:slot长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
            if(2 == i)
        	{
        		rx_dst_addr = (uint32_t)SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0;//CSU_RX_DUMMYBUFFER_ADDR;
        	}
			else
			{
				rx_dst_addr = (uint32_t)SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1;//CSU_RX_DUMMYBUFFER_ADDR;
			}
    	}
    	else if (4 == i)
        {
            size = 16*2;//LTE AxC数据，一个BF有2个AxC 16B
            allnum = (30720*2*2);//1ms, 1:subframe长度, 2:两天线交织, 2:一个样点压缩之后的数据长度
//            rx_dst_addr = (uint32_t)LOAD_EX_W(&cell->tasks_inf_ptr->lte_cell_odd_rx_addr);
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_ODD_RX_ADDR_CPRI;
        }
    	else //if (5 == i)
        {
        //    size = 2;//NR AGC因子，一个BF 2B
            size = 3;//AGC因子，一个BF 3B
            bf_num = (61440*2*2)/64;
            allnum = size*bf_num;//1ms, 2 slot长度
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_ODD_COM_AGC_ADDR;//CSU_RX_DUMMYBUFFER_ADDR;
        }
		/*******
    	else// if (6 == i)
        {
            size = 1;//LTE AGC因子，一个BF 2B
            bf_num = (30720*2)/16;//1ms, 2 slot长度
            allnum = size*bf_num;
            rx_dst_addr = (uint32_t)SM1_LTE_CELL0_ODD_COM_AGC_ADDR;//CSU_RX_DUMMYBUFFER_ADDR;
        }
		*******/

        xnum = size*rx_cycle_num;

    	//RX源端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx_odd_link_addr + 2*i,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_SRC,
                                            CPRIENDFLAG,
                                            CPRIEND_ADDR,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
       	//RX目的端地址
        UCP_API_CPRI_CSU_MdDma_LinkNodeGen((stCsuLinkDesc1L3D*)rx_odd_link_addr + 2*i + 1,
                                            DUAL_END_MD_DMA,
                                            LINKLIST_NODE_TYPE_DST,
                                            NONCPRIENDFLAG,
                                            rx_dst_addr,
                                            axc_id,
                                            xnum,
                                            allnum,//双边链表215:192有效
                                            latch_id,
                                            CGran,
                                            0,
                                            0);
    }
}

/*!   
* @brief:  
* @author:  guicheng.liu
* @Date:  2023年3月16日
* @param: axc_id_num :       [param description ]
*/
void Cpri_Csu_Reg_Init(uint32_t axc_id_num)
{
    //链表地址放在ECS SM里面, 长度0x200,共可存储8个64byte的双边多维链表，目前使用的axc_id_num=5个节点的链表
    phy_csu_link_info_t* link = &g_phy_lte_csu_link;

    //tx的链表地址
    uint32_t tx_even_link_addr  = link->tx_even_link_addr; // 0x721E800;
    uint32_t tx_odd_link_addr   = link->tx_odd_link_addr; // 0x721EA00;
    uint32_t tx_last_link_addr  = link->tx_last_link_addr; // 0x721EC00;

    //rx的链表地址
    uint32_t rx_first_link_addr = link->rx_first_link_addr; // 0x721EE00;
    uint32_t rx_even_link_addr  = link->rx_even_link_addr; // 0x721F000;
    uint32_t rx_odd_link_addr   = link->rx_odd_link_addr; // 0x721F200;

    //tx
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(0,  //第0组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx_even_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(1,  //第1组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx_odd_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(2,  //第2组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 tx_last_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    //rx
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(3,  //第3组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 rx_first_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(4,  //第4组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 rx_even_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
    UCP_API_CPRI_CSU_DmaParamReg_Cfg(5,  //第5组寄存器
									 DMA_PARAM_MODE_LINKLIST,
									 rx_odd_link_addr, 
									 0,
									 0,
								     0,
									 0,
									 axc_id_num);
}


/*!   
* @brief:  
* @author:  guicheng.liu
* @Date:  2023年3月16日
* @param: pTxCmdFifo :       [param description ]
* @param: pRxCmdFifo :       [param description ]
*/
void Cpri_Csu_Cmd_Gen(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo)
{
    uint32_t tx_even_cmd_14_h = 0;
    uint32_t tx_even_cmd_32_l = 0;
    uint32_t tx_odd_cmd_14_h = 0;
    uint32_t tx_odd_cmd_32_l = 0;
    uint32_t tx_last_cmd_14_h = 0;
    uint32_t tx_last_cmd_32_l = 0;

    uint32_t rx_1st_cmd_14_h = 0;
    uint32_t rx_1st_cmd_32_l = 0;
    uint32_t rx_even_cmd_14_h = 0;
    uint32_t rx_even_cmd_32_l = 0;
    uint32_t rx_odd_cmd_14_h = 0;
    uint32_t rx_odd_cmd_32_l = 0;


    //FIFO1 用于TX发送数据
    //[1:0]dma_mode_s, 1:一级链表模式 DMA
    //[3:2]dma_mode_d, 1:一级链表模式 DMA
    //[4]dma_dimension, 1:多维 DMA
    //[5]axi4_master_sel 非APE模式,0:访问 DDR 和 Share Memory 选择 AXI4 Master0（经过非 CCI 总线）
    //[6]continue_next_dma 1:下一个 DMA 源端数据的读取无需等待当前 DMA目的端数据写完
    //[7]continue_last_dma 1:下一个 DMA 源端数据的读取无需等待上一个 DMA目的端数据写完
    //[12:8]dma_buffer_id_s 存放源端 DMA 参数的寄存器 ID
    //[17:13]dma_buffer_id_d 存放目的端 DMA 参数的寄存器 ID
    //[22:18]cmd_tag
    //[23]clear非APE模式,0:当前DMA之前,不清空CSU内部缓存
    tx_even_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(0<<8) |(0<<13)|(0<<18); 
    tx_even_cmd_14_h = 0;

    tx_odd_cmd_32_l  = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(1<<8) |(1<<13)|(1<<18);
    tx_odd_cmd_14_h  = 0;

    tx_last_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(2<<8) |(2<<13)|(2<<18);
    tx_last_cmd_14_h = 0;

    pTxCmdFifo->cmdFifo_num = 4;
    //前2.5ms需要压入3个subframe的链表
    pTxCmdFifo->cmdFifo[0].cmd_num = 3;
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd32l = tx_even_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[0].cmd14h = tx_even_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd32l = tx_odd_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[1].cmd14h = tx_odd_cmd_14_h;
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd32l = tx_even_cmd_32_l;
    pTxCmdFifo->cmdFifo[0].cmd[2].cmd14h = tx_even_cmd_14_h;

    pTxCmdFifo->cmdFifo[1].cmd_num = 2;
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd32l = tx_odd_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[0].cmd14h = tx_odd_cmd_14_h;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd32l = tx_even_cmd_32_l;
    pTxCmdFifo->cmdFifo[1].cmd[1].cmd14h = tx_even_cmd_14_h;

    pTxCmdFifo->cmdFifo[2].cmd_num = 3;
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd32l = tx_odd_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[0].cmd14h = tx_odd_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd32l = tx_even_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[1].cmd14h = tx_even_cmd_14_h;
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd32l = tx_odd_cmd_32_l;
    pTxCmdFifo->cmdFifo[2].cmd[2].cmd14h = tx_odd_cmd_14_h;

    pTxCmdFifo->cmdFifo[3].cmd_num = 2;
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd32l = tx_even_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[0].cmd14h = tx_even_cmd_14_h;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd32l = tx_last_cmd_32_l;
    pTxCmdFifo->cmdFifo[3].cmd[1].cmd14h = tx_last_cmd_14_h;

    //FIFO0 用于RX接收数据
//  rx_1st_cmd_32_l  = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(4<<8) |(4<<13)|(4<<18);
	rx_1st_cmd_32_l  = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(3<<8) |(3<<13)|(3<<18);
//  rx_1st_cmd_14_h  = 0;
	rx_1st_cmd_14_h  =  (1 << 4);

//  rx_even_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(5<<8) |(5<<13)|(5<<18);
	rx_even_cmd_32_l = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(4<<8) |(4<<13)|(4<<18);
    rx_even_cmd_14_h = 0;

//  rx_odd_cmd_32_l  = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(6<<8) |(6<<13)|(6<<18);
	rx_odd_cmd_32_l  = 1 | (1<<2) |(1<<4)|(0 <<5) |(3<<6) |(5<<8) |(5<<13)|(5<<18);
    rx_odd_cmd_14_h  = 0;

    pRxCmdFifo->cmdFifo_num = 4;
    //前2.5ms需要压入3个subframe的链表
    pRxCmdFifo->cmdFifo[0].cmd_num = 3;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd32l = rx_1st_cmd_32_l;
    pRxCmdFifo->cmdFifo[0].cmd[0].cmd14h = rx_1st_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd32l = rx_odd_cmd_32_l;
    pRxCmdFifo->cmdFifo[0].cmd[1].cmd14h = rx_odd_cmd_14_h;
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd32l = rx_even_cmd_32_l;
    pRxCmdFifo->cmdFifo[0].cmd[2].cmd14h = rx_even_cmd_14_h;

    pRxCmdFifo->cmdFifo[1].cmd_num = 2;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd32l = rx_odd_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[0].cmd14h = rx_odd_cmd_14_h;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd32l = rx_even_cmd_32_l;
    pRxCmdFifo->cmdFifo[1].cmd[1].cmd14h = rx_even_cmd_14_h;

    pRxCmdFifo->cmdFifo[2].cmd_num = 3;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd32l = rx_odd_cmd_32_l;
    pRxCmdFifo->cmdFifo[2].cmd[0].cmd14h = rx_odd_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd32l = rx_even_cmd_32_l;
    pRxCmdFifo->cmdFifo[2].cmd[1].cmd14h = rx_even_cmd_14_h;
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd32l = rx_odd_cmd_32_l;
    pRxCmdFifo->cmdFifo[2].cmd[2].cmd14h = rx_odd_cmd_14_h;

    pRxCmdFifo->cmdFifo[3].cmd_num = 2;
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd32l = rx_even_cmd_32_l;//rx_odd_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[0].cmd14h = rx_even_cmd_14_h;//rx_odd_cmd_14_h;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd32l = rx_odd_cmd_32_l;//rx_even_cmd_32_l;
    pRxCmdFifo->cmdFifo[3].cmd[1].cmd14h = rx_odd_cmd_14_h;//rx_even_cmd_14_h;
}

 /*!   
 * @brief:  配置NR小区的CPRI CSU链表
 * @author:  guicheng.liu
 * @Date:  2023年1月15日
 * @param: cell :             [NR 小区参数]
 */
//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell)
void Config_Cpri_Csu_Lte()

{
    /*
    为兼容OTIC标准下10137.6M线速率下双模（NR 4TR+LTE 2TR）场景，驱动平台按照该模式配置map表，
    对应的物理层的CPRI CSU链表也需按照双模模式配置：
    port0---latch0
    port1---latch1
    port2---latch2
    port3---latch2
    port4---latch3
    port5---latch3
    port6---latch4
    port7---latch4
    port8---latch5
    port9---latch6
    */

    uint32_t rx_cycle_num = 4;//根据芯片建议
    uint32_t tx_cycle_num = 4;
    uint32_t axc_id_num = 9;//10; //1+1个指数因子,4+2个天线, 1+1个AGC因子共10个port
    uint32_t out_latch_num = 6;//7;
    uint32_t in_latch_num = 6;//7;//共7个latch

//    uint32_t w_r_flag = 0;//0:w, 1:r
//    uint32_t send_threshold = 0;
//    uint32_t almostfull_threshold = 0;
    stCpriCsuCmdFifoInfo tx_cmdfifo;
    stCpriCsuCmdFifoInfo rx_cmdfifo;

    memset(&tx_cmdfifo, 0, sizeof(stCpriCsuCmdFifoInfo));
    memset(&rx_cmdfifo, 0, sizeof(stCpriCsuCmdFifoInfo));

    UCP_API_CPRI_CSU_Set_AxcIdNum(axc_id_num);
    UCP_API_CPRI_CSU_Set_LatchNum(in_latch_num);
	Phy_Lte_Timer_Csu_Init();

    //! step1 初始化所有的必要的寄存器
    Cpri_Csu_Init();
	
	//!step3: RX 和TX 的链表节点的配置
   // Cpri_Csu_Link_Init(cell, axc_id_num, in_latch_num, out_latch_num, rx_cycle_num, tx_cycle_num);
	Cpri_Csu_Link_Init(axc_id_num, in_latch_num, out_latch_num, rx_cycle_num, tx_cycle_num);
	
	//!step2 配置TX&RX data outlatch
	Cpri_Csu_Latch_Init(axc_id_num, in_latch_num, out_latch_num, rx_cycle_num);

	//!step4: RX和TX参数寄存器的配置
//    Cpri_Csu_Reg_Init(axc_id_num);
	Cpri_Csu_Reg_Init(in_latch_num);

	//!step5: 根据配置生成cmd fifo命令
    Cpri_Csu_Cmd_Gen(&tx_cmdfifo, &rx_cmdfifo);

    //!step6：把生成好的FIFO命令配置给驱动
    UCP_API_CPRI_CSU_Get_CmdFIFO(&tx_cmdfifo, &rx_cmdfifo);
}

/*!   
* @brief:  根据NR配置 Timer和JESD/CPRI CSU Timer&DMA链表
* @author:  guicheng.liu
* @Date:  2022年7月8日
* @param: cell :             [NR 小区参数]
*/
//void Phy_Timer_Csu_Config_Nr(lte_cell_info_t* cell)
//{

//}

/*!   
* @brief:  根据LTE配置 Timer和JESD/CPRI CSU Timer&DMA链表
* @author:  guicheng.liu
* @Date:  2022年7月8日
* @param: cell :             [LTE 小区参数]
*/
#if 0
void Phy_Timer_Csu_Config_Lte(lte_cell_info_t* cell)
{
    //uint8_t num_subframe = (cell->duplexing_mode == 0) ? 
    //                        cell->nrOfDlSubframe : (cell->nrOfDlSubframe + cell->nrOfUlSubframe + 1);
    //uint8_t num_tx_tti = (cell->duplexing_mode == 0) ? 
    //                        cell->nrOfDlSubframe : (cell->nrOfDlSubframe + 1);
    
    //LTE FDD phy timer配置
    phy_timer_config_ind_t* csu_timer = &g_phy_csu_timer.cpri_timer;
    
    Config_Cpri_Csu_Lte(cell);
    
    g_phy_timer.flag = 1;
    g_phy_timer.inuse_timer.num_t = 1;
    g_phy_timer.inuse_timer.t_us = 1000;
    g_phy_timer.inuse_timer.period = 1000;

    //LTE暂时写死
    csu_timer->scsId = 0;
    csu_timer->runCoreId = 1;
    csu_timer->bandWidth = cell->dl_bandwidth;
    csu_timer->t_period = 10000;
    csu_timer->t_us = 1000;
    csu_timer->num_t = 10;
    csu_timer->num_t_per_sfn = 10;
    csu_timer->num_t_dl = 10;
    csu_timer->num_t_dl_symb = 14;
    csu_timer->num_t_ul_symb = 14;
    csu_timer->num_ants = cell->num_tx_ant;

    LOG_INFO_S("Timer, Bw:%u, P:%u, Us:%u, NumT:%u, Total:%u, DlSubframe:%u, DlSym:%u, UlSym:%u\n",
               csu_timer->bandWidth, csu_timer->t_period, csu_timer->t_us, csu_timer->num_t,
               csu_timer->num_t_per_sfn, csu_timer->num_t_dl, csu_timer->num_t_dl_symb, csu_timer->num_t_ul_symb);

    cpri_timer_init4buildcell_c0(csu_timer);
    //Config_Csu_Dma(cell->dl_bandwidth, cell->ul_bandwidth, 
    //               cell->num_tx_ant, cell->num_rx_ant,
    //               num_tx_tti, cell->nrOfUlSubframe);
    //Config_Csu_Timer(cell->dl_bandwidth, cell->num_tx_ant,
    //                 num_subframe, cell->nrOfDlSubframe,
    //                 cell->nrOfDlSymbol, cell->nrOfUlSymbol, 0);
}
#endif

