/*
 * ===================================================================
 *
 *        Filename:  ucp_rfc.h
 *
 *         Created:  2019-06-25 11:00:12 AM
 *   Last Modified:  2019-06-25 11:00:28 AM
 *
 *          Author:  Lipeng YANG , lipeng.yang@ia.ac.cn
 *    Organization:  Beijing Smart Logic Technology Co., Ltd.
 *                   National ASIC Design Engineering Center, IACAS
 *
 *     Description:  
 *
 * ===================================================================
 */
#ifndef __UCP_RFC_H__
#define __UCP_RFC_H__


#define  ENABLE_RX   0x1
#define  TXNRX_TX    0x2

#define RF_BASE_ADDR          0x047e0000
#define RF_GPIO_ADDR          0x047e0800   
/*-----------------------------------------------------
                RF0_REG
-------------------------------------------------------*/
#define RF_MODE_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x00*4 )))/* 0x0 */
#define IO_CTRL_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x01*4 )))/* 0x4 */
#define CG_CTRL_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x02*4 )))
#define ADC_STATUS_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x04*4 )))/* 0x10 */
#define ADC_CTRL_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x05*4 )))/* 0x14 */
#define ADC_DFMT_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x06*4 )))
#define ADC_EOF_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x07*4 )))
#define DP_PN_CG_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x08*4 )))
#define DAC_CTRL_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x09*4 )))
#define DAC_DIV_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x0A*4 )))
#define DAC_PAT1_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x0B*4 )))
#define DAC_PAT2_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x0C*4 )))
#define DAC_EOF_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x0D*4 )))
#define DP_BIAS_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x10*4 )))
#define DP_RTERM0_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0x11*4 )))
#define DP_RTERM1_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0x12*4 )))
#define CK_RTERM_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x13*4 )))
#define LVDS_EN_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x14*4 )))
#define LVDS_CM_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x15*4 )))
#define LVDS_TXDRV_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x16*4 )))
#define CMOS_IE_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x17*4 )))
#define CMOS_OE_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x18*4 )))
#define CMOS_PULLDN_REG_0    (*((volatile uint32_t *)( RF_BASE_ADDR + 0x19*4 )))
#define CMOS_SMT_REG_0       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x1A*4 )))
#define CK_TUNING_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0x1B*4 )))
#define FRM_TUNING_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x1C*4 )))
#define CMOS_TUNING0_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x1D*4 )))
#define CMOS_TUNING1_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x1E*4 )))
#define CMOS_TUNING2_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x1F*4 )))
#define CMOS_TUNING3_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x20*4 )))
#define CMOS_TUNING4_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x21*4 )))
#define CMOS_TUNING5_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x22*4 )))
#define LVDS_TUNING0_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x23*4 )))
#define LVDS_TUNING1_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x24*4 )))
#define LVDS_PMUX0_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x25*4 )))
#define LVDS_PMUX1_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x26*4 )))

/*-----------------------------------------------------
                RF1_REG
-------------------------------------------------------*/
#define RF_MODE_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x30*4 )))
#define IO_CTRL_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x31*4 )))
#define CG_CTRL_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x32*4 )))
#define ADC_STATUS_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x34*4 )))
#define ADC_CTRL_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x35*4 )))
#define ADC_DFMT_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x36*4 )))
#define ADC_EOF_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x37*4 )))
#define DP_PN_CG_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x38*4 )))
#define DAC_CTRL_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x39*4 )))
#define DAC_DIV_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x3A*4 )))
#define DAC_PAT1_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x3B*4 )))
#define DAC_PAT2_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x3C*4 )))
#define DAC_EOF_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x3D*4 )))
#define DP_BIAS_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x40*4 )))
#define DP_RTERM0_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0x41*4 )))
#define DP_RTERM1_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0x42*4 )))
#define CK_RTERM_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x43*4 )))
#define LVDS_EN_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x44*4 )))
#define LVDS_CM_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x45*4 )))
#define LVDS_TXDRV_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x46*4 )))
#define CMOS_IE_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x47*4 )))
#define CMOS_OE_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x48*4 )))
#define CMOS_PULLDN_REG_1    (*((volatile uint32_t *)( RF_BASE_ADDR + 0x49*4 )))
#define CMOS_SMT_REG_1       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x4A*4 )))
#define CK_TUNING_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0x4B*4 )))
#define FRM_TUNING_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x4C*4 )))
#define CMOS_TUNING0_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x4D*4 )))
#define CMOS_TUNING1_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x4E*4 )))
#define CMOS_TUNING2_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x4F*4 )))
#define CMOS_TUNING3_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x50*4 )))
#define CMOS_TUNING4_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x51*4 )))
#define CMOS_TUNING5_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x52*4 )))
#define LVDS_TUNING0_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x53*4 )))
#define LVDS_TUNING1_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0x54*4 )))
#define LVDS_PMUX0_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x55*4 )))
#define LVDS_PMUX1_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x56*4 )))
/*-----------------------------------------------------
                RF common reg
-------------------------------------------------------*/
#define PIN_CTRL_REG_ADDR        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x5B*4 )))
#define SYNC_GEN_REG_ADDR        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x5C*4 )))
#define SYNC_CTRL_REG_ADDR       (*((volatile uint32_t *)( RF_BASE_ADDR + 0x5D*4 )))
#define TMR_CTRL_REG_ADDR        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x60*4 )))
#define RF_INTC_REG_ADDR         (*((volatile uint32_t *)( RF_BASE_ADDR + 0x61*4 )))
#define TMR_SCR_REQ_REG_ADDR     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x62*4 )))
/*-----------------------------------------------------
                GPIO pin MUX
-------------------------------------------------------*/
#define GPIO_PMUX0_REG        (*((volatile uint32_t *)( RF_GPIO_ADDR + 0x00*4 )))
#define GPIO_CTRL0_REG        (*((volatile uint32_t *)( RF_GPIO_ADDR + 0x01*4 )))
#define GPIO_CTRL1_REG        (*((volatile uint32_t *)( RF_GPIO_ADDR + 0x02*4 )))
#define GPIO_CTRL2_REG        (*((volatile uint32_t *)( RF_GPIO_ADDR + 0x03*4 )))
#define GPIO_CTRL3_REG        (*((volatile uint32_t *)( RF_GPIO_ADDR + 0x04*4 )))
/*-----------------------------------------------------
                timer0 reg
-------------------------------------------------------*/
#define TMR_TEVENT_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x80*4 )))
#define TMR_TSCR_TRG_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0x81*4 )))
#define TMR_TWREQ_REG_0         (*((volatile uint32_t *)( RF_BASE_ADDR + 0x82*4 )))
#define TMR_TINTE0_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x83*4 )))
#define TMR_TINTF0_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x84*4 )))
#define TMR_TINTE1_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x85*4 )))
#define TMR_TINTF1_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x86*4 )))
#define TMR_TINTE2_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x87*4 )))
#define TMR_TINTF2_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x88*4 )))
#define TMR_CEVENT_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x89*4 )))
#define TMR_CMSK_REG_0          (*((volatile uint32_t *)( RF_BASE_ADDR + 0x8A*4 )))
#define TMR_CINTE0_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x8B*4 )))
#define TMR_CINTF0_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x8C*4 )))
#define TMR_CINTE1_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x8D*4 )))
#define TMR_CINTF1_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x8E*4 )))
#define TMR_CINTE2_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x8F*4 )))
#define TMR_CINTF2_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x90*4 )))
#define TMR_OVFL_REG_0          (*((volatile uint32_t *)( RF_BASE_ADDR + 0x91*4 )))
#define TMR_OVFH_REG_0          (*((volatile uint32_t *)( RF_BASE_ADDR + 0x92*4 )))
#define TMR_RXDP_EN0L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x93*4 )))
#define TMR_RXDP_EN0H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x94*4 )))
#define TMR_RXDP_EN1L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x95*4 )))
#define TMR_RXDP_EN1H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x96*4 )))
#define TMR_TXDP_EN0L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x97*4 )))
#define TMR_TXDP_EN0H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x98*4 )))
#define TMR_TXDP_EN1L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x99*4 )))
#define TMR_TXDP_EN1H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x9A*4 )))
#define TMR_RXEOFL_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x9B*4 )))
#define TMR_RXEOFH_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x9C*4 )))
#define TMR_TXEOFL_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x9D*4 )))
#define TMR_TXEOFH_REG_0        (*((volatile uint32_t *)( RF_BASE_ADDR + 0x9E*4 )))
#define TMR_EN_CTRL0L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0x9F*4 )))
#define TMR_EN_CTRL0H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA0*4 )))
#define TMR_EN_CTRL1L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA1*4 )))
#define TMR_EN_CTRL1H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA2*4 )))
#define TMR_EN_CTRL2L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA3*4 )))
#define TMR_EN_CTRL2H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA4*4 )))
#define TMR_EN_CTRL3L_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA5*4 )))
#define TMR_EN_CTRL3H_REG_0     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA6*4 )))
#define TMR_TXRX_CTRL0L_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA7*4 )))
#define TMR_TXRX_CTRL0H_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA8*4 )))
#define TMR_TXRX_CTRL1L_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xA9*4 )))
#define TMR_TXRX_CTRL1H_REG_0   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xAA*4 )))
#define TMR_SCRATH0L_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xAB*4 )))
#define TMR_SCRATH0H_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xAC*4 )))
#define TMR_SCRATH1L_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xAD*4 )))
#define TMR_SCRATH1H_REG_0      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xAE*4 )))
#define TMR_1PPSL_REG_0         (*((volatile uint32_t *)( RF_BASE_ADDR + 0xAF*4 )))
#define TMR_1PPSH_REG_0         (*((volatile uint32_t *)( RF_BASE_ADDR + 0xB0*4 )))
/*-----------------------------------------------------
                timer1 reg
-------------------------------------------------------*/
#define TMR_TEVENT_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC0*4 )))
#define TMR_TSCR_TRG_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC1*4 )))
#define TMR_TWREQ_REG_1         (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC2*4 )))
#define TMR_TINTE0_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC3*4 )))
#define TMR_TINTF0_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC4*4 )))
#define TMR_TINTE1_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC5*4 )))
#define TMR_TINTF1_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC6*4 )))
#define TMR_TINTE2_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC7*4 )))
#define TMR_TINTF2_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC8*4 )))
#define TMR_CEVENT_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xC9*4 )))
#define TMR_CMSK_REG_1          (*((volatile uint32_t *)( RF_BASE_ADDR + 0xCA*4 )))
#define TMR_CINTE0_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xCB*4 )))
#define TMR_CINTF0_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xCC*4 )))
#define TMR_CINTE1_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xCD*4 )))
#define TMR_CINTF1_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xCE*4 )))
#define TMR_CINTE2_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xCF*4 )))
#define TMR_CINTF2_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD0*4 )))
#define TMR_OVFL_REG_1          (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD1*4 )))
#define TMR_OVFH_REG_1          (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD2*4 )))
#define TMR_RXDP_EN0L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD3*4 )))
#define TMR_RXDP_EN0H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD4*4 )))
#define TMR_RXDP_EN1L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD5*4 )))
#define TMR_RXDP_EN1H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD6*4 )))
#define TMR_TXDP_EN0L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD7*4 )))
#define TMR_TXDP_EN0H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD8*4 )))
#define TMR_TXDP_EN1L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xD9*4 )))
#define TMR_TXDP_EN1H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xDA*4 )))
#define TMR_RXEOFL_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xDB*4 )))
#define TMR_RXEOFH_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xDC*4 )))
#define TMR_TXEOFL_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xDD*4 )))
#define TMR_TXEOFH_REG_1        (*((volatile uint32_t *)( RF_BASE_ADDR + 0xDE*4 )))
#define TMR_EN_CTRL0L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xDF*4 )))
#define TMR_EN_CTRL0H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE0*4 )))
#define TMR_EN_CTRL1L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE1*4 )))
#define TMR_EN_CTRL1H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE2*4 )))
#define TMR_EN_CTRL2L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE3*4 )))
#define TMR_EN_CTRL2H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE4*4 )))
#define TMR_EN_CTRL3L_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE5*4 )))
#define TMR_EN_CTRL3H_REG_1     (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE6*4 )))
#define TMR_TXRX_CTRL0L_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE7*4 )))
#define TMR_TXRX_CTRL0H_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE8*4 )))
#define TMR_TXRX_CTRL1L_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xE9*4 )))
#define TMR_TXRX_CTRL1H_REG_1   (*((volatile uint32_t *)( RF_BASE_ADDR + 0xEA*4 )))
#define TMR_SCRATH0L_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xEB*4 )))
#define TMR_SCRATH0H_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xEC*4 )))
#define TMR_SCRATH1L_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xED*4 )))
#define TMR_SCRATH1H_REG_1      (*((volatile uint32_t *)( RF_BASE_ADDR + 0xEE*4 )))
#define TMR_1PPSL_REG_1         (*((volatile uint32_t *)( RF_BASE_ADDR + 0xEF*4 )))
#define TMR_1PPSH_REG_1         (*((volatile uint32_t *)( RF_BASE_ADDR + 0xF0*4 )))


/*-----------------------------------------------------
                timer array
-------------------------------------------------------*/
#define TMR0_ARRAY_BASE       RF_BASE_ADDR+0x400
#define TMR1_ARRAY_BASE       RF_BASE_ADDR+0x500

#define TMR_TNL_REG0_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x00*4 ))) 
#define TMR_TNH_REG0_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x01*4 ))) 
#define TMR_TNL_REG1_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x02*4 ))) 
#define TMR_TNH_REG1_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x03*4 ))) 
#define TMR_TNL_REG2_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x04*4 ))) 
#define TMR_TNH_REG2_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x05*4 ))) 
#define TMR_TNL_REG3_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x06*4 ))) 
#define TMR_TNH_REG3_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x07*4 ))) 
#define TMR_TNL_REG4_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x08*4 ))) 
#define TMR_TNH_REG4_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x09*4 ))) 
#define TMR_TNL_REG5_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x0A*4 ))) 
#define TMR_TNH_REG5_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x0B*4 ))) 
#define TMR_TNL_REG6_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x0C*4 ))) 
#define TMR_TNH_REG6_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x0D*4 ))) 
#define TMR_TNL_REG7_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x0E*4 ))) 
#define TMR_TNH_REG7_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x0F*4 ))) 
#define TMR_TNL_REG8_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x10*4 ))) 
#define TMR_TNH_REG8_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x11*4 ))) 
#define TMR_TNL_REG9_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x12*4 ))) 
#define TMR_TNH_REG9_0          (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x13*4 ))) 
#define TMR_TNL_REG10_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x14*4 ))) 
#define TMR_TNH_REG10_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x15*4 ))) 
#define TMR_TNL_REG11_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x16*4 ))) 
#define TMR_TNH_REG11_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x17*4 ))) 
#define TMR_TNL_REG12_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x18*4 ))) 
#define TMR_TNH_REG12_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x19*4 ))) 
#define TMR_TNL_REG13_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x1A*4 )))
#define TMR_TNH_REG13_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x1B*4 )))
#define TMR_TNL_REG14_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x1C*4 )))
#define TMR_TNH_REG14_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x1D*4 )))
#define TMR_TNL_REG15_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x1E*4 )))
#define TMR_TNH_REG15_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x1F*4 )))
#define TMR_TNL_REG16_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x20*4 )))
#define TMR_TNH_REG16_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x21*4 )))
#define TMR_TNL_REG17_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x22*4 )))
#define TMR_TNH_REG17_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x23*4 )))
#define TMR_TNL_REG18_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x24*4 )))
#define TMR_TNH_REG18_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x25*4 )))
#define TMR_TNL_REG19_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x26*4 )))
#define TMR_TNH_REG19_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x27*4 )))
#define TMR_TNL_REG20_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x28*4 )))
#define TMR_TNH_REG20_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x29*4 )))
#define TMR_TNL_REG21_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x2A*4 )))
#define TMR_TNH_REG21_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x2B*4 )))
#define TMR_TNL_REG22_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x2C*4 )))
#define TMR_TNH_REG22_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x2D*4 )))
#define TMR_TNL_REG23_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x2E*4 )))
#define TMR_TNH_REG23_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x2F*4 )))
#define TMR_TNL_REG24_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x30*4 )))
#define TMR_TNH_REG24_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x31*4 )))
#define TMR_TNL_REG25_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x32*4 )))
#define TMR_TNH_REG25_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x33*4 )))
#define TMR_TNL_REG26_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x34*4 )))
#define TMR_TNH_REG26_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x35*4 )))
#define TMR_TNL_REG27_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x36*4 )))
#define TMR_TNH_REG27_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x37*4 )))
#define TMR_TNL_REG28_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x38*4 )))
#define TMR_TNH_REG28_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x39*4 )))
#define TMR_TNL_REG29_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x3A*4 )))
#define TMR_TNH_REG29_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x3B*4 )))
#define TMR_TNL_REG30_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x3C*4 )))
#define TMR_TNH_REG30_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x3D*4 )))
#define TMR_TNL_REG31_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x3E*4 )))
#define TMR_TNH_REG31_0         (*((volatile uint32_t *)( TMR0_ARRAY_BASE + 0x3F*4 )))

#define TMR_TNL_REG0_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x00*4 ))) 
#define TMR_TNH_REG0_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x01*4 ))) 
#define TMR_TNL_REG1_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x02*4 ))) 
#define TMR_TNH_REG1_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x03*4 ))) 
#define TMR_TNL_REG2_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x04*4 ))) 
#define TMR_TNH_REG2_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x05*4 ))) 
#define TMR_TNL_REG3_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x06*4 ))) 
#define TMR_TNH_REG3_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x07*4 ))) 
#define TMR_TNL_REG4_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x08*4 ))) 
#define TMR_TNH_REG4_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x09*4 ))) 
#define TMR_TNL_REG5_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x0A*4 ))) 
#define TMR_TNH_REG5_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x0B*4 ))) 
#define TMR_TNL_REG6_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x0C*4 ))) 
#define TMR_TNH_REG6_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x0D*4 ))) 
#define TMR_TNL_REG7_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x0E*4 ))) 
#define TMR_TNH_REG7_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x0F*4 ))) 
#define TMR_TNL_REG8_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x10*4 ))) 
#define TMR_TNH_REG8_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x11*4 ))) 
#define TMR_TNL_REG9_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x12*4 ))) 
#define TMR_TNH_REG9_1          (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x13*4 ))) 
#define TMR_TNL_REG10_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x14*4 ))) 
#define TMR_TNH_REG10_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x15*4 ))) 
#define TMR_TNL_REG11_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x16*4 ))) 
#define TMR_TNH_REG11_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x17*4 ))) 
#define TMR_TNL_REG12_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x18*4 ))) 
#define TMR_TNH_REG12_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x19*4 ))) 
#define TMR_TNL_REG13_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x1A*4 )))
#define TMR_TNH_REG13_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x1B*4 )))
#define TMR_TNL_REG14_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x1C*4 )))
#define TMR_TNH_REG14_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x1D*4 )))
#define TMR_TNL_REG15_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x1E*4 )))
#define TMR_TNH_REG15_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x1F*4 )))
#define TMR_TNL_REG16_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x20*4 )))
#define TMR_TNH_REG16_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x21*4 )))
#define TMR_TNL_REG17_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x22*4 )))
#define TMR_TNH_REG17_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x23*4 )))
#define TMR_TNL_REG18_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x24*4 )))
#define TMR_TNH_REG18_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x25*4 )))
#define TMR_TNL_REG19_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x26*4 )))
#define TMR_TNH_REG19_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x27*4 )))
#define TMR_TNL_REG20_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x28*4 )))
#define TMR_TNH_REG20_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x29*4 )))
#define TMR_TNL_REG21_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x2A*4 )))
#define TMR_TNH_REG21_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x2B*4 )))
#define TMR_TNL_REG22_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x2C*4 )))
#define TMR_TNH_REG22_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x2D*4 )))
#define TMR_TNL_REG23_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x2E*4 )))
#define TMR_TNH_REG23_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x2F*4 )))
#define TMR_TNL_REG24_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x30*4 )))
#define TMR_TNH_REG24_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x31*4 )))
#define TMR_TNL_REG25_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x32*4 )))
#define TMR_TNH_REG25_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x33*4 )))
#define TMR_TNL_REG26_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x34*4 )))
#define TMR_TNH_REG26_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x35*4 )))
#define TMR_TNL_REG27_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x36*4 )))
#define TMR_TNH_REG27_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x37*4 )))
#define TMR_TNL_REG28_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x38*4 )))
#define TMR_TNH_REG28_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x39*4 )))
#define TMR_TNL_REG29_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x3A*4 )))
#define TMR_TNH_REG29_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x3B*4 )))
#define TMR_TNL_REG30_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x3C*4 )))
#define TMR_TNH_REG30_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x3D*4 )))
#define TMR_TNL_REG31_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x3E*4 )))
#define TMR_TNH_REG31_1         (*((volatile uint32_t *)( TMR1_ARRAY_BASE + 0x3F*4 )))

/*-----------------------------------------------------
                RF_REG MASK
-------------------------------------------------------*/
/////RF_REG_mask/////
#define RF_MODE_REG_MASK             0x800003FF
#define IO_CTRL_REG_MASK             0x00000003
#define ADC_STATUS_REG_MASK          0x00000F0F
#define ADC_CTRL_REG_MASK            0x3300010F
#define ADC_DFMT_REG_MASK            0x00000FFF
#define DAC_STATUS_REG_MASK          0xFF000000
#define ADC_EOF_REG_MASK             0x80000000
#define DAC_CTRL_REG_MASK            0x0000030B
#define DAC_DIV_REG_MASK             0x0000FFFF
#define DAC_PAT1_REG_MASK            0xFFFFFFFF
#define DAC_PAT2_REG_MASK            0xFFFFFFFF
#define DAC_EOF_REG_MASK             0x80000000
#define DP_BIAS_REG_MASK             0xFFFFFFFF
#define DP_RTERM0_REG_MASK           0x3F777777
#define DP_RTERM1_REG_MASK           0x3F777777
#define CK_RTERM_REG_MASK            0x0000FFFF
#define LVDS_EN_REG_MASK             0x00FF00FF
//#define DEBUG_LVDS_REG_MASK          0x003F003F
#define LVDS_CM_REG_MASK             0xFFFFFFFF
#define LVDS_TXDRV_REG_MASK           0xFFFFFFFF
#define CMOS_IE_REG_MASK             0xCFFF0FFF
#define CMOS_OE_REG_MASK             0xCFFF0FFF
#define CMOS_PULLDN_REG_MASK           0xF03F003F
#define CMOS_SMT_REG_MASK            0xF03F003F
#define CK_TUNING_REG_MASK           0x0000FFFF
#define FRM_TUNING_REG_MASK          0x000000FF
#define CMOS_TUNING0_REG_MASK        0xFFFFFFFF
#define CMOS_TUNING1_REG_MASK        0xFFFFFFFF
#define CMOS_TUNING2_REG_MASK        0xFFFFFFFF
#define CMOS_TUNING3_REG_MASK        0xFFFFFFFF
#define CMOS_TUNING4_REG_MASK        0xFFFFFFFF
#define CMOS_TUNING5_REG_MASK        0xFFFFFFFF
#define LVDS_TUNING0_REG_MASK        0x00FFFFFF
#define LVDS_TUNING1_REG_MASK        0x00FFFFFF
#define LVDS_PMUX0_REG_MASK          0xFFFFFFFF
#define LVDS_PMUX1_REG_MASK          0xFFFFFFFF

#define PIN_CTRL_REG_MASK            0xC0007F7F   //!!!0xC0003F3F
#define SYNC_GEN_REG_MASK            0x00000001
#define SYNC_CTRL_REG_MASK           0x000000FF
#define TMR_CTRL_REG_MASK            0x8000C303
#define RF_INTC_REG_MASK             0x00030000
#define TMR_SCR_REQ_REG_MASK         0x00000000

/////timer_reg_mask

#define TMR_MASK                     0x00000000
#define TMR_UNMASK                   0xFFFFFFFF
#define TMR_TSCR_TRG_MASK            0xFF000000
#define TMR_CEVENT_MASK              0x0000007F
#define TMR_CMSK_MASK                0x00003333
#define TMR_CINTE_MASK               0x0000007F  
#define TMR_OVFH_MASK                0x3FFFFFFF




/* �ж�ʹ�� TMR0_CINTE_REG */
#define   TMR_CINTE_1PPS        0x8000
#define   TMR_CINTE_TXNRX1      0x4000
#define   TMR_CINTE_TXNRX0      0x2000
#define   TMR_CINTE_ENABLE3     0x1000
#define   TMR_CINTE_ENABLE2     0x0800
#define   TMR_CINTE_ENABLE1     0x0400
#define   TMR_CINTE_ENABLE0     0x0200
#define   TMR_CINTE_TEOF        0x0100

#define   TMR_CINTE_REOF        0x0008
#define   TMR_CINTE_CNT14H      0x0004
#define   TMR_CINTE_CNT16M      0x0002
#define   TMR_CINTE_CNT32L      0x0001


/* TMR0_CEVENT_REG �����ź��¼�Դ�Ĵ��� */
#define   TMR_CEVENT_1PPS        0x8000
#define   TMR_CEVENT_TXNRX1      0x4000
#define   TMR_CEVENT_TXNRX0      0x2000
#define   TMR_CEVENT_ENABLE3     0x1000
#define   TMR_CEVENT_ENABLE2     0x0800
#define   TMR_CEVENT_ENABLE1     0x0400
#define   TMR_CEVENT_ENABLE0     0x0200
#define   TMR_CEVENT_TEOF        0x0100
#define   TMR_CEVENT_REOF        0x0080


#define   TMR_CEVENT_CNT14H      0x0004
#define   TMR_CEVENT_CNT16M      0x0002
#define   TMR_CEVENT_CNT32L      0x0001

#endif

//******************** (C) COPYRIGHT 2019 SmartLogic*******************************
// FileName           : ucp_jesd204.h
// Author             : sunpeng, peng.sun@smartlogictech.com
// Date First Issued  : 2019-06-06 11:00:00 AM
// Last Modified      : 2019-10-31 05:11:18 PM
// Description        :
// ------------------------------------------------------------
// Modification History:
// Version    Date       Author    Modification Description
//
//**********************************************************************************
#ifndef __JESD_DMA__
#define __JESD_DMA__

#define DMA_BASE              0x049B0000  //AHB_SL_BASE_ADDR_1 [start addr 32'h1000,offset is 32'h1000]
#define TX_BASE               0x049B2000  //AHB_SL_BASE_ADDR_2 [start addr 32'h2000,offset is 32'h1000]
#define RX_BASE               0x049B3000  //AHB_SL_BASE_ADDR_3 [start addr 32'h3000,offset is 32'h1000]
#define Mtimer_BASE           0x05250000  //JESD MTIMER BASE ADDR
#define DMA_COM_BASE          DMA_BASE + 0x00000000
#define DMA_SG_BASE           DMA_BASE + 0x00000190
//#define DMA_SG2_BASE          DMA_BASE + 0x00000320

#define DMA_MM_S_BASE         DMA_BASE + 0x000004B0
//#define DMA_S_MM_BASE       DMA_BASE + 0x000004E8

//define JESD_DEV_CLK SYSREF SYNC_B has define in ucp_rfc.h & ucp_sfr_c.h
//#define PIN_CTRL_REG          (*((volatile uint32_t *)(0X047E0000 + 0x16C)))
//#define LVDS_EN_REG           (*((volatile uint32_t *)(0X047E0000 + 0x50)))
//#define LVDS_TXDRV_REG        (*((volatile uint32_t *)(0X047E0000 + 0x58)))
//#define PAD_SYNC_ENABLE       (*((volatile uint32_t *)(0X047E0000 + 0x110)))
//#define RFC_DP_BIAS_EN        (*((volatile uint32_t *)(0X047E0000 + 0x40)))
//#define RFC_CLK_EN_TEMP_REG   (*((volatile uint32_t *)(0X03670000 + 0x190)))

//define DMA_CMD_REG
#define DMA_IP_CORE_VERSION                          (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 0))))
#define DMA_CONTROL                                  (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 1))))
#define DMA_STATUS                                   (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 2))))
#define DMA_COMMON_ERROR_STATUS                      (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 3))))
#define DMA_PRIORITY_ENCODER_SCHEME                  (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 4))))
#define DMA_PRIORITY_WEIGHT_MAP_LSB                  (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 5))))
#define DMA_PRIORITY_WEIGHT_MAP_MSB                  (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 6))))
#define DMA_CHANNEL_ENABLE                           (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 7))))
#define DMA_ENDIAN_FORMAT                            (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 8))))
#define DMA_GENERAL_INTERRUPT_REG                    (*((volatile uint32_t *)(DMA_COM_BASE + (0x4 * 9))))

//define DMA_SG1_REG
#define DMA_SG1_CURR_RD_DESCR_PTR_LSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  0))))
#define DMA_SG1_CURR_RD_DESCR_PTR_MSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  1))))
#define DMA_SG1_CURR_WR_DESCR_PTR_LSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  2))))
#define DMA_SG1_CURR_WR_DESCR_PTR_MSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  3))))
#define DMA_SG1_START_FETCH    		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  4))))
#define DMA_SG1_RD_INTERRUPT_ENABLE	                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  5))))
#define DMA_SG1_WR_INTERRUPT_ENABLE	                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  6))))
#define DMA_SG1_RD_DLY_INTERRUPT_TIMEOUT             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  7))))
#define DMA_SG1_WR_DLY_INTERRUPT_TIMEOUT             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  8))))
#define DMA_SG1_RD_IOC_THRESHOLD	                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 *  9))))
#define DMA_SG1_WR_IOC_THRESHOLD		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 10))))
#define DMA_SG1_RD_INTERRUPT_STATUS		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 11))))
#define DMA_SG1_WR_INTERRUPT_STATUS		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 12))))
#define DMA_SG1_RD_ERROR_STATUS		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 13))))
#define DMA_SG1_WR_ERROR_STATUS		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 14))))
#define DMA_SG1_SEQUENCE_NUMBER		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 15))))
#define DMA_SG1_NON_SG_MODE_RD_IF		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 16))))
#define DMA_SG1_NON_SG_MODE_WR_IF		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 17))))
#define DMA_SG1_NON_SG_MODE_WR_IF_BYTES              (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 18))))

//define DMA_SG2_REG
#define DMA_SG2_CURR_RD_DESCR_PTR_LSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 19))))
#define DMA_SG2_CURR_RD_DESCR_PTR_MSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 20))))
#define DMA_SG2_CURR_WR_DESCR_PTR_LSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 21))))
#define DMA_SG2_CURR_WR_DESCR_PTR_MSB                (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 22))))
#define DMA_SG2_START_FETCH    		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 23))))
#define DMA_SG2_RD_INTERRUPT_ENABLE	                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 24))))
#define DMA_SG2_WR_INTERRUPT_ENABLE	                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 25))))
#define DMA_SG2_RD_DLY_INTERRUPT_TIMEOUT             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 26))))
#define DMA_SG2_WR_DLY_INTERRUPT_TIMEOUT             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 27))))
#define DMA_SG2_RD_IOC_THRESHOLD	                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 28))))
#define DMA_SG2_WR_IOC_THRESHOLD		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 29))))
#define DMA_SG2_RD_INTERRUPT_STATUS		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 30))))
#define DMA_SG2_WR_INTERRUPT_STATUS		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 31))))
#define DMA_SG2_RD_ERROR_STATUS		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 32))))
#define DMA_SG2_WR_ERROR_STATUS		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 33))))
#define DMA_SG2_SEQUENCE_NUMBER		                 (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 34))))
#define DMA_SG2_NON_SG_MODE_RD_IF		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 35))))
#define DMA_SG2_NON_SG_MODE_WR_IF		             (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 36))))
#define DMA_SG2_NON_SG_MODE_WR_IF_BYTES              (*((volatile uint32_t *)(DMA_SG_BASE + (0x4 * 37))))

//define DMA_MM_S_1_REG
#define DMA_CH0_M_S_CURR_RD_DESCR_PTR_LSB	         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  0))))
#define DMA_CH0_M_S_CURR_RD_DESCR_PTR_MSB	         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  1))))
#define DMA_CH0_M_S_START_FETCH      		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  2))))
#define DMA_CH0_M_S_INTERRUPT_ENABLE		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  3))))
#define DMA_CH0_M_S_DLY_INTERRUPT_TIMEOUT	         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  4))))
#define DMA_CH0_M_S_IOC_THRESHOLD		             (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  5))))
#define DMA_CH0_M_S_INTERRUPT_STATUS		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  6))))
#define DMA_CH0_M_S_ERROR_STATUS		             (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  7))))
#define DMA_CH0_M_S_CHANNEL_STATUS		             (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  8))))
#define DMA_CH0_M_S_SEQUENCE_NUMBER 		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 *  9))))
#define DMA_CH0_M_S_NON_SG_MODE_RD_IF		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 10))))
#define DMA_CH0_M_S_NON_SG_MODE_CONTROL              (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 11))))
#define DMA_CH0_M_S_NON_SG_MODE_STATUS               (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 12))))
#define DMA_CH0_M_S_NON_SG_MODE_WR_IF_BYTES          (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 13))))

//define DMA_S_MM_1_REG
#define DMA_CH0_S_M_CURR_RD_DESCR_PTR_LSB	         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 14))))
#define DMA_CH0_S_M_CURR_RD_DESCR_PTR_MSB	         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 15))))
#define DMA_CH0_S_M_START_FETCH      		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 16))))
#define DMA_CH0_S_M_INTERRUPT_ENABLE		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 17))))
#define DMA_CH0_S_M_DLY_INTERRUPT_TIMEOUT	         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 18))))
#define DMA_CH0_S_M_IOC_THRESHOLD		             (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 19))))
#define DMA_CH0_S_M_INTERRUPT_STATUS		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 20))))
#define DMA_CH0_S_M_ERROR_STATUS		             (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 21))))
#define DMA_CH0_S_M_CHANNEL_STATUS		             (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 22))))
#define DMA_CH0_S_M_SEQUENCE_NUMBER 		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 23))))
#define DMA_CH0_S_M_NON_SG_MODE_RD_IF		         (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 24))))
#define DMA_CH0_S_M_NON_SG_MODE_CONTROL              (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 25))))
#define DMA_CH0_S_M_NON_SG_MODE_STATUS               (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 26))))
#define DMA_CH0_S_M_NON_SG_MODE_WR_IF_BYTES          (*((volatile uint32_t *)(DMA_MM_S_BASE + (0x4 * 27))))

//TX ID REG [TABLE.17]
#define TX_BID                                       (*((volatile uint32_t *)(TX_BASE + 0x00)))
#define TX_DID                                       (*((volatile uint32_t *)(TX_BASE + 0x04)))
#define TX_LID_0_5                                   (*((volatile uint32_t *)(TX_BASE + 0x08)))
#define TX_LID_6_11                                  (*((volatile uint32_t *)(TX_BASE + 0x0C)))
#define TX_LID_12_17                                 (*((volatile uint32_t *)(TX_BASE + 0x10)))
#define TX_LID_18_23                                 (*((volatile uint32_t *)(TX_BASE + 0x14)))

//TX CORE CONFIGURATION REG [TABLE.18]
#define TX_SUBCLASS                                  (*((volatile uint32_t *)(TX_BASE + 0x1C)))
#define TX_CF                                        (*((volatile uint32_t *)(TX_BASE + 0x20)))
#define TX_CS                                        (*((volatile uint32_t *)(TX_BASE + 0x24)))
#define TX_F                                         (*((volatile uint32_t *)(TX_BASE + 0x28)))
#define TX_K                                         (*((volatile uint32_t *)(TX_BASE + 0x2C)))
#define TX_L                                         (*((volatile uint32_t *)(TX_BASE + 0x30)))
#define TX_N                                         (*((volatile uint32_t *)(TX_BASE + 0x34)))
#define TX_M                                         (*((volatile uint32_t *)(TX_BASE + 0x38)))
#define TX_NTOTAL                                    (*((volatile uint32_t *)(TX_BASE + 0x3C)))
#define TX_S                                         (*((volatile uint32_t *)(TX_BASE + 0x40)))
#define TX_HD                                        (*((volatile uint32_t *)(TX_BASE + 0x44)))
#define TX_SCR                                       (*((volatile uint32_t *)(TX_BASE + 0x48)))
#define TX_CLK_RATIO                                 (*((volatile uint32_t *)(TX_BASE + 0x13C)))
#define TX_ILAS_DELAY                                (*((volatile uint32_t *)(TX_BASE + 0x2C0)))
#define TX_SOFT_SYNC                                 (*((volatile uint32_t *)(TX_BASE + 0x2D0)))
#define TX_TL_TEST_MODE_REG                          (*((volatile uint32_t *)(TX_BASE + 0x2DC)))

//TX TEST CONFIGURATION REG [TABLE.19]
#define TX_ENABLEMODULE                              (*((volatile uint32_t *)(TX_BASE + 0x50)))
#define TX_ENABLELINKTEST                            (*((volatile uint32_t *)(TX_BASE + 0x54)))
#define TX_TAILBITS                                  (*((volatile uint32_t *)(TX_BASE + 0x58)))

//TX LINK TEST REG [TABLE.20]
#define TX_LINKTEST_CUSTOM_DATA                      (*((volatile uint32_t *)(TX_BASE + 0x5C)))
#define TX_LINKTEST_CUSTOM_ENABLE                    (*((volatile uint32_t *)(TX_BASE + 0x60)))
#define TX_PRBS_TEST_ENABLE                          (*((volatile uint32_t *)(TX_BASE + 0x134)))
#define TX_JTSPAT_TEST_ENABLE                        (*((volatile uint32_t *)(TX_BASE + 0x138)))

//TX FEATURE DISABLE REG [TABLE.21]
#define TX_FEATURE_DISABLE                           (*((volatile uint32_t *)(TX_BASE + 0x120)))
#define TX_CORE_INTERRUPT_MASK                       (*((volatile uint32_t *)(TX_BASE + 0x124)))
#define TX_CORE_INTERRUPT_STATUS                     (*((volatile uint32_t *)(TX_BASE + 0x128)))

//TX INITIAL LANE ALIGNMENT REG [TABLE.23]
#define TX_ILAS_AND_MISC_DETAILS                     (*((volatile uint32_t *)(TX_BASE + 0x12C)))
//TX LMFC DELAY REG [TABLE.24]
#define TX_LMFC_DELAY                                (*((volatile uint32_t *)(TX_BASE + 0x2E0)))
#define TX_SYSREF_MAXSHIFY                           (*((volatile uint32_t *)(TX_BASE + 0x2E4)))

//RX ID REG [TABLE.4]
#define RX_BID                                       (*((volatile uint32_t *)(RX_BASE + 0x00)))
#define RX_DID                                       (*((volatile uint32_t *)(RX_BASE + 0x04)))
#define RX_LID_0_5                                   (*((volatile uint32_t *)(RX_BASE + 0x08)))
#define RX_LID_6_11                                  (*((volatile uint32_t *)(RX_BASE + 0x0C)))
#define RX_LID_12_17                                 (*((volatile uint32_t *)(RX_BASE + 0x10)))
#define RX_LID_18_23                                 (*((volatile uint32_t *)(RX_BASE + 0x14)))

//RX CORE CONFIGURATION REG [TABLE.5]
#define RX_SUBCLASS                                  (*((volatile uint32_t *)(RX_BASE + 0x1C)))
#define RX_CF                                        (*((volatile uint32_t *)(RX_BASE + 0x20)))
#define RX_CS                                        (*((volatile uint32_t *)(RX_BASE + 0x24)))
#define RX_F                                         (*((volatile uint32_t *)(RX_BASE + 0x28)))
#define RX_K                                         (*((volatile uint32_t *)(RX_BASE + 0x2C)))
#define RX_L                                         (*((volatile uint32_t *)(RX_BASE + 0x30)))
#define RX_N                                         (*((volatile uint32_t *)(RX_BASE + 0x34)))
#define RX_M                                         (*((volatile uint32_t *)(RX_BASE + 0x38)))
#define RX_NTOTAL                                    (*((volatile uint32_t *)(RX_BASE + 0x3C)))
#define RX_S                                         (*((volatile uint32_t *)(RX_BASE + 0x40)))
#define RX_HD                                        (*((volatile uint32_t *)(RX_BASE + 0x44)))
#define RX_SCR                                       (*((volatile uint32_t *)(RX_BASE + 0x48)))
#define RX_CLK_RATIO                                 (*((volatile uint32_t *)(RX_BASE + 0x13C)))
#define RX_SOFT_SYNC                                 (*((volatile uint32_t *)(RX_BASE + 0x2D0)))
#define RX_TL_TEST_MODE_REG                          (*((volatile uint32_t *)(RX_BASE + 0x2DC)))
#define RX_LMFC_DELAY                                (*((volatile uint32_t *)(RX_BASE + 0x2E0)))
#define RX_SYSREF_MAXSHIFY                           (*((volatile uint32_t *)(RX_BASE + 0x2E4)))

//RX TEST CONFIGURATION REG [TABLE.6]
#define RX_LINKCONFIGURATIONERRO                     (*((volatile uint32_t *)(RX_BASE + 0x4C)))
#define RX_ENABLEMODULE                              (*((volatile uint32_t *)(RX_BASE + 0x50)))
#define RX_ENABLELINKTEST                            (*((volatile uint32_t *)(RX_BASE + 0x54)))
#define RX_JTSPAT_TEST_ENABLE                        (*((volatile uint32_t *)(RX_BASE + 0x138)))

//RX PRBS-15 TEST REG [TABLE.7]
#define RX_PRBS_TEST_ENABLE                          (*((volatile uint32_t *)(RX_BASE + 0x134)))

//RX LINK TEST REG [TABLE.8]
#define RX_INKTEST_0_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x58)))
#define RX_INKTEST_1_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x5C)))
#define RX_INKTEST_2_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x60)))
#define RX_INKTEST_3_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x64)))
#define RX_INKTEST_4_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x68)))
#define RX_INKTEST_5_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x6C)))
#define RX_INKTEST_6_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x70)))
#define RX_INKTEST_7_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x74)))
#define RX_INKTEST_8_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x78)))
#define RX_INKTEST_9_RECEIVECOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x7C)))
#define RX_INKTEST_10_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x80)))
#define RX_INKTEST_11_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x84)))
#define RX_INKTEST_12_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x88)))
#define RX_INKTEST_13_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x8C)))
#define RX_INKTEST_14_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x90)))
#define RX_INKTEST_15_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x94)))
#define RX_INKTEST_16_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x98)))
#define RX_INKTEST_17_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x9C)))
#define RX_INKTEST_18_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0xA0)))
#define RX_INKTEST_19_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0xA4)))
#define RX_INKTEST_20_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0xA8)))
#define RX_INKTEST_21_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0xAC)))
#define RX_INKTEST_22_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0xB0)))
#define RX_INKTEST_23_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0xB4)))

#define RX_INKTEST_0_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xC0 )))
#define RX_INKTEST_1_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xC4 )))
#define RX_INKTEST_2_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xC8 )))
#define RX_INKTEST_3_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xCC )))
#define RX_INKTEST_4_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xD0 )))
#define RX_INKTEST_5_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xD4 )))
#define RX_INKTEST_6_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xD8 )))
#define RX_INKTEST_7_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xDC )))
#define RX_INKTEST_8_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xE0 )))
#define RX_INKTEST_9_ERRORCOUNTER                    (*((volatile uint32_t *)(RX_BASE + 0xE4 )))
#define RX_INKTEST_10_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0xE8 )))
#define RX_INKTEST_11_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0xEC )))
#define RX_INKTEST_12_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0xF0 )))
#define RX_INKTEST_13_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0xF4 )))
#define RX_INKTEST_14_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0xF8 )))
#define RX_INKTEST_15_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0xFC )))
#define RX_INKTEST_16_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x100)))
#define RX_INKTEST_17_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x104)))
#define RX_INKTEST_18_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x108)))
#define RX_INKTEST_19_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x10C)))
#define RX_INKTEST_20_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x110)))
#define RX_INKTEST_21_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x114)))
#define RX_INKTEST_22_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x118)))
#define RX_INKTEST_23_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x11C)))

//RX PRBS TEST REG [TABLE.9]
#define RX_PRBSTEST_0_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x200)))
#define RX_PRBSTEST_1_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x204)))
#define RX_PRBSTEST_2_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x208)))
#define RX_PRBSTEST_3_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x20C)))
#define RX_PRBSTEST_4_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x210)))
#define RX_PRBSTEST_5_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x214)))
#define RX_PRBSTEST_6_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x218)))
#define RX_PRBSTEST_7_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x21C)))
#define RX_PRBSTEST_8_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x220)))
#define RX_PRBSTEST_9_RECEIVECOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x224)))
#define RX_PRBSTEST_10_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x228)))
#define RX_PRBSTEST_11_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x22C)))
#define RX_PRBSTEST_12_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x230)))
#define RX_PRBSTEST_13_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x234)))
#define RX_PRBSTEST_14_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x238)))
#define RX_PRBSTEST_15_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x23C)))
#define RX_PRBSTEST_16_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x240)))
#define RX_PRBSTEST_17_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x244)))
#define RX_PRBSTEST_18_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x248)))
#define RX_PRBSTEST_19_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x24C)))
#define RX_PRBSTEST_20_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x250)))
#define RX_PRBSTEST_21_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x254)))
#define RX_PRBSTEST_22_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x258)))
#define RX_PRBSTEST_23_RECEIVECOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x25C)))

#define RX_PRBSTEST_0_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x140)))
#define RX_PRBSTEST_1_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x144)))
#define RX_PRBSTEST_2_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x148)))
#define RX_PRBSTEST_3_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x14C)))
#define RX_PRBSTEST_4_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x150)))
#define RX_PRBSTEST_5_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x154)))
#define RX_PRBSTEST_6_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x158)))
#define RX_PRBSTEST_7_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x15C)))
#define RX_PRBSTEST_8_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x160)))
#define RX_PRBSTEST_9_ERRORCOUNTER                   (*((volatile uint32_t *)(RX_BASE + 0x164)))
#define RX_PRBSTEST_10_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x168)))
#define RX_PRBSTEST_11_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x16C)))
#define RX_PRBSTEST_12_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x170)))
#define RX_PRBSTEST_13_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x174)))
#define RX_PRBSTEST_14_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x178)))
#define RX_PRBSTEST_15_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x17C)))
#define RX_PRBSTEST_16_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x180)))
#define RX_PRBSTEST_17_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x184)))
#define RX_PRBSTEST_18_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x188)))
#define RX_PRBSTEST_19_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x18C)))
#define RX_PRBSTEST_20_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x190)))
#define RX_PRBSTEST_21_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x194)))
#define RX_PRBSTEST_22_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x198)))
#define RX_PRBSTEST_23_ERRORCOUNTER                  (*((volatile uint32_t *)(RX_BASE + 0x19C)))

//RX JISPAT TEST REG [TABLE.10]
#define RX_JTSPATTEST_0_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x260)))
#define RX_JTSPATTEST_1_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x264)))
#define RX_JTSPATTEST_2_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x268)))
#define RX_JTSPATTEST_3_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x26C)))
#define RX_JTSPATTEST_4_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x270)))
#define RX_JTSPATTEST_5_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x274)))
#define RX_JTSPATTEST_6_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x278)))
#define RX_JTSPATTEST_7_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x27C)))
#define RX_JTSPATTEST_8_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x280)))
#define RX_JTSPATTEST_9_RECEIVECOUNTER               (*((volatile uint32_t *)(RX_BASE + 0x284)))
#define RX_JTSPATTEST_10_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x288)))
#define RX_JTSPATTEST_11_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x28C)))
#define RX_JTSPATTEST_12_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x290)))
#define RX_JTSPATTEST_13_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x294)))
#define RX_JTSPATTEST_14_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x298)))
#define RX_JTSPATTEST_15_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x29C)))
#define RX_JTSPATTEST_16_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2A0)))
#define RX_JTSPATTEST_17_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2A4)))
#define RX_JTSPATTEST_18_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2A8)))
#define RX_JTSPATTEST_19_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2AC)))
#define RX_JTSPATTEST_20_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2B0)))
#define RX_JTSPATTEST_21_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2B4)))
#define RX_JTSPATTEST_22_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2B8)))
#define RX_JTSPATTEST_23_RECEIVECOUNTER              (*((volatile uint32_t *)(RX_BASE + 0x2BC)))

#define RX_JTSPATTEST_0_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1A0)))
#define RX_JTSPATTEST_1_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1A4)))
#define RX_JTSPATTEST_2_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1A8)))
#define RX_JTSPATTEST_3_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1AC)))
#define RX_JTSPATTEST_4_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1B0)))
#define RX_JTSPATTEST_5_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1B4)))
#define RX_JTSPATTEST_6_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1B8)))
#define RX_JTSPATTEST_7_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1BC)))
#define RX_JTSPATTEST_8_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1C0)))
#define RX_JTSPATTEST_9_ERRORCOUNTER                 (*((volatile uint32_t *)(RX_BASE + 0x1C4)))
#define RX_JTSPATTEST_10_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1C8)))
#define RX_JTSPATTEST_11_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1CC)))
#define RX_JTSPATTEST_12_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1D0)))
#define RX_JTSPATTEST_13_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1D4)))
#define RX_JTSPATTEST_14_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1D8)))
#define RX_JTSPATTEST_15_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1DC)))
#define RX_JTSPATTEST_16_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1E0)))
#define RX_JTSPATTEST_17_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1E4)))
#define RX_JTSPATTEST_18_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1E8)))
#define RX_JTSPATTEST_19_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1EC)))
#define RX_JTSPATTEST_20_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1F0)))
#define RX_JTSPATTEST_21_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1F4)))
#define RX_JTSPATTEST_22_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1F8)))
#define RX_JTSPATTEST_23_ERRORCOUNTER                (*((volatile uint32_t *)(RX_BASE + 0x1FC)))

//RX FEATURE DISABLE REG [TABLE.11]
#define RX_FEATURE_DISABLE                           (*((volatile uint32_t *)(RX_BASE + 0x120)))

//RX CORE INTERRUPT REGISTERS [TABLE.12]
#define RX_CORE_INTERRUPT_MASK                       (*((volatile uint32_t *)(RX_BASE + 0x124)))
#define RX_CORE_INTERRUPT_STATUS                     (*((volatile uint32_t *)(RX_BASE + 0x128)))

//RX INITIAL LANE ALIGNMENT REG [TABLE.13]
#define RX_ILAS_AND_MISC_DETAILS                     (*((volatile uint32_t *)(RX_BASE + 0x12C)))

//ERROR INJECTION REG [TABLE.14]
#define RX_ERR_INJ_REQ                               (*((volatile uint32_t *)(RX_BASE + 0x130)))
//Mtimer REG define 0x05250000
#define PIN_CTRL_REG                                 (*((volatile uint32_t *)(Mtimer_BASE + 0x00*4)))
#define IO_CTRL_REG                                  (*((volatile uint32_t *)(Mtimer_BASE + 0x01*4)))
#define TMR_INTC_REG                                 (*((volatile uint32_t *)(Mtimer_BASE + 0x02*4)))
#define TMR_SCR_CTRL_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x03*4)))
#define TMR_CTRL_REG                                 (*((volatile uint32_t *)(Mtimer_BASE + 0x04*4)))
#define TMR_TEVENT_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x10*4)))
#define TMR_TSCR_TRG_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x11*4)))
#define TMR_TWREQ_REG                                (*((volatile uint32_t *)(Mtimer_BASE + 0x12*4)))
#define TMR_TINTE0_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x13*4)))
#define TMR_TINTF0_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x14*4)))
#define TMR_TINTE1_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x15*4)))
#define TMR_TINTF1_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x16*4)))
#define TMR_TINTE2_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x17*4)))
#define TMR_TINTF2_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x18*4)))
#define TMR_CEVENT_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x19*4)))
#define TMR_CMSK_REG                                 (*((volatile uint32_t *)(Mtimer_BASE + 0x1A*4)))
#define TMR_CINTE0_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x1B*4)))
#define TMR_CINTF0_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x1C*4)))
#define TMR_CINTE1_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x1D*4)))
#define TMR_CINTF1_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x1E*4)))
#define TMR_CINTE2_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x1F*4)))
#define TMR_CINTF2_REG                               (*((volatile uint32_t *)(Mtimer_BASE + 0x20*4)))
#define TMR_OVFL_REG                                 (*((volatile uint32_t *)(Mtimer_BASE + 0x21*4)))
#define TMR_OVFH_REG                                 (*((volatile uint32_t *)(Mtimer_BASE + 0x22*4)))
#define TMR_RXEN0_0L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x23*4)))
#define TMR_RXEN0_0H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x24*4)))
#define TMR_RXEN0_1L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x25*4)))
#define TMR_RXEN0_1H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x26*4)))
#define TMR_TXEN0_0L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x27*4)))
#define TMR_TXEN0_0H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x28*4)))
#define TMR_TXEN0_1L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x29*4)))
#define TMR_TXEN0_1H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x2A*4)))
#define TMR_RXEN1_0L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x2B*4)))
#define TMR_RXEN1_0H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x2C*4)))
#define TMR_RXEN1_1L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x2D*4)))
#define TMR_RXEN1_1H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x2E*4)))
#define TMR_TXEN1_0L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x2F*4)))
#define TMR_TXEN1_0H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x30*4)))
#define TMR_TXEN1_1L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x31*4)))
#define TMR_TXEN1_1H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x32*4)))
#define TMR_RXEN2CSU0L_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x33*4)))
#define TMR_RXEN2CSU0H_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x34*4)))
#define TMR_RXEN2CSU1L_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x35*4)))
#define TMR_RXEN2CSU1H_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x36*4)))
#define TMR_TXEN2CSU0L_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x37*4)))
#define TMR_TXEN2CSU0H_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x38*4)))
#define TMR_TXEN2CSU1L_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x39*4)))
#define TMR_TXEN2CSU1H_REG                           (*((volatile uint32_t *)(Mtimer_BASE + 0x3A*4)))
#define TMR_SCRATH0L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x3B*4)))
#define TMR_SCRATH0H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x3C*4)))
#define TMR_SCRATH1L_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x3D*4)))
#define TMR_SCRATH1H_REG                             (*((volatile uint32_t *)(Mtimer_BASE + 0x3E*4)))
#define TMR_RX_SCRL_REG                              (*((volatile uint32_t *)(Mtimer_BASE + 0x3F*4)))
#define TMR_RX_SCRH_REG                              (*((volatile uint32_t *)(Mtimer_BASE + 0x40*4)))
#define TMR_TX_SCRL_REG                              (*((volatile uint32_t *)(Mtimer_BASE + 0x41*4)))
#define TMR_TX_SCRH_REG                              (*((volatile uint32_t *)(Mtimer_BASE + 0x42*4)))
#define TMR_1PPSL_REG                                (*((volatile uint32_t *)(Mtimer_BASE + 0x43*4)))
#define TMR_1PPSH_REG                                (*((volatile uint32_t *)(Mtimer_BASE + 0x44*4)))
#define TMR_TnL_REG0                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*0))*4)))
#define TMR_TnL_REG1                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*1))*4)))
#define TMR_TnL_REG2                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*2))*4)))
#define TMR_TnL_REG3                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*3))*4)))
#define TMR_TnL_REG4                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*4))*4)))
#define TMR_TnL_REG5                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*5))*4)))
#define TMR_TnL_REG6                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*6))*4)))
#define TMR_TnL_REG7                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*7))*4)))
#define TMR_TnL_REG8                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*8))*4)))
#define TMR_TnL_REG9                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*9))*4)))
#define TMR_TnL_REG10                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*10))*4)))
#define TMR_TnL_REG11                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*11))*4)))
#define TMR_TnL_REG12                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*12))*4)))
#define TMR_TnL_REG13                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*13))*4)))
#define TMR_TnL_REG14                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*14))*4)))
#define TMR_TnL_REG15                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*15))*4)))
#define TMR_TnL_REG16                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*16))*4)))
#define TMR_TnL_REG17                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*17))*4)))
#define TMR_TnL_REG18                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*18))*4)))
#define TMR_TnL_REG19                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*19))*4)))
#define TMR_TnL_REG20                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*20))*4)))
#define TMR_TnL_REG21                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*21))*4)))
#define TMR_TnL_REG22                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*22))*4)))
#define TMR_TnL_REG23                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*23))*4)))
#define TMR_TnL_REG24                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*24))*4)))
#define TMR_TnL_REG25                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*25))*4)))
#define TMR_TnL_REG26                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*26))*4)))
#define TMR_TnL_REG27                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*27))*4)))
#define TMR_TnL_REG28                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*28))*4)))
#define TMR_TnL_REG29                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*29))*4)))
#define TMR_TnL_REG30                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*30))*4)))
#define TMR_TnL_REG31                                (*((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*31))*4)))
#define TMR_TnH_REG0                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*0))*4)))
#define TMR_TnH_REG1                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*1))*4)))
#define TMR_TnH_REG2                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*2))*4)))
#define TMR_TnH_REG3                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*3))*4)))
#define TMR_TnH_REG4                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*4))*4)))
#define TMR_TnH_REG5                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*5))*4)))
#define TMR_TnH_REG6                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*6))*4)))
#define TMR_TnH_REG7                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*7))*4)))
#define TMR_TnH_REG8                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*8))*4)))
#define TMR_TnH_REG9                                 (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*9))*4)))
#define TMR_TnH_REG10                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*10))*4)))
#define TMR_TnH_REG11                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*11))*4)))
#define TMR_TnH_REG12                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*12))*4)))
#define TMR_TnH_REG13                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*13))*4)))
#define TMR_TnH_REG14                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*14))*4)))
#define TMR_TnH_REG15                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*15))*4)))
#define TMR_TnH_REG16                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*16))*4)))
#define TMR_TnH_REG17                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*17))*4)))
#define TMR_TnH_REG18                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*18))*4)))
#define TMR_TnH_REG19                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*19))*4)))
#define TMR_TnH_REG20                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*20))*4)))
#define TMR_TnH_REG21                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*21))*4)))
#define TMR_TnH_REG22                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*22))*4)))
#define TMR_TnH_REG23                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*23))*4)))
#define TMR_TnH_REG24                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*24))*4)))
#define TMR_TnH_REG25                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*25))*4)))
#define TMR_TnH_REG26                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*26))*4)))
#define TMR_TnH_REG27                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*27))*4)))
#define TMR_TnH_REG28                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*28))*4)))
#define TMR_TnH_REG29                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*29))*4)))
#define TMR_TnH_REG30                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*30))*4)))
#define TMR_TnH_REG31                                (*((volatile uint32_t *)(Mtimer_BASE + (0x51+(2*31))*4)))

#define TMR_TnL_REG4_ADDR                                 ((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*4))*4))
#define TMR_TnL_REG3_ADDR                                 ((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*3))*4))

#define TMR_TnL_REG19_ADDR                                ((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*19))*4))
#define TMR_TnL_REG26_ADDR                                ((volatile uint32_t *)(Mtimer_BASE + (0x50+(2*26))*4))

#endif



