// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : cpri_test_case34.c
// Author        : xinxin.li
// Created On    : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#include "typedef.h"
#include "ucp_utility.h"
#include "cpri_csu_nr_7ds2u.h"
#include "cpri_test_case34.h"
#include "cpri_timer.h"
#include "ape_csu.h"
#include "cpri_test.h"
#include "ucp_printf.h"
#include "HeaderRam.h"
#include "cpri_driver.h"
#include "phy_para.h"
#include "hw_cpri.h"
#include "rfm1_drv.h"
//#include "spu_hw_queue.h"
//#include "spu_log.h"
//#include "ecs_rfm_spu1_heap.h"
//#include "app_interface.h"

#include <malloc.h>
uint32_t srcImData[4*1024] = {0};	// 16KB
extern uint32_t 		gCpriTestMode;
extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];

extern uint32_t gCpriTestMode;
//extern uint32_t           CPRI_OPTION;
extern uint32_t			gCpriCsuDummyFlag;
extern volatile uint32_t gVendorFlag;

#define HeaderTestCnt   10

int32_t fh_data_init(void)
{
	gCpriTestMode = CPRI_TEST_MODE;
	gCpriCsuDummyFlag  = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300

//	Get_Cpri_OptionId();//get cpri option value
//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
		
	Axc_data_init();//init axc data
	UCP_PRINT_EMPTY("Axc data init.\r\n");
	HeaderTxRam_data_init();
	//HeaderTxRam_init();

	return 0;
}

int32_t fh_drv_init(void)
{
	stFrontHaulDrvPara fhDrvPara;
	memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));

	fhDrvPara.protocolSel = PROTOCOL_CPRI;
	fhDrvPara.rateOption = CPRI_OPTION_8;
	fhDrvPara.mapOption = OTIC_MAP_FIGURE12;

	fronthaul_drv_cfg(&fhDrvPara);

	return 0;
}

int32_t fh_csu_test_init(void)
{
	stCpriCsuCmdFifoInfo		txTestCmdFifo;
	stCpriCsuCmdFifoInfo		rxTestCmdFifo;
	
	cpri_csu_axc_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
	cpri_csu_axcctrl_init_timing();
	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);

	return 0;
}

void fh_test_case()
{
	UCP_API_CPRI_CSU_START();
}

uint32_t gCompWordCnt = 0;
uint32_t gErrSlotIdCnt = 0;
uint32_t gCompSlotIdCnt = 0;
uint32_t gBfStartErr = 0;
uint32_t cnt = 0;
void fh_data_check(uint32_t times)
{
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
	if (4 <= pMtimerInt->csuEnCnt)
	{
		gCompWordCnt = 0;
		for (int32_t i = 0; i < (CPRI_CASE34_SLOT_NUM>>1); i++)
		{
			cpri_check_slot_data(i);
		}
		if(24000 <= pMtimerInt->csuEnCnt)
		{ 
			
			//if(0 == cnt)
			{
				if(0 == gErrSlotIdCnt)
				{ 
					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
					UCP_PRINT_WARN("cpri test pass!\r\n");
				}
				else
				{
					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
				}
				cnt++;				
			}
		}
		Cpri_Header_Rx();
	}
}

void Get_Cpri_OptionId()
{
//	CPRI_OPTION = CPRI_OPTION_8;
    return;
}

void HeaderTxRam_data_init()
{
	for(int i=0;i<16*HeaderTestCnt;i++)
	{
		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
	}
#if 0
	for(int i=0;i<16*HeaderTestCnt;i++)
	{
		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
	}
#endif
}
#if 0
void HeaderTxRam_init()
{
	uint32_t i,j;
	HeaderRam_ins_disable();
	for(i=0;i<64;i++)//Ns
	{
		for(j=0;j<4;j++)//
		{
			HeaderRam_Tx(i+64*j,0,0,0);//vendor
			HeaderRam_Tx(i+64*j,1,0,0);//vendor
			HeaderRam_Tx(i+64*j,2,0,0);//vendor
			HeaderRam_Tx(i+64*j,3,0,0);//vendor
		}
	}
	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
}
#endif
void Axc_data_init()
{
	uint8_t idID = 0;
	uint8_t idSlot = 0;			// even slot, odd slot
	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
	uint8_t idSymbol = 0;
	uint16_t idBF = 0;
	uint16_t idWord = 0;

	uint32_t* pSrcAddr = 0;
	uint32_t  srcAddr = 0;
	uint32_t  dstAddr = 0;
	uint32_t  dataLen = 0;
	uint16_t  bfByteCnt = 0;
	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;
	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;
	uint32_t  symbolBfCnt = 0;
	uint32_t  idSlotBf = 0;
	uint32_t  val = 0;
	
	//uint32_t* srcImData = dmalloc(10240, DM0);
	
	//debug_write((DBG_DDR_IDX_DRV_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
	//debug_write((DBG_DDR_IDX_DRV_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304

	uint32_t cpyCnt = 0;
	//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
	//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
	cpyCnt++;

	// valid data
	// compress factor
	for (idSlot = 0; idSlot <= 1; idSlot++)
	{
		bfByteCnt = 2;
		
		pSrcAddr = srcImData;
		if (0 == idSlot)	// even slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
		}
		else				// odd slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
		}
		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
		{
			val = (idSlot<<28) | ((idBF<<1)<<8) | (0);
			*pSrcAddr = val;
			pSrcAddr++;
		}
		dataLen = (bfByteCnt*slotBfCnt); 
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//		cpyCnt++;
		
		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
	}

	// IQ data	
	for (idID = 1; idID < 5; idID++)
	{
		bfByteCnt = 64;
		for (idSlot = 0; idSlot <= 1; idSlot++)
		{
			idSlotBf = 0;
			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
			{
				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
				}
				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
				}
				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
				}
				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
				{
					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
				}
				for (idSymbol = 0; idSymbol < 7; idSymbol++)
				{
					pSrcAddr = srcImData;
					if ((0 == idSymbol) && (0 == idSymbolBlock))
					{
						symbolBfCnt = LONGCP_BF_CNT;
					}
					else
					{
						symbolBfCnt = SHORTCP_BF_CNT;
					}
					for (idBF = 0; idBF < symbolBfCnt; idBF++)	// basic frame
			 		{
						for (idWord = 0; idWord < (bfByteCnt>>2); idWord++)
						{
								val = (idSlot<<28) | (idID<<24) | ((idSlotBf++)<<8) | (idWord);
								*pSrcAddr = val;
								pSrcAddr++;
						}
			 		}
					dataLen = symbolBfCnt*bfByteCnt;
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//					cpyCnt++;
					memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
					dstAddr += dataLen;
				}
			}
		}
	}

	// agc factor
	for (idSlot = 0; idSlot <= 1; idSlot++)
	{
		bfByteCnt = 2;
		
		pSrcAddr = srcImData;
		if (0 == idSlot)	// even slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_AGC_ADDR;
		}
		else				// odd slot
		{
			dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR;
		}
		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
		{
			val = (idSlot<<28) | (5<<24) | ((idBF<<1)<<8) | (0);
			*pSrcAddr = val;
			//do_write(((uint32_t)pSrcAddr), val);
			pSrcAddr++;
		}
		dataLen = (bfByteCnt*slotBfCnt); 
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//		cpyCnt++;
		
		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	}

	// dummy data
	// compress factor
	uint8_t bitOffset = 1; // one bf, 2B
	//uint8_t tag = 0;
	// S slot, symbol6~13, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
	dstAddr = CPRI_NR7DS2U_TX_DUMMY_COMPRESS_ADDR;
	dataLen = (SHORTCP_BF_CNT*8)<<bitOffset;
	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);

	// slot8, even slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
	// slot9, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);

	// axc data
	bitOffset = 6;		// one bf, 64B
	for (uint8_t antId = 0; antId < 4; antId++)
	{
		// S slot, symbol6, odd slot
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (antId*(f7BfCnt<<bitOffset)) + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
		dstAddr = CPRI_NR7DS2U_TX_DUMMY_AXC1DATA_ADDR + antId*CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN;
		dataLen = (SHORTCP_BF_CNT)<<bitOffset;
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
		// S slot, symbol7~13
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (antId*(b7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = b7BfCnt<<bitOffset;
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
		// slot8, even slot, symbol0~6
		srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + (antId*(f7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = f7BfCnt<<bitOffset;
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
		// slot8, even slot, symbol7~13
		srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + (antId*(b7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = b7BfCnt<<bitOffset;
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
		// slot9, odd slot, symbol0~6
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (antId*(f7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = f7BfCnt<<bitOffset;
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
		// slot9, odd slot, symbol7~13
		srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (antId*(b7BfCnt<<bitOffset));
		dstAddr += dataLen;
		dataLen = b7BfCnt<<bitOffset;
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
		//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
		cpyCnt++;
		//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
	}

	// AGC factor
	bitOffset = 1; // one bf, 2B
	// S slot, symbol6~13, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
	dstAddr = CPRI_NR7DS2U_TX_DUMMY_AGC_ADDR;
	dataLen = (SHORTCP_BF_CNT*8)<<bitOffset;
	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
	// slot8, even slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_AGC_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
	// slot9, odd slot
	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR;
	dstAddr += dataLen;
	dataLen = slotBfCnt<<bitOffset;
	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
}

uint32_t Txdata[48] ={0};
uint32_t Rxdata0[48] ={0};

uint32_t Header_error0=0;
uint32_t Header_error1 = 0;
//uint32_t HeaderRxtimes = 0;
extern uint32_t HeaderTxtimes;

void Cpri_Header_Rx(void)
{
	uint32_t j= 0;
	if(OTIC_MAP_FIGURE12 == gVendorFlag)
	{
//		HeaderRxtimes++;
#if 1
		while(1)
		{
			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
			{
				break;
			}
		}
#endif
		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));

		for(j=0;j<4;j++)
		{
			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);

		}
		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
		for(j=0;j<48;j++)
		{
			if (Rxdata0[j] != Txdata[j])//vendor
			{
				Header_error0++;
				Header_error1++;
			}
		}

		
		if(Header_error1!=0)
		{
			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
			Header_error1 =0;
		}
		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
		}
}


void cpri_check_slot_data(uint32_t slotNum)
{
	// move data from sm to ddr
	uint32_t slotId = 0;
	uint32_t srcAddr = 0;
	uint32_t srcAddr1 = 0;
	uint32_t realSrcAddr = 0;
	uint32_t dataLen = 0;
	uint8_t bitOffset = 0;
	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
	uint8_t	bfWordCnt = 0;

	uint8_t slotVal = 0;
	uint8_t idVal = 0;
	int32_t bfStart = 0;

	uint32_t compVal = 0;
	uint32_t recvVal = 0;
	uint32_t recvAddr = 0;
	
	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
//	__ucps2_synch(0);
	for (uint32_t i = 0; i < 5; i++)
	{
		gCompSlotIdCnt++;
		idVal = i;
		bfStart = 0;
//		__ucps2_synch(0);
		if ((slotId >=0) && (slotId <= 6))
		{
			slotVal = slotId & 0x1;
			
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = 64>>2;
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
			}
			dataLen = slotBfCnt << bitOffset;
		}
		else if (7 == slotId)		// compare S slot, odd slot
		{
			bfStart = (LONGCP_BF_CNT+SHORTCP_BF_CNT*9);
			slotVal = 1;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset);
				srcAddr1 = CPRI_NR7DS2U_RX_SLOTS_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = (64>>2);
				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(slotBfCnt<<bitOffset);
				srcAddr1 = CPRI_NR7DS2U_RX_SLOTS_AXCDATA_ADDR + (i-1)*((SHORTCP_BF_CNT*4)<<bitOffset);
			}
			dataLen = slotBfCnt << bitOffset;
		}
		else if (8 == slotId)		// current slot is odd slot, compare even slot, slot8
		{
			slotVal = 0;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = (64>>2);
				srcAddr = CPRI_NR7DS2U_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)*(slotBfCnt<<bitOffset));
			}
			dataLen = slotBfCnt << bitOffset;
		}
		else if (9 == slotId)	// compare odd slot, slot9
		{
			slotVal = 1;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NR7DS2U_RX_SLOT_ODD_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 6;	// one BF, 64B
				bfWordCnt = (64>>2);
				srcAddr = CPRI_NR7DS2U_RX_SLOT_ODD_AXCDATA_ADDR + ((i-1)*(slotBfCnt<<bitOffset));
			}
			dataLen = slotBfCnt << bitOffset;
		}

		if (0 == i)	// compress factor
		{
			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
					compVal = (slotVal<<28) | (idVal<<24) | ((idBf<<1)<<8) | (idWord);
					
					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;
					__ucps2_synch(0);
					
					if ((7 == slotId) && (686 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
						if (0 > (idBf-(bfStart>>1)))
						{
							gBfStartErr++;
							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
						}
						realSrcAddr = srcAddr1;
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						if (gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
						}
						gErrSlotIdCnt++;
//						break;
//						break;
					}
//					__ucps2_synch(0);
				}
			}
		}
		else		// axc data
		{
			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
					compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<4)+idWord)<<8) | (idWord);
					
//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;
					__ucps2_synch(0);
					
					if ((7 == slotId) && (1372 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
						realSrcAddr = srcAddr1;
						if (0 > (idBf-bfStart))
						{
							gBfStartErr++;
							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
						}
					}
					else
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
//					__ucps2_synch(0);
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						if (gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
						}
						gErrSlotIdCnt++;
//						break;
//						break;
					}
				}
			}
		}
		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
	}
}

