// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : phy_init.c
// Author        : xianfeng.du
// Created On    : 2022-12-27
// Last Modified :
// -----------------------------------------------------------------
// Description:
// ecs_rfm_spu1 phy_init
//
// -FHDR------------------------------------------------------------

#include "phy_para.h"
#include "mtimer_cell.h"
#include "ucp_utility.h"
#include "hw_cpri.h"
#include "app_interface.h"

#define CELL_SETUP_TYPE_SIMULATION (0x5a6b7c8d)

#define ECS_RFM1_TEST_MSG_SIZE   (8)
#define ECS_RFM1_MSG_TYPE        (0)

uint8_t gu8_send_create_task_cnt = 0;
uint8_t gu8_send_del_task_cnt = 0;
void ecs_rfm1_send_create_task_info(uint8_t dst_core_id)
{
    uint32_t core_id = get_core_id();
    int32_t  ret = 0;
    char* addr = NULL;
    addr = osp_alloc_msg(ECS_RFM1_TEST_MSG_SIZE);
    if (NULL == addr)
    {
        debug_write(DBG_DDR_COMMON_IDX(core_id, 58), 0xa1);
        debug_write(DBG_DDR_COMMON_IDX(core_id, 59), dst_core_id);
        return ;
    }
	debug_write(DBG_DDR_COMMON_IDX(core_id, 4), (uint32_t)addr);
    do_write(addr, 0xa1a2a3a4);
    do_write((addr+4), 0xb1b2b3b4);
    ret = osp_send_msg((uint32_t)(addr),
                        ECS_RFM1_TEST_MSG_SIZE,
                        ECS_RFM1_MSG_TYPE,
                        11,     // src que id
                        dst_core_id,      // dst que id
                        50,     // src task id
                        50);    // dst task id
    
    if (0 != ret)
    {
        debug_write(DBG_DDR_COMMON_IDX(core_id, 58), 0xa2);
        debug_write(DBG_DDR_COMMON_IDX(core_id, 59), dst_core_id);
        return ;
    }
    debug_write(DBG_DDR_COMMON_IDX(core_id, 60), ++gu8_send_create_task_cnt);
    return ;
}

void ecs_rfm1_send_del_task_info(uint8_t dst_core_id)
{
    uint32_t core_id = get_core_id();
    int32_t  ret = 0;
    char* addr = NULL;
    addr = osp_alloc_msg(ECS_RFM1_TEST_MSG_SIZE);
    if (NULL == addr)
    {
        debug_write(DBG_DDR_COMMON_IDX(core_id, 61), 0xa1);
        debug_write(DBG_DDR_COMMON_IDX(core_id, 62), dst_core_id);
        return ;
    }
	debug_write(DBG_DDR_COMMON_IDX(core_id, 4), (uint32_t)addr);
    do_write(addr, 0xa1a2a3a4);
    do_write((addr+4), 0xb1b2b3b4);
    ret = osp_send_msg((uint32_t)(addr),
                        ECS_RFM1_TEST_MSG_SIZE,
                        ECS_RFM1_MSG_TYPE,
                        11,     // src que id
                        dst_core_id,      // dst que id
                        51,     // src task id
                        51);    // dst task id
    
    if (0 != ret)
    {
        debug_write(DBG_DDR_COMMON_IDX(core_id, 61), 0xa2);
        debug_write(DBG_DDR_COMMON_IDX(core_id, 62), dst_core_id);
        return ;
    }
    debug_write(DBG_DDR_COMMON_IDX(core_id, 63), ++gu8_send_del_task_cnt);
    return ;
}

void ecs_rfm1_build_cell(uint32_t scsId, uint32_t flag)
{
	phy_timer_config_ind_t my_cpritmr;

	if (NR_SCS_30K == scsId)
	{
		my_cpritmr.scsId = NR_SCS_30K;
#ifdef TEST_ENABLE
		my_cpritmr.runCoreId = 0;
#else
		if (0 == flag)
		{
			my_cpritmr.runCoreId = 0xF; 	// 0x3; //
		}
		else
		{
			my_cpritmr.runCoreId = 0xF0;	// 0x3; //
		}
#endif
		my_cpritmr.t_period = 5000;
		my_cpritmr.t_us = 500;
		my_cpritmr.num_tti = 10;
		my_cpritmr.num_tti_per_sfn = 20;
	
		my_cpritmr.num_t_dl[0] = 7;		// dl slot num
		my_cpritmr.num_t_dl_symb[0] = 6;	// dl symbol num
		my_cpritmr.num_t_ul_symb[0] = 4;	// ul symbol num
		my_cpritmr.num_ants[0] = 4;
	}
	else if (LTE_SCS_ID == scsId)
	{
		my_cpritmr.scsId = LTE_SCS_ID;
#ifdef TEST_ENABLE
		my_cpritmr.runCoreId = 0;
#else
		if (0 == flag)
		{
			my_cpritmr.runCoreId = 0xF; 	// 0x3; //
		}
		else
		{
			my_cpritmr.runCoreId = 0xF0;    // 0x3; //
		}
#endif
		my_cpritmr.t_period = 10000;
		my_cpritmr.t_us = 1000;
		my_cpritmr.num_tti = 10;
		my_cpritmr.num_tti_per_sfn = 10;
	
		my_cpritmr.num_t_dl[0] =10;// 7;		// dl slot num
		my_cpritmr.num_t_dl_symb[0] = 14;//6;	// dl symbol num
		my_cpritmr.num_t_ul_symb[0] = 14;//4;	// ul symbol num
		my_cpritmr.num_ants[0] = 2;
	}

	mtimer_init4phy(&my_cpritmr);

	uint32_t apeId = 0;
	uint32_t runCore = my_cpritmr.runCoreId;
	volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
	while (h1Pos != 32)
	{
		apeId = 31 - h1Pos;
		if (8 <= apeId)
		{
			return;
		}

		ecs_rfm1_send_create_task_info(apeId);
		
		runCore &= (~(1 << apeId));
		h1Pos = __builtin_clz(runCore);
	}

	//for (int32_t coreId = 0; coreId < 4; coreId++)
	{
		//ecs_rfm1_send_create_task_info(coreId);
	}
}

void ecs_rfm1_delete_cell(uint32_t scsId, uint32_t nflag)
{
	int32_t ret = 0;
#ifdef PALLADIUM_TEST
	int32_t flag = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+52), flag);		// 0xb7e060d0
#endif
	
	stPhyDelCell myDelCell;
	myDelCell.scsId = scsId;
	if (0 == nflag)
	{
		myDelCell.delCoreId = 0xF0;
	}
	else if (1 == nflag)
	{
		myDelCell.delCoreId = 0xF;
	}
	else
	{
		return;
	}

	uint32_t apeId = 0;
	uint32_t runCore = myDelCell.delCoreId;
	volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
	while (h1Pos != 32)
	{
		apeId = 31 - h1Pos;
		if (8 <= apeId)
		{
			return;
		}

		ecs_rfm1_send_del_task_info(apeId);
		
		runCore &= (~(1 << apeId));
		h1Pos = __builtin_clz(runCore);
	}
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+52), flag);		// 0xb7e060d0
#endif

	ret = mtimer_del_cell_cfg(&myDelCell);
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+52), flag);		// 0xb7e060d0
#endif
}

volatile uint32_t gCellFlag = 0;
void phy_init(void)
{
	gCellFlag = 0;
	return;
}

void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
{
	uint32_t msg_buf = do_read(u32msg_addr);
	uint32_t msg_type = do_read(msg_buf);
    if ((CELL_SETUP_TYPE_SIMULATION == msg_type) && (2 > gCellFlag))
    //if ((CELL_SETUP_TYPE_SIMULATION == msg_type) && (0 == gCellFlag)) 
	{
#ifdef CPRI_TIMING_7D2U_TEST
        ecs_rfm1_build_cell(NR_SCS_30K, gCellFlag);
#endif
		
#ifdef CPRI_TIMING_LTE_FDD_TEST
        ecs_rfm1_build_cell(LTE_SCS_ID, gCellFlag);
#endif
		if (0 == gCellFlag)
		{
			debug_write(DBG_DDR_COMMON_IDX(get_core_id(),2), msg_type);
		}
		else if (1 == gCellFlag)
		{
			debug_write(DBG_DDR_COMMON_IDX(get_core_id(),3), msg_type);
		}
		else
		{
		}
        ++gCellFlag;
		debug_write(DBG_DDR_COMMON_IDX(get_core_id(),1), gCellFlag);
	}

	return;
}


uint32_t gDdrCallCnt = 0;
void ddr_wr_callback()
{
	gDdrCallCnt++;
	debug_write((DBG_DDR_IDX_DRV_BASE+127), gDdrCallCnt); // 0x1fc
}

uint32_t gFapiCallCnt = 0;
void rfm1_fapi_callback()
{
	gFapiCallCnt++;
	debug_write((DBG_DDR_IDX_DRV_BASE+123), gFapiCallCnt); // 0x1ec
}


