#include "ecpri_timer.h"

#include "ucp_ecpri.h"
#include "phy_para.h"
#include "mtimer_com.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "ucp_mtimer.h"
#include "inter_vector.h"
#include "ecs_rfm_dm_mgt.h"
#include "mtimer_drv.h"
#include "ucp_js_ctrl.h"

extern stPhyScsPara* phyPara;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];

void ecpri_init()
{
#ifdef PALLADIUM_TEST
	int32_t flag = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif

	// 扩皮模式下，ecpri timer使用cpri_div33_tx_clk，与cpri core clk同源
	init_ecpri_clk();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif
#if 0
	init_ecpri_pma_rst();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif
#endif

	ecpri_pcs_rst_ctrl();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif
	ecpri_mtimer_init(LTE_SCS_ID, 10);
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif
}

void init_ecpri_clk(void)
{
	//JECS_CRG_PLLSEL |=BIT11+BIT4+BIT5+BIT31;
	//JECS_CRG_PLLSEL |=BIT11+BIT5+BIT31;
	JECS_CRG_PLLSEL |= BIT11;
	//JECS_CRG_CLK_CTRL6		 =	 0x521000; //SYSAPB /2	apb_aclk_i
	//switch_core_clk_i,
	//switch_sch_clk_i,
	//JECS_CRG_CLK_CTRL7		 =	 0x520000;//jecs_pma_tx0_ropll_div33_clk
	//ecpri_switch_mae_core_clk
	//JECS_CRG_CLK_CTRL8		=	 0x520000;//jecs_pma_tx0_ropll_div33_clk
	//ecpri_pcs_xgmii_tx_clk
	JECS_CRG_CLK_CTRL9		=	 0x521000;//jecs_pcs_xgmii_tx_clk
	//ecpri_pcs_xgmii_rx_clk
	//JECS_CRG_CLK_CTRL0		=	 0x521000;//jecs_pma_rx0_div33_clk
}

void init_ecpri_pma_rst(void)
{
  //cancell jecs pma rst
  JECS_CRG_PMA16_RST_CTRL |= BIT24;
  JECS_CRG_PMA8_RST_CTRL  |= BIT24;
  JECS_CRG_PMA9_RST_CTRL  |= BIT24;
  JECS_CRG_PMA10_RST_CTRL |= BIT24;
  JECS_CRG_PMA11_RST_CTRL |= BIT24;
  JECS_CRG_PMA12_RST_CTRL |= BIT24;
  JECS_CRG_PMA13_RST_CTRL |= BIT24;
  JECS_CRG_PMA14_RST_CTRL |= BIT24;
  JECS_CRG_PMA15_RST_CTRL |= BIT24;
}

void ecpri_pcs_rst_ctrl()
{
  //cancell ecpri's rst
  //JECS_CRG_MANTICORE0_RST_CTRL      |= BIT24;
  //JECS_CRG_MANTICORE1_RST_CTRL      |= BIT24;
  //JECS_CRG_MANTICORE2_RST_CTRL      |= BIT24;
  JECS_CRG_MANTICORE3_RST_CTRL      |= BIT24;	// manticore tx
  //JECS_CRG_MANTICORE4_RST_CTRL      |= BIT24;
  //JECS_CRG_MANTICORE5_RST_CTRL      |= BIT24;	// ecpri_serdes_reset_tx
  //JECS_CRG_MANTICORE6_RST_CTRL      |= BIT24;
  //JECS_CRG_MANTICORE7_RST_CTRL      |= BIT24;
  //JECS_CRG_MANTICORE8_RST_CTRL      |= BIT24;
  //ECPRI_RST_CFG_REG                 |= BIT24;
}

void ecpri_mtimer_init(int32_t nScsId, int32_t nTddSlotNum)
{
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_ECPRI_ID];
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_ECPRI_ID];
	stMtimerSfnCal* pMtimerCalPara = &gMtimerSfnCalPara[MTIMER_ECPRI_ID];
	
	memset(pMtimerInt, 0, sizeof(stMtimerIntStat));
	memset(pMtimerSfn, 0, sizeof(stMtimerPhyPara));
	memset(pMtimerCalPara, 0, sizeof(stMtimerSfnCal));
	
	mtimer_para_init(MTIMER_ECPRI_ID, nScsId, nTddSlotNum);
	
    ecpri_timer_init(nScsId, nTddSlotNum);
}

void ecpri_timer_init(int32_t nScsId, int32_t nTddSlotNum)
{
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_ECPRI_ID];

	mtimer_clear_all_event(MTIMER_ECPRI_ID);
	set_ecpri_tmr_period();
	ecpri_1pps_src_init(ECPRI_PP1S_SRC_STC);
	set_ecpri_1pps_scratch();
	set_ecpri_timer_int();

	pMtimerInt->tmrIntInitFinished = 1;
}

void ecpri_timer_reconfig(phy_timer_config_ind_t *my_ecpritmr)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_ECPRI_ID];
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_ECPRI_ID];
	
	pMtimerPara->scsId = my_ecpritmr->scsId;
	pMtimerPara->tddPeriod = my_ecpritmr->t_period; // us
	pMtimerPara->tddSlotNum = my_ecpritmr->num_tti;
	pMtimerPara->slotPeriod = my_ecpritmr->t_us;
	pMtimerPara->slotMaxNum = my_ecpritmr->num_tti_per_sfn;
	pMtimerSfn->slotMaxNum = my_ecpritmr->num_tti_per_sfn;

	//gScsId = my_ecpritmr->scsId;
	//gMtimerId = MTIMER_ECPRI_ID;

	//gCellSfnPara[MTIMER_ECPRI_ID].scsId = my_ecpritmr->scsId;

	do_write_short((&(phyPara[my_ecpritmr->scsId].slotNumOfTdd)), my_ecpritmr->num_tti);
	do_write_short((&(phyPara[my_ecpritmr->scsId].mtimerId)), MTIMER_ECPRI_ID);
	__ucps2_synch(0);

	set_ecpri_tmr_period();					// set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status

	//set_ecpri_tdd_offset();					// 5ms int, tevent2 for all ape cores, dma

	set_ecpri_tx_slot_offset();
	set_ecpri_rx_slot_offset();

	if (LTE_SCS_ID == my_ecpritmr->scsId)
	{
		set_ecpri_lte_fapi_offset();
	}

}

void ecpri_timer_clear_cell(uint8_t scsId)
{
	clear_ecpri_tx_slot_offset();
	clear_ecpri_rx_slot_offset();
	if (LTE_SCS_ID == scsId)
	{
		clear_ecpri_lte_fapi_offset();
	}
}

void ecpri_1pps_src_init(uint8_t srcId)
{
	JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 13);
	JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 13);
}


void set_ecpri_1pps_scratch(void)
{
	set_mtimer_1pps_scratch(MTIMER_ECPRI_ID);
}


void set_ecpri_tmr_period(void)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_ECPRI_ID];
	
	// 设置计数器溢出值
	uint32_t tempL = pMtimerPara->tmrMsPeriod * pMtimerPara->slotPeriod / 1000;
	uint32_t tempM = 2; //gCpriTimerPara.tddSlotNum;
	uint32_t tempH = SFN_PERIOD / pMtimerPara->slotPeriod / 2; //gCpriTimerPara.tddSlotNum;

	set_mtimer_period(MTIMER_ECPRI_ID, tempL, tempM, tempH);
}

void set_ecpri_tdd_offset(void)
{
    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_ECPRI_ID];
	uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
	offset = pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif	
	uint32_t tmr2Point = pMtimerPara->tddPeriod - offset;  // us // 5ms
	set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_TDD_OFFSET, tmr2Point, MTIMER_MASK_48BIT);
	enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_TDD_OFFSET, MTMR_INT_TDD_OFFSET);
}

void set_ecpri_tx_slot_offset()
{
	uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
	EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
	
	uint32_t tmr3Point = SFN_PERIOD - offset; // us
	set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_TXSLOT_OFFSET, tmr3Point, MTIMER_MASK_32BIT);
	enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_TXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
	
	//uint32_t tempL = gCpriTimerPara.tmrMsPeriod * (tmr3Point % gCpriTimerPara.slotPeriod) / 1000;
	//uint32_t addr = (uint32_t)&(phyPara[gCpriTimerPara.scsId].txSetVal);
	//do_write(addr, tempL);

#if 0
	// ape tmrpoints
	for (int32_t i = 0; i < APE_NUM; i++)
	{
		int32_t tmrId = MTMR_APE0_TXSLOT + (i<<1);
		set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT);
		enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_SLOT_OFFSET+i));
	}
#endif
}

void clear_ecpri_tx_slot_offset()
{
	disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_TXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}

void set_ecpri_rx_slot_offset()
{
	int32_t offset = 0;
#ifdef DISTRIBUTED_BS
	EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
#endif

	uint32_t tmr4Point = 0; // offset; // us
	if (offset < 0)
	{
		tmr4Point = (~offset) + 1;
	}
	else
	{
		tmr4Point = SFN_PERIOD - offset; // us
	}
	set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_RXSLOT_OFFSET, tmr4Point, MTIMER_MASK_32BIT);
	enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
	
	//uint32_t tempL = gCpriTimerPara.tmrMsPeriod * (tmr3Point % gCpriTimerPara.slotPeriod) / 1000;
	//uint32_t addr = (uint32_t)&(phyPara[gCpriTimerPara.scsId].txSetVal);
	//do_write(addr, tempL);

#if 0
	// ape tmrpoints
	for (int32_t i = 0; i < APE_NUM; i++)
	{
		int32_t tmrId = MTMR_APE0_RXSLOT + (i<<1);
		set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT);
		enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_SLOT_OFFSET+i));
	}
#endif
}

void clear_ecpri_rx_slot_offset()
{
	disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}

void set_ecpri_lte_fapi_offset(void)
{
	uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
	EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
	uint32_t tmr30Point = SFN_PERIOD - offset - 500; // us

	set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_LTE_FAPI, tmr30Point, MTIMER_MASK_32BIT);
	enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_LTE_FAPI, MTMR_INT_SLOT_OFFSET);

}

void clear_ecpri_lte_fapi_offset(void)
{
	disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_LTE_FAPI, MTMR_INT_SLOT_OFFSET);
}

int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId)
{
	uint32_t txOffset = 0;
	uint32_t rxOffset = 0;
	uint32_t runCore = apeCoreId;
	volatile uint32_t h1Pos = 0;
	uint8_t apeId = 0;
	int32_t tmrId = 0;
#ifdef DISTRIBUTED_BS
	EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
	txOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
	rxOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
#endif

	uint32_t tmr3Point = SFN_PERIOD - txOffset; // us
	uint32_t tmr4Point = 0; // offset; // us
	if (rxOffset < 0)
	{
		tmr4Point = (~rxOffset) + 1;
	}
	else
	{
		tmr4Point = SFN_PERIOD - rxOffset; // us
	}
	
	// ape tmrpoints
	h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
	__ucps2_synch(0);
	while (32 > h1Pos)
	{
		apeId = 31 - h1Pos;
		if (8 <= apeId)
		{
			return -1;
		}
		// tx slot int
		tmrId = MTMR_APE0_TXSLOT + (apeId<<1);
		set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT);
		enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
		// rx slot int
		tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
		set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT);
		enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));

		runCore &= (~(1 << apeId));
		h1Pos = __builtin_clz(runCore);
		__ucps2_synch(0);
	}

	return 0;
}

int32_t clear_ecpri_ape_slot_offset(uint32_t apeCoreId)
{
	uint32_t runCore = apeCoreId;
	volatile uint32_t h1Pos = 0;
	uint8_t apeId = 0;
	int32_t tmrId = 0;

	// ape tmrpoints
	h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
	__ucps2_synch(0);
	while (32 > h1Pos)
	{
		apeId = 31 - h1Pos;
		if (8 <= apeId)
		{
			return -1;
		}
		// tx slot int
		tmrId = MTMR_APE0_TXSLOT + (apeId<<1);
		disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
		// rx slot int
		tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
		disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));

		runCore &= (~(1 << apeId));
		h1Pos = __builtin_clz(runCore);
		__ucps2_synch(0);
	}

	return 0;
}

void set_ecpri_timer_int(void)
{
	int32_t apeId = get_core_id();

	uint32_t intNum = APC_ECPRI_SUB_INTR2;
	// attach interrupt func
	int32_t ret = smart_irq_request(intNum, isr_ecpri_timer);
	if (0 != ret)
	{
		UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
		debug_write(DBG_DDR_ERR_IDX(apeId, 33), ret);
	}
}

void start_ecpri_timer(void)
{
	start_mtimer(MTIMER_ECPRI_ID);
}

void stop_ecpri_timer(void)
{
	stop_mtimer(MTIMER_ECPRI_ID);
}

void isr_ecpri_timer(void)
{
	uint32_t tmrIntcFlag = 0;
	uint32_t tEventFlag = 0;
	uint32_t cEventFlag = 0;
	uint32_t tFlagAddr = 0;
	uint32_t cFlagAddr = 0;
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_ECPRI_ID];
	stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_ECPRI_ID];
	uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_ECPRI_ID);

	pMtimerInt->tmrIntCnt++;
#ifdef PALLADIUM_TEST
	debug_write((DBG_DDR_IDX_DRV_BASE+2048), pMtimerInt->tmrIntCnt);	// 0xb7e08000
#endif	
	tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG);

	if ((tmrIntcFlag & (1 << MTMR_INT_10ms)))  /* tmr int */
	{
		cFlagAddr = tmrBaseAddr + MTMR_CINTF0_REG + 2*(MTMR_INT_10ms<<2);
		cEventFlag = do_read_volatile(cFlagAddr);
		__ucps2_synch(0);
		if (cEventFlag & BIT17) // 1pps int
		{
			do_write((tmrBaseAddr+MTMR_CEVENT_REG), BIT17);
			do_write(cFlagAddr, BIT17); // clear int flag

			if (0 == pMtimerInt->pp1sIntCnt)
			{
				start_ecpri_timer();
			}

#ifdef ENABLE_SFNCAL
			//mtimer_1pps_func(MTIMER_CPRI_ID);
#endif
			pMtimerInt->pp1sIntCnt++;
			debug_write((DBG_DDR_IDX_DRV_BASE+2048+1), pMtimerInt->pp1sIntCnt); // 0xb7e08004
		}
		do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_10ms)); 		// clear int
	}
	if ((tmrIntcFlag & (1 << MTMR_INT_TDD_OFFSET)))  /* tmr int */
	{
		tFlagAddr = tmrBaseAddr + MTMR_TINTF00_REG + 6*(MTMR_INT_TDD_OFFSET<<2);
		tEventFlag = do_read_volatile(tFlagAddr);
		if (tEventFlag & (1<<MTMR_TDD_OFFSET))		// tdd offset int
		{
			do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET));
			do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET));	// clear int flag
			pMtimerInt->tddOffsetIntCnt++;
			// start_csu_timing
#ifdef PALLADIUM_TEST
			debug_write((DBG_DDR_IDX_DRV_BASE+2048+2), pMtimerInt->tddOffsetIntCnt); // 0xb7e08008
#endif
			tEventFlag = do_read_volatile(tFlagAddr);
		}
		do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); 		// clear int
	}

	if ((tmrIntcFlag & (1 << MTMR_INT_SLOT_OFFSET)))  /* tmr int */
	{
		tFlagAddr = tmrBaseAddr + MTMR_TINTF00_REG + 6*(MTMR_INT_SLOT_OFFSET<<2);
		tEventFlag = do_read_volatile(tFlagAddr);
		if (tEventFlag & ((1<<MTMR_TXSLOT_OFFSET)|(1<<MTMR_RXSLOT_OFFSET)))
		{
			if (tEventFlag & (1<<MTMR_TXSLOT_OFFSET)) // tx slot offset
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TXSLOT_OFFSET));
				do_write(tFlagAddr, (1<<MTMR_TXSLOT_OFFSET));	// clear int flag
				pMtimerInt->txSlotIntCnt++;
				//uint32_t addr = 0;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+2048+4), pMtimerInt->txSlotIntCnt);	// 0xb7e08010
#endif
				pMtimerSfn->txSlotNum++;
				__ucps2_synch(0);
				if (pMtimerSfn->txSlotNum == pMtimerSfn->slotMaxNum)
				{
					pMtimerSfn->txSfnNum++;
					pMtimerSfn->txSfnNum &= 0x3FF;
					pMtimerSfn->txSlotNum = 0;
				}
				__ucps2_synch(0);
			}
			if (tEventFlag & (1<<MTMR_RXSLOT_OFFSET)) // rx slot offset
			{
				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_RXSLOT_OFFSET));
				do_write(tFlagAddr, (1<<MTMR_RXSLOT_OFFSET));	// clear int flag
				pMtimerInt->rxSlotIntCnt++;
				//uint32_t addr = 0;
#ifdef PALLADIUM_TEST
				debug_write((DBG_DDR_IDX_DRV_BASE+2048+5), pMtimerInt->rxSlotIntCnt);	// 0xb7e08014
#endif
				pMtimerSfn->rxSlotNum++;
				__ucps2_synch(0);
				if (pMtimerSfn->rxSlotNum == pMtimerSfn->slotMaxNum)
				{
					pMtimerSfn->rxSfnNum++;
					pMtimerSfn->rxSfnNum &= 0x3FF;
					pMtimerSfn->rxSlotNum = 0;
				}
				__ucps2_synch(0);
			}
			tEventFlag = do_read_volatile(tFlagAddr);
		}
		do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_SLOT_OFFSET));			// clear int
	}
}


