#include "rfm0_ecpri_timer.h"
#include "ucp_drv_common.h"
#include "ucp_ecpri.h"
#include "ucp_param.h"
#include "mtimer_com.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "smartos.h"

// int cnt
//UINT32 gRfm0TxSlotIntCnt = 0;
//UINT32 gRfm0RxSlotIntCnt = 0;
extern stSfnPara gCellSfnPara[2];
#if 0
void set_ecpri_timer_rfm0_int(void)
{
    int32_t apeId = get_core_id();

    // tx slot
    uint32_t intNum = APC_ECPRI_SUB_INTR2;
    int32_t ret = smart_irq_request(intNum, isr_ecpri_rfm0_slot_offset);
    if (0 != ret)
    {
        debug_write(DBG_DDR_ERR_IDX(apeId, 33), ret);
        UCP_PRINT_EMPTY("attach int num: 0x%x error. \r\n", intNum);
    }
}

// temp to be deleted
int32_t gRfm0IntCnt2 = 0;
void isr_ecpri_rfm0_slot_offset(void)
{
	uint32_t tmrIntcFlag = 0;
	uint32_t tEventFlag = 0;
	int32_t eventId = ECPRI_TMR_INT_RFM0_SLOT;

#ifdef PALLADIUM_TEST
	// temp 
	gRfm0IntCnt2++;
	debug_write((DBG_DDR_IDX_DRV_BASE+121), gRfm0IntCnt2);	// 0x1e4
#endif	

	tmrIntcFlag = do_read_volatile(&ECPRI_TMR_INTC_REG);
	if (tmrIntcFlag & (1 << eventId))  /* tmr int */
	{
		uint32_t flagAddr = (uint32_t)((uint32_t*)(&ECPRI_TMR_TINTF00_REG) + 6*ECPRI_TMR_INT_RFM0_SLOT);
		int32_t txSlotTmrId = ECPRI_TMR_RFM0_TXSLOT;
		int32_t rxSlotTmrId = ECPRI_TMR_RFM0_RXSLOT;
		tEventFlag = do_read_volatile(flagAddr);
		if (tEventFlag & ((1<<txSlotTmrId) | (1<<rxSlotTmrId)))
		{
			if (tEventFlag & (1<<txSlotTmrId)) // tx slot offset
			{
				uint32_t crVal = (1<<txSlotTmrId);
				do_write(((uint32_t*)(&ECPRI_TMR_TEVENT0_REG)), crVal);
				do_write(flagAddr, crVal);

				gCellSfnPara[MTIMER_ECPRI_ID].txSlotNum++;
				__ucps2_synch(0);
				if (gCellSfnPara[MTIMER_ECPRI_ID].txSlotNum == gCellSfnPara[MTIMER_ECPRI_ID].slotMaxNum)
				{
					gCellSfnPara[MTIMER_ECPRI_ID].txSfnNum++;
					gCellSfnPara[MTIMER_ECPRI_ID].txSfnNum &= 0x3FF;
					gCellSfnPara[MTIMER_ECPRI_ID].txSlotNum = 0;
				}

#ifdef PALLADIUM_TEST
				gCellSfnPara[MTIMER_ECPRI_ID].txSlotIntCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+98), gCellSfnPara[MTIMER_ECPRI_ID].txSlotIntCnt);	// 0x190
				debug_write(((DBG_DDR_IDX_DRV_BASE+448)+(gCellSfnPara[MTIMER_ECPRI_ID].txSlotIntCnt&0x3F)), GET_STC_CNT()); // 0x700
#endif
			}
			if (tEventFlag & (1<<rxSlotTmrId)) // rx slot offset
			{
				uint32_t crVal = ((1<<rxSlotTmrId));
				do_write(((uint32_t*)(&ECPRI_TMR_TEVENT0_REG)), crVal);
				do_write(flagAddr, crVal);

				gCellSfnPara[MTIMER_ECPRI_ID].rxSlotNum++;
				__ucps2_synch(0);
				if (gCellSfnPara[MTIMER_ECPRI_ID].rxSlotNum == gCellSfnPara[MTIMER_ECPRI_ID].slotMaxNum)
				{
					gCellSfnPara[MTIMER_ECPRI_ID].rxSfnNum++;
					gCellSfnPara[MTIMER_ECPRI_ID].rxSfnNum &= 0x3FF;
					gCellSfnPara[MTIMER_ECPRI_ID].rxSlotNum = 0;
				}

#ifdef PALLADIUM_TEST
				gCellSfnPara[MTIMER_ECPRI_ID].rxSlotIntCnt++;
				debug_write((DBG_DDR_IDX_DRV_BASE+99), gCellSfnPara[MTIMER_ECPRI_ID].rxSlotIntCnt);	// 0x194
				debug_write(((DBG_DDR_IDX_DRV_BASE+512)+(gCellSfnPara[MTIMER_ECPRI_ID].rxSlotIntCnt&0x3F)), GET_STC_CNT());	// 0x800
#endif
			}
			tEventFlag = do_read_volatile(flagAddr);
		}
	}
	do_write((&ECPRI_TMR_INTC_REG), (1 << eventId));			// clear int
}
#endif

