// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : cpri_test_case44.c
// Author        : xinxin.li
// Created On    : 2023-03-22s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_lte_fdd.h"
#include "jesd_test.h"
#include "jesd_test_case90.h"

extern uint32_t antDataLte[122880]; 

extern uint32_t 		gJesdTestMode;
extern uint32_t			gJesdIOMode;
extern uint32_t			gJesdTFMode;

void jesd_data_init()
{
	gJesdTestMode = JESD_TEST_MODE;
	debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
	debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
	debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
		
	jesd_tx_data_init();//init tx data
}

void jesd_test_csu_init()
{
	jesd_csu_init_lte_fdd();

	//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
	//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
}

void jesd_tx_data_init()
{
	uint8_t antNum = 2;
	uint8_t idAnt = 0;
	uint8_t idSlot = 0;
	uint32_t  srcAddr = 0;
	uint32_t  dstAddr = 0;
	uint32_t  dataLen = 0;
	uint16_t  samByteCnt = 4;
	uint32_t  slotSamCnt = JESD_LTEFDD_SUBFRAME_SAM_CNT;

	uint32_t cpyCnt = 0;
	// valid data
	// IQ data	
	samByteCnt = 4;
	for (idAnt = 0; idAnt < antNum; idAnt++)
	{
		for (idSlot = 0; idSlot <= 1; idSlot++)
		{
			if (0 == idSlot)	// even slot
			{
				dataLen = samByteCnt * slotSamCnt;
				srcAddr = (uint32_t)(&antDataLte[0]) + idAnt*slotSamCnt;
				dstAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
			}
			else if (1 == idSlot)	// odd slot
			{
				dataLen = samByteCnt * slotSamCnt;
				srcAddr = (uint32_t)(&antDataLte[0]) + idAnt*slotSamCnt;
				dstAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
			}
				//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
				//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
				//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
//			memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
			ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
			cpyCnt++;
		}
	}
	memset((void*)JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
	memset((void*)JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
}

void jesd_csu_config()
{
}

void jesd_test_case()
{
	//jesd_csu_start_nr_7ds2u();
}



