// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : cpri_test_case34.c
// Author        : xinxin.li
// Created On    : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#include "typedef.h"
#include "ucp_utility.h"
#include "cpri_csu_api.h"
#include "cpri_test_case71.h"
#include "cpri_timer.h"
#include "ape_csu.h"
#include "cpri_test.h"
#include "ucp_printf.h"
#include "HeaderRam.h"
#include "cpri_driver.h"
#include "nr_mem_def.h"
#include "phy_timer_csu_config.h"
#include "mem_sections.h"
#include "phy_para.h"
#include "hw_cpri.h"

#include <malloc.h>

extern uint32_t compressData0[1920];
extern uint32_t compressData1[1920];
extern uint32_t antData0[122880];
extern uint32_t antData1[122880];
extern uint32_t antData2[122880];
extern uint32_t antData3[122880];

//DDR0 uint32_t srcImData[5*1024] = {0};	// 16KB
extern uint32_t 		gCpriTestMode;
extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];

extern uint32_t gCpriTestMode;
//extern uint32_t           CPRI_OPTION;
extern uint32_t			gCpriCsuDummyFlag;

#define HeaderTestCnt   10

int32_t fh_data_init(void)
{
	gCpriTestMode = CPRI_TEST_MODE;
	gCpriCsuDummyFlag  = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300

//	Get_Cpri_OptionId();//get cpri option value
//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
		
	Axc_data_init();//init axc data
	UCP_PRINT_EMPTY("Axc data init.\r\n");
	HeaderTxRam_data_init();
	//HeaderTxRam_init();
	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
	return 0;
}

int32_t fh_drv_init(void)
{
	cpri_init(CPRI_OPTION_10, OTIC_MAP_FIGURE16);

	return 0;
}


int32_t fh_csu_test_init(void)
{
	 Phy_Timer_Csu_Config_Nr();
	return 0;
}

void fh_test_case()
{
	UCP_API_CPRI_CSU_START();
}

void HeaderTxRam_data_init()
{
	for(int i=0;i<16*HeaderTestCnt;i++)
	{
		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
	}
#if 0
	for(int i=0;i<16*HeaderTestCnt;i++)
	{
		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
	}
#endif
}

void Axc_data_init()
{
	uint8_t idID = 0;
	uint8_t idSlot = 0;			// even slot, odd slot
	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
//	uint8_t idSymbol = 0;
//	uint16_t idBF = 0;
//	uint16_t idWord = 0;

	uint32_t* pSrcAddr = NULL;
//	uint32_t  srcAddr = 0;
	uint32_t  dstAddr = 0;
	uint32_t  dataLen = 0;
	uint16_t  bfByteCnt = 0;
	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//前7symbol
	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//后7symbol
//	uint32_t  symbolBfCnt = 0;
	uint32_t  idSlotBf = 0;
//	uint32_t  val = 0;
	uint32_t cpyCnt = 0;
	
	cpyCnt++;
	// valid data
	/********** compress factor*********/
	for(idID =0 ; idID < 2; idID++)
	{
     	for (idSlot = 0; idSlot <= 1; idSlot++)//NR cell
		{
			bfByteCnt = 2;
			if (0 == idSlot)	// even slot
			{
				if(0 == idID)
				{
					pSrcAddr =compressData0;
					dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;				
				}
				else
				{
					dstAddr = SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR;
					pSrcAddr =compressData1;
				}			
			}
			else				// odd slot
			{
				if(0 == idID)
				{
					dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
					pSrcAddr =compressData0;// + (1920>>1);
				}
				else
				{
					dstAddr = SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR;
					pSrcAddr =compressData1;// + (1920>>1);
				}
				
			}
			dataLen = (bfByteCnt*slotBfCnt); 
		    memcpy_ucp((void*)dstAddr,(void*)pSrcAddr, dataLen);
		}
	}
	
	// IQ data	NR 
	for (idID = 2; idID < 6; idID++)
	{
		bfByteCnt = 64*2;
		for (idSlot = 0; idSlot <= 1; idSlot++)
		{
			idSlotBf = 0;
			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
			{
				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
				{
					switch(idID)
					{
						case 2:
							pSrcAddr = antData0;
							dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
							break;
						case 3:
							pSrcAddr = antData1;
							dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
							break;	
						case 4:
							pSrcAddr = antData2;
							dstAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
							break;
						case 5:
							pSrcAddr = antData3;
							dstAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
							break;
					}
					dataLen = f7BfCnt*bfByteCnt;
				}
				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
				{
					switch(idID)
					{
						case 2:
							pSrcAddr = antData0 + 30752;
							dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
							break;
						case 3:
							pSrcAddr = antData1  + 30752;
							dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
							break;	
						case 4:
							pSrcAddr = antData2  + 30752;
							dstAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
							break;
						case 5:
							pSrcAddr = antData3  + 30752;
							dstAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
							break;
					}
					dataLen = b7BfCnt*bfByteCnt;
				}
				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
				{
					switch(idID)
					{
						case 2:
							pSrcAddr = antData0;// + 61440;
							dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
							break;
						case 3:
							pSrcAddr = antData1;//  + 61440;
							dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
							break;	
						case 4:
							pSrcAddr = antData2;//  + 61440;
							dstAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
							break;
						case 5:
							pSrcAddr = antData3;//  + 61440;
							dstAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
							break;
					}
					dataLen = f7BfCnt*bfByteCnt;
				}
				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
				{
					switch(idID)
					{
						case 2:
							pSrcAddr = antData0 + 30752;// + 61440 + 30752 ;
							dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
							break;
						case 3:
							pSrcAddr = antData1 + 30752;//+ 61440 + 30752;
							dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
							break;	
						case 4:
							pSrcAddr = antData2 + 30752;//+ 61440 + 30752;
							dstAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
							break;
						case 5:
							pSrcAddr = antData3 + 30752;//+ 61440 + 30752;
							dstAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
							break;
					}
					dataLen = b7BfCnt*bfByteCnt;
				}
			    memcpy_ucp((void*)dstAddr,(void*)pSrcAddr, dataLen);
			}
		}
	}

}

uint32_t Txdata[48] ={0};
uint32_t Rxdata0[48] ={0};

uint32_t Header_error0=0;
uint32_t Header_error1 = 0;
//uint32_t HeaderRxtimes = 0;
extern uint32_t HeaderTxtimes;
extern volatile uint32_t gVendorFlag;

void Cpri_Header_Rx(void)
{
	uint32_t j= 0;
	if(OTIC_MAP_FIGURE12 == gVendorFlag)
	{
//		HeaderRxtimes++;
#if 1
		while(1)
		{
			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
			{
				break;
			}
		}
#endif
		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));

		for(j=0;j<4;j++)
		{
			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);

		}
		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
		for(j=0;j<48;j++)
		{
			if (Rxdata0[j] != Txdata[j])//vendor
			{
				Header_error0++;
				Header_error1++;
			}
		}

		
		if(Header_error1!=0)
		{
			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
			Header_error1 =0;
		}
		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
	}
}




uint32_t gCompWordCnt = 0;
uint32_t gErrSlotIdCnt = 0;
uint32_t gCompSlotIdCnt = 0;
uint32_t gBfStartErr = 0;
uint32_t cnt = 0;
void fh_data_check(uint32_t times)
{
	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
	if (4 <= pMtimerInt->csuEnCnt)
	{
		gCompWordCnt = 0;
		for (int32_t i = 0; i < (CPRI_CASE70_SLOT_NUM>>1); i++)
	//	for (int32_t i = 7; i < (CPRI_CASE70_SLOT_NUM>>1); i++)
		{
			cpri_check_slot_data(i);
		}
#if 0
		if(24000 <= pMtimerInt->csuEnCnt)
		{ 
			
			//if(0 == cnt)
			{
				if(0 == gErrSlotIdCnt)
				{ 
					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
					UCP_PRINT_WARN("cpri test pass!\r\n");
				}
				else
				{
					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
				}
				cnt++;				
			}
		}
#endif
	}
	Cpri_Header_Rx();
}


void cpri_check_slot_data(uint32_t slotNum)
{
	// move data from sm to ddr
	uint32_t slotId = 0;
	uint32_t srcAddr = 0;
	uint32_t srcAddr1 = 0;
	uint32_t realSrcAddr = 0;
	uint32_t dataLen = 0;
	uint8_t bitOffset = 0;
	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
	uint8_t	bfWordCnt = 0;

	uint8_t slotVal = 0;
	uint8_t idVal = 0;
	int32_t bfStart = 0;

	uint32_t compVal = 0;
	uint32_t recvVal = 0;
	uint32_t recvAddr = 0;
	
	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
	
//	__ucps2_synch(0);
	for (uint32_t i = 0; i < 6; i++)//no agc
	{
		gCompSlotIdCnt++;
		idVal = i;
		bfStart = 0;
//		__ucps2_synch(0);
		if ((slotId >=0) && (slotId <= 6))
		{
			slotVal = slotId & 0x1;
#if 1
			if (2 > i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN; //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
			}
			else
			{
				bitOffset = 7;	// one BF, 64*2B
				bfWordCnt = (128>>2);
				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
			}
			dataLen = slotBfCnt << bitOffset;
#endif
		}
		else if (7 == slotId)		// compare S slot, odd slot
		{
			bfStart = (LONGCP_BF_CNT+SHORTCP_BF_CNT*9);
			slotVal = 1;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset);//Rx symbol 0~5地址
				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR;//Rx symbol 6~13地址
			}
			else if(1 == i)
			{
				bitOffset = 1;	// one BF, 2B
				bfWordCnt = 1;
				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN;
				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR;
			}
			else if((2 == i)||(3 == i))
			{
				bitOffset = 7;	// one BF, 64*2B
				bfWordCnt = (128>>2);
				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR + 0x448+(i-2)*((SHORTCP_BF_CNT*4)<<bitOffset);//0x448是cell0的压缩因子的长度
			}
			else //if((4 == i)||(5 == i))
			{
				bitOffset = 7;	// one BF, 64*2B
				bfWordCnt = (128>>2);
				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR +  0x448+(i-4)*((SHORTCP_BF_CNT*4)<<bitOffset);
			}
			
			dataLen = slotBfCnt << bitOffset;
		}
		else if (8 == slotId)		// current slot is even slot, compare even slot, slot8
		{
			slotVal = 0;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 4B
				bfWordCnt = 1;
				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
			}
			else if(1 == i)
			{
				bitOffset = 1;	// one BF, 4B
				bfWordCnt = 1;
				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
			}
			else if((2 == i)||(3 == i))
			{
				bitOffset = 7;	// one BF, 128B
				bfWordCnt = (128>>2);
				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR + 0xF00 +((i-2)*(slotBfCnt<<bitOffset));
			}
			else// if((4 == i)||(5 == i))
			{
			    bitOffset = 7;	// one BF, 128B
				bfWordCnt = (128>>2);
				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR + 0xF00 + ((i-4)*(slotBfCnt<<bitOffset));
			}
			
			dataLen = slotBfCnt << bitOffset;
		}
		else if (9 == slotId)	// compare odd slot, slot9
		{
			slotVal = 1;
			if (0 == i)
			{
				bitOffset = 1;	// one BF, 4B
				bfWordCnt = 1;
				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_ODD_COMPRESS_ADDR;
			}
			else if(1 == i)
			{
				bitOffset = 1;	// one BF, 4B
				bfWordCnt = 1;
				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR;
			}
			else if((2 == i)||(3 == i))
			{
				bitOffset = 7;	// one BF, 128B
				bfWordCnt = (128>>2);
				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR +  0xF00 +((i-2)*(slotBfCnt<<bitOffset));
			}
			else //if((4 == i)||(5 == i))
			{
				bitOffset = 7;	// one BF, 128B
				bfWordCnt = (128>>2);
				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR +  0xF00+ ((i-4)*(slotBfCnt<<bitOffset));
			}
			
			dataLen = slotBfCnt << bitOffset;
		}

		if (2 > i)	// NR cell compress factor
		{
			for (int32_t idBf = 0; idBf <  (slotBfCnt>>1); idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
					compVal = (slotVal<<28) | (idVal<<24) | ((idBf<<1)<<8) | (i);
					
					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;
					__ucps2_synch(0);
								
						if ((7 == slotId) && (686 <= idBf))
						{
							recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
							if (0 > (idBf-(bfStart>>1)))
							{
								gBfStartErr++;
								debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
							}
							realSrcAddr = srcAddr1;
						}
						else 
						{
							recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
							realSrcAddr = srcAddr;
						}
					
						recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
						__ucps2_synch(0);
						if (recvVal != compVal)
						{
							if (gErrSlotIdCnt < 0x100)
							{
								debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
								debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
								debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
								debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
								debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
								debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
								debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
							}
							gErrSlotIdCnt++;
						}				
//					__ucps2_synch(0);
				}
			}
		}
		else //if((1 < i)	&& (6 > i))// NR CELL0
		{
			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
			{
				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
				{
					compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
					
//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
					gCompWordCnt++;
					__ucps2_synch(0);
					
					if ((7 == slotId) && (1372 <= idBf))
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
						realSrcAddr = srcAddr1;
						if (0 > (idBf-bfStart))
						{
							gBfStartErr++;
							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
						}
					}
					else 
					{
						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
						realSrcAddr = srcAddr;
					}
					
//					__ucps2_synch(0);
					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
					__ucps2_synch(0);
					if (recvVal != compVal)
					{
						if (gErrSlotIdCnt < 0x100)
						{
							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
						}
						gErrSlotIdCnt++;
					}
				}
			}
		}
		
		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
	}
}

