/**********************************************************************************************************************
*  Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
*  File Name: ecpri_driver.s.c
*  Create Date: 23/08/18
*  Description: eCPRI Driver Module Source File
*  Change History: 
*      <author>      <time>      <version>   <desc>
*    1. ShangH      23/08/18        1.0       Build this module
**********************************************************************************************************************/


/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_driver.h"
#include "hw_cpri.h"
#include "ecpri_timer.h"

/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */


/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
*  Function: vnet_send_packet
*  Description: vnet send packet
*  Input: 
*    <name>        <type>               <desc>
*     skb           sk_buff *            socket buffer
*     dev           net_device *         network device
*  Output: none
*  Return: operation result - success or failure.
*  Others: none
**********************************************************************************************************************/

void ecpri_init(uint8_t nOption)
{
#ifdef PALLADIUM_TEST
	int32_t flag = 1;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif
	phy_para_init(PROTOCOL_ECPRI, nOption);

	ecpri_init_ex(nOption); // (10);
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif
	
	cpri_ecprimode_init();
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif

	ecpri_mtimer_init(LTE_SCS_ID, 10);
#ifdef PALLADIUM_TEST
	flag++;
	debug_write((DBG_DDR_IDX_DRV_BASE+56), flag);	// 0xE0
#endif
}

void ecpri_cprimode_init()
{
	// 扩皮模式下，ecpri timer使用cpri_div33_tx_clk，与cpri core clk同源
	ecpri_timer_cprimode_clk_init();

	ecpri_mtimer_init(LTE_SCS_ID, 10);
}

void ecpri_clk_init(uint32_t ecpri_speed_sel)
{
    if (ecpri_speed_sel == 10) //10G
    {
        do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT11+BIT5+BIT31+BIT16+BIT17+BIT18+BIT19));
        do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2  apb_aclk_i
        //switch_core_clk_i,
        //switch_sch_clk_i,
        do_write(&JECS_CRG_CLK_CTRL7, 0x520000);//jecs_pma_tx0_ropll_div33_clk
        //ecpri_switch_mae_core_clk
        do_write(&JECS_CRG_CLK_CTRL8, 0x520000);//jecs_pma_tx0_ropll_div33_clk
        //ecpri_pcs_xgmii_tx_clk
        do_write(&JECS_CRG_CLK_CTRL9, 0x521000);//jecs_pma_tx0_ropll_div33_clk
        //ecpri_pcs_xgmii_rx_clk
        do_write(&JECS_CRG_CLK_CTRL0, 0x521000);//jecs_pma_rx0_div33_clk
        do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
        do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
    }
    else if (ecpri_speed_sel == 25) //25G
    {
        do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT11+BIT5+BIT16+BIT17+BIT18+BIT19));
        do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2  apb_aclk_i
        //switch_core_clk_i,
        //switch_sch_clk_i,
        do_write(&JECS_CRG_CLK_CTRL7, 0x521000);//jecs_pma_tx0_ropll_div33_clk
        //ecpri_switch_mae_core_clk
        do_write(&JECS_CRG_CLK_CTRL8, 0x521000);//jecs_pma_tx0_ropll_div33_clk
        //ecpri_pcs_xgmii_tx_clk
        do_write(&JECS_CRG_CLK_CTRL9, 0x521000);//jecs_pma_tx0_ropll_div33_clk
        //ecpri_pcs_xgmii_rx_clk
        do_write(&JECS_CRG_CLK_CTRL0, 0x521000);//jecs_pma_rx0_div33_clk
        do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
        do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
    }
}

void ecpri_init_ex(uint32_t ecpri_speed_sel)
{
    ecpri_clk_init(10);

    ecpri_pcs_rst_ctrl_ex();

    init_ecpri_pma_rst_ex();

    init_jecspma(10);

    init_jecspma_rxtx();

    ecpri_roec_init();

    ecpri_pcs_init(10);

    ecpri_mac_init(10);

    ecpri_switch_init(10);

    ecpri_pma_rx_adapt();

    /* waiting for eCPRI PCS to link up */
    while (!ecpri_pcs_link_status_get());

    do_write(SERDES_INIT_FLAG_ADDR, 1);
}


