/**********************************************************************************************************************
*  Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
*  File Name: ecpri_pma.s.c
*  Create Date: 23/08/18
*  Description: eCPRI PMA Module Source File
*  Change History: 
*      <author>      <time>      <version>   <desc>
*    1. ShangH      23/08/18        1.0       Build this module
**********************************************************************************************************************/


/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_pma.h"


/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */


/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
*  Function: vnet_send_packet
*  Description: vnet send packet
*  Input: 
*    <name>        <type>               <desc>
*     skb           sk_buff *            socket buffer
*     dev           net_device *         network device
*  Output: none
*  Return: operation result - success or failure.
*  Others: none
**********************************************************************************************************************/
void ecpri_pcs_rst_ctrl_ex(void)
{
  //cancell ecpri's rst
  do_write(&JECS_CRG_MANTICORE0_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE0_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE1_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE1_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE2_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE2_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE3_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE3_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE4_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE4_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE5_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE5_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE6_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE6_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE7_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE7_RST_CTRL) | BIT24);
  do_write(&JECS_CRG_MANTICORE8_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE8_RST_CTRL) | BIT24);
  do_write(&ECPRI_RST_CFG_REG, do_read_volatile(&ECPRI_RST_CFG_REG) | BIT24);
}

/**********************************************************************************************************************
*  Function: vnet_recv_packet
*  Description: vnet receive packet
*  Input: 
*    <name>        <type>               <desc>
*     dev           net_device *         network device
*     data          uint8_t *            data received
*     len           uint32_t             data length
*  Output: none
*  Return: operation result - success or failure.
*  Others: none
**********************************************************************************************************************/
void init_ecpri_pma_rst_ex(void)
{
    //cancell jecs pma rst
    do_write(&JECS_CRG_PMA16_RST_CTRL, do_read_volatile(&JECS_CRG_PMA16_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA8_RST_CTRL, do_read_volatile(&JECS_CRG_PMA8_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA9_RST_CTRL, do_read_volatile(&JECS_CRG_PMA9_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA10_RST_CTRL, do_read_volatile(&JECS_CRG_PMA10_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA11_RST_CTRL, do_read_volatile(&JECS_CRG_PMA11_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA12_RST_CTRL, do_read_volatile(&JECS_CRG_PMA12_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA13_RST_CTRL, do_read_volatile(&JECS_CRG_PMA13_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA14_RST_CTRL, do_read_volatile(&JECS_CRG_PMA14_RST_CTRL) | BIT24);
    do_write(&JECS_CRG_PMA15_RST_CTRL, do_read_volatile(&JECS_CRG_PMA15_RST_CTRL) | BIT24);
}

/**********************************************************************************************************************
*  Function: vnet_set_mac_address
*  Description: vnet set mac address
*  Input: 
*    <name>        <type>               <desc>
*     dev           net_device *         network device
*     addr          void *               network address
*  Output: none
*  Return: operation result - success or failure.
*  Others: none
**********************************************************************************************************************/
void init_pma_commonconfig_ex(uint32_t ecpri_speed_sel)
{
    uint32_t ate_ref_range                ;
    uint32_t ate_ref_clk_div2_en          ;
    uint32_t ate_ref_raw_clk_div2_en      ;
    uint32_t ate_ref_clk_mplla_div        ;
    uint32_t ate_lane_ref_sel             ;
    uint32_t ate_mplla_fb_clk_div4_en     ;
    uint32_t ate_mplla_multiplier         ;
    uint32_t ate_mplla_tx_clk_div         ;
    uint32_t ate_mplla_word_clk_div       ;
    uint32_t ate_mplla_ssc_en             ;
    uint32_t ate_mplla_ssc_up_spread      ;
    uint32_t ate_mplla_ssc_peak           ;
    uint32_t ate_mplla_ssc_step_size      ;
    uint32_t ate_mplla_frac_en            ;
    uint32_t ate_mplla_frac_quot          ;
    uint32_t ate_mplla_frac_den           ;
    uint32_t ate_mplla_frac_rem           ;
    uint32_t ate_refa_lane_clk_en         ;
    uint32_t ate_bs_rx_level              ;
    uint32_t ate_bs_tx_lowswing           ;
    uint32_t ate_bs_rx_bigswing           ;
    uint32_t ate_mplla_init_cal_disable   ;
    uint32_t ate_refa_dig_clk_sel         ;
    uint32_t ate_ref_dco_bypass           ;
    uint32_t ate_refa_dco_ld_val          ;
    uint32_t ate_ref_dco_target           ;
    uint32_t ate_ref_dco_dig_range        ;
    uint32_t ate_mplla_bw_threshold       ;
    uint32_t ate_mplla_bw_low             ;
    uint32_t ate_mplla_bw_high            ;
    uint32_t ate_mplla_ctl_buf_bypass     ;
    uint32_t ate_mplla_short_lock_en      ;
    uint32_t ate_rx_term_offset           ;
    uint32_t ate_txdn_term_offset         ;
    uint32_t ate_txup_term_offset         ;
    uint32_t ate_sup_misc                 ;
    uint32_t ate_rx_vref_ctrl             ;
    uint32_t ate_rx_ref_ld_val            ;
    uint32_t ate_rx_vco_ld_val            ;
    uint32_t ate_rx_cdr_ppm_max           ;
    //lane
    uint32_t ate_tx_misc                  ;
    uint32_t ate_tx_dcc_ctrl_diff_range   ;
    uint32_t ate_tx_dcc_ctrl_cm_range     ;
    uint32_t ate_tx_width                 ;
    uint32_t ate_tx_ropll_cp_ctl_intg     ;
    uint32_t ate_tx_ropll_cp_ctl_prop     ;
    uint32_t ate_tx_ropll_rc_filter       ;
    uint32_t ate_tx_ropll_v2i_mode        ;
    uint32_t ate_tx_ropll_vco_low_freq    ;
    uint32_t ate_tx_ropll_postdiv         ;
    uint32_t ate_tx_rate                  ;
    uint32_t ate_tx_ropll_div16p5_clk_en  ;
    uint32_t ate_tx_ropll_125mhz_clk_en   ;
    uint32_t ate_tx_term_ctrl             ;
    uint32_t ate_tx_dly_cal_en            ;
    uint32_t ate_tx_pll_word_clk_freq     ;
    uint32_t ate_tx_dig_ropll_div_clk_sel ;
    uint32_t ate_tx_dual_cntx_en          ;
    uint32_t ate_tx_ropll_bypass          ;
    uint32_t ate_tx_ropll_refdiv          ;
    uint32_t ate_tx_ropll_refsel          ;
    uint32_t ate_tx_ropll_fbdiv           ;
    uint32_t ate_tx_ropll_div_clk_en      ;
    uint32_t ate_tx_ropll_out_div         ;
    uint32_t ate_tx_ropll_word_clk_div_sel;
    uint32_t txX_ropll_word_clk_div_lte   ;
    uint32_t ate_tx_fastedge_en           ;
    uint32_t ate_tx_eq_pre                ;
    uint32_t ate_tx_eq_post               ;
    uint32_t ate_tx_eq_main               ;
    uint32_t ate_tx_align_wide_xfer_en    ;
    uint32_t ate_rx_eq_att_lvl            ;
    uint32_t ate_rx_eq_ctle_boost         ;
    uint32_t ate_rx_eq_ctle_pole          ;
    uint32_t ate_rx_eq_afe_rate           ;
    uint32_t ate_rx_eq_vga_gain           ;
    uint32_t ate_rx_eq_afe_config         ;
    uint32_t ate_rx_eq_dfe_tap1           ;
    uint32_t ate_rx_eq_dfe_tap2           ;
    uint32_t ate_rx_delta_iq              ;
    uint32_t ate_rx_cdr_vco_config        ;
    uint32_t ate_rx_dcc_ctrl_diff_range   ;
    uint32_t ate_rx_dcc_ctrl_cm_range     ;
    uint32_t ate_rx_sigdet_lf_threshold   ;
    uint32_t ate_rx_sigdet_hf_threshold   ;
    uint32_t ate_rx_misc                  ;
    uint32_t ate_rx_term_ctrl             ;
    uint32_t ate_rx_width                 ;
    uint32_t ate_rx_dig_div_clk_sel       ;
    uint32_t ate_rx_div_clk_en            ;
    uint32_t ate_rx_div_clk_sel           ;
    uint32_t ate_rx_rate                  ;
    uint32_t ate_rx_dfe_bypass            ;
    uint32_t ate_rx_offcan_cont           ;
    uint32_t ate_rx_adapt_cont            ;
    uint32_t ate_rx_eq_dfe_float_en       ;
    uint32_t ate_rx_div16p5_clk_en        ;
    uint32_t ate_rx_125mhz_clk_en         ;
    uint32_t ate_rx_cdr_ssc_en            ;
    uint32_t ate_rx_sigdet_hf_en          ;
    uint32_t ate_rx_sigdet_lfps_filter_en ;
    uint32_t ate_rx_term_acdc             ;
    uint32_t ate_rx_adapt_sel             ;
    uint32_t ate_rx_adapt_mode            ;
    uint32_t ate_rx_adapt_en              ;

    uint32_t ate_ref_clk_mpllb_div        ;
    uint32_t ate_mpllb_fb_clk_div4_en     ;
    uint32_t ate_mpllb_multiplier         ;
    uint32_t ate_mpllb_tx_clk_div         ;
    uint32_t ate_mpllb_word_clk_div       ;
    uint32_t ate_mpllb_ssc_en             ;
    uint32_t ate_mpllb_ssc_up_spread      ;
    uint32_t ate_mpllb_ssc_peak           ;
    uint32_t ate_mpllb_ssc_step_size      ;
    uint32_t ate_mpllb_frac_en            ;
    uint32_t ate_mpllb_frac_quot          ;
    uint32_t ate_mpllb_frac_den           ;
    uint32_t ate_mpllb_frac_rem           ;
    uint32_t ate_refb_lane_clk_en         ;
    uint32_t ate_mpllb_init_cal_disable   ;
    uint32_t ate_refb_dig_clk_sel         ;
    uint32_t ate_refb_dco_ld_val          ;
    uint32_t ate_mpllb_bw_high            ;
    uint32_t ate_mpllb_bw_low             ;
    uint32_t ate_mpllb_bw_threshold       ;
    uint32_t ate_mpllb_ctl_buf_bypass     ;
    uint32_t ate_mpllb_short_lock_en      ;

    //const
    uint32_t ate_mplla_force_en             = 0;//
    uint32_t ate_mpllb_force_en             = 0;//
    uint32_t ate_pcs_pwr_stable             = 1;//
    uint32_t ate_pg_mode_en                 = 0;//
    uint32_t ate_pg_reset                   = 0;//
    uint32_t ate_pma_pwr_stable             = 1;//
    uint32_t ate_refa_clk_en                = 1;//
    uint32_t ate_refb_clk_en                = 0;//
    uint32_t ate_ref_repeat_clk_en          = 1;//
    uint32_t ate_rx_pstate                  = 2;//
    uint32_t ate_rx_invert                  = 0;//
    uint32_t ate_rx_lpd                     = 0;//
    uint32_t ate_rx_term_en                 = 1;//
    uint32_t ate_tx_pstate                  = 2;//
    uint32_t ate_tx_clk_rdy                 = 1;//
    uint32_t ate_tx_invert                  = 0;//
    uint32_t ate_tx_lpd                     = 0;//
    uint32_t ate_tx_mpll_en                 = 1;//

    if(ecpri_speed_sel == 10)
    {
        ate_ref_range                   = 4    ;
        ate_ref_clk_div2_en             = 0    ;
        ate_ref_raw_clk_div2_en         = 1    ;
        ate_ref_clk_mplla_div           = 1    ;
        ate_lane_ref_sel                = 0    ;
        ate_mplla_fb_clk_div4_en        = 0    ;
        ate_mplla_multiplier            = 120  ;
        ate_mplla_tx_clk_div            = 1    ;
        ate_mplla_word_clk_div          = 2    ;
        ate_mplla_ssc_en                = 0    ;
        ate_mplla_ssc_up_spread         = 0    ;
        ate_mplla_ssc_peak              = 0    ;
        ate_mplla_ssc_step_size         = 0    ;
        ate_mplla_frac_en               = 0    ;
        ate_mplla_frac_quot             = 0    ;
        ate_mplla_frac_den              = 0    ;
        ate_mplla_frac_rem              = 0    ;
        ate_refa_lane_clk_en            = 0    ;
        ate_bs_rx_level                 = 7    ;
        ate_bs_tx_lowswing              = 0    ;
        ate_bs_rx_bigswing              = 1    ;
        ate_mplla_init_cal_disable      = 0    ;
        ate_refa_dig_clk_sel            = 0    ;
        ate_ref_dco_bypass              = 0    ;
        ate_refa_dco_ld_val             = 78   ;
        ate_ref_dco_target              = 150  ;
        ate_ref_dco_dig_range           = 6    ;
        ate_mplla_bw_threshold          = 75   ;
        ate_mplla_bw_low                = 1583 ;
        ate_mplla_bw_high               = 1583 ;
        ate_mplla_ctl_buf_bypass        = 0    ;
        ate_mplla_short_lock_en         = 0    ;
        ate_rx_term_offset              = 0    ;
        ate_txdn_term_offset            = 0    ;
        ate_txup_term_offset            = 0    ;
        ate_sup_misc                    = 3    ;
        ate_rx_vref_ctrl                = 5    ;
        ate_rx_ref_ld_val               = 21   ;
        ate_rx_vco_ld_val               = 1386 ;
        ate_rx_cdr_ppm_max              = 18   ;
        //lane
        ate_tx_misc                     = 0   ;
        ate_tx_dcc_ctrl_diff_range      = 8   ;
        ate_tx_dcc_ctrl_cm_range        = 8   ;
        ate_tx_width                    = 4   ;
        ate_tx_ropll_cp_ctl_intg        = 79  ;
        ate_tx_ropll_cp_ctl_prop        = 79  ;
        ate_tx_ropll_rc_filter          = 4   ;
        ate_tx_ropll_v2i_mode           = 3   ;
        ate_tx_ropll_vco_low_freq       = 2   ;
        ate_tx_ropll_postdiv            = 1   ;
        ate_tx_rate                     = 1   ;
        ate_tx_ropll_div16p5_clk_en     = 1   ;
        ate_tx_ropll_125mhz_clk_en      = 0   ;
        ate_tx_term_ctrl                = 0   ;
        ate_tx_dly_cal_en               = 0   ;
        ate_tx_pll_word_clk_freq        = 6   ;
        ate_tx_dig_ropll_div_clk_sel    = 0   ;
        ate_tx_dual_cntx_en             = 0   ;
        ate_tx_ropll_bypass             = 0   ;
        ate_tx_ropll_refdiv             = 5   ;
        ate_tx_ropll_refsel             = 0   ;
        ate_tx_ropll_fbdiv              = 11  ;
        ate_tx_ropll_div_clk_en         = 0   ;
        ate_tx_ropll_out_div            = 4   ;
        ate_tx_ropll_word_clk_div_sel   = 2   ;
        txX_ropll_word_clk_div_lte      = 2   ;
        ate_tx_fastedge_en              = 0   ;
        ate_tx_eq_pre                   = 0   ;
        ate_tx_eq_post                  = 0   ;
        ate_tx_eq_main                  = 24  ;
        ate_tx_align_wide_xfer_en       = 0   ;
        ate_rx_eq_att_lvl               = 0   ;
        ate_rx_eq_ctle_boost            = 16  ;
        ate_rx_eq_ctle_pole             = 1   ;
        ate_rx_eq_afe_rate              = 6   ;
        ate_rx_eq_vga_gain              = 16  ;
        ate_rx_eq_afe_config            = 1300;
        ate_rx_eq_dfe_tap1              = 12  ;
        ate_rx_eq_dfe_tap2              = 128 ;
        ate_rx_delta_iq                 = 6   ;
        ate_rx_cdr_vco_config           = 1027;
        ate_rx_dcc_ctrl_diff_range      = 11  ;
        ate_rx_dcc_ctrl_cm_range        = 11  ;
        ate_rx_sigdet_lf_threshold      = 4   ;
        ate_rx_sigdet_hf_threshold      = 2   ;
        ate_rx_misc                     = 0   ;
        ate_rx_term_ctrl                = 0   ;
        ate_rx_width                    = 4   ;
        ate_rx_dig_div_clk_sel          = 0   ;
        ate_rx_div_clk_en               = 0   ;
        ate_rx_div_clk_sel              = 0   ;
        ate_rx_rate                     = 1   ;
        ate_rx_dfe_bypass               = 0   ;
        ate_rx_offcan_cont              = 1   ;
        ate_rx_adapt_cont               = 1   ;
        ate_rx_eq_dfe_float_en          = 0   ;
        ate_rx_div16p5_clk_en           = 1   ;
        ate_rx_125mhz_clk_en            = 0   ;
        ate_rx_cdr_ssc_en               = 0   ;
        ate_rx_sigdet_hf_en             = 0   ;
        ate_rx_sigdet_lfps_filter_en    = 0   ;
        ate_rx_term_acdc                = 1   ;
        ate_rx_adapt_sel                = 0   ;
        ate_rx_adapt_mode               = 4   ;
        ate_rx_adapt_en                 = 0   ;//1
    }

    if (ecpri_speed_sel == 25)
    {
        ate_ref_range                   = 4    ;
        ate_ref_clk_div2_en             = 0    ;
        ate_ref_raw_clk_div2_en         = 1    ;
        ate_ref_clk_mplla_div           = 1    ;
        ate_lane_ref_sel                = 0    ;
        ate_mplla_fb_clk_div4_en        = 0    ;
        ate_mplla_multiplier            = 120  ;
        ate_mplla_tx_clk_div            = 1    ;
        ate_mplla_word_clk_div          = 2    ;
        ate_mplla_ssc_en                = 0    ;
        ate_mplla_ssc_up_spread         = 0    ;
        ate_mplla_ssc_peak              = 0    ;
        ate_mplla_ssc_step_size         = 0    ;
        ate_mplla_frac_en               = 0    ;
        ate_mplla_frac_quot             = 0    ;
        ate_mplla_frac_den              = 0    ;
        ate_mplla_frac_rem              = 0    ;
        ate_refa_lane_clk_en            = 0    ;
        ate_bs_rx_level                 = 7    ;
        ate_bs_tx_lowswing              = 0    ;
        ate_bs_rx_bigswing              = 1    ;
        ate_mplla_init_cal_disable      = 0    ;
        ate_refa_dig_clk_sel            = 0    ;
        ate_ref_dco_bypass              = 0    ;
        ate_refa_dco_ld_val             = 78   ;
        ate_ref_dco_target              = 150  ;
        ate_ref_dco_dig_range           = 6    ;
        ate_mplla_bw_threshold          = 75   ;
        ate_mplla_bw_low                = 1583 ;
        ate_mplla_bw_high               = 1583 ;
        ate_mplla_ctl_buf_bypass        = 0    ;
        ate_mplla_short_lock_en         = 0    ;
        ate_rx_term_offset              = 0    ;
        ate_txdn_term_offset            = 0    ;
        ate_txup_term_offset            = 0    ;
        ate_sup_misc                    = 3    ;
        ate_rx_vref_ctrl                = 5    ;
        ate_rx_ref_ld_val               = 17   ;
        ate_rx_vco_ld_val               = 1403 ;
        ate_rx_cdr_ppm_max              = 19   ;
        //lane
        ate_tx_misc                     = 0    ;
        ate_tx_dcc_ctrl_diff_range      = 8    ;
        ate_tx_dcc_ctrl_cm_range        = 8    ;
        ate_tx_width                    = 4    ;
        ate_tx_ropll_cp_ctl_intg        = 105  ;
        ate_tx_ropll_cp_ctl_prop        = 67   ;
        ate_tx_ropll_rc_filter          = 4    ;
        ate_tx_ropll_v2i_mode           = 3    ;
        ate_tx_ropll_vco_low_freq       = 2    ;
        ate_tx_ropll_postdiv            = 0    ;
        ate_tx_rate                     = 0    ;
        ate_tx_ropll_div16p5_clk_en     = 1    ;
        ate_tx_ropll_125mhz_clk_en      = 0    ;
        ate_tx_term_ctrl                = 0    ;
        ate_tx_dly_cal_en               = 0    ;
        ate_tx_pll_word_clk_freq        = 6    ;
        ate_tx_dig_ropll_div_clk_sel    = 0    ;
        ate_tx_dual_cntx_en             = 0    ;
        ate_tx_ropll_bypass             = 0    ;
        ate_tx_ropll_refdiv             = 4    ;
        ate_tx_ropll_refsel             = 0    ;
        ate_tx_ropll_fbdiv              = 11   ;
        ate_tx_ropll_div_clk_en         = 0    ;
        ate_tx_ropll_out_div            = 4    ;
        ate_tx_ropll_word_clk_div_sel   = 2    ;
        txX_ropll_word_clk_div_lte      = 2    ;
        ate_tx_fastedge_en              = 0    ;
        ate_tx_eq_pre                   = 0    ;
        ate_tx_eq_post                  = 0    ;
        ate_tx_eq_main                  = 24   ;
        ate_tx_align_wide_xfer_en       = 1    ;
        ate_rx_eq_att_lvl               = 0    ;
        ate_rx_eq_ctle_boost            = 20   ;
        ate_rx_eq_ctle_pole             = 3    ;
        ate_rx_eq_afe_rate              = 1    ;
        ate_rx_eq_vga_gain              = 16   ;
        ate_rx_eq_afe_config            = 2364 ;
        ate_rx_eq_dfe_tap1              = 12   ;
        ate_rx_eq_dfe_tap2              = 128  ;
        ate_rx_delta_iq                 = 3    ;
        ate_rx_cdr_vco_config           = 34   ;
        ate_rx_dcc_ctrl_diff_range      = 11   ;
        ate_rx_dcc_ctrl_cm_range        = 11   ;
        ate_rx_sigdet_lf_threshold      = 4    ;
        ate_rx_sigdet_hf_threshold      = 2    ;
        ate_rx_misc                     = 0    ;
        ate_rx_term_ctrl                = 0    ;
        ate_rx_width                    = 4    ;
        ate_rx_dig_div_clk_sel          = 0    ;
        ate_rx_div_clk_en               = 0    ;
        ate_rx_div_clk_sel              = 0    ;
        ate_rx_rate                     = 0    ;
        ate_rx_dfe_bypass               = 0    ;
        ate_rx_offcan_cont              = 1    ;
        ate_rx_adapt_cont               = 1    ;
        ate_rx_eq_dfe_float_en          = 1    ;
        ate_rx_div16p5_clk_en           = 1    ;
        ate_rx_125mhz_clk_en            = 0    ;
        ate_rx_cdr_ssc_en               = 0    ;
        ate_rx_sigdet_hf_en             = 0    ;
        ate_rx_sigdet_lfps_filter_en    = 0    ;
        ate_rx_term_acdc                = 1    ;
        ate_rx_adapt_sel                = 0    ;
        ate_rx_adapt_mode               = 4    ;
        ate_rx_adapt_en                 = 0    ;//
    }

    ate_tx_term_ctrl               = ate_tx_term_ctrl +8;
    ate_rx_term_ctrl               = ate_rx_term_ctrl +8;
    ate_ref_clk_mpllb_div          = ate_ref_clk_mplla_div;//
    ate_mpllb_fb_clk_div4_en       = ate_mplla_fb_clk_div4_en;//
    ate_mpllb_multiplier           = ate_mplla_multiplier;//
    ate_mpllb_tx_clk_div           = ate_mplla_tx_clk_div;//
    ate_mpllb_word_clk_div         = ate_mplla_word_clk_div;//
    ate_mpllb_ssc_en               = ate_mplla_ssc_en;//
    ate_mpllb_ssc_up_spread        = ate_mplla_ssc_up_spread;//
    ate_mpllb_ssc_peak             = ate_mplla_ssc_peak;//
    ate_mpllb_ssc_step_size        = ate_mplla_ssc_step_size;//
    ate_mpllb_frac_en              = ate_mplla_frac_en;//
    ate_mpllb_frac_quot            = ate_mplla_frac_quot;//
    ate_mpllb_frac_den             = ate_mplla_frac_den;//
    ate_mpllb_frac_rem             = ate_mplla_frac_den;//
    ate_refb_lane_clk_en           = ate_refa_lane_clk_en;//
    ate_mpllb_init_cal_disable     = ate_mplla_init_cal_disable;//
    ate_refb_dig_clk_sel           = ate_refa_dig_clk_sel;
    ate_refb_dco_ld_val            = ate_refa_dco_ld_val;
    ate_mpllb_bw_high              = ate_mplla_bw_high     ;//
    ate_mpllb_bw_low               = ate_mplla_bw_low      ;//
    ate_mpllb_bw_threshold         = ate_mplla_bw_threshold;//
    ate_mpllb_ctl_buf_bypass       = ate_mplla_ctl_buf_bypass;//
    ate_mpllb_short_lock_en        = ate_mplla_short_lock_en;//

    do_write(&JECS_PMA1_REF_CLK_CTRL, 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12));
    do_write(&JECS_PMA1_REFB_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en);
    do_write(&JECS_PMA1_REFA_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en);
    do_write(&JECS_PMA1_BROADCAST_LANE_REFCLK_SEL, ate_lane_ref_sel);
    do_write(&JECS_PMA1_MPLLA_PARAM6, (ate_mplla_fb_clk_div4_en<<4));
    do_write(&JECS_PMA1_MPLLB_PARAM6, (ate_mpllb_fb_clk_div4_en<<4));
    do_write(&JECS_PMA1_MPLLA_PARAM5, (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8));
    do_write(&JECS_PMA1_MPLLB_PARAM5, (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8));
    do_write(&JECS_PMA1_REFA_CLK_CTRL1, 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en);
    do_write(&JECS_PMA1_REFB_CLK_CTRL1, 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en);
    do_write(&JECS_PMA1_MPLLA_SSC_CTRL2, ate_mplla_ssc_peak);
    do_write(&JECS_PMA1_MPLLB_SSC_CTRL2, ate_mpllb_ssc_peak);
    do_write(&JECS_PMA1_MPLLA_SSC_CTRL5, ate_mplla_ssc_step_size);
    do_write(&JECS_PMA1_MPLLB_SSC_CTRL5, ate_mpllb_ssc_step_size);
    do_write(&JECS_PMA1_MPLLA_FRAC_CTRL1, ate_mplla_frac_den);
    do_write(&JECS_PMA1_MPLLB_FRAC_CTRL1, ate_mpllb_frac_den);
    do_write(&JECS_PMA1_MPLLA_FRAC_CTRL2, ate_mplla_frac_en);
    do_write(&JECS_PMA1_MPLLB_FRAC_CTRL2, ate_mpllb_frac_en);
    do_write(&JECS_PMA1_MPLLA_FRAC_CTRL3, ate_mplla_frac_quot);
    do_write(&JECS_PMA1_MPLLB_FRAC_CTRL3, ate_mpllb_frac_quot);
    do_write(&JECS_PMA1_MPLLA_FRAC_CTRL4, ate_mplla_frac_rem);
    do_write(&JECS_PMA1_MPLLB_FRAC_CTRL4, ate_mpllb_frac_rem);
    do_write(&JECS_PMA1_MPLLA_PARAM3, (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold);
    do_write(&JECS_PMA1_MPLLB_PARAM3, (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold);
    do_write(&JECS_PMA1_MPLLA_SSC_CTRL1, ate_mplla_ssc_en);
    do_write(&JECS_PMA1_MPLLB_SSC_CTRL1, ate_mpllb_ssc_en);
    do_write(&JECS_PMA1_MPLLA_SSC_CTRL4, ate_mplla_ssc_up_spread);
    do_write(&JECS_PMA1_MPLLB_SSC_CTRL4, ate_mpllb_ssc_up_spread);
    do_write(&JECS_PMA1_SUP_MISC, ate_sup_misc);
    do_write(&JECS_PMA1_MPLLA_PARAM4, ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12));
    do_write(&JECS_PMA1_MPLLB_PARAM4, ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12));
    do_write(&JECS_PMA1_RTUNE_CTRL1, ate_rx_term_offset);
    do_write(&JECS_PMA1_RTUNE_CTRL2, ate_txdn_term_offset);
    do_write(&JECS_PMA1_RTUNE_CTRL3, ate_txup_term_offset);
    do_write(&JECS_PMA1_MPLLA_PARAM1, ate_mplla_bw_high);
    do_write(&JECS_PMA1_MPLLB_PARAM1, ate_mpllb_bw_high);
    do_write(&JECS_PMA1_MPLLA_PARAM2, ate_mplla_bw_low);
    do_write(&JECS_PMA1_MPLLB_PARAM2, ate_mpllb_bw_low);
    do_write(&JECS_PMA1_RX_BIAS_CURRENT_CTRL, ate_rx_vref_ctrl+BIT8);//20220214
    do_write(&JECS_PMA1_MPLLA_FORCE_EN, ate_mplla_force_en);
    do_write(&JECS_PMA1_MPLLB_FORCE_EN, ate_mpllb_force_en);
    do_write(&JECS_PMA1_POWER_GATING_SIGNAL1, ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12));

    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7, ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8));
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8, ate_rx_vco_ld_val);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1, ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12));
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2, ate_tx_misc + (ate_tx_term_ctrl<<8));
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2, (ate_tx_width<<4) + ate_tx_rate);
    do_write(&JECS_PMA1_BROADCAST_ETH_CLK_CTRL, (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en);
    do_write(&JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL, ate_tx_dig_ropll_div_clk_sel);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_CONTROL, (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8));
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4, (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3, (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass +  (ate_rx_eq_att_lvl<<8));
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9, ate_rx_width);
    do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL2, (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2);
    do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL1, (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2, ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12));
    do_write(&JECS_PMA1_BROADCAST_RX_ADAPT_CTRL, ate_rx_adapt_sel);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING, (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8));
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, ate_tx_eq_main);
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, ate_tx_eq_post);
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, ate_tx_eq_pre);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6, (ate_rx_misc<<8));
    do_write(&JECS_PMA1_BROADCAST_RX_DCC_CTRL, ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4));
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5, (ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2, (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en);
    do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3, ate_rx_sigdet_lfps_filter_en);
    do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2, ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7));
    do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4, ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14));
    do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3, ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7));
    do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5, ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100);
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1, (ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4));
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY,  ate_tx_clk_rdy);
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING, ate_tx_align_wide_xfer_en + (ate_tx_invert<<4));
    do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1,  ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8));
    do_write(&JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3, ate_tx_dual_cntx_en);
    do_write(&JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL, ate_tx_dly_cal_en);
    do_write(&JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL, ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8));
}

/**********************************************************************************************************************
*  Function: vnet_set_mac_address
*  Description: vnet set mac address
*  Input: 
*    <name>        <type>               <desc>
*     dev           net_device *         network device
*     addr          void *               network address
*  Output: none
*  Return: operation result - success or failure.
*  Others: none
**********************************************************************************************************************/
void init_jecspma(uint32_t ecpri_speed_sel)
{
    uint32_t i = 0;

    //PCS Protocol Sel
    do_write(&JECS_CTRL_PROTOCOL_SEL, do_read_volatile(&JECS_CTRL_PROTOCOL_SEL) | BIT1); //??
    do_write(&JECS_PMA1_CPRI_PCS_STATUS_CTRL, 0);  //""
    do_write(&JECS_PMA1_PCS_BIT_REV_CTRL, 0x111);//20220207 modify 32BIT&REVERSE
    do_write(&JECS_PMA1_CPRI_SIGDET, BIT4|BIT0);//pcs signal detect sel by manual
    do_write(&JECS_PMA1_TX_CLK_SEL, 0x1);

#if 1 //10G
    do_write(&JECS_PHY_BS_CTRL, (BIT4 + (7<<6)));
#endif

    init_pma_commonconfig_ex(ecpri_speed_sel);

#if 1 //10G
      //do_write(&JECS_PMA1_BROADCAST_PMA_LOOPBACK_CTRL, (0x8000 + BIT4));
      //do_write(&JECS_PMA1_BROADCAST_PMA_LOOPBACK_CTRL, (0x8000 + BIT4));

      //define eq para 
      do_write(&JECS_PMA1_BROADCAST_EQ_INIT_C0, 0x40);
      do_write(&JECS_PMA1_BROADCAST_EQ_INIT_CN1, 0x4);//c-1
      do_write(&JECS_PMA1_BROADCAST_EQ_INIT_CP1, 0x1c);

      do_write(&JECS_PMA1_BROADCAST_EQ_PRESET_C0, 92);//c0
      do_write(&JECS_PMA1_BROADCAST_EQ_PRESET_CN1, 4);//c-1 pre
      do_write(&JECS_PMA1_BROADCAST_EQ_PRESET_CP1, 0);//c+1

    //do_write(&JECS_PMA1_PCS_PRBS_UDP_SEND, 0x1);
#endif

    do_write(&JECS_PMA1_PHY_RESET, 0x1); //phy_reset=1
    //printf("[init_jecspma] JECS PHY RESET\n");
    do_write(&JECS_PMA1_SRAM_CTRL, 0x101); //SHH:0x1//sram_bootload_bypass=1
    do_write(&JECS_PMA1_PHY_RESET, 0x0); //phy_reset=0
    while ((do_read_volatile(&JECS_PMA1_SRAM_STATUS) & BIT0) != BIT0); //check sram_init_done=1
    //init_fastjecspma();

    /* ecpri PMA1 Clock cfg start */
    for (i = 0; i < 16384; i++)
    {
        do_write((JECS_PMA1_CFG + 0xc000ul * 4 + i * 4), do_read_volatile(&pma_fw[i]));
    }

    do_write((JECS_PMA1_CFG + 0x101ul * 4), do_read_volatile(JECS_PMA1_CFG + 0x101ul * 4) | BIT1);

    for (i = 0; i < 16384; i++)
    {
        do_write((JECS_PMA1_CFG + 0xc000ul * 4 + i * 4), do_read_volatile(&pma_fw[i+16384]));
    }
    /* ecpri PMA1 Clock cfg end */

    //SRAM ECC DisEn and Init Done
    do_write(&JECS_PMA1_SRAM_CTRL, 0x1101); //SHH:0x1001//sram_ext_ld_done=1
    //printf("[init_jecspma] JECS  SRAM EXTDONE\n");
}

/**********************************************************************************************************************
*  Function: vnet_init
*  Description: vnet module load function
*  Input: none
*  Output: none
*  Return: operation result - success or failure.
*  Others: none
**********************************************************************************************************************/
void init_jecspma_rxtx(void)
{

  //Disable Tx and Rx RST
  do_write(&JECS_PMA1_LANE0_TRANSMITTER_CONTROL1, 0x0);
  do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, 0x0);

  //Wait Ack Done
  while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0);
  while (do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0);
  //printf("[init_jecspma_rxtx] JECS TRX ACK DONE\n");

  //Enable TX and RX Req
  do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1);
  do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1);

  //Wait ACK and Disable Req
  while (!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0));
  while (!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0));
  do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0);
  do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0);

  //Wait Ack Done
  while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0);
  while (do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0);
  //printf("[init_jecspma_rxtx] JECS TRX ACK DONE\n");

  //P0 PSTATE
  do_write(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7) & 0xfff0);
  do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1, do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1) & 0xff);
  do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1);
  do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1);

  //Wait ACK and Disable Req
  while (!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0));
  while (!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0));
  do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0);
  do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0);

  //Wait Ack Done
  while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0);
  while (do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0);
  //printf("[init_jecspma_rxtx] JECS TRX ACK DONE\n");

  //Enable Data
  do_write(&JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN, 0x1);
  do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, 0x1);

  while(do_read_volatile(&JECS_PMA1_LANE0_TRANS_PLL_STATE) == 0);
   //printf("[init_jecspma_rxtx] JECS TX VALID\n");

  //wait rx valid
  while(do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) == 0);
  //printf("[init_jecspma_rxtx] JECS RX RX VALID\n");

}

/**********************************************************************************************************************
*  Function: vnet_exit
*  Description: vnet module unload function
*  Input: none
*  Output: none
*  Return: none
*  Others: none
**********************************************************************************************************************/
void ecpri_pma_rx_adapt(void)
{
    uint32_t i = 0;

#if 1 //10G
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, 24);
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, 0);
    do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, 0);
    //printf("[ecpri_init] P4\n");

    //usleep(100);
    ucp_nop(100000);
    //delay_us(100);

    for (i = 0; i < 1; i++)
    {
        do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4);//reg rx_data_en
        do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4);//RX_ADAPT_IN_PROG
        //do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_MUX_CTRL, 0x1);//cfg sel rxX_adapt_in_prog
        //do_write(&JECS_PMA1_LANE0_RECEIVER_CONTROL_MUX_CTRL, 0x1);

        do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) | BIT4);//rx0_reset 
        //usleep(5);
        ucp_nop(5000);
        //delay_us(5);

        do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) & (~BIT4));
        //printf("[ecpri_init]wait ack down\n");
        while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK) & BIT0);
        //printf("[ecpri_init]pma ack down\n");
        do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, (BIT4 + BIT0));//reg
        //wait rx0_valid
        while ((do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) & BIT0) != 0x1) ;

        do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, (BIT4 + BIT0));//RX_ADAPT_IN_PROG +adapt req
        //printf("[ecpri_init]pma valid\n");
        while (!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK) & BIT0));
        //printf("[ecpri_init]pma adpt ack 1\n");
        do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4);
        while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK) & BIT0);
        //printf("[ecpri_init]pma adpt ack 0\n");
        do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, 0);
        //printf("[ecpri_init]pma 12.2 ok\n");
    }
#endif
}   



