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YB_Platform/public/common/driver/inc/ucp_sfr_c.h

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2023-07-13 11:27:03 +08:00
//******************** (C) COPYRIGHT 2019 SmartLogic*******************************
// FileName : ucp_sfr_c.h
// Author : lijian, jian.li@smartlogictech.com
// Date First Issued : 2019-03-29 04:08:48 PM
// Last Modified : 2022-06-15 04:39:20 PM
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef __UCP_SFR_C_H__
#define __UCP_SFR_C_H__
#include <stdint.h>
#include "ucp_param.h"
#define DDRC_BASE 0x04570000
#define DDRSYS_BASE 0x04578000
#define DDRPHY_BASE 0x0d800000
//pin mux
#define PIN_MUX_BASE_ADDR 0x04458000
#define PAD1_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x01*4)))
#define PAD2_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x02*4)))
#define PAD3_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x03*4)))
#define PAD4_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x04*4)))
#define PAD5_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x05*4)))
#define PAD6_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x06*4)))
#define PAD7_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x07*4)))
#define PAD8_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x08*4)))
#define PAD9_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x09*4)))
#define PAD10_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x0a*4)))
#define PAD11_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x0b*4)))
#define PAD12_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x0c*4)))
#define PAD13_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x0d*4)))
#define PAD14_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x0e*4)))
#define PAD15_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x0f*4)))
#define PAD16_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x10*4)))
#define PAD17_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x11*4)))
#define PA0_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x12*4)))
#define PA1_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x13*4)))
#define PA2_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x14*4)))
#define PA3_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x15*4)))
#define PA4_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x16*4)))
#define PA5_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x17*4)))
#define PA6_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x18*4)))
#define PA7_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x19*4)))
#define PA8_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x1a*4)))
#define PA9_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x1b*4)))
#define PA10_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x1c*4)))
#define PA11_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x1d*4)))
#define PA12_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x1e*4)))
#define PA13_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x1f*4)))
#define PA14_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x20*4)))
#define PB0_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x21*4)))
#define PB1_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x22*4)))
#define PB2_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x23*4)))
#define PB3_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x24*4)))
#define PB4_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x25*4)))
#define PB5_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x26*4)))
#define PB6_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x27*4)))
#define PB7_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x28*4)))
#define PB8_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x29*4)))
#define PB9_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x2a*4)))
#define PB10_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x2b*4)))
#define PB11_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x2c*4)))
#define PB12_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x2d*4)))
#define PB13_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x2e*4)))
#define PB14_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x2f*4)))
#define PC0_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x30*4)))
#define PC1_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x31*4)))
#define PC2_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x32*4)))
#define PC3_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x33*4)))
#define PC4_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x34*4)))
#define PC5_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x35*4)))
#define PC6_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x36*4)))
#define PC7_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x37*4)))
#define PC8_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x38*4)))
#define PC9_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x39*4)))
#define PC10_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x3a*4)))
#define PC11_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x3b*4)))
#define PC12_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x3c*4)))
#define PC13_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x3d*4)))
#define PC14_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x3e*4)))
#define PD0_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x3f*4)))
#define PD1_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x40*4)))
#define PD2_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x41*4)))
#define PD3_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x42*4)))
#define PD4_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x43*4)))
#define PD5_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x44*4)))
#define PD6_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x45*4)))
#define PD7_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x46*4)))
#define PD8_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x47*4)))
#define PD9_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x48*4)))
#define PD10_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x49*4)))
#define PD11_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x4a*4)))
#define PD12_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x4b*4)))
#define PD13_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x4c*4)))
#define PD14_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x4d*4)))
#define PD15_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x4e*4)))
#define PD16_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x4f*4)))
#define PD17_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x50*4)))
#define PD18_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x51*4)))
#define PD19_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x52*4)))
#define PD20_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x53*4)))
#define PD21_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x54*4)))
#define PE0_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x55*4)))
#define PE1_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x56*4)))
#define PE2_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x57*4)))
#define PE3_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x58*4)))
#define PE4_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x59*4)))
#define PE5_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x5a*4)))
#define PE6_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x5b*4)))
#define PE7_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x5c*4)))
#define PE8_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x5d*4)))
#define PE9_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x5e*4)))
#define PA_PMUX_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x5f*4)))
#define PB_PMUX_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x60*4)))
#define PC_PMUX_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x61*4)))
#define PD_PMUX0_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x62*4)))
#define PD_PMUX1_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x63*4)))
#define PE_PMUX_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x64*4)))
#define PE10_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x65*4)))
#define PE11_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x66*4)))
#define PB15_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x69*4)))
#define PB16_CTRL_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x6a*4)))
#define PB_PMUX1_REG (*((volatile uint32_t *)(PIN_MUX_BASE_ADDR + 0x68*4)))
//CRG
#define CRG_BASE_ADDR 0x04550000
#define PLL0_CTL_REG0 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0000)))
#define PLL0_CTL_REG1 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0004)))
#define PLL0_CTL_REG2 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0008)))
#define PLL0_CTL_REG3 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x000C)))
#define PLL0_CTL_REG4 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0010)))
#define PLL1_CTL_REG0 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0014)))
#define PLL1_CTL_REG1 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0018)))
#define PLL1_CTL_REG2 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x001C)))
#define PLL1_CTL_REG3 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0020)))
#define PLL1_CTL_REG4 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0024)))
#define PLL2_CTL_REG0 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0028)))
#define PLL2_CTL_REG1 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x002C)))
#define PLL2_CTL_REG2 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0030)))
#define PLL2_CTL_REG3 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0034)))
#define PLL2_CTL_REG4 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0038)))
#define PLL3_CTL_REG0 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x003C)))
#define PLL3_CTL_REG1 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0040)))
#define PLL3_CTL_REG2 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0044)))
#define PLL3_CTL_REG3 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0048)))
#define PLL3_CTL_REG4 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x004C)))
#define PLL4_CTL_REG0 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0050)))
#define PLL4_CTL_REG1 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0054)))
#define PLL4_CTL_REG2 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0058)))
#define PLL4_CTL_REG3 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x005C)))
#define PLL4_CTL_REG4 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0060)))
#define PLL5_CTL_REG0 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0064)))
#define PLL5_CTL_REG1 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0068)))
#define PLL5_CTL_REG2 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x006C)))
#define PLL5_CTL_REG3 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0070)))
#define PLL5_CTL_REG4 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0074)))
#define CLK_CTL_REG0 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00C4)))
#define CLK_CTL_REG1 (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00C8)))
#define PLL0_TESTCLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00CC)))
#define PLL1_TESTCLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00D0)))
#define PLL2_TESTCLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00D4)))
#define PLL3_TESTCLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00D8)))
#define PLL4_TESTCLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00DC)))
#define PLL5_TESTCLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00E0)))
#define SDIO_TUNING_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00F0)))
#define SDIO_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00F4)))
#define APC0_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00F8)))
#define APC1_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x00FC)))
#define APC2_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0100)))
#define APC3_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0104)))
#define APC0_SYSCNT_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0108)))
#define APC1_SYSCNT_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x010C)))
#define APC2_SYSCNT_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0110)))
#define APC3_SYSCNT_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0114)))
#define SRIO0_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0120)))
#define SRIO1_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0124)))
#define SRIO2_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0128)))
#define MAIN_HI_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0134)))
#define JS_HI_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0138)))
#define ES_HI_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x013C)))
#define PET_HI_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0140)))
#define MAIN_LO_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0144)))
#define JS_LO_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0148)))
#define ES_LO_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x014C)))
#define PET_LO_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0150)))
#define MAINH_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0154)))
#define JSH_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0158)))
#define ESH_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x015C)))
#define PETH_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0160)))
#define MAINP_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0164)))
#define JSP_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0168)))
#define ESP_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x016C)))
#define PETP_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0170)))
#define DMAS0_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0174)))
#define DMAS1_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0178)))
#define SSI0_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x017C)))
#define SSI1_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0180)))
#define SSI2_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0184)))
#define SSI3_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0188)))
#define IIC0_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x018C)))
#define IIC1_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0190)))
#define TIMER00_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0194)))
#define TIMER01_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0198)))
#define TIMER02_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x019C)))
#define TIMER03_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01A0)))
#define TIMER04_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01A4)))
#define TIMER05_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01A8)))
#define TIMER06_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01AC)))
#define TIMER07_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01B0)))
#define TIMER10_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01B4)))
#define TIMER11_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01B8)))
#define TIMER12_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01BC)))
#define TIMER13_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01C0)))
#define TIMER14_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01C4)))
#define TIMER15_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01C8)))
#define TIMER16_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01CC)))
#define TIMER17_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01D0)))
#define TIMER20_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01D4)))
#define TIMER21_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01D8)))
#define TIMER22_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01DC)))
#define TIMER23_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01E0)))
#define TIMER24_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01E4)))
#define TIMER25_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01E8)))
#define TIMER26_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01EC)))
#define TIMER27_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01F0)))
#define UART0_FRAC_DIV_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01F4)))
#define UART1_FRAC_DIV_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01F8)))
#define UART2_FRAC_DIV_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x01FC)))
#define UART3_FRAC_DIV_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0200)))
#define UART0_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0204)))
#define UART1_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0208)))
#define UART2_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x020C)))
#define UART3_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0210)))
#define GMAC0_PRE_TX_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0214)))
#define GMAC1_PRE_TX_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0218)))
#define GMAC0_TX_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x021C)))
#define GMAC1_TX_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0220)))
#define GMAC0_TUNING_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0224)))
#define GMAC1_TUNING_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0228)))
#define GMAC0_PTP_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x022C)))
#define GMAC1_PTP_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0230)))
#define TMAC_PTP_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0234)))
#define RTC_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0238)))
#define GPIO_PRE_DB_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x023C)))
#define GPIO_DB_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0240)))
#define RFC_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0244)))
//#define JESD_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0248)))
#define PCIE_AUX_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x024C)))
#define M3_TPIU_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0250)))
#define M3_DAP_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0254)))
#define M3_AHB_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0258)))
#define PLL_STATUS_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0264)))
#define PLL_LOCK_MASK (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0268)))
#define WDT_RST_CRG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x026C)))
#define SDIO_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0270)))
#define APC0_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0274)))
#define APC1_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0278)))
#define APC2_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x027C)))
#define APC3_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0280)))
#define APC0_SYSCNT_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0284)))
#define APC1_SYSCNT_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0288)))
#define APC2_SYSCNT_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x028C)))
#define APC3_SYSCNT_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0290)))
#define SRIO0_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0294)))
#define SRIO1_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0298)))
#define SRIO2_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x029C)))
#define MAIN_HI_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02A0)))
#define JS_HI_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02A4)))
#define ES_HI_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02A8)))
#define PET_HI_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02AC)))
#define MAIN_LO_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02B0)))
#define JS_LO_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02B4)))
#define ES_LO_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02B8)))
#define PET_LO_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02BC)))
#define MAINH_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02C0)))
#define JSH_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02C4)))
#define ESH_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02C8)))
#define PETH_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02CC)))
#define MAINP_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02D0)))
#define JSP_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02D4)))
#define ESP_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02D8)))
#define PETP_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02DC)))
#define DMAS0_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02E0)))
#define DMAS1_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02E4)))
#define SSI0_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02E8)))
#define SSI1_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02EC)))
#define SSI2_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02F0)))
#define SSI3_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02F4)))
#define IIC0_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02F8)))
#define IIC1_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x02FC)))
#define TIMER00_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0300)))
#define TIMER01_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0304)))
#define TIMER02_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0308)))
#define TIMER03_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x030C)))
#define TIMER04_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0310)))
#define TIMER05_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0314)))
#define TIMER06_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0318)))
#define TIMER07_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x031C)))
#define TIMER10_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0320)))
#define TIMER11_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0324)))
#define TIMER12_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0328)))
#define TIMER13_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x032C)))
#define TIMER14_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0330)))
#define TIMER15_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0334)))
#define TIMER16_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0338)))
#define TIMER17_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x033C)))
#define TIMER20_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0340)))
#define TIMER21_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0344)))
#define TIMER22_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0348)))
#define TIMER23_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x034C)))
#define TIMER24_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0350)))
#define TIMER25_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0354)))
#define TIMER26_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0358)))
#define TIMER27_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x035C)))
#define UART0_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0360)))
#define UART1_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0364)))
#define UART2_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0368)))
#define UART3_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x036C)))
#define GPIO_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0370)))
#define RTC_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0374)))
#define GMAC0_TX_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0378)))
#define GMAC1_TX_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x037C)))
#define TMAC_PTP_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0380)))
#define RFC_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0384)))
#define JS_PMA_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0388)))
#define ES_PMA_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x038C)))
#define PET_PMA_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0390)))
#define JS_PMA_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0394)))
#define ES_PMA_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0398)))
#define PET_PMA_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x039C)))
#define JESD_SYSREF_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03A0)))
#define M3_TPIU_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03A4)))
#define M3_DAP_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03A8)))
#define M3_PORN_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03AC)))
#define M3_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03B0)))
#define M3_AHB_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03B4)))
#define USBPHY_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03B8)))
#define SYSC_RST_MASK (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03BC)))
#define SMMU_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03C0)))
#define SMMU_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03C4)))
#define EFUSE_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03C8)))
#define EFUSE_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03CC)))
#define SPACC_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03D0)))
#define SPACC_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03D4)))
#define PLL0_DYNAMIC_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03D8)))
#define PLL1_DYNAMIC_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03DC)))
#define PLL2_DYNAMIC_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03E0)))
#define PLL3_DYNAMIC_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03E4)))
#define PLL4_DYNAMIC_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03E8)))
#define PLL5_DYNAMIC_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03EC)))
#define PLL01_FBDIV_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03F0)))
#define PLL23_FBDIV_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03F4)))
#define PLL45_FBDIV_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03F8)))
#define PLL0_FRAC_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x03FC)))
#define PLL1_FRAC_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0400)))
#define PLL2_FRAC_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0404)))
#define PLL3_FRAC_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0408)))
#define PLL4_FRAC_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x040C)))
#define PLL5_FRAC_DY_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0410)))
#define PLL_FIFO_FULL_ST_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0414)))
#define PLL_FIFO_EMPTY_ST_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0418)))
#define PLL0_FIFO_DY_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x041C)))
#define PLL1_FIFO_DY_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0420)))
#define PLL2_FIFO_DY_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0424)))
#define PLL3_FIFO_DY_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0428)))
#define PLL4_FIFO_DY_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x042C)))
#define PLL5_FIFO_DY_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0430)))
#define EIP_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0434)))
#define EIP_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0438)))
#define PMA_SUB_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0444)))
#define DEBUG_SCAN_CLK_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x0448)))
#define DEBUG_SCAN_RST_CFG_REG (*((volatile uint32_t *)(CRG_BASE_ADDR + 0x044C)))
//SYSCTRL
#define SYSCFG_BASE_ADDR 0x04560000
#define APC_CTRL_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x00*4)))
#define QOS_CTRL1_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x01*4)))
#define QOS_CTRL2_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x02*4)))
#define APCS1_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x03*4)))
#define APCS1_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x04*4)))
#define APCS1_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x05*4)))
#define APCS2_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x06*4)))
#define APCS2_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x07*4)))
#define APCS2_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x08*4)))
#define APCS3_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x09*4)))
#define APCS3_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x0a*4)))
#define APCS3_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x0b*4)))
#define APCS0_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x0c*4)))
#define APCS0_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x0d*4)))
#define APCS0_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x0e*4)))
#define GMAC0_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x0f*4)))
#define GMAC0_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x10*4)))
#define GMAC0_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x11*4)))
#define GMAC1_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x12*4)))
#define GMAC1_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x13*4)))
#define GMAC1_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x14*4)))
#define APRFM_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x15*4)))
#define APRFM_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x16*4)))
#define PET_MAIN_AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x17*4)))
#define PET_MAIN_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x18*4)))
#define PET_MAIN_ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x19*4)))
#define TESTMODE_SYS_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x1a*4)))
#define BOOT_I2C_GPIO_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x1b*4)))
#define PET_MAIN_RUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x1c*4)))
#define PET_MAIN_BUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x1d*4)))
#define CCI_QOS_ACCEPT_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x1e*4)))
#define DMAS_SDMMC_REGCTRL (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x1f*4)))
#define CCI_EVNTBUS6_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x20*4)))
#define CCI_EVNTBUS7_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x21*4)))
#define SMMU_SHARE_CTRL (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x22*4)))
#define A72_EVENT_SEL (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x25*4)))
#define A72_CTRL0_STATUS_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x26*4)))
#define A72_CTRL1_STATUS_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x27*4)))
#define QOS_CTRL3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x28*4)))
#define CCI_ADDRMAP_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x29*4)))
#define CCI_ARVMIDEXTS_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x2a*4)))
#define CCI_ARUSERS3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x2b*4)))
#define CCI_AWUSERS3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x2c*4)))
#define CCI_WUSERS3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x2d*4)))
#define CCI_CTRL_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x2e*4)))
#define CCI_EVNTBUS0_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x2f*4)))
#define CCI_EVNTBUS1_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x30*4)))
#define CCI_EVNTBUS2_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x31*4)))
#define CCI_EVNTBUS3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x32*4)))
#define CCI_EVNTBUS4_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x33*4)))
#define CCI_EVNTBUS5_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x34*4)))
#define CCI_OVERGLOW_MASK_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x35*4)))
#define EVENT_ZERO_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x36*4)))
#define RSB_CFG_RTC_UART_TIMER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x37*4)))
#define SDIO_HADDR_GMAC1_GMAC0_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x38*4)))
#define HAUSER_M3_M3_SUB_S_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x39*4)))
#define APRFM_USER0_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x3a*4)))
#define APRFM_USER1_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x3b*4)))
#define APRFM_USER2_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x3c*4)))
#define APRFM_USER3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x3d*4)))
#define APRFM_USER4_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x3e*4)))
#define APRFM_USER5_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x3f*4)))
#define SMMU_WDT_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x40*4)))
#define APC_QOS_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x41*4)))
#define RFCQOS_SM_APCSEL_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x42*4)))
#define PLL_TESTCLK_SEL_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x43*4)))
#define DFTCTRL_SYS_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x44*4)))
#define M4_WUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x45*4)))
#define SYSC_CTC0_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x46*4)))
#define SYSC_CTC1_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x47*4)))
#define SYSC_CTC2_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x48*4)))
#define SYSC_CTC3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x49*4)))
#define SYSC_CTC4_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x4A*4)))
#define SYSC_CTC5_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x4B*4)))
#define SYSC_CTC6_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x4C*4)))
#define SYSC_CTC7_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x4D*4)))
#define SYSC_CTC8_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x4E*4)))
#define SYSC_CTC9_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x4F*4)))
#define SYSC_CTC10_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x50*4)))
#define SYSC_CTC11_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x51*4)))
#define SYSC_CTC12_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x52*4)))
#define SYSC_CTC13_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x53*4)))
#define SYSC_CTC14_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x54*4)))
#define SYSC_CTC15_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x55*4)))
#define SYSC_CTC16_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x56*4)))
#define SYSC_CTC17_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x57*4)))
#define SYSC_CTC18_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x58*4)))
#define SYSC_CTC19_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x59*4)))
#define SYSC_CTC20_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x5A*4)))
#define SYSC_CTC21_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x5B*4)))
#define SYSC_CTC22_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x5C*4)))
#define SYSC_CTC23_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x5D*4)))
#define SYSC_CTC24_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x5E*4)))
#define SYSC_CTC25_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x5F*4)))
#define SYSC_CTC26_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x60*4)))
#define SYSC_CTC27_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x61*4)))
#define SYSC_CTC28_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x62*4)))
#define SYSC_CTC29_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x63*4)))
#define SYSC_CTC30_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x64*4)))
#define SYSC_CTC31_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x65*4)))
#define SYSC_CTC32_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x66*4)))
#define SYSC_CTC33_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x67*4)))
#define SYSC_CTC34_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x68*4)))
#define SYSC_CTC35_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x69*4)))
#define SYSC_CTC36_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x6A*4)))
#define SYSC_CTC37_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x6B*4)))
#define SYSC_CTC38_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x6C*4)))
#define SYSC_CTC39_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x6D*4)))
#define SYSC_CTC40_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x6E*4)))
#define SYSC_CTC41_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x6F*4)))
#define SYSC_CTC42_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x70*4)))
#define SYSC_CTC43_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x71*4)))
#define SYSC_CTC44_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x72*4)))
#define SYSC_CTC45_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x73*4)))
#define SYSC_CTC46_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x74*4)))
#define SYSC_CTC47_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x75*4)))
#define SYSC_CTC48_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x76*4)))
#define SYSC_CTC49_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x77*4)))
#define SYSC_CTC50_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x78*4)))
#define SYSC_CTC51_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x79*4)))
#define SYSC_CTC52_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x7A*4)))
#define SYSC_CTC53_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x7B*4)))
#define SYSC_CTC54_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x7C*4)))
#define SYSC_CTC55_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x7D*4)))
#define SYSC_CTC56_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x7E*4)))
#define SYSC_CTC57_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x7F*4)))
#define SYSC_CTC58_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x80*4)))
#define SYSC_CTC59_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x81*4)))
#define SYSC_CTC60_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x82*4)))
#define SYSC_CTC61_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x83*4)))
#define SYSC_CTC62_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x84*4)))
#define SYSC_CTC63_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x85*4)))
#define SYSC_CTC64_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x86*4)))
#define SYSC_CTC65_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x87*4)))
#define SYSC_CTC66_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x88*4)))
#define SYSC_CTC67_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x89*4)))
#define SYSC_CTC68_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x8A*4)))
#define SYSC_CTC69_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x8B*4)))
#define SYSC_CTC70_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x8C*4)))
#define SYSC_CTC71_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x8D*4)))
#define M3ARUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x8E*4)))
#define M3AWUSER_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x8F*4)))
#define ARUSER_M1_CSU_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x90*4)))
#define AWUSER_M1_CSU_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x91*4)))
#define WUSER_M1_CSU_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x92*4)))
#define CCI_ARUSER_S4_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x93*4)))
#define CCI_AWUSER_S4_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x94*4)))
#define CCI_WUSER_S4_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x95*4)))
#define SYSC_CP_R0_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x96*4)))
#define SYSC_CP_R1_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x97*4)))
#define SYSC_CP_R2_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x98*4)))
#define SYSC_CP_R3_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x99*4)))
#define SYSC_CP_R4_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x9A*4)))
#define SYSC_CP_R5_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x9B*4)))
#define SYSC_CP_R6_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x9C*4)))
#define SYSC_CP_R7_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x9D*4)))
#define SYSC_CP_R8_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x9E*4)))
#define SYSC_CP_R9_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0x9F*4)))
#define SYSC_CP_R10_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA0*4)))
#define SYSC_CP_R11_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA1*4)))
#define SYSC_CP_R12_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA2*4)))
#define SYSC_CP_R13_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA3*4)))
#define SYSC_CP_R14_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA4*4)))
#define SYSC_CP_R15_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA5*4)))
#define SYSC_CP_R16_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA6*4)))
#define SYSC_CP_R17_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA7*4)))
#define SYSC_CP_R18_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xA8*4)))
#define EFUSE_CTRL_REG (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0XA9*4)))
#define CCI_NSAIDS_REG0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xAa*4)))
#define CCI_NSAIDS_REG1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xAb*4)))
#define CCI_NSAIDM_REG1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xAc*4)))
#define APSPACC_ADDR_CTRL (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xAD*4)))
#define CPSPACC_ADDR_CTRL (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xAE*4)))
#define CCI_NSAIDS_REG2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 0xAF*4)))
#define SYSCTRL_REG0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 176*4)))
#define SYSCTRL_REG1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 177*4)))
#define SYSCTRL_REG2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 178*4)))
#define SYSCTRL_REG3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 179*4)))
#define APC0_INT_MASK0_PTR ((volatile uint32_t *)(SYSCFG_BASE_ADDR + 180*4))
#define APC0_INT_MASK0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 180*4)))
#define APC0_INT_MASK1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 181*4)))
#define APC0_INT_MASK2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 182*4)))
#define APC0_INT_MASK3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 183*4)))
#define APC0_INT_MASK4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 184*4)))
#define APC0_INT_MASK5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 185*4)))
#define APC0_INT_MASK6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 186*4)))
#define APC0_INT_MASK7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 187*4)))
#define APC0_INT_MASK8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 188*4)))
#define APC0_INT_MASK9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 189*4)))
#define APC0_INT_MASK10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 190*4)))
#define APC0_INT_MASK11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 191*4)))
#define APC0_INT_MASK12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 192*4)))
#define APC0_INT_MASK13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 193*4)))
#define APC0_INT_MASK14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 194*4)))
#define APC0_INT_MASK15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 195*4)))
#define APC1_INT_MASK0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 196*4)))
#define APC1_INT_MASK1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 197*4)))
#define APC1_INT_MASK2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 198*4)))
#define APC1_INT_MASK3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 199*4)))
#define APC1_INT_MASK4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 200*4)))
#define APC1_INT_MASK5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 201*4)))
#define APC1_INT_MASK6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 202*4)))
#define APC1_INT_MASK7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 203*4)))
#define APC1_INT_MASK8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 204*4)))
#define APC1_INT_MASK9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 205*4)))
#define APC1_INT_MASK10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 206*4)))
#define APC1_INT_MASK11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 207*4)))
#define APC1_INT_MASK12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 208*4)))
#define APC1_INT_MASK13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 209*4)))
#define APC1_INT_MASK14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 210*4)))
#define APC1_INT_MASK15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 211*4)))
#define APC2_INT_MASK0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 212*4)))
#define APC2_INT_MASK1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 213*4)))
#define APC2_INT_MASK2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 214*4)))
#define APC2_INT_MASK3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 215*4)))
#define APC2_INT_MASK4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 216*4)))
#define APC2_INT_MASK5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 217*4)))
#define APC2_INT_MASK6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 218*4)))
#define APC2_INT_MASK7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 219*4)))
#define APC2_INT_MASK8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 220*4)))
#define APC2_INT_MASK9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 221*4)))
#define APC2_INT_MASK10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 222*4)))
#define APC2_INT_MASK11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 223*4)))
#define APC2_INT_MASK12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 224*4)))
#define APC2_INT_MASK13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 225*4)))
#define APC2_INT_MASK14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 226*4)))
#define APC2_INT_MASK15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 227*4)))
#define APC3_INT_MASK0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 228*4)))
#define APC3_INT_MASK1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 229*4)))
#define APC3_INT_MASK2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 230*4)))
#define APC3_INT_MASK3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 231*4)))
#define APC3_INT_MASK4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 232*4)))
#define APC3_INT_MASK5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 233*4)))
#define APC3_INT_MASK6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 234*4)))
#define APC3_INT_MASK7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 235*4)))
#define APC3_INT_MASK8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 236*4)))
#define APC3_INT_MASK9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 237*4)))
#define APC3_INT_MASK10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 238*4)))
#define APC3_INT_MASK11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 239*4)))
#define APC3_INT_MASK12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 240*4)))
#define APC3_INT_MASK13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 241*4)))
#define APC3_INT_MASK14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 242*4)))
#define APC3_INT_MASK15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 243*4)))
#define EIP0_AWUSER (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 300*4)))
#define EIP0_WUSER (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 301*4)))
#define EIP0_ARUSER (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 302*4)))
#define EIP1_AWUSER (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 303*4)))
#define EIP1_WUSER (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 304*4)))
#define EIP1_ARUSER (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 305*4)))
#define EIP0_QOS (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 306*4)))
#define EIP1_QOS (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 307*4)))
#define SYSCTRL_REG4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 308*4)))
#define SYSCTRL_REG5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 309*4)))
#define SYSCTRL_REG6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 310*4)))
#define SYSCTRL_REG7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 311*4)))
#define APC0_INT_STATUS0_PTR ((volatile uint32_t *)(SYSCFG_BASE_ADDR + 312*4))
#define APC0_INT_STATUS0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 312*4)))
#define APC0_INT_STATUS1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 313*4)))
#define APC0_INT_STATUS2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 314*4)))
#define APC0_INT_STATUS3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 315*4)))
#define APC0_INT_STATUS4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 316*4)))
#define APC0_INT_STATUS5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 317*4)))
#define APC0_INT_STATUS6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 318*4)))
#define APC0_INT_STATUS7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 319*4)))
#define APC0_INT_STATUS8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 320*4)))
#define APC0_INT_STATUS9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 321*4)))
#define APC0_INT_STATUS10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 322*4)))
#define APC0_INT_STATUS11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 323*4)))
#define APC0_INT_STATUS12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 324*4)))
#define APC0_INT_STATUS13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 325*4)))
#define APC0_INT_STATUS14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 326*4)))
#define APC0_INT_STATUS15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 327*4)))
#define APC1_INT_STATUS0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 328*4)))
#define APC1_INT_STATUS1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 329*4)))
#define APC1_INT_STATUS2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 330*4)))
#define APC1_INT_STATUS3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 331*4)))
#define APC1_INT_STATUS4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 332*4)))
#define APC1_INT_STATUS5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 333*4)))
#define APC1_INT_STATUS6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 334*4)))
#define APC1_INT_STATUS7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 335*4)))
#define APC1_INT_STATUS8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 336*4)))
#define APC1_INT_STATUS9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 337*4)))
#define APC1_INT_STATUS10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 338*4)))
#define APC1_INT_STATUS11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 339*4)))
#define APC1_INT_STATUS12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 340*4)))
#define APC1_INT_STATUS13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 341*4)))
#define APC1_INT_STATUS14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 342*4)))
#define APC1_INT_STATUS15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 343*4)))
#define APC2_INT_STATUS0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 344*4)))
#define APC2_INT_STATUS1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 345*4)))
#define APC2_INT_STATUS2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 346*4)))
#define APC2_INT_STATUS3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 347*4)))
#define APC2_INT_STATUS4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 348*4)))
#define APC2_INT_STATUS5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 349*4)))
#define APC2_INT_STATUS6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 350*4)))
#define APC2_INT_STATUS7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 351*4)))
#define APC2_INT_STATUS8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 352*4)))
#define APC2_INT_STATUS9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 353*4)))
#define APC2_INT_STATUS10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 354*4)))
#define APC2_INT_STATUS11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 355*4)))
#define APC2_INT_STATUS12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 356*4)))
#define APC2_INT_STATUS13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 357*4)))
#define APC2_INT_STATUS14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 358*4)))
#define APC2_INT_STATUS15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 359*4)))
#define APC3_INT_STATUS0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 360*4)))
#define APC3_INT_STATUS1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 361*4)))
#define APC3_INT_STATUS2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 362*4)))
#define APC3_INT_STATUS3 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 363*4)))
#define APC3_INT_STATUS4 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 364*4)))
#define APC3_INT_STATUS5 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 365*4)))
#define APC3_INT_STATUS6 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 366*4)))
#define APC3_INT_STATUS7 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 367*4)))
#define APC3_INT_STATUS8 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 368*4)))
#define APC3_INT_STATUS9 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 369*4)))
#define APC3_INT_STATUS10 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 370*4)))
#define APC3_INT_STATUS11 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 371*4)))
#define APC3_INT_STATUS12 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 372*4)))
#define APC3_INT_STATUS13 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 373*4)))
#define APC3_INT_STATUS14 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 374*4)))
#define APC3_INT_STATUS15 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 375*4)))
#define HSMA_QOS_CTRL (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 376*4)))
#define HSMA_QOS0 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 377*4)))
#define HSMA_QOS1 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 378*4)))
#define HSMA_QOS2 (*((volatile uint32_t *)(SYSCFG_BASE_ADDR + 379*4)))
//SYSDBG
#define SYSCNT0_BASE_ADDR 0x02110000
#define CNTCR (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x00*4)))
#define CNTSR (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x04*4)))
#define CNTCVL (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x08*4)))
#define CNTCVU (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x0C*4)))
#define CNTFID0 (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x20*4)))
#define CNT0CR (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x00*4)))
#define CNT0SR (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x04*4)))
#define CNT0CVL (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x08*4)))
#define CNT0CVU (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x0C*4)))
#define CNT0FID0 (*((volatile uint32_t *)(SYSCNT0_BASE_ADDR + 0x20*4)))
#define SYSCNT1_BASE_ADDR 0x02110000
#define CNT1CR (*((volatile uint32_t *)(SYSCNT1_BASE_ADDR + 0x00*4)))
#define CNT1SR (*((volatile uint32_t *)(SYSCNT1_BASE_ADDR + 0x04*4)))
#define CNT1CVL (*((volatile uint32_t *)(SYSCNT1_BASE_ADDR + 0x08*4)))
#define CNT1CVU (*((volatile uint32_t *)(SYSCNT1_BASE_ADDR + 0x0C*4)))
#define CNT1FID0 (*((volatile uint32_t *)(SYSCNT1_BASE_ADDR + 0x20*4)))
#if 0
#include "dw_tmac.h"
#include "dw_tpcs.h"
#include "dw_ahb_gpmc.h"
#include "dw_ahb_usb.h"
#include "dw_apb_gpio.h"
#include "dw_apb_i2c.h"
#include "dw_apb_rtc.h"
#include "dw_apb_spi.h"
#include "dw_apb_timers.h"
#include "dw_apb_uart.h"
#include "dw_apb_wdt.h"
#include "dw_apb_ddr.h"
#include "dw_axi_dmac.h"
#include "dw_gmac.h"
#include "dw_sdio.h"
#include "gic_500.h"
#include "smmu_500.h"
#include "cci550.h"
#include "a72_ctrl.h"
#include "gs_que.h"
#include "pvt_all.h"
#include "efuse.h"
#include "dw_pcie.h"
#include "pcie_pma.h"
#include "ucp_js_ctrl.h"
#include "ucp_pma.h"
#include "ucp_srio_ctrl.h"
#include "ucp_srio.h"
#include "pet_ctrl.h"
#include "ucp_js_subcrg.h"
#include "apcs.h"
#include "jesd204.h"
#include "ucp_rfc.h"
#include "sec_sm.h"
#include "csu.h"
#include "trng.h"
#include "spacc.h"
#include "pka.h"
#include "cpri.h"
#include "ecpri.h"
#include "mailbox.h"
#include "ucp_rfc.h"
#define EIP0_BASE 0X01060000
#define EIP1_BASE 0X01260000
#define EIP2_BASE 0X08760000
#define C2UVM_FLAG (*((volatile uint32_t *)(CPSM_BASE + 0x1FF00 )))
#define UVM2C_FLAG (*((volatile uint32_t *)(CPSM_BASE + 0x1FF04 )))
#define SIMULATION_END (*((volatile uint32_t *)(CPSM_BASE + 0x1FF08 )))
#define APE_FLAG (*((volatile uint32_t *)(CPSM_BASE + 0x1FF0C )))
#define TUBE_C (*((volatile unsigned char *)(CPSM_BASE + 0x1FF20 )))
#define RNG_VALUE (*((volatile uint32_t *)(CPSM_BASE + 0x1FF10 )))
#define ECC_VALUE (*((volatile uint32_t *)(CPSM_BASE + 0x1FF14 )))
#define FAST_DDR (*((volatile uint32_t *)(CPSM_BASE + 0x1FF18 )))
#define POST_SIM_FLAG (*((volatile uint32_t *)(CPSM_BASE + 0x1FF1C )))
#define C2UVM_FLAG_RFM (*((volatile uint32_t *)(SM5_BASE + 0x0017FF00 + 0x00 )))
#define UVM2C_FLAG_RFM (*((volatile uint32_t *)(SM5_BASE + 0x0017FF00 + 0x04 )))
#define SIMULATION_END_RFM (*((volatile uint32_t *)(SM5_BASE + 0x0017FF00 + 0x08 )))
#endif
#endif
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