YB_Platform/public/common/ecs_dm/inc/gpio_drv.h

#ifndef _GPIO_DRV_H_
#define _GPIO_DRV_H_

#include "dw_apb_gpio.h"
#include "typedef.h"

#define JESD_RF_CH_NUM		4

#define JESD_GPIOGROUP_NUM	9

typedef enum _tagGpioLValid
{
	LOW_AS_VALID	= 0,
	HIGH_AS_VALID
}gpioLValid;

typedef enum _tagJesdGpioTRCH
{
	JESD_TRANS_TX    = 0,
	JESD_RF_TX       = 1,
	JESD_ANT_TX      = 2,
	JESD_TRANS_RX    = 3,
	JESD_RF_RX       = 4,
	JESD_ANT_RX      = 5,
	JESD_TRANS_ORX   = 6,
	JESD_RF_ORX      = 7,
	JESD_ANT_ORX     = 8,
	JESD_TRCH_MAXNUM = 9
}jesdGpioTRch;

typedef enum _tagGpioState
{
	GPIO_OFF = 0,
	GPIO_ON = 1
}jesdGpioState;

typedef struct _tagGpioInfo
{
	uint8_t pinId;	// 0~31
	uint8_t vaFlag;	// 0: low as valid; 1: high as valid
}stGpioInfo;

typedef struct _tagRfGpioInfo
{
	uint32_t pinInfo;	// 1 bit 1 pin
	uint32_t validInfo;	// 0: low as valid; 1: high as valid
}stRfGpioInfo;

typedef struct _tagGpioJesd
{
	stRfGpioInfo   txRfGpioInfo[JESD_RF_CH_NUM];
	stRfGpioInfo   rxRfGpioInfo[JESD_RF_CH_NUM];
	stRfGpioInfo   orxRfGpioInfo[JESD_RF_CH_NUM];
	
	stGpioInfo txTransGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo txGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo txAntGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo rxTransGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo rxGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo rxAntGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo orxTransGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo orxGpioInfo[JESD_RF_CH_NUM];
	stGpioInfo orxAntGpioInfo[JESD_RF_CH_NUM];
}stGpioJesd;

typedef struct _tagGpioOnBoard
{
	stGpioJesd jesdGpioInfo;
	stGpioInfo triggerGpioInfo;
}stGpioOnBoard;

int32_t hw_gpio_init();

int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState);

int32_t set_jesd_all_rf_state(uint8_t nTRCh, uint8_t nState); // tx, rx, orx

int32_t set_trigger_state(uint8_t nState);

#if 0
int32_t set_tx_on();

int32_t set_tx_off();

int32_t set_rx_on();

int32_t set_rx_off();
#endif
#endif