YB_Platform/public/ecs_rfm_spu1/top/src/main.s.c

// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 SmartLogic.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : main.c
// Author        : xianfeng.du
// Created On    : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

#include "ucp_printf.h"
#include "rfm1_drv.h"
#include "ucp_heartbeat.h"
#include "ecs_rfm_spu1_top.h"
#include "msg_transfer_queue.h"
#include "log_server.h"
#include "ucp_utility.h"
#include "phy_queue_proc.h"
#include "cpri_test_mode.h"
#include "spu_shell.h"
#include "gtimer_drv.h"
#include "rfm1_gtimer2.h"
#include "ecs_rfm_spu1_oam.h"
#include "phy_para.h"
#include "hw_cpri.h"
#include "hwque.h"

#ifdef TEST_ENABLE
#include "fh_test.h"
#endif

#ifdef DDR_MONITOR
void spu_ddr_monitor()
{
    if (1 == do_read_volatile(DDR_MONITOR_ENABLE))
    {
        clear_rfm1_gtimer2_1_intcnt();
        gtimer2_int_enable(0);
        do_write(DDR_MONITOR_ENABLE, 0);
    }
    volatile uint32_t nMonitorCnt = do_read_volatile(DDR_MONITOR_CNT);
    __ucps2_synch(0);
    if (nMonitorCnt < get_rfm1_gtimer2_1_intcnt())
    {
        gtimer2_int_disable(0);
        do_write(DDR_MONITOR_CNT, 0);
    }
}
#endif

extern uint32_t     gCpriCsuDummyFlag;

int32_t main(int32_t argc, char* argv[])
{
    UCP_PRINT_EMPTY("Hello world from ECS RFM SPU1,coreId[0x%x]",  get_core_id());
    debug_write(DBG_DDR_COMMON_IDX(get_core_id(), 0), PLATFORM_BUILD_DATA);

    /* hw_debug_init  */
    int32_t core_id = get_core_id();
    int ret = 0;
    ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN);  // 推荐384，实际512
    if (0 != ret)
    {
        debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);
    }

    spu_log_client_init();

    spu_log_server_init();

    ecs_rfm_spu1_drv_init();

    ecs_rfm_spu1_msg_transfer_init();

    spu_shell_init();

    spu_shell_cpri_cmd();

    oam_msg_init();
    
    while (1)
    {
#ifdef TEST_ENABLE
		do_write(CSU_TX_ADVANCE_SAMPLE, 10000);		// 10us
		do_write(CSU_RX_TD_SAMPLE, 10000);
		
		check_test_outcome(0);
#endif
#if 0
		if (1 == do_read_volatile(0x0A4D726C))
		{
#ifdef CPRI_TIMING_7D2U_TEST
	        ecs_rfm1_build_cell(NR_SCS_30K, 1);
#endif
#ifdef CPRI_TIMING_LTE_FDD_TEST
	        ecs_rfm1_build_cell(LTE_SCS_ID, 1);
#endif
			do_write(0x0A4D726C, 2);
		}
		if (2 == do_read_volatile(0x0A4D726C))
		{
			check_phy_cell();
		}
		if (3 == do_read_volatile(0x0A4D726C))
		{
#ifdef CPRI_TIMING_7D2U_TEST
			ecs_rfm1_delete_cell(NR_SCS_30K, 0);
#endif
			
#ifdef CPRI_TIMING_LTE_FDD_TEST
			ecs_rfm1_delete_cell(LTE_SCS_ID, 0);
#endif
			do_write(0x0A4D726C, 0);
		}
		if (4 == do_read_volatile(0x0A4D726C))
		{
#ifdef CPRI_TIMING_7D2U_TEST
			ecs_rfm1_delete_cell(NR_SCS_30K, 1);
#endif
			
#ifdef CPRI_TIMING_LTE_FDD_TEST
			ecs_rfm1_delete_cell(LTE_SCS_ID, 1);
#endif
			do_write(0x0A4D726C, 0);
		}
#endif		
		
        phy_queue_polling();

#ifdef DISTRIBUTED_BS
        check_cpri();

        check_10ms_offset();
#endif
        spu_log_server_proc();
        spu_shell_task();
#ifdef DDR_MONITOR
        spu_ddr_monitor();
#endif
    }

    return 0;
}