2023-07-13 11:27:03 +08:00
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/*********************************************************************
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*
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* Filename: hw_cpri.h
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*
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* Created: 2022-05-5 05:20:34 PM
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* Last Modified: 2022-05-5 05:20:34 PM
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* Author: xinxin.li
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* Organization: Beijing Smart Logic Technology Co., Ltd.
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*
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* Description:
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*
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*
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********************************************************************/
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#ifndef __HW_CPRI_H__
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#define __HW_CPRI_H__
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#include "typedef.h"
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//#define CPRI_NOTIMING_TEST
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//#define CPRI_TIMING_TEST
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#define CPRI_TIMING_7D2U_TEST
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//#define CPRI_TIMING_LTE_FDD_TEST
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2023-07-25 11:11:08 +08:00
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#define CPRI_10G_TEST
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//#define CPRI_24G_TEST
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2023-07-13 11:27:03 +08:00
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typedef struct _tagCpriPara
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{
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uint32_t option_num;
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uint32_t core_clk;
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uint32_t pcs_core_clk;
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uint32_t cpu_clk;
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uint32_t gmii_tx_rx_clk;
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uint32_t pcs_fine_delay_clk;
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uint32_t pcs_serdes_clk;
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uint32_t serdes_data_width;
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uint32_t cpri_rate_coff;
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uint32_t line_rate;
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uint32_t valid_line_rate;
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uint32_t encode_flag; // 0:8B/10B; 1:64B/66B
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uint32_t rs_fec_flag; // RS-FEC
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uint32_t len_word;
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uint32_t len_ctrl_word;
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uint32_t aux_cnt_pos_max;
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}stCpriPara;
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typedef struct _tagCpriIntStat
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{
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int32_t cpriIntCnt;
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int32_t rxRfpIntCnt;
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int32_t txRfpIntCnt;
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int32_t alarmIntCnt;
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int32_t ddrFifoIntCnt;
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int32_t rxFifoIntCnt;
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int32_t l1ResetIntCnt;
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int32_t lofIntCnt;
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int32_t syncIntCnt;
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int32_t gmacIntCnt;
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uint32_t cpriSyncFlag;
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//uint32_t gScrRxRfpValL;
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//uint32_t gScrRxRfpValH;
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}stCpriIntStat;
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2023-07-24 09:27:15 +08:00
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void cpri_init(uint32_t option);
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2023-07-13 11:27:03 +08:00
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// cpri参数初始化
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2023-07-24 09:27:15 +08:00
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void cpri_para_init(uint32_t option);
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2023-07-13 11:27:03 +08:00
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void cpri_int_init(void);
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void isr_cpri_int(void);
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void isr_gmac_int(void);
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#endif
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