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Merge branch 'dev_ck_v2.1_EVMY_bug#1133#' into 'dev_ck_v2.1'

Browse Source 
UCP4008_SL_EVMY bug#1133#

See merge request ucp/driver/ucp4008_platform_spu!45
This commit is contained in:
Xianfeng Du 2023-10-13 01:32:05 +00:00
commit 0042b331a6
11 changed files with 491635 additions and 101 deletions
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8
public/common/driver/inc/mtimer_com.h
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@ -57,11 +57,12 @@ typedef enum _tagMTmrTID
MTMR_RFM0_TXSLOT, // 21
MTMR_RFM0_RXSLOT,
MTMR_CSU_INSERT = 24,
MTMR_JESD_RXON = 23,
MTMR_CSU_INSERT = 24, // also as MTMR_JESD_RXOFF = 24,
MTMR_TDD_OFFSET_10000 = 25,
MTMR_TDD_OFFSET_2500 = 26, // also as MTMR_JESD_RXON = 26,
MTMR_TDD_OFFSET_7500 = 27, // also as MTMR_JESD_RXOFF = 27,
MTMR_TDD_OFFSET_2500 = 26,
MTMR_TDD_OFFSET_7500 = 27,
MTMR_JESD_TXOFF = 28,
MTMR_JESD_TXON = 29,
@ -125,6 +126,7 @@ typedef struct _tagMtimerPara{
// scratch count
uint32_t tmrScrCnt;
// phy para
uint32_t frameType;
uint32_t scsId;
uint16_t runCoreId;
uint16_t reCfgFlag;

40
public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c
View File

@ -320,10 +320,8 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId)
}
// ape tmrpoints
uint8_t i = 0;
h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
__ucps2_synch(0);
debug_write((DBG_DDR_IDX_DRV_BASE+48+i), h1Pos); // 0xb7e060c0
while (32 > h1Pos)
{
apeId = 31 - h1Pos;
@ -343,9 +341,6 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId)
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
__ucps2_synch(0);
i++;
debug_write((DBG_DDR_IDX_DRV_BASE+48+i), h1Pos); // 0xb7e060c0
}
reCfgFlag = 4;
@ -454,10 +449,45 @@ void isr_ecpri_timer(void)
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_ECPRI_ID);
pMtimerInt->tmrIntCnt++;
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG);
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+2048), pMtimerInt->tmrIntCnt); // 0xb7e08000
debug_write((DBG_DDR_IDX_DRV_BASE+2048+3), tmrIntcFlag); // 0xb7e0800C
#endif
uint32_t runApe = 0;
uint32_t intApeFlag = 0;
uint8_t intApeId = 0;
runApe = do_read_volatile((&(phyPara[pMtimerPara->scsId].runCoreId)));
if (0 == runApe)
{
intApeFlag = ((tmrIntcFlag>>MTMR_INT_APE0_SLOT) & 0xFF) & (~runApe);
debug_write((DBG_DDR_IDX_DRV_BASE+48), runApe); // 0xb7e08004
debug_write((DBG_DDR_IDX_DRV_BASE+49), intApeFlag); // 0xb7e08004
volatile uint32_t h1Pos = __builtin_clz(intApeFlag); // 从高bit开始，第一个1前面的0的个数
while (32 > h1Pos)
{
intApeId = 31 - h1Pos;
if (8 <= intApeId)
{
return;
}
tFlagAddr = tmrBaseAddr+MTMR_TINTF00_REG + 6*((MTMR_INT_APE0_SLOT+intApeId)<<2);
tEventAddr = tmrBaseAddr + MTMR_TEVENT0_REG;
tEventFlag = do_read_volatile(tFlagAddr);
do_write(tEventAddr, tEventFlag);
do_write(tFlagAddr, tEventFlag); // clear int flag
do_write((tmrBaseAddr+MTMR_INTC_REG), (tmrIntcFlag & 0xFF0)); // clear int
__ucps2_synch(0);
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG);
intApeFlag = ((tmrIntcFlag>>MTMR_INT_APE0_SLOT) & 0xFF) & (~runApe);
h1Pos = __builtin_clz(intApeFlag);
}
}
if ((tmrIntcFlag & (1 << MTMR_INT_10ms))) /* tmr int */
{

115
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
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@ -177,15 +177,23 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
#endif
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerPara* pMtimerTxPara = pEcsDmLocalMgt->pMtimerPara[nTmrId+2];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
int32_t scsId = my_jesdtmr->scsId;
pMtimerPara->frameType = my_jesdtmr->frameType;
pMtimerPara->scsId = scsId;
pMtimerPara->runCoreId = (uint16_t)my_jesdtmr->runCoreId;
pMtimerPara->tddPeriod = my_jesdtmr->t_period; // us
pMtimerPara->tddSlotNum = my_jesdtmr->num_tti;
pMtimerPara->slotPeriod = my_jesdtmr->t_us;
pMtimerPara->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
pMtimerTxPara->tddPeriod = my_jesdtmr->t_period; // us
pMtimerTxPara->tddSlotNum = my_jesdtmr->num_tti;
pMtimerTxPara->slotPeriod = my_jesdtmr->t_us;
pMtimerTxPara->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
pMtimerSfn->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
if (FDD_MODE == my_jesdtmr->frameType)
{
@ -216,6 +224,13 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
}
#endif
pMtimerPara->tempL_max = pMtimerPara->tmrMsPeriod * pMtimerPara->slotPeriod / 1000 - 1;
pMtimerPara->tempM_max = pMtimerPara->tddSlotNum-1;
pMtimerPara->tempH_max = SFN_PERIOD / pMtimerPara->slotPeriod / pMtimerPara->tddSlotNum - 1;
pMtimerTxPara->tempL_max = pMtimerPara->tmrMsPeriod * pMtimerPara->slotPeriod / 1000 - 1;
pMtimerTxPara->tempM_max = pMtimerPara->tddSlotNum-1;
pMtimerTxPara->tempH_max = SFN_PERIOD / pMtimerPara->slotPeriod / pMtimerPara->tddSlotNum - 1;
enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
#ifdef PALLADIUM_TEST
flag++;
@ -444,29 +459,9 @@ void clear_jesd_tdd_offset(int32_t nTmrId)
void set_jesd_tx_slot_offset(int32_t nTmrId)
{
//EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
uint32_t tmr3Point = SFN_PERIOD - gJesdDelay.txOffset; // us
set_mtimer_tmrpoint(nTmrId, MTMR_TXSLOT_OFFSET, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_TXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
//uint32_t tempL = gCpriTimerPara.tmrMsPeriod * (tmr3Point % gCpriTimerPara.slotPeriod) / 1000;
//uint32_t addr = (uint32_t)&(phyPara[gCpriTimerPara.scsId].txSetVal);
//do_write(addr, tempL);
#if 0
// ape tmrpoints
for (int32_t i = 0; i < APE_NUM; i++)
{
int32_t tmrId = MTMR_APE0_TXSLOT + (i<<1);
set_mtimer_tmrpoint(nTmrId, tmrId, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+i));
}
// rfm0 tmrpoints
int32_t tmrId = MTMR_RFM0_TXSLOT;
set_mtimer_tmrpoint(nTmrId, tmrId, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, tmrId, MTMR_INT_RFM0_SLOT);
#endif
}
void clear_jesd_tx_slot_offset(int32_t nTmrId)
@ -476,29 +471,9 @@ void clear_jesd_tx_slot_offset(int32_t nTmrId)
void set_jesd_rx_slot_offset(int32_t nTmrId)
{
//EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
uint32_t tmr4Point = SFN_PERIOD - gJesdDelay.txOffset; //gJesdDelay.rxOffset; // // us
int32_t tmr4Point = SFN_PERIOD - gJesdDelay.txOffset; //gJesdDelay.rxOffset; // // us
set_mtimer_tmrpoint(nTmrId, MTMR_RXSLOT_OFFSET, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
//uint32_t tempL = gCpriTimerPara.tmrMsPeriod * (tmr3Point % gCpriTimerPara.slotPeriod) / 1000;
//uint32_t addr = (uint32_t)&(phyPara[gCpriTimerPara.scsId].txSetVal);
//do_write(addr, tempL);
#if 0
// ape tmrpoints
for (int32_t i = 0; i < APE_NUM; i++)
{
int32_t tmrId = MTMR_APE0_RXSLOT + (i<<1);
set_mtimer_tmrpoint(nTmrId, tmrId, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+i));
}
// rfm0 tmrpoints
int32_t tmrId = MTMR_RFM0_RXSLOT;
set_mtimer_tmrpoint(nTmrId, tmrId, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, tmrId, MTMR_INT_RFM0_SLOT);
#endif
}
void clear_jesd_rx_slot_offset(int32_t nTmrId)
{
@ -612,7 +587,6 @@ void set_jesd_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
shortcp = my_jesdtmr->num_t_dl_symb[0] + gapSymbolCnt - 1; // ul start point
//ulStartSymbol = my_jesdtmr->num_t_dl_symb + gapSymbolCnt - 1; // ul start point, 6+4-1, symbol9
if (MTIMER_JESD_RX0_ID == nTmrId)
{
/* rx */
@ -750,8 +724,8 @@ void set_jesd_rxon_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
uint32_t gapSymbolStart = LONGCP_SAM_CNT + (my_jesdtmr->num_t_dl_symb[0]-1) * SHORTCP_SAM_CNT;
uint32_t tmr26Point = (sSymbolStart + gapSymbolStart) * 1000 / pMtimerPara->tmrMsPeriod + JESD_TXRX_CHANGE_GAP;
set_mtimer_tmrpoint(nTmrId, MTMR_TDD_OFFSET_2500, tmr26Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_TDD_OFFSET_2500, MTMR_INT_TDD_OFFSET);
set_mtimer_tmrpoint(nTmrId, MTMR_JESD_RXON, tmr26Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_RXON, MTMR_INT_TDD_OFFSET);
}
void set_jesd_rxoff_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
@ -769,8 +743,8 @@ void set_jesd_rxoff_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
uint32_t tmr27Point = pMtimerPara->tddPeriod - JESD_TXRX_CHANGE_GAP;
set_mtimer_tmrpoint(nTmrId, MTMR_TDD_OFFSET_7500, tmr27Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_TDD_OFFSET_7500, MTMR_INT_TDD_OFFSET);
set_mtimer_tmrpoint(nTmrId, MTMR_CSU_INSERT, tmr27Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_CSU_INSERT, MTMR_INT_TDD_OFFSET);
}
void start_jesd_timer(int32_t nTmrId)
@ -890,7 +864,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+1), pMtimerInt->pp1sIntCnt); // 0x104
#ifdef PALLADIUM_TEST
#if 0 //def PALLADIUM_TEST
uint32_t val = 0;
for (int32_t core = 0; core < 12; core++)
{
@ -926,6 +900,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
jesd_timer_rcfg_act(nTmrId);
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
pMtimerCal->sfnCalFinished = 1;
pMtimerInt->tddOffsetIntCnt = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
}
@ -983,7 +958,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
tEventFlag = do_read_volatile(tFlagAddr);
__ucps2_synch(0);
if ((tEventFlag & ((1<<MTMR_TDD_OFFSET)|(1<<MTMR_JESD_TXOFF)|(1<<MTMR_JESD_TXON)|(1<<MTMR_TDD_OFFSET_2500)|(1<<MTMR_TDD_OFFSET_7500))) || (cEventFlag & (BIT11|BIT12)))
if ((tEventFlag & ((1<<MTMR_TDD_OFFSET)|(1<<MTMR_JESD_TXOFF)|(1<<MTMR_JESD_TXON)|(1<<MTMR_JESD_RXON)|(1<<MTMR_CSU_INSERT))) || (cEventFlag & (BIT11|BIT12)))
{
if (tEventFlag & (1<<MTMR_TDD_OFFSET)) // tdd offset int
{
@ -994,37 +969,27 @@ void jesd_tdd_callback(uint8_t nTmrId)
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+4), pMtimerInt->tddOffsetIntCnt); // 0x110
#endif
#if 1
// if (0 == do_read_volatile(CSU_STOP_CMD_ADDR))
{
// uint32_t startTick = GET_STC_CNT();
jesd_csu_start();
if ((FDD_MODE == gJesdTFMode) || (JESD_IO_CTRL == gJesdIOMode))
{
jesd_csu_rx_start();
}
// uint32_t cost = GET_STC_CNT() - startTick;
// do_write(DDR_ADDR_90, cost);
}
#endif
}
if (tEventFlag & (1<<MTMR_TDD_OFFSET_2500)) // rx on int
if (tEventFlag & (1<<MTMR_JESD_RXON)) // rx on int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET_2500));
do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET_2500)); // clear int flag
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_RXON));
do_write(tFlagAddr, (1<<MTMR_JESD_RXON)); // clear int flag
gRxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+5), gRxOnCnt); // 0x114
//RxOn();
debug_write((DBG_DDR_IDX_DRV_BASE+78), gRxOnCnt); // 0x138
set_jesd_rf_state(JESD_RF_RX, GPIO_ON);
jesd_csu_rx_start();
}
if (tEventFlag & (1<<MTMR_TDD_OFFSET_7500)) // rx off int
if (tEventFlag & (1<<MTMR_CSU_INSERT)) // rx off int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET_7500));
do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET_7500)); // clear int flag
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_CSU_INSERT));
do_write(tFlagAddr, (1<<MTMR_CSU_INSERT)); // clear int flag
gRxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), gRxOffCnt); // 0x118
//RxOff();
debug_write((DBG_DDR_IDX_DRV_BASE+79), gRxOffCnt); // 0x13C
set_jesd_rf_state(JESD_RF_RX, GPIO_OFF);
}
if (tEventFlag & (1<<MTMR_JESD_TXON)) // tx on int
@ -1033,7 +998,6 @@ void jesd_tdd_callback(uint8_t nTmrId)
do_write(tFlagAddr, (1<<MTMR_JESD_TXON)); // clear int flag
gTxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+76), gTxOnCnt); // 0x130
//TxOn();
set_jesd_rf_state(JESD_RF_TX, GPIO_ON);
//jesd_csu_start();
}
@ -1043,23 +1007,22 @@ void jesd_tdd_callback(uint8_t nTmrId)
do_write(tFlagAddr, (1<<MTMR_JESD_TXOFF)); // clear int flag
gTxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+77), gTxOffCnt); // 0x134
//TxOff();
set_jesd_rf_state(JESD_RF_TX, GPIO_OFF);
}
if (cEventFlag & BIT11)
if (cEventFlag & (1<<MTMR_CEVENT_RXEN2CSU0))
{
do_write((tmrBaseAddr+MTMR_CEVENT_REG), BIT11);
do_write(cFlagAddr, BIT11); // clear int flag
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT24)); // GPIO1B24, high
do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_RXEN2CSU0));
do_write(cFlagAddr, (1<<MTMR_CEVENT_RXEN2CSU0)); // clear int flag
//do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT24)); // GPIO1B24, high
gRxCsuOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+8), gRxCsuOnCnt); // 0x120
debug_write((DBG_DDR_IDX_DRV_BASE+64+9), GET_STC_CNT()); // 0x124
}
if (cEventFlag & BIT12)
if (cEventFlag & (1<<MTMR_CEVENT_RXEN2CSU1))
{
do_write((tmrBaseAddr+MTMR_CEVENT_REG), BIT12);
do_write(cFlagAddr, BIT12); // clear int flag
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT24)))); // GPIO1B24, high
do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_RXEN2CSU1));
do_write(cFlagAddr, (1<<MTMR_CEVENT_RXEN2CSU1)); // clear int flag
//do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT24)))); // GPIO1B24, high
gRxCsuOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+10), gRxCsuOffCnt); // 0x128
debug_write((DBG_DDR_IDX_DRV_BASE+64+11), GET_STC_CNT()); // 0x12C

12
public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c
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@ -83,12 +83,6 @@ void ecs_rfm1_drv_init(void)
#endif
#endif
hw_gpio_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
ecs_hw_que_init(apeId);
ecs_hw_que_init_noirq(apeId, apeId);
ecs_msg_que_init(apeId);
@ -110,6 +104,12 @@ void ecs_rfm1_drv_init(void)
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
hw_gpio_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
rfm_stc_init();
#ifdef PALLADIUM_TEST
flag++;

4
public/ecs_rfm_spu1/top/src/main.s.c
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@ -106,8 +106,8 @@ int32_t main(int32_t argc, char* argv[])
check_10ms_offset();
}
#ifdef TEST_ENABLE
do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
do_write(CSU_RX_TD_SAMPLE, 10000);
//do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
//do_write(CSU_RX_TD_SAMPLE, 10000);
check_test_outcome(0);
#endif

7
public/ecs_rfm_spu1/top/src/phy_init.s.c
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@ -132,12 +132,13 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
if (NR_SCS_30K == scsId)
{
my_cpritmr.t_period = 5000;
my_cpritmr.frameType = TDD_MODE;
my_cpritmr.t_period = 5000; //2500; //
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti = 10; //5; //
my_cpritmr.num_tti_per_sfn = 20;
my_cpritmr.num_t_dl[0] = 7; // dl slot num
my_cpritmr.num_t_dl[0] = 7; //1; // // dl slot num
my_cpritmr.num_t_dl_symb[0] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 4; // ul symbol num
my_cpritmr.num_ants[0] = 4;

122753
public/test/testcases/case44/fronthaul/DATA/265_slot0_jesd/dl_ant_post7.dat Normal file
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123009
public/test/testcases/case44/fronthaul/DATA/265_slot0_jesd/dl_ant_pre7.dat Normal file
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8
public/test/testcases/case44/fronthaul/src/jesd_test_case44.s.c
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@ -58,7 +58,8 @@ int32_t fh_csu_test_init(void)
{
if (JESD_CSU_CTRL == gJesdIOMode)
{
jesd_csu_init_nr_7ds2u();
//jesd_csu_init_nr_7ds2u();
jesd_csu_init_nr_7d2u_slot0();
}
else if (JESD_IO_CTRL == gJesdIOMode)
{
@ -96,6 +97,11 @@ void jesd_tx_data_init()
uint32_t b7SamCnt = SHORTCP_SAM_CNT*7;
uint32_t cpyCnt = 0;
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
// valid data
// IQ data
samByteCnt = 4;

122757
public/test/testcases/case44/fronthaul/src/jesd_test_case44_antdata_post7.s.c
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123013
public/test/testcases/case44/fronthaul/src/jesd_test_case44_antdata_pre7.s.c
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