diff --git a/public/ape_spu/osp/inc/osp_cfgfile.h b/public/ape_spu/osp/inc/osp_cfgfile.h index c4661e1..663e0c4 100644 --- a/public/ape_spu/osp/inc/osp_cfgfile.h +++ b/public/ape_spu/osp/inc/osp_cfgfile.h @@ -3,7 +3,7 @@ #include "osp_type_def.h" -#define APE_CFG_FILE_NAME_LEN (64) +#define APE_CFG_FILE_NAME_LEN (32) //(64) /* 为节省内存开销，文件名长度由64->32字节 */ #define APE_CFG_FILE_NUM (64) #define OSP_CFG_FLAG_START (0xB0B0B0B0) /* 默认Flag，表示等待读配置文件 */ diff --git a/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c b/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c index 3f260c9..281f1d7 100644 --- a/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c +++ b/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c @@ -1,3611 +1,3613 @@ -#include "cpri_driver.h" - -#include "ucp_param.h" -#include "ucp_cpri.h" -#include "ucp_js_ctrl.h" -#include "ucp_js_subcrg.h" -#include "ucp_pet_ctrl.h" -#include "ucp_pma.h" -#include "dw_gmac.h" -#include "hw_cpri.h" -#include "cpri_csu.h" -#include "ucp_drv_common.h" -#include "ucp_printf.h" -#include "ucp_utility.h" -#include "mem_sections.h" -#include "ucp_sfr_c.h" -#include "phy_para.h" - -//#define CPRI_SPEED 8//option 8 - -//8 option8 10137.6Mbit/s 64B/66B -//7 option7 9830.4Mbit/s 8B/10B -//10 option10 24330.24Mbit/s 64B/66B -extern DDR0 uint32_t pma_fw[16384*2]; -//extern volatile int32_t gCpriSyncIntCnt; -extern volatile uint32_t gVendorFlag; - -uint32_t PLLSEL_temp = 0; -//切换xtal_clk时钟 -void Clk_To_XTAL() -{ - do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x121000); //暂停输出core时钟 - PLLSEL_temp = do_read_volatile(&JECS_CRG_PLLSEL); - do_write(&JECS_CRG_PLLSEL, (PLLSEL_temp&0xF87FFFF0)|(BIT23)|(BIT3));//ecs pll选择xtal_clk时钟输入并输出给cpri core div - do_write(&ESP_CLK_CFG_REG, 0x121000); //暂停apb时钟输出 - do_write(&CLK_CTL_REG1, ((do_read_volatile(&CLK_CTL_REG1))&(~BIT2))); //切换PLL2时钟源为xtal_clk时钟 - do_write(&ESP_CLK_CFG_REG, 0x521000); //使能apb时钟输出 - do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x520000); //使能输出core时钟 - -} - -//恢复正常 -void Clk_To_Normal() -{ - - do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x121000); //暂停输出core时钟 - do_write(&JECS_CRG_PLLSEL, PLLSEL_temp); //切换CORE时钟源为正常的PMA TX给cpri core div - do_write(&ESP_CLK_CFG_REG, 0x121000); //暂停apb时钟输出 - do_write(&CLK_CTL_REG1, do_read_volatile(&CLK_CTL_REG1) | BIT2);//切换PLL2时钟为PLL2输出时钟 - do_write(&ESP_CLK_CFG_REG, 0x524000); //使能apb时钟输出 - do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x520000); //使能输出core时钟 - -} -/***************************CPRI*************************/ -void Init_cpri_clk(uint32_t cpri_speed_sel) -{ - if(cpri_speed_sel <= 7)//8B/10B - { - //JECS_CRG_PLLSEL |= BIT24;//IP REC MODE - do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | BIT24); - //cdr div clk output divided by 4 - JECS_CRG_CPRI_CDR_CLK_CTRL = 0x523000; - //u_cpri_core_div div cfg - JECS_CRG_CPRI_CORE_CLK_CTRL = 0x521000; - //u_cpri_pcs_core_div div cfg - JECS_CRG_CPRI_PCS_CORE_CLK_CTRL = 0x520000; - } - else //64B/66B - { - // JECS_CRG_PLLSEL |= (BIT26|BIT24);//IP REC MODE - do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT26|BIT24)); - //cdr div clk output divided by 11 - do_write(&JECS_CRG_CPRI_CDR_CLK_CTRL, 0x52a000); - //u_cpri_core_div div cfg - //JECS_CRG_CPRI_CORE_CLK_CTRL = 0x520000; - do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x520000); - //u_cpri_pcs_core_div div cfg - // JECS_CRG_CPRI_PCS_CORE_CLK_CTRL = 0x521000; - do_write(&JECS_CRG_CPRI_PCS_CORE_CLK_CTRL, 0x521000); - } - ucp_nop(400); - //JECS_CRG_PLLSEL &= (~BIT4); //？？？ - do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) &(~BIT4)); - ucp_nop(400); - //(*((volatile uint32_t *)(JS_CRG_BASE + 4*11))) = 0x520000; - //JS_CRG_SAM3_CLK_CTRL = 0x520000; - do_write(&JS_CRG_SAM3_CLK_CTRL, 0x520000); - ucp_nop(400); -} - -#if 0 -void Init_config_cpri(uint32_t cpri_speed_sel) -{ - switch(cpri_speed_sel) - { - case 7: - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - CPRI_FRAME_RX_CFG = 0x10|BIT8;//bit9:Default 150 HF=10ms mode & bit0:7;cfg_frm_rate set & bit8:enable Extract Control AxC data to external port - CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 - CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 - CPRI_FRAME_TX_SCRAMBLER = 0x61cd; - break; - - case 8: - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - CPRI_FRAME_RX_CFG = 0x14|BIT8;//bit9:short frame mode & bit0:7;cfg_frm_rate set & bit8:enable Extract Control AxC data to external port - CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 - CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 - CPRI_FRAME_TX_SCRAMBLER = 0x0; - break; - - case 10: - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - CPRI_FRAME_RX_CFG = 0x30|BIT8;//bit9:short frame mode & bit0:7;cfg_frm_rate set & bit8:enable Extract Control AxC data to external port - CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 - CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 - CPRI_FRAME_TX_SCRAMBLER = 0x0; - break; - - default://option 8 - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - CPRI_FRAME_RX_CFG = 0x14|BIT8;//0x70 - CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 - CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 - CPRI_FRAME_TX_SCRAMBLER = 0x0; - break; - } -/***************move to finish map config - CPRI_MAP_CFG = BIT4|BIT0;//enable map Tx and Rx - CPRI_MAP_TOGGLE = BIT4|BIT0;//Activate config maps - ************************/ - CPRI_FRAME_TX_BFN_INIT = 0x10000;//initial TX BFN value 0,bit16：load BFN;bit11:0,BFN value - - CPRI_FRAME_TX_CFG = BIT2|BIT1;//Default 150 HF=10ms mode&master mode&tx enable&enable insertion of ctrl AxC - -} - -/***********************pcs******************************/ - -void Init_config_pcs(uint32_t cpri_speed_sel) -{ - //cancell cpri's rst - JECS_CRG_CPRI0_RST_CTRL |= BIT24; - JECS_CRG_CPRI1_RST_CTRL |= BIT24; - JECS_CRG_CPRI2_RST_CTRL |= BIT24; - JECS_CRG_CPRI3_RST_CTRL |= BIT24; - JECS_CRG_CPRI4_RST_CTRL |= BIT24; - JECS_CRG_CPRI5_RST_CTRL |= BIT24; - JECS_CRG_CPRI6_RST_CTRL |= BIT24; - ECPRI_RST_CFG_REG |= BIT24; - AUX_CTRL_REG &= (~BIT2); - //delay_us(1); - //ucp_nop(400); - - switch(cpri_speed_sel) - { - case 7: - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - - CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 - CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection - CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 - - CPRI_PCS_ADDR_CFG = 0x1C;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x1;//DATA_CFG - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xB8;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x14<<7|BIT5|BIT14;//DATA_CFG cpri_enable - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xBC;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x14<<7|BIT5|BIT14;//DATA_CFG cpri_enable - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR - CPRI_PCS_DATA_TX_CFG = 0; // RS-FEC disable - CPRI_PCS_CTRL_CFG = 0x2;//WR -// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x1E<<1;//bit8:1： Tx Buffer initial fill =8 -// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 -// -// CPRI_PCS_ADDR_CFG = 0xC4;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x1E<<1;//bit8:1： Rx Buffer initial fill =5 -// CPRI_PCS_CTRL_CFG = 0X2;//WR - break; - - case 8: - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - - CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 - CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection - CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 - - CPRI_PCS_ADDR_CFG = 0x1C;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x0;//DATA_CFG - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xB8;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xBC;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT15;//DATA_CFG with scramble enable - //CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT15;//DATA_CFG Bypass scrambler in 64b/66b decoder - CPRI_PCS_CTRL_CFG = 0x2;//WR - -// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x8<<1;//bit8:1： Tx Buffer initial fill =8 -// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 -#if 1 - CPRI_PCS_ADDR_CFG = 0xC4;//ADDR, CFG_RX - CPRI_PCS_DATA_TX_CFG = BIT10|(3<<1);//DATA_CFG serdes_loopback, bit8:1： Rx Buffer initial fill =3 - CPRI_PCS_CTRL_CFG = 0x2;//WR -#endif - CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR - CPRI_PCS_DATA_TX_CFG = (2<<1); // RS-FEC enable - CPRI_PCS_CTRL_CFG = 0x2;//WR - - break; - - case 10: - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - - CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 - CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection - CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 - - CPRI_PCS_ADDR_CFG = 0x1C;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x0;//DATA_CFG - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xB8;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xBC;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG with scramble enable - //CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT15;//DATA_CFG Bypass scrambler in 64b/66b decoder - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR - CPRI_PCS_DATA_TX_CFG = (2<<1); // RS-FEC enable - CPRI_PCS_CTRL_CFG = 0x2;//WR - -// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x8<<1;//bit8:1： Tx Buffer initial fill =8 -// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 -// -// CPRI_PCS_ADDR_CFG = 0xC4;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x5<<1;//bit8:1： Rx Buffer initial fill =5 -// CPRI_PCS_CTRL_CFG = 0X2;//WR - break; - default://option 8 - CPRI_PCS_64B66B_CFG = 0x0;//0x40 - - CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 - CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection - CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 - - CPRI_PCS_ADDR_CFG = 0x1C;//ADDR - CPRI_PCS_DATA_TX_CFG = 0x0;//DATA_CFG - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xB8;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable - CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable reser tx - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = 0xBC;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG with scramble enable - CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT0;//DATA_CFG Bypass scrambler in 64b/66b decoder - CPRI_PCS_CTRL_CFG = 0x2;//WR - - CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR - CPRI_PCS_DATA_TX_CFG = (2<<1); // RS-FEC enable - CPRI_PCS_CTRL_CFG = 0x2;//WR - -// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR -// CPRI_PCS_DATA_TX_CFG = 0x8<<1;//bit8:1： Tx Buffer initial fill =8 -// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 -// - CPRI_PCS_ADDR_CFG = 0xC4;//ADDR - CPRI_PCS_DATA_TX_CFG = BIT10|(3<<1);//bit8:1： Rx Buffer initial fill =5 - CPRI_PCS_CTRL_CFG = 0X2;//WR - - } -#if 0 - UINT32 PCS_status; - - /**********配置PCS寄存器REG_RW_GENERAL_TX************/ - CPRI_PCS_ADDR_CFG = 0xB8;//ADDR - CPRI_PCS_DATA_TX_CFG &= 0xFFFE;//bit0:normal operate - CPRI_PCS_CTRL_CFG = 0x2;//WR - - /**********配置PCS寄存器REG_RW_GENERAL_RX************/ - CPRI_PCS_ADDR_CFG = 0xBC;//ADDR - CPRI_PCS_DATA_TX_CFG &= 0xFFFE;//bit0:normal operate - CPRI_PCS_CTRL_CFG = 0x2;//WR - - /**********读取PCS寄存器PCS_STATUS_2************/ - CPRI_PCS_ADDR_CFG = 0x20;//ADDR - CPRI_PCS_CTRL_CFG = 0x1;//Read - PCS_status = CPRI_PCS_DATA_RX_STAT; - while((PCS_status & (BIT10|BIT11)) != 0);//check no fault on Tx and Rx -#endif -// UCP_PRINT_LOG("PCS REG INIT DONE!\r\n"); -} -#endif -/**********************cpri_pma***********************/ - -void init_cpri_pma_rst(void){ -#if 0 - //cancell jecs pma rst - JECS_CRG_PMA16_RST_CTRL |= BIT24; - JECS_CRG_PMA0_RST_CTRL |= BIT24; - JECS_CRG_PMA1_RST_CTRL |= BIT24; - JECS_CRG_PMA2_RST_CTRL |= BIT24; - JECS_CRG_PMA3_RST_CTRL |= BIT24; - JECS_CRG_PMA8_RST_CTRL |= BIT24; - JECS_CRG_PMA9_RST_CTRL |= BIT24; - JECS_CRG_PMA10_RST_CTRL |= BIT24; - JECS_CRG_PMA11_RST_CTRL |= BIT24; - JECS_CRG_PMA12_RST_CTRL |= BIT24; - JECS_CRG_PMA13_RST_CTRL |= BIT24; - JECS_CRG_PMA14_RST_CTRL |= BIT24; - JECS_CRG_PMA15_RST_CTRL |= BIT24; - //cancell pet pma rst - PET_EQ0_RST_CFG |= BIT24; - PET_EQ1_RST_CFG |= BIT24; - PET_EQ2_RST_CFG |= BIT24; - PET_EQ3_RST_CFG |= BIT24; - PET_PAMRX0_RST_CFG |= BIT24; - PET_PAMRX1_RST_CFG |= BIT24; - PET_PAMRX2_RST_CFG |= BIT24; - PET_PAMRX3_RST_CFG |= BIT24; - PET_RX0_RST_CFG |= BIT24; - PET_RX1_RST_CFG |= BIT24; - PET_RX2_RST_CFG |= BIT24; - PET_RX3_RST_CFG |= BIT24; - PET_TX0_RST_CFG |= BIT24; - PET_TX1_RST_CFG |= BIT24; - PET_TX2_RST_CFG |= BIT24; - PET_TX3_RST_CFG |= BIT24; - PET_PWR_RST_CFG |= BIT24; -#endif - do_write(&JECS_CRG_PMA16_RST_CTRL, do_read_volatile(&JECS_CRG_PMA16_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA0_RST_CTRL, do_read_volatile(&JECS_CRG_PMA0_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA1_RST_CTRL, do_read_volatile(&JECS_CRG_PMA1_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA2_RST_CTRL, do_read_volatile(&JECS_CRG_PMA2_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA3_RST_CTRL, do_read_volatile(&JECS_CRG_PMA3_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA8_RST_CTRL, do_read_volatile(&JECS_CRG_PMA8_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA9_RST_CTRL, do_read_volatile(&JECS_CRG_PMA9_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA10_RST_CTRL, do_read_volatile(&JECS_CRG_PMA10_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA11_RST_CTRL, do_read_volatile(&JECS_CRG_PMA11_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA12_RST_CTRL, do_read_volatile(&JECS_CRG_PMA12_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA13_RST_CTRL, do_read_volatile(&JECS_CRG_PMA13_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA14_RST_CTRL, do_read_volatile(&JECS_CRG_PMA14_RST_CTRL) | BIT24); - do_write(&JECS_CRG_PMA15_RST_CTRL, do_read_volatile(&JECS_CRG_PMA15_RST_CTRL) | BIT24); - do_write(&PET_EQ0_RST_CFG, do_read_volatile(&PET_EQ0_RST_CFG) | BIT24); - do_write(&PET_EQ1_RST_CFG, do_read_volatile(&PET_EQ1_RST_CFG) | BIT24); - do_write(&PET_EQ2_RST_CFG, do_read_volatile(&PET_EQ2_RST_CFG) | BIT24); - do_write(&PET_EQ3_RST_CFG, do_read_volatile(&PET_EQ3_RST_CFG) | BIT24); - do_write(&PET_PAMRX0_RST_CFG, do_read_volatile(&PET_PAMRX0_RST_CFG) | BIT24); - do_write(&PET_PAMRX1_RST_CFG, do_read_volatile(&PET_PAMRX1_RST_CFG) | BIT24); - do_write(&PET_PAMRX2_RST_CFG, do_read_volatile(&PET_PAMRX2_RST_CFG) | BIT24); - do_write(&PET_PAMRX3_RST_CFG, do_read_volatile(&PET_PAMRX3_RST_CFG) | BIT24); - do_write(&PET_RX0_RST_CFG, do_read_volatile(&PET_RX0_RST_CFG) | BIT24); - do_write(&PET_RX1_RST_CFG, do_read_volatile(&PET_RX1_RST_CFG) | BIT24); - do_write(&PET_RX2_RST_CFG, do_read_volatile(&PET_RX2_RST_CFG) | BIT24); - do_write(&PET_RX3_RST_CFG, do_read_volatile(&PET_RX3_RST_CFG) | BIT24); - do_write(&PET_TX0_RST_CFG, do_read_volatile(&PET_TX0_RST_CFG) | BIT24); - do_write(&PET_TX1_RST_CFG, do_read_volatile(&PET_TX1_RST_CFG) | BIT24); - do_write(&PET_TX2_RST_CFG, do_read_volatile(&PET_TX2_RST_CFG) | BIT24); - do_write(&PET_TX3_RST_CFG, do_read_volatile(&PET_TX3_RST_CFG) | BIT24); - do_write(&PET_PWR_RST_CFG, do_read_volatile(&PET_PWR_RST_CFG) | BIT24); -} - -DDR0 uint32_t ate_tx_eq_pre[22] = {0, 0, 0, 0, 0, 8, 12, 10, 12, 16, 0, 0, 0, 0, 0, 0, 8, 8, 8, 10, 12, 0}; -DDR0 uint32_t ate_tx_eq_post[22] = {24,16,20,12, 0, 0, 0, 18, 12, 0, 32, 16, 12, 16, 8, 0, 0, 0, 12, 10, 0, 24}; -DDR0 uint32_t ate_tx_eq_main[22] = {18,20,19,21,24,22, 21, 17, 18, 20, 16, 14, 15, 14,16,18,16,16, 13, 13, 15, 12}; -void init_pma_commonconfig(uint32_t pma_sel,uint32_t cpri_speed_sel) -{ - uint32_t m=1; - uint32_t n=0; - uint32_t t=1; - uint32_t ate_ref_range = 0; - uint32_t ate_ref_clk_div2_en = 0; - uint32_t ate_ref_raw_clk_div2_en = 0; - uint32_t ate_ref_clk_mplla_div = 0; - uint32_t ate_lane_ref_sel = 0; - uint32_t ate_mplla_fb_clk_div4_en = 0; - uint32_t ate_mplla_multiplier = 0; - uint32_t ate_mplla_tx_clk_div = 0; - uint32_t ate_mplla_word_clk_div = 0; - uint32_t ate_mplla_ssc_en = 0; - uint32_t ate_mplla_ssc_up_spread = 0; - uint32_t ate_mplla_ssc_peak = 0; - uint32_t ate_mplla_ssc_step_size = 0; - uint32_t ate_mplla_frac_en = 0; - uint32_t ate_mplla_frac_quot = 0; - uint32_t ate_mplla_frac_den = 0; - uint32_t ate_mplla_frac_rem = 0; - uint32_t ate_refa_lane_clk_en = 0; - uint32_t ate_bs_rx_level = 0; - uint32_t ate_bs_tx_lowswing = 0; - uint32_t ate_bs_rx_bigswing = 0; - uint32_t ate_mplla_init_cal_disable = 0; - uint32_t ate_refa_dig_clk_sel = 0; - uint32_t ate_ref_dco_bypass = 0; - uint32_t ate_refa_dco_ld_val = 0; - uint32_t ate_ref_dco_target = 0; - uint32_t ate_ref_dco_dig_range = 0; - uint32_t ate_mplla_bw_threshold = 0; - uint32_t ate_mplla_bw_low = 0; - uint32_t ate_mplla_bw_high = 0; - uint32_t ate_mplla_ctl_buf_bypass = 0; - uint32_t ate_mplla_short_lock_en = 0; - uint32_t ate_rx_term_offset = 0; - uint32_t ate_txdn_term_offset = 0; - uint32_t ate_txup_term_offset = 0; - uint32_t ate_sup_misc = 0; - uint32_t ate_rx_vref_ctrl = 0; - uint32_t ate_rx_ref_ld_val = 0; - uint32_t ate_rx_vco_ld_val = 0; - uint32_t ate_rx_cdr_ppm_max = 0; - //lane - uint32_t ate_tx_misc = 0; - uint32_t ate_tx_dcc_ctrl_diff_range = 0; - uint32_t ate_tx_dcc_ctrl_cm_range = 0; - uint32_t ate_tx_width = 0; - uint32_t ate_tx_ropll_cp_ctl_intg = 0; - uint32_t ate_tx_ropll_cp_ctl_prop = 0; - uint32_t ate_tx_ropll_rc_filter = 0; - uint32_t ate_tx_ropll_v2i_mode = 0; - uint32_t ate_tx_ropll_vco_low_freq = 0; - uint32_t ate_tx_ropll_postdiv = 0; - uint32_t ate_tx_rate = 0; - uint32_t ate_tx_ropll_div16p5_clk_en = 0; - uint32_t ate_tx_ropll_125mhz_clk_en = 0; - uint32_t ate_tx_term_ctrl = 0; - uint32_t ate_tx_dly_cal_en = 0; - uint32_t ate_tx_pll_word_clk_freq = 0; - uint32_t ate_tx_dig_ropll_div_clk_sel = 0; - uint32_t ate_tx_dual_cntx_en = 0; - uint32_t ate_tx_ropll_bypass = 0; - uint32_t ate_tx_ropll_refdiv = 0; - uint32_t ate_tx_ropll_refsel = 0; - uint32_t ate_tx_ropll_fbdiv = 0; - uint32_t ate_tx_ropll_div_clk_en = 0; - uint32_t ate_tx_ropll_out_div = 0; - uint32_t ate_tx_ropll_word_clk_div_sel= 0; - uint32_t txX_ropll_word_clk_div_lte = 0; - uint32_t ate_tx_fastedge_en = 0; -// uint32_t ate_tx_eq_pre = 0; -// uint32_t ate_tx_eq_post = 0; -// uint32_t ate_tx_eq_main = 0; - uint32_t ate_tx_align_wide_xfer_en = 0; - uint32_t ate_rx_eq_att_lvl = 0; - uint32_t ate_rx_eq_ctle_boost = 0; - uint32_t ate_rx_eq_ctle_pole = 0; - uint32_t ate_rx_eq_afe_rate = 0; - uint32_t ate_rx_eq_vga_gain = 0; - uint32_t ate_rx_eq_afe_config = 0; - uint32_t ate_rx_eq_dfe_tap1 = 0; - uint32_t ate_rx_eq_dfe_tap2 = 0; - uint32_t ate_rx_delta_iq = 0; - uint32_t ate_rx_cdr_vco_config = 0; - uint32_t ate_rx_dcc_ctrl_diff_range = 0; - uint32_t ate_rx_dcc_ctrl_cm_range = 0; - uint32_t ate_rx_sigdet_lf_threshold = 0; - uint32_t ate_rx_sigdet_hf_threshold = 0; - uint32_t ate_rx_misc = 0; - uint32_t ate_rx_term_ctrl = 0; - uint32_t ate_rx_width = 0; - uint32_t ate_rx_dig_div_clk_sel = 0; - uint32_t ate_rx_div_clk_en = 0; - uint32_t ate_rx_div_clk_sel = 0; - uint32_t ate_rx_rate = 0; - uint32_t ate_rx_dfe_bypass = 0; - uint32_t ate_rx_offcan_cont = 0; - uint32_t ate_rx_adapt_cont = 0; - uint32_t ate_rx_eq_dfe_float_en = 0; - uint32_t ate_rx_div16p5_clk_en = 0; - uint32_t ate_rx_125mhz_clk_en = 0; - uint32_t ate_rx_cdr_ssc_en = 0; - uint32_t ate_rx_sigdet_hf_en = 0; - uint32_t ate_rx_sigdet_lfps_filter_en = 0; - uint32_t ate_rx_term_acdc = 0; - uint32_t ate_rx_adapt_sel = 0; - uint32_t ate_rx_adapt_mode = 0; - uint32_t ate_rx_adapt_en = 0; - - uint32_t ate_ref_clk_mpllb_div = 0; - uint32_t ate_mpllb_fb_clk_div4_en = 0; - uint32_t ate_mpllb_multiplier = 0; - uint32_t ate_mpllb_tx_clk_div = 0; - uint32_t ate_mpllb_word_clk_div = 0; - uint32_t ate_mpllb_ssc_en = 0; - uint32_t ate_mpllb_ssc_up_spread = 0; - uint32_t ate_mpllb_ssc_peak = 0; - uint32_t ate_mpllb_ssc_step_size = 0; - uint32_t ate_mpllb_frac_en = 0; - uint32_t ate_mpllb_frac_quot = 0; - uint32_t ate_mpllb_frac_den = 0; - uint32_t ate_mpllb_frac_rem = 0; - uint32_t ate_refb_lane_clk_en = 0; - uint32_t ate_mpllb_init_cal_disable = 0; - uint32_t ate_refb_dig_clk_sel = 0; - uint32_t ate_refb_dco_ld_val = 0; - uint32_t ate_mpllb_bw_high = 0; - uint32_t ate_mpllb_bw_low = 0; - uint32_t ate_mpllb_bw_threshold = 0; - uint32_t ate_mpllb_ctl_buf_bypass = 0; - uint32_t ate_mpllb_short_lock_en = 0; - - //const - uint32_t ate_mplla_force_en = 0;// - uint32_t ate_mpllb_force_en = 0;// - uint32_t ate_pcs_pwr_stable = 1;// - uint32_t ate_pg_mode_en = 0;// - uint32_t ate_pg_reset = 0;// - uint32_t ate_pma_pwr_stable = 1;// - uint32_t ate_refa_clk_en = 1;// - uint32_t ate_refb_clk_en = 0;// - uint32_t ate_ref_repeat_clk_en = 1;// - uint32_t ate_rx_pstate = 2;// - uint32_t ate_rx_invert = 0;// - uint32_t ate_rx_lpd = 0;// - uint32_t ate_rx_term_en = 1;// - uint32_t ate_tx_pstate = 2;// - uint32_t ate_tx_clk_rdy = 1;// - uint32_t ate_tx_invert = 0;// - uint32_t ate_tx_lpd = 0;// - uint32_t ate_tx_mpll_en = 1;// - -#if 0 - if(cpri_speed_sel == 2){ - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 1 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 17 ; - ate_rx_vco_ld_val = 1360; - ate_rx_cdr_ppm_max = 18 ; - //lane - ate_tx_misc = 128 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 3 ; - ate_tx_ropll_cp_ctl_intg = 91 ; - ate_tx_ropll_cp_ctl_prop = 91 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 3 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 4 ; - ate_tx_ropll_div16p5_clk_en = 0 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 0 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 9 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 16 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 3 ; - txX_ropll_word_clk_div_lte = 3 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 12 ; - ate_rx_eq_ctle_pole = 0 ; - ate_rx_eq_afe_rate = 7 ; - ate_rx_eq_vga_gain = 20 ; - ate_rx_eq_afe_config = 1300; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 1027; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 128 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 3 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - //ate_rx_rate = 3 ; - ate_rx_rate = 4 ;//different with pdf - ate_rx_dfe_bypass = 1 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 0 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 0 ; - ate_rx_adapt_en = 0 ; - } - if(cpri_speed_sel == 3){ - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 1 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 17 ; - ate_rx_vco_ld_val = 1360; - ate_rx_cdr_ppm_max = 18 ; - //lane - ate_tx_misc = 128 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 3 ; - ate_tx_ropll_cp_ctl_intg = 91 ; - ate_tx_ropll_cp_ctl_prop = 91 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 3 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 3 ; - ate_tx_ropll_div16p5_clk_en = 0 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - //ate_tx_pll_word_clk_freq = A ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 9 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 16 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 3 ; - txX_ropll_word_clk_div_lte = 3 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 12 ; - ate_rx_eq_ctle_pole = 0 ; - ate_rx_eq_afe_rate = 7 ; - ate_rx_eq_vga_gain = 20 ; - ate_rx_eq_afe_config = 1300; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 1027; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 128 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 3 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 3 ; - ate_rx_dfe_bypass = 1 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 0 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 0 ; - ate_rx_adapt_en = 0 ; - } - if(cpri_speed_sel == 4){ - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 1 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 14 ; - ate_rx_vco_ld_val = 1400; - ate_rx_cdr_ppm_max = 19 ; - //lane - ate_tx_misc = 128 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 3 ; - ate_tx_ropll_cp_ctl_intg = 105 ; - ate_tx_ropll_cp_ctl_prop = 99 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 2 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 3 ; - ate_tx_ropll_div16p5_clk_en = 0 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 9 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 20 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 3 ; - txX_ropll_word_clk_div_lte = 3 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 12 ; - ate_rx_eq_ctle_pole = 0 ; - ate_rx_eq_afe_rate = 7 ; - ate_rx_eq_vga_gain = 20 ; - ate_rx_eq_afe_config = 1300 ; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 34 ; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 128 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 3 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 3 ; - ate_rx_dfe_bypass = 1 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 0 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 0 ; - ate_rx_adapt_en = 0 ; - } - if(cpri_speed_sel == 5){ - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 1 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 17 ; - ate_rx_vco_ld_val = 1360; - ate_rx_cdr_ppm_max = 18 ; - //lane - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 3 ; - ate_tx_ropll_cp_ctl_intg = 91 ; - ate_tx_ropll_cp_ctl_prop = 91 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 3 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 2 ; - ate_tx_ropll_div16p5_clk_en = 0 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 4 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 9 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 16 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 3 ; - txX_ropll_word_clk_div_lte = 3 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 12 ; - ate_rx_eq_ctle_pole = 1 ; - ate_rx_eq_afe_rate = 6 ; - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = 1300 ; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 1027 ; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 3 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 2 ; - ate_rx_dfe_bypass = 1 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 0 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 0 ; - ate_rx_adapt_en = 0 ; - } - if(cpri_speed_sel == 6){ - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 1 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 14 ; - ate_rx_vco_ld_val = 1400; - ate_rx_cdr_ppm_max = 19 ; - //lane - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 3 ; - ate_tx_ropll_cp_ctl_intg = 105 ; - ate_tx_ropll_cp_ctl_prop = 99 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 2 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 2 ; - ate_tx_ropll_div16p5_clk_en = 1 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - //ate_tx_pll_word_clk_freq = NA ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 9 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 20 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 3 ; - txX_ropll_word_clk_div_lte = 3 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 12 ; - ate_rx_eq_ctle_pole = 1 ; - ate_rx_eq_afe_rate = 6 ; - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = 1300; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 34 ; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 3 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 2 ; - ate_rx_dfe_bypass = 1 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 0 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 0 ; - ate_rx_adapt_en = 0 ; - } - if(cpri_speed_sel == 7){ - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 1 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 17 ; - ate_rx_vco_ld_val = 1360; - ate_rx_cdr_ppm_max = 18 ; - //lane - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 3 ; - ate_tx_ropll_cp_ctl_intg = 91 ; - ate_tx_ropll_cp_ctl_prop = 91 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 3 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 1 ; - ate_tx_ropll_div16p5_clk_en = 1 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 6 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 9 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 16 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 3 ; - txX_ropll_word_clk_div_lte = 3 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 16 ; - ate_rx_eq_ctle_pole = 1 ; - ate_rx_eq_afe_rate = 5 ; - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = 332 ; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 1027; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 3 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 1 ; - ate_rx_dfe_bypass = 0 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 0 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 4 ; - ate_rx_adapt_en = 1 ; - } - if(cpri_speed_sel == 11){ - ate_ref_range = 4 ;//option7A - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 2 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 21 ; - ate_rx_vco_ld_val = 1386; - ate_rx_cdr_ppm_max = 18 ; - //lane - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 4 ; - ate_tx_ropll_cp_ctl_intg = 84 ; - ate_tx_ropll_cp_ctl_prop = 97 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 3 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 1 ; - ate_tx_ropll_div16p5_clk_en = 1 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 6 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 15 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 22 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 2 ; - txX_ropll_word_clk_div_lte = 2 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 16 ; - ate_rx_eq_ctle_pole = 1 ; - ate_rx_eq_afe_rate = 5 ; - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = 332 ; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 1027; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 4 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 1 ; - ate_rx_dfe_bypass = 0 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 1 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 4 ; - ate_rx_adapt_en = 1 ; - } - #endif - - if(cpri_speed_sel == 8) - { - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 2 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599 ; - ate_mplla_bw_high = 1599 ; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 17 ; - ate_rx_vco_ld_val = 1403 ; - ate_rx_cdr_ppm_max = 19 ; - //lane - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 4 ; - ate_tx_ropll_cp_ctl_intg = 79 ; - ate_tx_ropll_cp_ctl_prop = 79 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 2 ; - ate_tx_ropll_postdiv = 1 ; - ate_tx_rate = 1 ; - ate_tx_ropll_div16p5_clk_en = 1 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 6 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 6 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 11 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 2 ; - txX_ropll_word_clk_div_lte = 2 ; - ate_tx_fastedge_en = 0 ; - // ate_tx_eq_pre = 0 ; - // ate_tx_eq_post = 0 ; - // ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 16 ; - ate_rx_eq_ctle_pole = 1 ; - ate_rx_eq_afe_rate = 5 ; - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = 332 ; - ate_rx_eq_dfe_tap1 = 0 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 0 ; - ate_rx_cdr_vco_config = 1027 ; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 4 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 1 ; - ate_rx_dfe_bypass = 0 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 1 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 4 ; - ate_rx_adapt_en = 1 ; - } -#if 0 - if(cpri_speed_sel == 9){ - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 2 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 14 ; - ate_rx_vco_ld_val = 1386; - ate_rx_cdr_ppm_max = 18 ; - //lane - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 4 ; - ate_tx_ropll_cp_ctl_intg = 105 ; - ate_tx_ropll_cp_ctl_prop = 67 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 2 ; - ate_tx_ropll_postdiv = 0 ; - ate_tx_rate = 1 ; - ate_tx_ropll_div16p5_clk_en = 1 ; - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 4 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 5 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 11 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 2 ; - txX_ropll_word_clk_div_lte = 2 ; - ate_tx_fastedge_en = 0 ; - ate_tx_eq_pre = 0 ; - ate_tx_eq_post = 0 ; - ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 0 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 16 ; - ate_rx_eq_ctle_pole = 1 ; - ate_rx_eq_afe_rate = 4 ; - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = 396 ; - ate_rx_eq_dfe_tap1 = 10 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 6 ; - ate_rx_cdr_vco_config = 34 ; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 4 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 1 ; - ate_rx_dfe_bypass = 0 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 0 ; - ate_rx_div16p5_clk_en = 1 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 4 ; - ate_rx_adapt_en = 1 ; - } - #endif - if(cpri_speed_sel == 10) - { -#if 0 - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 2 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 14 ; - ate_rx_vco_ld_val = 1386; - ate_rx_cdr_ppm_max = 18 ; - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 4 ; - ate_tx_ropll_cp_ctl_intg = 105 ; - ate_tx_ropll_cp_ctl_prop = 67 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 2 ; - ate_tx_ropll_postdiv = 0 ; - ate_tx_rate = 0 ; - ate_tx_ropll_div16p5_clk_en = 1 ;//20220215 - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 6 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 5 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 11 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 2 ; - txX_ropll_word_clk_div_lte = 2 ; - ate_tx_fastedge_en = 0 ; - ate_tx_align_wide_xfer_en = 1 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 20 ; - ate_rx_eq_ctle_pole = 3 ; - ate_rx_eq_afe_rate = 2 ; - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = 2456; - ate_rx_eq_dfe_tap1 = 12 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 3 ; - ate_rx_cdr_vco_config = 34 ; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 0 ; - ate_rx_width = 4 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 0 ; - ate_rx_dfe_bypass = 0 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 1 ; - ate_rx_div16p5_clk_en = 1 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 4 ; - ate_rx_adapt_en = 1 ; -#endif - ate_ref_range = 4 ; - ate_ref_clk_div2_en = 0 ; - ate_ref_raw_clk_div2_en = 0 ; - ate_ref_clk_mplla_div = 1 ; - ate_lane_ref_sel = 0 ; - ate_mplla_fb_clk_div4_en = 0 ; - ate_mplla_multiplier = 180 ; - ate_mplla_tx_clk_div = 1 ; - ate_mplla_word_clk_div = 2 ; - ate_mplla_ssc_en = 0 ; - ate_mplla_ssc_up_spread = 0 ; - ate_mplla_ssc_peak = 0 ; - ate_mplla_ssc_step_size = 0 ; - ate_mplla_frac_en = 0 ; - ate_mplla_frac_quot = 0 ; - ate_mplla_frac_den = 0 ; - ate_mplla_frac_rem = 0 ; - ate_refa_lane_clk_en = 0 ; - ate_bs_rx_level = 7 ; - ate_bs_tx_lowswing = 0 ; - ate_bs_rx_bigswing = 1 ; - ate_mplla_init_cal_disable = 0 ; - ate_refa_dig_clk_sel = 0 ; - ate_ref_dco_bypass = 0 ; - ate_refa_dco_ld_val = 123 ; - ate_ref_dco_target = 150 ; - ate_ref_dco_dig_range = 6 ; - ate_mplla_bw_threshold = 75 ; - ate_mplla_bw_low = 1599; - ate_mplla_bw_high = 1599; - ate_mplla_ctl_buf_bypass = 0 ; - ate_mplla_short_lock_en = 0 ; - ate_rx_term_offset = 0 ; - ate_txdn_term_offset = 0 ; - ate_txup_term_offset = 0 ; - ate_sup_misc = 3 ; - ate_rx_vref_ctrl = 5 ; - ate_rx_ref_ld_val = 14 ; - ate_rx_vco_ld_val = 1386; - ate_rx_cdr_ppm_max = 18 ; - //lane - ate_tx_misc = 0 ; - ate_tx_dcc_ctrl_diff_range = 8 ; - ate_tx_dcc_ctrl_cm_range = 8 ; - ate_tx_width = 4 ; - ate_tx_ropll_cp_ctl_intg = 105 ; - ate_tx_ropll_cp_ctl_prop = 67 ; - ate_tx_ropll_rc_filter = 4 ; - ate_tx_ropll_v2i_mode = 3 ; - ate_tx_ropll_vco_low_freq = 2 ; - ate_tx_ropll_postdiv = 0 ; - ate_tx_rate = 0 ; - ate_tx_ropll_div16p5_clk_en = 1 ;//20220215 - ate_tx_ropll_125mhz_clk_en = 0 ; - ate_tx_term_ctrl = 0 ; - ate_tx_dly_cal_en = 0 ; - ate_tx_pll_word_clk_freq = 6 ; - ate_tx_dig_ropll_div_clk_sel = 0 ; - ate_tx_dual_cntx_en = 0 ; - ate_tx_ropll_bypass = 0 ; - ate_tx_ropll_refdiv = 5 ; - ate_tx_ropll_refsel = 0 ; - ate_tx_ropll_fbdiv = 11 ; - ate_tx_ropll_div_clk_en = 0 ; - ate_tx_ropll_out_div = 4 ; - ate_tx_ropll_word_clk_div_sel = 2 ; - txX_ropll_word_clk_div_lte = 2 ; - ate_tx_fastedge_en = 0 ; -// ate_tx_eq_pre = 0 ; -// ate_tx_eq_post = 0 ; -// ate_tx_eq_main = 24 ; - ate_tx_align_wide_xfer_en = 1 ; - ate_rx_eq_att_lvl = 0 ; - ate_rx_eq_ctle_boost = 20 ; - ate_rx_eq_ctle_pole = 3 ; - ate_rx_eq_afe_rate = 1 ;//24gtest 2 - ate_rx_eq_vga_gain = 16 ; - ate_rx_eq_afe_config = (9<<8)+(m<<6)+(n<<4)+(t<<2)+0;//24gtest 2456 - ate_rx_eq_dfe_tap1 = 12 ; - ate_rx_eq_dfe_tap2 = 128 ; - ate_rx_delta_iq = 3 ; - ate_rx_cdr_vco_config = 34 ; - ate_rx_dcc_ctrl_diff_range = 11 ; - ate_rx_dcc_ctrl_cm_range = 11 ; - ate_rx_sigdet_lf_threshold = 4 ; - ate_rx_sigdet_hf_threshold = 2 ; - ate_rx_misc = 0 ; - ate_rx_term_ctrl = 2 ;//24gtest 0 - ate_rx_width = 4 ; - ate_rx_dig_div_clk_sel = 0 ; - ate_rx_div_clk_en = 0 ; - ate_rx_div_clk_sel = 0 ; - ate_rx_rate = 0 ; - ate_rx_dfe_bypass = 0 ; - ate_rx_offcan_cont = 1 ; - ate_rx_adapt_cont = 1 ; - ate_rx_eq_dfe_float_en = 1 ; - ate_rx_div16p5_clk_en = 1 ; - ate_rx_125mhz_clk_en = 0 ; - ate_rx_cdr_ssc_en = 0 ; - ate_rx_sigdet_hf_en = 0 ; - ate_rx_sigdet_lfps_filter_en = 0 ; - ate_rx_term_acdc = 0 ; - ate_rx_adapt_sel = 0 ; - ate_rx_adapt_mode = 4 ; - ate_rx_adapt_en = 0 ; - } - - ate_tx_term_ctrl = ate_tx_term_ctrl +8; - ate_rx_term_ctrl = ate_rx_term_ctrl +8; - ate_ref_clk_mpllb_div = ate_ref_clk_mplla_div;// - ate_mpllb_fb_clk_div4_en = ate_mplla_fb_clk_div4_en;// - ate_mpllb_multiplier = ate_mplla_multiplier;// - ate_mpllb_tx_clk_div = ate_mplla_tx_clk_div;// - ate_mpllb_word_clk_div = ate_mplla_word_clk_div;// - ate_mpllb_ssc_en = ate_mplla_ssc_en;// - ate_mpllb_ssc_up_spread = ate_mplla_ssc_up_spread;// - ate_mpllb_ssc_peak = ate_mplla_ssc_peak;// - ate_mpllb_ssc_step_size = ate_mplla_ssc_step_size;// - ate_mpllb_frac_en = ate_mplla_frac_en;// - ate_mpllb_frac_quot = ate_mplla_frac_quot;// - ate_mpllb_frac_den = ate_mplla_frac_den;// - ate_mpllb_frac_rem = ate_mplla_frac_den;// - ate_refb_lane_clk_en = ate_refa_lane_clk_en;// - ate_mpllb_init_cal_disable = ate_mplla_init_cal_disable;// - ate_refb_dig_clk_sel = ate_refa_dig_clk_sel; - ate_refb_dco_ld_val = ate_refa_dco_ld_val; - ate_mpllb_bw_high = ate_mplla_bw_high ;// - ate_mpllb_bw_low = ate_mplla_bw_low ;// - ate_mpllb_bw_threshold = ate_mplla_bw_threshold;// - ate_mpllb_ctl_buf_bypass = ate_mplla_ctl_buf_bypass;// - ate_mpllb_short_lock_en = ate_mplla_short_lock_en;// - - //if(pma_sel ==0) - { -#if 0 - JECS_PHY_BS_CTRL = BIT4 + (7<<6); - - JECS_PMA1_REF_CLK_CTRL = 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12); - JECS_PMA1_REFB_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en; - JECS_PMA1_REFA_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en; - JECS_PMA1_BROADCAST_LANE_REFCLK_SEL = ate_lane_ref_sel; - JECS_PMA1_MPLLA_PARAM6 = (ate_mplla_fb_clk_div4_en<<4); - JECS_PMA1_MPLLB_PARAM6 = (ate_mpllb_fb_clk_div4_en<<4); - JECS_PMA1_MPLLA_PARAM5 = (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8); - JECS_PMA1_MPLLB_PARAM5 = (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8); - JECS_PMA1_REFA_CLK_CTRL1 = 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en; - JECS_PMA1_REFB_CLK_CTRL1 = 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en; - JECS_PMA1_MPLLA_SSC_CTRL2 = ate_mplla_ssc_peak; - JECS_PMA1_MPLLB_SSC_CTRL2 = ate_mpllb_ssc_peak; - JECS_PMA1_MPLLA_SSC_CTRL5 = ate_mplla_ssc_step_size; - JECS_PMA1_MPLLB_SSC_CTRL5 = ate_mpllb_ssc_step_size; - JECS_PMA1_MPLLA_FRAC_CTRL1 = ate_mplla_frac_den; - JECS_PMA1_MPLLB_FRAC_CTRL1 = ate_mpllb_frac_den; - JECS_PMA1_MPLLA_FRAC_CTRL2 = ate_mplla_frac_en; - JECS_PMA1_MPLLB_FRAC_CTRL2 = ate_mpllb_frac_en; - JECS_PMA1_MPLLA_FRAC_CTRL3 = ate_mplla_frac_quot; - JECS_PMA1_MPLLB_FRAC_CTRL3 = ate_mpllb_frac_quot; - JECS_PMA1_MPLLA_FRAC_CTRL4 = ate_mplla_frac_rem; - JECS_PMA1_MPLLB_FRAC_CTRL4 = ate_mpllb_frac_rem; - JECS_PMA1_MPLLA_PARAM3 = (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold; - JECS_PMA1_MPLLB_PARAM3 = (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold; - JECS_PMA1_MPLLA_SSC_CTRL1 = ate_mplla_ssc_en; - JECS_PMA1_MPLLB_SSC_CTRL1 = ate_mpllb_ssc_en; - JECS_PMA1_MPLLA_SSC_CTRL4 = ate_mplla_ssc_up_spread; - JECS_PMA1_MPLLB_SSC_CTRL4 = ate_mpllb_ssc_up_spread; - JECS_PMA1_SUP_MISC = ate_sup_misc; - JECS_PMA1_MPLLA_PARAM4 = ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12); - JECS_PMA1_MPLLB_PARAM4 = ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12); - JECS_PMA1_RTUNE_CTRL1 = ate_rx_term_offset; - JECS_PMA1_RTUNE_CTRL2 = ate_txdn_term_offset; - JECS_PMA1_RTUNE_CTRL3 = ate_txup_term_offset; - JECS_PMA1_MPLLA_PARAM1 = ate_mplla_bw_high; - JECS_PMA1_MPLLB_PARAM1 = ate_mpllb_bw_high; - JECS_PMA1_MPLLA_PARAM2 = ate_mplla_bw_low; - JECS_PMA1_MPLLB_PARAM2 = ate_mpllb_bw_low; - JECS_PMA1_RX_BIAS_CURRENT_CTRL = ate_rx_vref_ctrl+BIT8;//20220214 - JECS_PMA1_MPLLA_FORCE_EN = ate_mplla_force_en; - JECS_PMA1_MPLLB_FORCE_EN = ate_mpllb_force_en; - JECS_PMA1_POWER_GATING_SIGNAL1 = ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12); - - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7 = ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8); - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8 = ate_rx_vco_ld_val; - JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1 = ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12); - JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2 = ate_tx_misc + (ate_tx_term_ctrl<<8); - JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2 = (ate_tx_width<<4) + ate_tx_rate; - JECS_PMA1_BROADCAST_ETH_CLK_CTRL = (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en; - JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL = ate_tx_dig_ropll_div_clk_sel; - JECS_PMA1_BROADCAST_RECEIVER_CONTROL= (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8); - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4 = (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost; - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3 = (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass + (ate_rx_eq_att_lvl<<8); - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9 = ate_rx_width; - JECS_PMA1_BROADCAST_RX_EQ_CTRL2 = (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2; - JECS_PMA1_BROADCAST_RX_EQ_CTRL1 = (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config; - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2 = ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12); - JECS_PMA1_BROADCAST_RX_ADAPT_CTRL = ate_rx_adapt_sel; - JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING = (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8); - JECS_PMA1_BROADCAST_TRANSMITTER_EQ1 = ate_tx_eq_main; - JECS_PMA1_BROADCAST_TRANSMITTER_EQ2 = ate_tx_eq_post; - JECS_PMA1_BROADCAST_TRANSMITTER_EQ3 = ate_tx_eq_pre; - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6 = (ate_rx_misc<<8); - JECS_PMA1_BROADCAST_RX_DCC_CTRL = ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4); - JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5 = (ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1; - JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2 = (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en; - JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3 = ate_rx_sigdet_lfps_filter_en; - JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2 = ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7); - JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4 = ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14); - JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3 = ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7); - JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5 = ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100; - JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1 = (ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4); - JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY = ate_tx_clk_rdy; - JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING = ate_tx_align_wide_xfer_en + (ate_tx_invert<<4); - JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1 = ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8); - JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3 = ate_tx_dual_cntx_en; - JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL = ate_tx_dly_cal_en; - JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL = ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8); - #endif - do_write(&JECS_PHY_BS_CTRL, BIT4 + (7<<6)); - do_write(&JECS_PMA1_REF_CLK_CTRL, 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12)); - do_write(&JECS_PMA1_REFB_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en); - do_write(&JECS_PMA1_REFA_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en); - do_write(&JECS_PMA1_BROADCAST_LANE_REFCLK_SEL, ate_lane_ref_sel); - do_write(&JECS_PMA1_MPLLA_PARAM6, (ate_mplla_fb_clk_div4_en<<4)); - do_write(&JECS_PMA1_MPLLB_PARAM6, (ate_mpllb_fb_clk_div4_en<<4)); - do_write(&JECS_PMA1_MPLLA_PARAM5, (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8)); - do_write(&JECS_PMA1_MPLLB_PARAM5, (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8)); - do_write(&JECS_PMA1_REFA_CLK_CTRL1, 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en); - do_write(&JECS_PMA1_REFB_CLK_CTRL1, 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en); - do_write(&JECS_PMA1_MPLLA_SSC_CTRL2, ate_mplla_ssc_peak); - do_write(&JECS_PMA1_MPLLB_SSC_CTRL2, ate_mpllb_ssc_peak); - do_write(&JECS_PMA1_MPLLA_SSC_CTRL5, ate_mplla_ssc_step_size); - do_write(&JECS_PMA1_MPLLA_SSC_CTRL5, ate_mpllb_ssc_step_size); - do_write(&JECS_PMA1_MPLLA_FRAC_CTRL1, ate_mplla_frac_den); - do_write(&JECS_PMA1_MPLLB_FRAC_CTRL1, ate_mpllb_frac_den); - do_write(&JECS_PMA1_MPLLA_FRAC_CTRL2, ate_mplla_frac_en); - do_write(&JECS_PMA1_MPLLB_FRAC_CTRL2, ate_mpllb_frac_en); - do_write(&JECS_PMA1_MPLLA_FRAC_CTRL3, ate_mplla_frac_quot); - do_write(&JECS_PMA1_MPLLB_FRAC_CTRL3, ate_mpllb_frac_quot); - do_write(&JECS_PMA1_MPLLA_FRAC_CTRL4, ate_mplla_frac_rem); - do_write(&JECS_PMA1_MPLLB_FRAC_CTRL4, ate_mpllb_frac_rem); - do_write(&JECS_PMA1_MPLLA_PARAM3, (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold); - do_write(&JECS_PMA1_MPLLB_PARAM3, (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold); - do_write(&JECS_PMA1_MPLLA_SSC_CTRL1 , ate_mplla_ssc_en); - do_write(&JECS_PMA1_MPLLB_SSC_CTRL1 , ate_mpllb_ssc_en); - do_write(&JECS_PMA1_MPLLA_SSC_CTRL4 , ate_mplla_ssc_up_spread); - do_write(&JECS_PMA1_MPLLB_SSC_CTRL4 , ate_mpllb_ssc_up_spread); - do_write(&JECS_PMA1_SUP_MISC , ate_sup_misc); - do_write(&JECS_PMA1_MPLLA_PARAM4 , ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12)); - do_write(&JECS_PMA1_MPLLB_PARAM4 , ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12)); - do_write(&JECS_PMA1_RTUNE_CTRL1 , ate_rx_term_offset); - do_write(&JECS_PMA1_RTUNE_CTRL2 , ate_txdn_term_offset); - do_write(&JECS_PMA1_RTUNE_CTRL3 , ate_txup_term_offset); - do_write(&JECS_PMA1_MPLLA_PARAM1 , ate_mplla_bw_high); - do_write(&JECS_PMA1_MPLLB_PARAM1 , ate_mpllb_bw_high); - do_write(&JECS_PMA1_MPLLA_PARAM2 , ate_mplla_bw_low); - do_write(&JECS_PMA1_MPLLB_PARAM2 , ate_mpllb_bw_low); - do_write(&JECS_PMA1_RX_BIAS_CURRENT_CTRL , ate_rx_vref_ctrl+BIT8); - do_write(&JECS_PMA1_MPLLA_FORCE_EN , ate_mplla_force_en); - do_write(&JECS_PMA1_MPLLB_FORCE_EN , ate_mpllb_force_en); - do_write(&JECS_PMA1_POWER_GATING_SIGNAL1 , ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12)); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7, ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8)); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8, ate_rx_vco_ld_val); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1, ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12)); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2, ate_tx_misc + (ate_tx_term_ctrl<<8)); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2, (ate_tx_width<<4) + ate_tx_rate); - do_write(&JECS_PMA1_BROADCAST_ETH_CLK_CTRL, (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en); - do_write(&JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL, ate_tx_dig_ropll_div_clk_sel); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_CONTROL, (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8)); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4, (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3, (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass + (ate_rx_eq_att_lvl<<8)); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9, ate_rx_width); - do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL2, (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2); - do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL1, (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2,ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12)); - do_write(&JECS_PMA1_BROADCAST_RX_ADAPT_CTRL,ate_rx_adapt_sel ); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING, (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8)); - if(8 == cpri_speed_sel) - { - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, ate_tx_eq_main[4]); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, ate_tx_eq_post[4]); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, ate_tx_eq_pre[4]); - } - if(10 == cpri_speed_sel) - { - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, ate_tx_eq_main[4]); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, ate_tx_eq_post[4]); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, ate_tx_eq_pre[4]); - } - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6, (ate_rx_misc<<8)); - do_write(&JECS_PMA1_BROADCAST_RX_DCC_CTRL, ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4)); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5,(ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2, (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en); - do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3, ate_rx_sigdet_lfps_filter_en); - do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2,ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7)); - do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4 , ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14)); - do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3 , ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7)); - do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5 , ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1 ,(ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4)); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY ,ate_tx_clk_rdy); - do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING , ate_tx_align_wide_xfer_en + (ate_tx_invert<<4)); - do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1 , ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8)); - do_write(&JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3 , ate_tx_dual_cntx_en); - do_write(&JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL , ate_tx_dly_cal_en); - do_write(&JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL , ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8)); - } - - #if 0 - if(pma_sel ==1){ - - PET_PHY_BS_CTRL = BIT4 + (7<<6); - - PET_PMA3_BROADCAST_RECEIVER_REQ_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_RECEIVER_ADAPT_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_RECEIVER_CONTROL_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_RECEIVER_RECAL_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_TRANSMITTER_REQ_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_TRANSMITTER_EQ_MUX_CTRL = 0x1; - PET_PMA3_BROADCAST_CONTEXT_RESTORE_MUX = 0x1; - PET_PMA3_BROADCAST_ETH_CLK_CTRL_MUX = 0x1; - PET_PMA3_BROADCAST_RECV_REQUEST_CTRL_MUX = 0x1; - PET_PMA3_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX = 0x1; - PET_PMA3_BROADCAST_MULTI_CLK_CTRL_MUX = 0x1; - PET_PMA3_BROADCAST_TRANS_REQ_MUX = 0x1; - PET_PMA3_BROADCAST_TRANS_INTERFACE_MUX = 0x1; - PET_PMA3_BROADCAST_PLL_STATE_MUX = 0x1; - PET_PMA3_REF_CLK_MUX = 0x1; - PET_PMA3_MPLL_CTRL_MUX = BIT4|BIT8|BIT0;//20220214 - - PET_PMA3_REF_CLK_CTRL = 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12); - PET_PMA3_REFB_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en; - PET_PMA3_REFA_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en; - PET_PMA3_BROADCAST_LANE_REFCLK_SEL = ate_lane_ref_sel; - PET_PMA3_MPLLA_PARAM6 = (ate_mplla_fb_clk_div4_en<<4); - PET_PMA3_MPLLB_PARAM6 = (ate_mpllb_fb_clk_div4_en<<4); - PET_PMA3_MPLLA_PARAM5 = (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8); - PET_PMA3_MPLLB_PARAM5 = (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8); - PET_PMA3_REFA_CLK_CTRL1 = 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en; - PET_PMA3_REFB_CLK_CTRL1 = 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en; - PET_PMA3_MPLLA_SSC_CTRL2 = ate_mplla_ssc_peak; - PET_PMA3_MPLLB_SSC_CTRL2 = ate_mpllb_ssc_peak; - PET_PMA3_MPLLA_SSC_CTRL5 = ate_mplla_ssc_step_size; - PET_PMA3_MPLLB_SSC_CTRL5 = ate_mpllb_ssc_step_size; - PET_PMA3_MPLLA_FRAC_CTRL1 = ate_mplla_frac_den; - PET_PMA3_MPLLB_FRAC_CTRL1 = ate_mpllb_frac_den; - PET_PMA3_MPLLA_FRAC_CTRL2 = ate_mplla_frac_en; - PET_PMA3_MPLLB_FRAC_CTRL2 = ate_mpllb_frac_en; - PET_PMA3_MPLLA_FRAC_CTRL3 = ate_mplla_frac_quot; - PET_PMA3_MPLLB_FRAC_CTRL3 = ate_mpllb_frac_quot; - PET_PMA3_MPLLA_FRAC_CTRL4 = ate_mplla_frac_rem; - PET_PMA3_MPLLB_FRAC_CTRL4 = ate_mpllb_frac_rem; - PET_PMA3_MPLLA_PARAM3 = (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold; - PET_PMA3_MPLLB_PARAM3 = (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold; - PET_PMA3_MPLLA_SSC_CTRL1 = ate_mplla_ssc_en; - PET_PMA3_MPLLB_SSC_CTRL1 = ate_mpllb_ssc_en; - PET_PMA3_MPLLA_SSC_CTRL4 = ate_mplla_ssc_up_spread; - PET_PMA3_MPLLB_SSC_CTRL4 = ate_mpllb_ssc_up_spread; - PET_PMA3_SUP_MISC = ate_sup_misc; - PET_PMA3_MPLLA_PARAM4 = ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12); - PET_PMA3_MPLLB_PARAM4 = ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12); - PET_PMA3_RTUNE_CTRL1 = ate_rx_term_offset; - PET_PMA3_RTUNE_CTRL2 = ate_txdn_term_offset; - PET_PMA3_RTUNE_CTRL3 = ate_txup_term_offset; - PET_PMA3_MPLLA_PARAM1 = ate_mplla_bw_high; - PET_PMA3_MPLLB_PARAM1 = ate_mpllb_bw_high; - PET_PMA3_MPLLA_PARAM2 = ate_mplla_bw_low; - PET_PMA3_MPLLB_PARAM2 = ate_mpllb_bw_low; - PET_PMA3_RX_BIAS_CURRENT_CTRL = ate_rx_vref_ctrl+BIT8;//20220214 - PET_PMA3_MPLLA_FORCE_EN = ate_mplla_force_en; - PET_PMA3_MPLLB_FORCE_EN = ate_mpllb_force_en; - PET_PMA3_POWER_GATING_SIGNAL1 = ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12); - - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM7 = ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8); - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM8 = ate_rx_vco_ld_val; - PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING1 = ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12); - PET_PMA3_BROADCAST_TRANSMITTER_CONTROL2 = ate_tx_misc + (ate_tx_term_ctrl<<8); - PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM2 = (ate_tx_width<<4) + ate_tx_rate; - PET_PMA3_BROADCAST_ETH_CLK_CTRL = (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en; - PET_PMA3_BROADCAST_TX_DIV_CLK_CTRL = ate_tx_dig_ropll_div_clk_sel; - PET_PMA3_BROADCAST_RECEIVER_CONTROL= (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8); - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM4 = (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost; - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM3 = (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass + (ate_rx_eq_att_lvl<<8); - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM9 = ate_rx_width; - PET_PMA3_BROADCAST_RX_EQ_CTRL2 = (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2; - PET_PMA3_BROADCAST_RX_EQ_CTRL1 = (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config; - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM2 = ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12); - PET_PMA3_BROADCAST_RX_ADAPT_CTRL = ate_rx_adapt_sel; - PET_PMA3_BROADCAST_RECEIVER_ADAPT_SETTING = (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8); - PET_PMA3_BROADCAST_TRANSMITTER_EQ1 = ate_tx_eq_main; - PET_PMA3_BROADCAST_TRANSMITTER_EQ2 = ate_tx_eq_post; - PET_PMA3_BROADCAST_TRANSMITTER_EQ3 = ate_tx_eq_pre; - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM6 = (ate_rx_misc<<8); - PET_PMA3_BROADCAST_RX_DCC_CTRL = ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4); - PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM5 = (ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1; - PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING2 = (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en; - PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING3 = ate_rx_sigdet_lfps_filter_en; - PET_PMA3_BROADCAST_TRANS_REQ_CTRL2 = ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7); - PET_PMA3_BROADCAST_TRANS_REQ_CTRL4 = ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14); - PET_PMA3_BROADCAST_TRANS_REQ_CTRL3 = ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7); - PET_PMA3_BROADCAST_TRANS_REQ_CTRL5 = ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100; - PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM1 = (ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4); - PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY = ate_tx_clk_rdy; - PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_SETTING = ate_tx_align_wide_xfer_en + (ate_tx_invert<<4); - PET_PMA3_BROADCAST_TRANS_REQ_CTRL1 = ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8); - PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL3 = ate_tx_dual_cntx_en; - PET_PMA3_BROADCAST_TRANS_INTERFACE_CTRL = ate_tx_dly_cal_en; - PET_PMA3_BROADCAST_RX_DIV_CLK_CTRL = ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8); - } - #endif -} - -void Init_jecspma(uint32_t cpri_speed_sel) -{ -#if 0 - JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | (BIT4); - //cancell jecs pma rst - JECS_CRG_PMA16_RST_CTRL |= BIT24; - JECS_CRG_PMA0_RST_CTRL |= BIT24; - JECS_CRG_PMA1_RST_CTRL |= BIT24; - JECS_CRG_PMA2_RST_CTRL |= BIT24; - JECS_CRG_PMA3_RST_CTRL |= BIT24; - JECS_CRG_PMA8_RST_CTRL |= BIT24; - JECS_CRG_PMA9_RST_CTRL |= BIT24; - JECS_CRG_PMA10_RST_CTRL |= BIT24; - JECS_CRG_PMA11_RST_CTRL |= BIT24; - JECS_CRG_PMA12_RST_CTRL |= BIT24; - JECS_CRG_PMA13_RST_CTRL |= BIT24; - JECS_CRG_PMA14_RST_CTRL |= BIT24; - JECS_CRG_PMA15_RST_CTRL |= BIT24; -#endif -#if 1 - uint32_t i =0; - uint32_t temp =0; - - //PCS Protocol Sel - // JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | (BIT2); - temp = do_read_volatile(&JECS_CTRL_PROTOCOL_SEL); - temp |= BIT2; - __ucps2_synch(0); - do_write(&JECS_CTRL_PROTOCOL_SEL, temp); - // JECS_PMA1_CPRI_PCS_STATUS_CTRL = 0; - do_write(&JECS_PMA1_CPRI_PCS_STATUS_CTRL, 0); - //PCS BIT REV - if(cpri_speed_sel<=7)//option~option7 - { - //JECS_PMA1_PCS_BIT_REV_CTRL = 0x211; - do_write(&JECS_PMA1_PCS_BIT_REV_CTRL, 0x211); - } - else - { - //JECS_PMA1_PCS_BIT_REV_CTRL = 0x111; - do_write(&JECS_PMA1_PCS_BIT_REV_CTRL, 0x111); - } - do_write(&JECS_PMA1_CPRI_SIGDET, (BIT4|BIT0)); - ucp_nop(400); - if(cpri_speed_sel==7) - { - // JECS_PMA1_TX_CLK_SEL = 0x0; - do_write(&JECS_PMA1_TX_CLK_SEL,0); - } - else if((cpri_speed_sel==3)| (cpri_speed_sel==9)) - { - //JECS_PMA1_TX_CLK_SEL = 0x2; - do_write(&JECS_PMA1_TX_CLK_SEL,0x2); - } - else if(cpri_speed_sel==2) - { - // JECS_PMA1_TX_CLK_SEL = 0x3; - do_write(&JECS_PMA1_TX_CLK_SEL,0x3); - } - else - { - //JECS_PMA1_TX_CLK_SEL = 0x1; - do_write(&JECS_PMA1_TX_CLK_SEL,0x1); - } - ucp_nop(400); - - init_pma_commonconfig(0,cpri_speed_sel); - ucp_nop(400); - - // JECS_PMA1_PHY_RESET = 0x1; - do_write(&JECS_PMA1_PHY_RESET,0x1); - ucp_nop(400); - //UARTPrintStr("JECS PHY RESET\n"); - //JECS_PMA1_SRAM_CTRL = 0x1; - //JECS_PMA1_PHY_RESET = 0x0; - //while((JECS_PMA1_SRAM_STATUS & BIT0)!=BIT0); - //init_fastjecspma();//to be changed - ////SRAM ECC DisEn and Init Done - //JECS_PMA1_SRAM_CTRL = 0x1001; - //UARTPrintStr("JECS SRAM EXTDONE\n"); - - // JECS_PMA1_SRAM_CTRL = 0x101; - do_write(&JECS_PMA1_SRAM_CTRL,0x101); - ucp_nop(400); - // JECS_PMA1_PHY_RESET = 0x0; - do_write(&JECS_PMA1_PHY_RESET,0); - //wait sram_load success - // while((JECS_PMA1_SRAM_STATUS&BIT0) != 1) ; - - __ucps2_synch(0); - while((do_read_volatile(&JECS_PMA1_SRAM_STATUS) & BIT0)!= 1){} - - for(i=0;i<16384;i++) - { - //(*((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4))) = pma_fw[i]; - - // do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4),pma_fw[i]); - - temp =do_read_volatile(&pma_fw[i]); - __ucps2_synch(0); - do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000*4+i*4),temp); - __ucps2_synch(0); - } - - // (*((volatile uint32_t *)(JECS_PMA1_CFG+0x101*4))) |= BIT1; - - do_write((volatile uint32_t *)(JECS_PMA1_CFG+0x101*4), do_read_volatile((volatile uint32_t *)(JECS_PMA1_CFG+0x101*4)) | BIT1); - __ucps2_synch(0); - for(i=0;i<16384;i++) - { - // (*((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4))) = pma_fw[i+16384]; - // do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4),pma_fw[i+16384]); - - temp =do_read_volatile(&pma_fw[i+16384]); - __ucps2_synch(0); - do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000*4+i*4),temp); - __ucps2_synch(0); - } - do_write(&JECS_PMA1_SRAM_CTRL,0x1101); - __ucps2_synch(0); -#endif -} - - - -void init_jecspma_recrx(){ - //Disable Tx and Rx RST - //JECS_PMA1_LANE0_TRANSMITTER_CONTROL1 = 0x0; - //JECS_PMA1_LANE0_RECEIVER_RESET = 0x0; - - //Wait Ack Done - //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); - //while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); - //UARTPrintStr("JECS RX ACK DONE\n"); - - //Enable TX and RX Req - do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1); - - //Wait ACK and Disable Req - while(!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0)); - do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0); - do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); - - //Wait Ack Done - while(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0); - - //P0 PSTATE - do_write(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7) & 0xfff0); - do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1); - - //Wait ACK and Disable Req - while(!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0)); - do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0); - do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); - - //Wait Ack Done - while(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0); - - //Enable Data - do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, 0x1); - - //wait rx valid - while(do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) == 0){} - - //UARTPrintStr("RECMODE:JECS RX RX VALID\n"); - -} - -void init_jecspma_rectx(){ - //Disable Tx and Rx RST -#if 0 - JECS_PMA1_LANE0_TRANSMITTER_CONTROL1 = 0x0; - JECS_PMA1_LANE0_RECEIVER_RESET = 0x0; - JECS_PMA1_LANE1_TRANSMITTER_CONTROL1 = 0x0; - JECS_PMA1_LANE1_RECEIVER_RESET = 0x0; - JECS_PMA1_LANE2_TRANSMITTER_CONTROL1 = 0x0; - JECS_PMA1_LANE2_RECEIVER_RESET = 0x0; - JECS_PMA1_LANE3_TRANSMITTER_CONTROL1 = 0x0; - JECS_PMA1_LANE3_RECEIVER_RESET = 0x0; -#endif - - do_write(&JECS_PMA1_LANE0_TRANSMITTER_CONTROL1, 0x0); - do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, 0x0); - do_write(&JECS_PMA1_LANE1_TRANSMITTER_CONTROL1, 0x0); - do_write(&JECS_PMA1_LANE1_RECEIVER_RESET, 0x0); - do_write(&JECS_PMA1_LANE2_TRANSMITTER_CONTROL1, 0x0); - do_write(&JECS_PMA1_LANE2_RECEIVER_RESET, 0x0); - do_write(&JECS_PMA1_LANE3_TRANSMITTER_CONTROL1, 0x0); - do_write(&JECS_PMA1_LANE3_RECEIVER_RESET, 0x0); - ucp_nop(400); - //Wait Ack Done - //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); - //while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); - __ucps2_synch(0); - while(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0); - __ucps2_synch(0); - while(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0){} - //UARTPrintStr("RECMODE:JECS TX ACK DONE\n"); - - //Enable TX and RX Req - //JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x1; - do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1); - //JECS_PMA1_LANE0_RECEIVER_REQ = 0x1; - - //Wait ACK and Disable Req - //while(!((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0))); - - //while(!((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0))); - __ucps2_synch(0); - while(!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0)); - //JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x0; - do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0); - // JECS_PMA1_LANE0_RECEIVER_REQ = 0x0; - do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); - - //Wait Ack Done - //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); - - //while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); - __ucps2_synch(0); - while(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0); - //UARTPrintStr("RECMODE:JECS TX ACK DONE\n"); - - //P0 PSTATE - //JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7 = (JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7&0xfff0); - - - // JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1 = (JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1&0xff); - __ucps2_synch(0); - do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1, do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1) &0xff); - - - // JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x1; - do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1); - //JECS_PMA1_LANE0_RECEIVER_REQ = 0x1; - - //Wait ACK and Disable Req - //while(!((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0))); - - // while(!((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0))); - __ucps2_synch(f_SM); - while(!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0)); - // JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x0; - do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x00); - //JECS_PMA1_LANE0_RECEIVER_REQ = 0x0; - do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); - - //Wait Ack Done - //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); - - // while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); - __ucps2_synch(f_SM); - while(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0); - //UARTPrintStr("RECMODE:JECS TX ACK DONE\n"); - - //Enable Data - // JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN = 0x1; - do_write(&JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN, 0x1); - //JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN = 0x1; - - //P0 PSTATE - //while(JECS_PMA1_LANE0_TRANS_PLL_STATE == 0); - __ucps2_synch(f_SM); - while(do_read_volatile(&JECS_PMA1_LANE0_TRANS_PLL_STATE) == 0){} - //UARTPrintStr("RECMODE:JECS TX READY\n"); - -} - -void jecspma_recrx_eq() -{ - uint32_t i=0; - uint32_t j=0; - init_jecspma_recrx(); - //for(uint32_t i = 0;i<10 ; i++) - //while(1) - { - i++; - //rx adapt eq - //UARTPrintStr("PMA RX ADAPT EQ START"); - //De-assert rx_data_en - if((0 == (j % 100)) && (1< j)) - { - Clk_To_XTAL(); - do_write(&CPRI_PCS_ADDR_CFG, 0); - do_write(&CPRI_PCS_DATA_TX_CFG, BIT15|BIT13|BIT6); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0); - do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0x1C); - do_write(&CPRI_PCS_DATA_TX_CFG, 0); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xB8); - do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xBC); - do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - Clk_To_Normal(); - - } - - do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4); - - //Assert rx_adapt_in_prog to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); - - //Toggle rx_reset to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) | BIT4); - do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) & (~BIT4)); - __ucps2_synch(f_SM); - - //Wait for de-assertion of rx_ack from the PHY - while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & 0x1 )!= 0); - //Assert rx_data_en to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4|BIT0); - __ucps2_synch(f_SM); - - //Wait for assertion of rx_valid from the PHY - while((do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) & BIT0 )!= 0x1); - - //Perform an RX adaptation request and assert rx_adapt_req - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4|BIT0); - __ucps2_synch(f_SM); - - //Wait for assertion of rx_adapt_ack from the PHY - while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)&BIT0) != BIT0); - debug_write((DBG_DDR_IDX_CPRI_BASE), do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)); - - //UARTPrintStr_f("JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK",JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK); - //De-assert rx_adapt_req to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); - - //De-assert rx_adapt_in_prog to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, 0); -#if 0 - do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL) & (~BIT24)); - // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL) & (~BIT24)); - ucp_nop(400); - do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL)| BIT24); - // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL)| BIT24); - -#endif - debug_write((DBG_DDR_IDX_CPRI_BASE+1), i); - debug_write((DBG_DDR_IDX_CPRI_BASE+2), j); -#if 0 - //ucp_nop(400); - - //if(0xA0 < (((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK))>>8) & 0xFF)) - if(0x80 < (((do_read_volatile((DBG_DDR_IDX_CPRI_BASE<<2)+DBG_DDR_ADDR_BASE))>>8) & 0xFF)) - { - j++; - delay_us(10000); - //if((do_read_volatile(&AUX_INT_FLAG) & BIT2) == 0x4) - if(do_read_volatile(&CPRI_FRAME_RX_STAT) == 0x1E) - //if (1 < gCpriSyncIntCnt) - { - break; - } - } - -#endif - - } - - -} -void jecspma_recrx_reset() -{ - uint32_t i=0; - uint32_t j=0; - init_jecspma_recrx(); - while(1) - { - i++; - //rx adapt eq - //UARTPrintStr("PMA RX ADAPT EQ START"); - //De-assert rx_data_en - - if((0 == (j % 100)) && (1< j)) - { - Clk_To_XTAL(); - do_write(&CPRI_PCS_ADDR_CFG, 0); - do_write(&CPRI_PCS_DATA_TX_CFG, BIT15|BIT13|BIT6); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0); - do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0x1C); - do_write(&CPRI_PCS_DATA_TX_CFG, 0); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xB8); - do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xBC); - do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - Clk_To_Normal(); - - } - - do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4); - - //Assert rx_adapt_in_prog to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); - - //Toggle rx_reset to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) | BIT4); - do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) & (~BIT4)); - __ucps2_synch(f_SM); - - //Wait for de-assertion of rx_ack from the PHY - while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & 0x1 )!= 0); - //Assert rx_data_en to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4|BIT0); - __ucps2_synch(f_SM); - - //Wait for assertion of rx_valid from the PHY - while((do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) & BIT0 )!= 0x1); - - //Perform an RX adaptation request and assert rx_adapt_req - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4|BIT0); - __ucps2_synch(f_SM); - - //Wait for assertion of rx_adapt_ack from the PHY - while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)&BIT0) != BIT0); - debug_write((DBG_DDR_IDX_CPRI_BASE+4), do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)); - - //UARTPrintStr_f("JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK",JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK); - //De-assert rx_adapt_req to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); - - //De-assert rx_adapt_in_prog to the PHY - do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, 0); -#if 0 - do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL) & (~BIT24)); - // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL) & (~BIT24)); - ucp_nop(400); - do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL)| BIT24); - // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL)| BIT24); - -#endif - debug_write((DBG_DDR_IDX_CPRI_BASE+5), i); - //debug_write((DBG_DDR_IDX_CPRI_BASE+4), j); -#if 1 - //ucp_nop(400); - - //if(0xA0 < (((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK))>>8) & 0xFF)) - if(0x80 < (((do_read_volatile(((DBG_DDR_IDX_CPRI_BASE+4)<<2)+DBG_DDR_ADDR_BASE))>>8) & 0xFF)) - { - j++; - debug_write((DBG_DDR_IDX_CPRI_BASE+6), j); - delay_us(10000); - //if((do_read_volatile(&AUX_INT_FLAG) & BIT2) == 0x4) - if(do_read_volatile(&CPRI_FRAME_RX_STAT) == 0x1E) - //if (1 < gCpriSyncIntCnt) - { - break; - } - } - - -#endif - - } - -#if 0 - uint32_t resynctimes = 0; - delay_us(10000); - for(uint32_t i=0;i<500;i++) - { - if(do_read_volatile(&CPRI_FRAME_RX_STAT) != 0x1E) - { - resynctimes++; - jecspma_recrx_eq(); - debug_write((DBG_DDR_IDX_CPRI_BASE+3), i); - debug_write((DBG_DDR_IDX_CPRI_BASE+7), resynctimes); - } - else - { - delay_us(1000); - } - } -#endif - -} -void init_cpri(uint32_t cpri_speed_sel) -{ -// uint32_t resynctimes = 0; - //JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | BIT4;//cpri tx pma sel jecs - do_write(&JECS_CTRL_PROTOCOL_SEL, do_read_volatile(&JECS_CTRL_PROTOCOL_SEL) | BIT4); - -#if 0 - /************************************ - 配置光模块使能：PD16/AP_GPIO0B29 - 低：光模块发射打开 - 高：光模块发射关闭 - *****************************************/ - // do_write((GPIO0_A29_PINMUX_REG_ADDR+0xc), (do_read_volatile((GPIO0_A29_PINMUX_REG_ADDR+0xc))|0x3)); - do_write((0x0445818c), (do_read_volatile(0x0445818c)|0x3));//pinmux - __ucps2_synch(f_SM); - do_write((0x04450010), (do_read_volatile(0x04450010)|(BIT29))); //dir:1:out;0:in - __ucps2_synch(f_SM); - do_write((0x0445000c), (do_read_volatile(0x0445000c)&(~(BIT29)))); // data:0 - __ucps2_synch(f_SM); - delay_us(1000); -#endif - - init_cpri_pma_rst(); - - Init_cpri_clk(cpri_speed_sel); - - Init_jecspma(cpri_speed_sel); - - init_jecspma_rectx(); - - do_write(SERDES_INIT_FLAG_ADDR, 1); // cpri serdes clk init finished - - do_write(&JECS_CRG_CPRI0_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI0_RST_CTRL) | BIT24); - do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL) | BIT24); - do_write(&JECS_CRG_CPRI2_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI2_RST_CTRL) | BIT24); - do_write(&JECS_CRG_CPRI3_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI3_RST_CTRL) | BIT24); - do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL) | BIT24); - do_write(&JECS_CRG_CPRI5_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI5_RST_CTRL) | BIT24); - do_write(&JECS_CRG_CPRI6_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI6_RST_CTRL) | BIT24); - do_write(&ECPRI_RST_CFG_REG, do_read_volatile(&ECPRI_RST_CFG_REG) | BIT24); - do_write(&AUX_CTRL_REG, do_read_volatile(&AUX_CTRL_REG) & (~BIT2)); - ucp_nop(400); - if(8 == cpri_speed_sel)//option8 - { - do_write(&CPRI_PCS_64B66B_CFG, 0); - do_write(&CPRI_FRAME_RX_CFG, 0x14|BIT8); - Clk_To_XTAL(); - do_write(&CPRI_PCS_ADDR_CFG, 0); - do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0x1C); - do_write(&CPRI_PCS_DATA_TX_CFG, 0); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xB8); - do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xBC); - do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - -//恢复正常 - Clk_To_Normal(); - - do_write(&CPRI_FRAME_TX_CM_CFG, 0x114); - do_write(&CPRI_FRAME_TX_PROT_VER, 0x1); - do_write(&CPRI_FRAME_TX_BFN_INIT, 0x10000); - do_write(&CPRI_FRAME_TX_SCRAMBLER, 0x0); - do_write(&CPRI_FRAME_TX_CFG, BIT2|BIT1); - } - else if(10 == cpri_speed_sel)//option10 - { - do_write(&CPRI_PCS_64B66B_CFG, 0); - do_write(&CPRI_FRAME_RX_CFG, 0x30|BIT8); - Clk_To_XTAL(); - do_write(&CPRI_PCS_ADDR_CFG, 0); - do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0x1C); - do_write(&CPRI_PCS_DATA_TX_CFG, 0); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xB8); - do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); - do_write(&CPRI_PCS_ADDR_CFG, 0xBC); - do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); -#if 1 - do_write(&CPRI_PCS_ADDR_CFG, 0x320); - do_write(&CPRI_PCS_DATA_TX_CFG, BIT2);//DATA_CFG Enable RS-FEC - do_write(&CPRI_PCS_CTRL_CFG, 0x2); - __ucps2_synch(f_SM); -#endif - Clk_To_Normal(); - do_write(&CPRI_FRAME_TX_CM_CFG, 0x114); - do_write(&CPRI_FRAME_TX_PROT_VER, 0x1); - do_write(&CPRI_FRAME_TX_BFN_INIT, 0x10000); - do_write(&CPRI_FRAME_TX_SCRAMBLER, 0x0); - do_write(&CPRI_FRAME_TX_CFG, BIT2|BIT1); - } - else - { - } - - - jecspma_recrx_eq(); -#if 0 - - delay_us(10000); - for(uint32_t i=0;i<3000;i++) - { - if(do_read_volatile(&CPRI_FRAME_RX_STAT) != 0x1E) - { - resynctimes++; - jecspma_recrx_eq(); - debug_write((DBG_DDR_IDX_CPRI_BASE+3), i); - debug_write((DBG_DDR_IDX_CPRI_BASE+7), resynctimes); - } - else - { - delay_us(10000); - } - } -#endif - do_write(&ALARM_FLAG,0x0); -} -DDR0 uint32_t ID_SIZE_buf[3][16] = { -{1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0}, -{1,1,8,8,8,8,2,2,1,0,0,0,0,0,0,0}, -{1,1,8,8,8,8,8,8,8,8,1,0,0,0,0,0} -}; -uint32_t ID_SIZE[16]={0}; - -void config_cpri_map_directed(uint32_t option,uint32_t MappingMode) -{ - uint64_t addr; - - - if(8 == option) - { - if(OTIC_MAP_FIGURE12 == MappingMode) - { - memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64); - } - else if(OTIC_MAP_FIGURE10 == MappingMode) - { - memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[1], 64); - } - } - else if(10 == option) - { - if(OTIC_MAP_FIGURE16 == MappingMode) - { - memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[2], 64); - } - } - else - { - memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64); - } - - //axc rx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< ID_SIZE[0]*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+0; //id 0 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+1; //id 1 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+2; //id 2 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+3; //id 3 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+4; //id 4 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+5; //id 5 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+6; //id 6 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+7; //id 7 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+8; //id 8 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+9; //id 9 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+10; //id 10 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+11; //id 11 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+12; //id 12 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+13; //id 13 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+14; //id 14 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14]+ID_SIZE[15])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+15; //id 15 - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = 0; - } - } - - //axc tx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< ID_SIZE[0]*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[0]<<16) + ((addr/4)<<8) + BIT7+0; //id 0 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[1]<<16) + ((addr/4)<<8) + BIT7+1; //id 1 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[2]<<16) + ((addr/4)<<8) + BIT7+2; //id 2 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[3]<<16) + ((addr/4)<<8) + BIT7+3; //id 3 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[4]<<16) + ((addr/4)<<8) + BIT7+4; //id 4 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[5]<<16) + ((addr/4)<<8) + BIT7+5; //id 5 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[6]<<16) + ((addr/4)<<8) + BIT7+6; //id 6 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[7]<<16) + ((addr/4)<<8) + BIT7+7; //id 7 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[8]<<16) + ((addr/4)<<8) + BIT7+8; //id 8 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[9]<<16) + ((addr/4)<<8) + BIT7+9; //id 9 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[10]<<16) + ((addr/4)<<8) + BIT7+10; //id 10 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[11]<<16) + ((addr/4)<<8) + BIT7+11; //id 11 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[12]<<16) + ((addr/4)<<8) + BIT7+12; //id 12 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[13]<<16) + ((addr/4)<<8) + BIT7+13; //id 13 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[14]<<16) + ((addr/4)<<8) + BIT7+14; //id 14 - } - else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14]+ID_SIZE[15])*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[15]<<16) + ((addr/4)<<8) + BIT7+15; //id 15 - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = 0; - } - } - - if(8 == option) - { - if(OTIC_MAP_FIGURE12 == MappingMode)//#ifdef CPRI_TIMING_7D2U_TEST - { - //map tx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< 5*4) - { - // op 0:pass 1:right 2:left 3:clr - //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64+8)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64+8+1)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - //(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0; - } - } - - //map rx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< 5*4) - { - // op 0:pass 1:right 2:left 3:clr - //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64+8)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64+8+1)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - //(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0; - } - } - } - if(OTIC_MAP_FIGURE10 == MappingMode) - { - //map tx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< 5*4) - { - // op 0:pass 1:right 2:left 3:clr - //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP - if(addr< 4*4) - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - else - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2)*4) - { - // (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (48<<8)+(1<<14)+(32<<16)+(1<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64+8)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - #if 0 - if(addr< (5+2+64+7)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else//获取NR AGC - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(0<<22)+(0<<24)+(3<<30); - } - #endif - } - else if(addr< (5+2+64+8+1)*4) - { - //(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (56<<8)+(1<<14)+(40<<16)+(1<<22)+(0<<24)+(3<<30); - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (40<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0; - } - } - - //map rx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< 5*4) - { - // op 0:pass 1:right 2:left 3:clr - //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - - } - else if(addr< (5+2)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(48<<16)+(2<<22)+(0<<24)+(3<<30); - - } - else if(addr< (5+2+64)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64+8)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); - } - else if(addr< (5+2+64+8+1)*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (40<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - // addr = addr +4; - // (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0 + BIT4 + BIT5 + (56<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0; - } - } - } - } - - if(10 == option) - { - if(OTIC_MAP_FIGURE16 == MappingMode) - { - //map tx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< 12*4) - { - // op 0:pass 1:right 2:left 3:clr - //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP - if(addr< 11*4) - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - } - else if(addr< (12+2)*4)//compress - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (48<<8)+(1<<14)+(32<<16)+(1<<22)+(0<<24)+(3<<30); //need to confirm location - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (12+2+64)*4)//NR小区0 - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (12+2+64+64)*4)//NR小区1 - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - } - else if(addr< (12+2+64+64+49)*4)//Reserve - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - } - else if(addr< (12+2+64+64+49+1)*4)//Agc - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0; - } - } - - //map rx cfg - for(addr = 0; addr<0x400;addr = addr +4) - { - if(addr< 12*4) - { // op 0:pass 1:right 2:left 3:clr - //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - - } - else if(addr< (12+2)*4)//compress - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//Compress NR小区0 - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(48<<16)+(2<<22)+(0<<24)+(3<<30);//Compress NR小区1 - - } - else if(addr< (12+2+64)*4)//NR小区0 - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); - } - else if(addr< (12+2+64+64)*4)//NR小区1 - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); - addr = addr +4; - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); - } - else if(addr< (12+2+64+64+49)*4)//Reserve - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - } - else if(addr< (12+2+64+64+49+1)*4)//AGC - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location - } - else - { - (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0; - } - } - - } - } - - CPRI_MAP_TOGGLE = BIT0; - //start_cpri_map(); -} - -void start_cpri_map(void) -{ -// CPRI_MAP_CFG = BIT4|BIT0;//enable map Tx and Rx - - do_write((&CPRI_MAP_CFG), (BIT4|BIT0)); -// do_write((&CPRI_MAP_CFG), BIT0); - -} - -void stop_cpri_map(void) -{ -// CPRI_MAP_CFG = BIT4|BIT0;//enable map Tx and Rx - - do_write((&CPRI_MAP_CFG), BIT0); - -} - -/*****************GMAC******************/ -/**************** - dma_ch:Queue0~7 - Tx_des_base:基地址 - Rx_des_base:基地址 -***********************/ -#if 0 -void init_cprigmac(uint32_t dma_ch,uint32_t Tx_des_base,uint32_t Rx_des_base) -{ - uint32_t i; - - JECS_CRG_CPRI1_CLK_CTRL = 0x527000;//for rx gmii 125M - JECS_CRG_CPRI2_CLK_CTRL = 0x527000;//for tx gmii 125M - //SET 1000M - GMAC2_MAC_Configuration = 0x00002003;//bit13:0代表全双工；bit14:15:1Gbps - //enable 4 rx q Queue enabled for DCB/Generic - GMAC2_MAC_RxQ_Ctrl0 = 0x000000aa; - // routing of multicast, broadcast, AV,DCB, and untagged packets to to the Rx queues - GMAC2_MAC_RxQ_Ctrl1 = 0x00000000+(dma_ch<<8)+(dma_ch<<4)+(dma_ch<<12)+(dma_ch<<16); - //set 4 rx q Priorities - GMAC2_MAC_RxQ_Ctrl2 = 0x08040201; - //VLAN Tag in Rx status is enabled and Always strip VLAN Tag - GMAC2_MAC_VLAN_Tag = 0x01600000; - //recv all packet Hash or Perfect Filter is enabled - GMAC2_MAC_Packet_Filter = 0x80000400; - //set mac for channel 0-3 - //GMAC2_MAC_Address0_High = 0x80000607; - //GMAC2_MAC_Address1_High = 0x80011607; - //GMAC2_MAC_Address2_High = 0x80022607; - //GMAC2_MAC_Address3_High = 0x80033607; - //GMAC2_MAC_Address0_Low = 0x08090a00; - //GMAC2_MAC_Address1_Low = 0x08090a00; - //GMAC2_MAC_Address2_Low = 0x08090a00; - //GMAC2_MAC_Address3_Low = 0x08090a00; - GMAC2_MAC_Ext_Configuration = 0; - GMAC2_MAC_Ext_Configuration = 0; - GMAC2_MAC_Ext_Configuration = 0; - GMAC2_MAC_Ext_Configuration = 0; - //SET Tran queue size 1 Transmit Queue Enable Transmit Store and Forward - //When this bit is set, the transmission starts when a full packet - //resides in the MTL Tx queue. - GMAC2_MTL_TxQ0_Operation_Mode = 0x0001000a; - GMAC2_MTL_TxQ1_Operation_Mode = 0x0001000a; - GMAC2_MTL_TxQ2_Operation_Mode = 0x0001000a; - GMAC2_MTL_TxQ3_Operation_Mode = 0x0001000a; - //set Quantum or Weights - GMAC2_MTL_TxQ0_Quantum_Weight = 0x5; - GMAC2_MTL_TxQ1_Quantum_Weight = 0x5; - GMAC2_MTL_TxQ2_Quantum_Weight = 0x14; - GMAC2_MTL_TxQ3_Quantum_Weight = 0x14; - //set0 - GMAC2_MTL_Operation_Mode = 0; - //set Receive Queue Threshold Control 128 bytes - //drop err packet recv less 64 packet - GMAC2_MTL_RxQ0_Operation_Mode = 0xf00033; - GMAC2_MTL_RxQ1_Operation_Mode = 0xf00033; - GMAC2_MTL_RxQ2_Operation_Mode = 0xf00033; - GMAC2_MTL_RxQ3_Operation_Mode = 0xf00033; - //rx q0 for dma0 q1 for dma1 q2 for dma2 q3 for dma3 - GMAC2_MTL_RxQ_DMA_Map0 = 0x03020100; - //GMAC2_MTL_RxQ_DMA_Map1 = 0x07060504; - //set Receive Queue Threshold Control 128 bytes - //drop err packet recv less 64 packet - //RQS 1 - GMAC2_MTL_RxQ0_Operation_Mode = 0x00f00033; - GMAC2_MTL_RxQ1_Operation_Mode = 0x00f00033; - GMAC2_MTL_RxQ2_Operation_Mode = 0x00f00033; - GMAC2_MTL_RxQ3_Operation_Mode = 0x00f00033; - //Receive Queue Overflow Interrupt Enable - //Transmit Queue Underflow Interrupt Enable - GMAC2_MTL_Q0_Interrupt_Control_Status = 0X01000100; - GMAC2_MTL_Q1_Interrupt_Control_Status = 0X01000100; - GMAC2_MTL_Q2_Interrupt_Control_Status = 0X01000100; - GMAC2_MTL_Q3_Interrupt_Control_Status = 0X01000100; - //Receive Queue Packet Arbitration is enable and weight 3 - GMAC2_MTL_RxQ0_Control = 0X00000007; - GMAC2_MTL_RxQ1_Control = 0X00000007; - GMAC2_MTL_RxQ2_Control = 0X00000007; - GMAC2_MTL_RxQ3_Control = 0X00000007; - //Transmit Programmable Burst Length = 16 Transmit Channel Weight = 3 - GMAC2_DMA_CH0_Tx_Control = 0x00100006; - GMAC2_DMA_CH1_Tx_Control = 0x00100006; - GMAC2_DMA_CH2_Tx_Control = 0x00100006; - GMAC2_DMA_CH3_Tx_Control = 0x00100006; - //DMA descriptor - GMAC2_DMA_CH0_TxDesc_List_Address = Tx_des_base ; - GMAC2_DMA_CH1_TxDesc_List_Address = Tx_des_base ; - GMAC2_DMA_CH2_TxDesc_List_Address = Tx_des_base ; - GMAC2_DMA_CH3_TxDesc_List_Address = Tx_des_base ; - //ring 1f - GMAC2_DMA_CH0_TxDesc_Ring_Length = 0x3ff; - GMAC2_DMA_CH1_TxDesc_Ring_Length = 0x3ff; - GMAC2_DMA_CH2_TxDesc_Ring_Length = 0x3ff; - GMAC2_DMA_CH3_TxDesc_Ring_Length = 0x3ff; - //set axi mode - GMAC2_DMA_SysBus_Mode = 0x0103000e + BIT11; - //set mode - - GMAC2_DMA_CH0_Control = 0; - GMAC2_DMA_CH1_Control = 0; - GMAC2_DMA_CH2_Control = 0; - GMAC2_DMA_CH3_Control = 0; - //Receive Programmable Burst Length 16 Receive Buffer size 4K - GMAC2_DMA_CH0_Rx_Control = 0x00101000; - GMAC2_DMA_CH1_Rx_Control = 0x00101000; - GMAC2_DMA_CH2_Rx_Control = 0x00101000; - GMAC2_DMA_CH3_Rx_Control = 0x00101000; - //DMA descriptor - GMAC2_DMA_CH0_RxDesc_List_Address = Rx_des_base ; - GMAC2_DMA_CH1_RxDesc_List_Address = Rx_des_base ; - GMAC2_DMA_CH2_RxDesc_List_Address = Rx_des_base ; - GMAC2_DMA_CH3_RxDesc_List_Address = Rx_des_base ; - //ring 1f - GMAC2_DMA_CH0_RxDesc_Ring_Length = 0X3Ff; - GMAC2_DMA_CH1_RxDesc_Ring_Length = 0X3Ff; - GMAC2_DMA_CH2_RxDesc_Ring_Length = 0X3Ff; - GMAC2_DMA_CH3_RxDesc_Ring_Length = 0X3Ff; - //int en - GMAC2_DMA_CH0_Interrupt_Enable = 0x0000f0df; - GMAC2_DMA_CH1_Interrupt_Enable = 0x0000f0df; - GMAC2_DMA_CH2_Interrupt_Enable = 0x0000f0df; - GMAC2_DMA_CH3_Interrupt_Enable = 0x0000f0df; - - GMAC2_DMA_Mode = 0; - - // sunny modify // -#if 0 - for(i=0;i<10;i++){ - //write descriptor - (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+0ul ))) = RX_DES_BASE + 0x08000000 + i*0x800;//4EE1 - (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+4ul ))) = 0 ; - (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+8ul ))) = RX_DES_BASE + 0x08000000 + i*0x800 + 0x40 ; - (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+12ul))) = 0xc1000000 ; - } -#endif - - switch(dma_ch){ - case 0x0 : GMAC2_DMA_CH0_RxDesc_Tail_Pointer = GMAC2_DMA_CH0_RxDesc_List_Address + 0x10*50; break; - case 0x1 : GMAC2_DMA_CH1_RxDesc_Tail_Pointer = GMAC2_DMA_CH1_RxDesc_List_Address + 0x10*50; break; - case 0x2 : GMAC2_DMA_CH2_RxDesc_Tail_Pointer = GMAC2_DMA_CH2_RxDesc_List_Address + 0x10*50; break; - case 0x3 : GMAC2_DMA_CH3_RxDesc_Tail_Pointer = GMAC2_DMA_CH3_RxDesc_List_Address + 0x10*50; break; - } - -// clean_all_cache(); - //start dma rx - switch(dma_ch){ - case 0x0 :GMAC2_DMA_CH0_Rx_Control |= BIT0; break; - case 0x1 :GMAC2_DMA_CH1_Rx_Control |= BIT0; break; - case 0x2 :GMAC2_DMA_CH2_Rx_Control |= BIT0; break; - case 0x3 :GMAC2_DMA_CH3_Rx_Control |= BIT0; break; - } - -} -#endif - -/***********************AUX interface**********************/ -void AUX_Rx_init(uint32_t Buffer0,uint32_t Buffer1,uint32_t Len0,uint32_t Len1) -{ - -// AWADDR0 = Buffer0;//axi首地址寄存器0 -// AXI_LEN0 = Len0; //axi长度寄存器0 -// AWADDR1 = Buffer1;//axi首地址寄存器1 -// AXI_LEN1 = Len1; //axi长度寄存器1 - do_write(&AWADDR0,Buffer0); - do_write(&AXI_LEN0,Len0); - do_write(&AWADDR1,Buffer1); - do_write(&AXI_LEN1,Len1); - -} -/************************************ -Axi_mode: - 01:写完第一块buffer停住 - 10：写完两块buffer停住 - 11:来回写两块buffer -*************************************/ -void AUX_Rx_enable(uint32_t Axi_mode) -{ - AUX_CTRL_REG |= (Axi_mode<<16);//bit17:16表示axi_mode:0x01:表示写完第一块buffer停住；0x10:写完两块buffer停住；0x11来回写两块buffer -} - -void AUX_Rx_Disable() -{ - - AUX_CTRL_REG &= 0xFFFCFFFF;//bit17:16 :0,axi disable，and aux_rx disable -} - - -void AUX_Tx_enable() -{ - - AUX_CTRL_REG |= BIT0;//bit0:aux_tx start -} - -void AUX_Tx_Disable() -{ - - AUX_CTRL_REG &= 0xFFFFFFFE;//bit0:aux_tx disable -} - - -/************************************** parameter description*************************** - uint32_t Num :tx aux插入点的个数，有效值为1~10; - uint32_t DATA_CNT[] :在一个Hyper Frame里，插入basic frame的位置，有效值为0~255; - uint32_t DATA_CNT_POS[] :在一个basic frame里，插入的位置，有效值根据速率而定（根据CPRI 6.1 IP手册,Table 7-7，Figure 7-10）; - //DATA_CNT_POS[] - //6:40; - //9:64; - //8:64; - //10:80; - //12:96; - //24:192; -***********************************************************************************/ - -void AUX_Data_insert(uint32_t Num,uint8_t DATA_CNT[],uint8_t DATA_CNT_POS[],uint32_t DATA_TX[],uint32_t DATA_EN[]) -{ - //AUX_CTRL_REG = BIT0;//enable aux tx - - AUX_INS_NUM = Num;//AUX_INS_NUM[3:0]:tx aux插入点的个数，有效值为1~10 - - /*******插入数据帧寄存器:DATA_CNT_X0/DATA_CNT_X1/DATA_CNT_X2*************** - DATA_CNT_X0[31:24]:插入帧3 aux_cnt_x3 - DATA_CNT_X0[23:16]:插入帧2 aux_cnt_x2 - DATA_CNT_X0[15:8] :插入帧1 aux_cnt_x1 - DATA_CNT_X0[7:0] :插入帧0 aux_cnt_x0 - - DATA_CNT_X1[31:24]:插入帧3 aux_cnt_x7 - DATA_CNT_X1[23:16]:插入帧2 aux_cnt_x6 - DATA_CNT_X1[15:8] :插入帧1 aux_cnt_x5 - DATA_CNT_X1[7:0] :插入帧0 aux_cnt_x4 - - DATA_CNT_X2[31:16]:reserved - DATA_CNT_X2[15:8] :插入帧1 aux_cnt_x1 - DATA_CNT_X2[7:0] :插入帧0 aux_cnt_x0 - *****************************************************************************/ - DATA_CNT_X0 = (DATA_CNT[3]<<24)+(DATA_CNT[2]<<16)+(DATA_CNT[1]<<8)+DATA_CNT[0]; - DATA_CNT_X1 = (DATA_CNT[7]<<24)+(DATA_CNT[6]<<16)+(DATA_CNT[5]<<8)+DATA_CNT[4]; - DATA_CNT_X2 = (DATA_CNT[9]<<8)+DATA_CNT[8]; - - /******插入数据位置寄存器:DATA_CNT_POS0/DATA_CNT_POS1/DATA_CNT_POS2******* - DATA_CNT_POS0[31:24]:插入位置3 aux_cnt_pos3 - DATA_CNT_POS0[23:16]:插入位置2 aux_cnt_pos2 - DATA_CNT_POS0[15:8] :插入位置1 aux_cnt_pos1 - DATA_CNT_POS0[7:0] :插入位置0 aux_cnt_pos0 - - DATA_CNT_POS1[31:24]:插入位置7 aux_cnt_pos7 - DATA_CNT_POS1[23:16]:插入位置6 aux_cnt_pos6 - DATA_CNT_POS1[15:8] :插入位置5 aux_cnt_pos5 - DATA_CNT_POS1[7:0] :插入位置4 aux_cnt_pos4 - - DATA_CNT_POS2[31:16]:reserved - DATA_CNT_POS2[15:8] :插入位置9 aux_cnt_pos9 - DATA_CNT_POS2[7:0] :插入位置8 aux_cnt_pos8 - *****************************************************************************/ - DATA_CNT_POS0 = (DATA_CNT_POS[3]<<24)+(DATA_CNT_POS[2]<<16)+(DATA_CNT_POS[1]<<8)+DATA_CNT_POS[0]; - DATA_CNT_POS1 = (DATA_CNT_POS[7]<<24)+(DATA_CNT_POS[6]<<16)+(DATA_CNT_POS[5]<<8)+DATA_CNT_POS[4]; - DATA_CNT_POS2 = (DATA_CNT_POS[9]<<8)+DATA_CNT_POS[8]; - - /* AUX_DATA_TX0~9[31:0]:插入data值 32bit*/ - AUX_DATA_TX0 = DATA_TX[0]; - AUX_DATA_TX1 = DATA_TX[1]; - AUX_DATA_TX2 = DATA_TX[2]; - AUX_DATA_TX3 = DATA_TX[3]; - AUX_DATA_TX4 = DATA_TX[4]; - AUX_DATA_TX5 = DATA_TX[5]; - AUX_DATA_TX6 = DATA_TX[6]; - AUX_DATA_TX7 = DATA_TX[7]; - AUX_DATA_TX8 = DATA_TX[8]; - AUX_DATA_TX9 = DATA_TX[9]; - - /* AUX_DATA_EN0~9:插入data按位使能 */ - AUX_DATA_EN0 = DATA_EN[0];//0xffffff00; - AUX_DATA_EN1 = DATA_EN[1];//0xffff00ff; - AUX_DATA_EN2 = DATA_EN[2];//0xff00ffff; - AUX_DATA_EN3 = DATA_EN[3];//0x00ffffff; - AUX_DATA_EN4 = DATA_EN[4];//0xffffffff; - AUX_DATA_EN5 = DATA_EN[5];//0xffffffff; - AUX_DATA_EN6 = DATA_EN[6];//0xffffffff; - AUX_DATA_EN7 = DATA_EN[7];//0xffffffff; - AUX_DATA_EN8 = DATA_EN[8];//0xffffffff; - AUX_DATA_EN9 = DATA_EN[9];//0xffffffff; - -} - - -/************************************** parameter description 同AUX_Data_insert()***************************/ - -void AUX_Ctrl_insert(uint32_t Num,uint8_t CTRL_CNT[],uint8_t CTRL_CNT_POS[],uint8_t CTRL_TX[],uint8_t CTRL_EN[]) -{ - /*************插入控制寄存器：CTRL_CNT_X0/CTRL_CNT_X1/CTRL_CNT_X2 - CTRL_CNT_X0[31:24]:插入控制帧3 ctrl_cnt_x3 - CTRL_CNT_X0[23:16]:插入控制帧2 ctrl_cnt_x2 - CTRL_CNT_X0[15:8] :插入控制帧1 ctrl_cnt_x1 - CTRL_CNT_X0[7:0] :插入控制帧0 ctrl_cnt_x0 - - CTRL_CNT_X1[31:24]:插入控制帧3 ctrl_cnt_x7 - CTRL_CNT_X1[23:16]:插入控制帧2 ctrl_cnt_x6 - CTRL_CNT_X1[15:8] :插入控制帧1 ctrl_cnt_x5 - CTRL_CNT_X1[7:0] :插入控制帧0 ctrl_cnt_x4 - - CTRL_CNT_X2[31:16]:reserved - CTRL_CNT_X2[15:8] :插入控制帧1 ctrl_cnt_x1 - CTRL_CNT_X2[7:0] :插入控制帧0 ctrl_cnt_x8 - *****************************************************************/ - CTRL_CNT_X0 = (CTRL_CNT[3]<<24)+(CTRL_CNT[2]<<16)+(CTRL_CNT[1]<<8)+CTRL_CNT[0]; - CTRL_CNT_X1 = (CTRL_CNT[7]<<24)+(CTRL_CNT[6]<<16)+(CTRL_CNT[5]<<8)+CTRL_CNT[4]; - CTRL_CNT_X2 = (CTRL_CNT[9]<<8)+CTRL_CNT[8]; - - /*************插入控制位置寄存器：CTRL_CNT_POS0/CTRL_CNT_POS1/CTRL_CNT_POS2 - CTRL_CNT_POS0[31:24]:插入控制位置3 ctrl_cnt_pos3 - CTRL_CNT_POS0[23:16]:插入控制位置2 ctrl_cnt_pos2 - CTRL_CNT_POS0[15:8] :插入控制位置1 ctrl_cnt_pos1 - CTRL_CNT_POS0[7:0] :插入控制位置0 ctrl_cnt_pos0 - - CTRL_CNT_POS1[31:24]:插入控制位置3 ctrl_cnt_pos7 - CTRL_CNT_POS1[23:16]:插入控制位置2 ctrl_cnt_pos6 - CTRL_CNT_POS1[15:8] :插入控制位置1 ctrl_cnt_pos5 - CTRL_CNT_POS1[7:0] :插入控制位置0 ctrl_cnt_pos4 - - CTRL_CNT_POS2[31:16]:reserved - CTRL_CNT_POS2[15:8] :插入控制位置1 ctrl_cnt_pos1 - CTRL_CNT_POS2[7:0] :插入控制位置0 ctrl_cnt_pos0 - *****************************************************************/ - CTRL_CNT_POS0 = (CTRL_CNT_POS[3]<<24)+(CTRL_CNT_POS[2]<<16)+(CTRL_CNT_POS[1]<<8)+CTRL_CNT_POS[0]; - CTRL_CNT_POS1 = (CTRL_CNT_POS[7]<<24)+(CTRL_CNT_POS[6]<<16)+(CTRL_CNT_POS[5]<<8)+CTRL_CNT_POS[4]; - CTRL_CNT_POS2 = (CTRL_CNT_POS[9]<<8)+CTRL_CNT_POS[8]; - - /* AUX_DATA_TX0~9[31:0]:插入控制值 4bit*/ - AUX_CTRL_TX0 = ((CTRL_TX[7]&0xf)<<28)+((CTRL_TX[6]&0xf)<<24)+((CTRL_TX[5]&0xf)<<20)+((CTRL_TX[4]&0xf)<<16)+((CTRL_TX[3]&0xf)<<12)+((CTRL_TX[2]&0xf)<<8)+((CTRL_TX[1]&0xf)<<4)+ (CTRL_TX[0]&0xf);//aux_ctrl_tx0~7,bit0:3,bit4:7,bit8:11,bit12:15,bit16:19,bit20:23,bit24:27,bit28:31 - AUX_CTRL_TX1 = ((CTRL_TX[9]&0xf)<<4)+ (CTRL_TX[8]&0xf);//aux_ctrl_tx8~9,bit0:3,bit4:7 - - /* AUX_DATA_TX0~9[31:0]:插入data值 4bit*/ - AUX_CTRL_EN_TX0 =((CTRL_EN[7]&0xf)<<28)+((CTRL_EN[6]&0xf)<<24)+((CTRL_EN[5]&0xf)<<20)+((CTRL_EN[4]&0xf)<<16)+((CTRL_EN[3]&0xf)<<12)+((CTRL_EN[2]&0xf)<<8)+((CTRL_EN[1]&0xf)<<4)+ (CTRL_EN[0]&0xf);//aux_ctrl_en_tx0~7,bit0:3,bit4:7,bit8:11,bit12:15,bit16:19,bit20:23,bit24:27,bit28:31 - AUX_CTRL_EN_TX1 = ((CTRL_EN[9]&0xf)<<4)+ (CTRL_EN[8]&0xf);//aux_ctrl_en_tx8~9,bit0:3,bit4:7 - -} - -/*******************HeaderRam************* -note:插入控制字，AUX优先级高于HeaderRam**/ - -void HeaderRam_ins_enable() -{ - //CPRI_FRAME_TX_CFG |= BIT5;//Enable TX CTRL HeaderRam insertion - - uint32_t val = do_read_volatile(&CPRI_FRAME_TX_CFG); - val |= BIT5; - do_write(&CPRI_FRAME_TX_CFG,val); -} -void HeaderRam_ins_disable() -{ - //CPRI_FRAME_TX_CFG &= (~BIT5);//disable TX CTRL HeaderRam insertion - - uint32_t val = do_read_volatile(&CPRI_FRAME_TX_CFG); - val &= (~BIT5); - do_write(&CPRI_FRAME_TX_CFG,val); -} - -//uint32_t BF_X:基本帧号 -//uint32_t BF_Ctrlword_wordnum:该基本帧的控制字的第几个32bit -//uint32_t Hdr_Data：要insert的数据 -void HeaderRam_Tx(uint32_t BF_X,uint32_t BF_Ctrlword_wordnum,uint32_t Hdr_Data,uint32_t Hdr_Data_en) -{ - //CPRI_FRAME_TX_HDR_ADDR = 0xF000000+(BF_X<<2)+BF_Ctrlword_wordnum*4;//bit27:24 每个bit位对应data的1个字节的插入使能 ;Hdr_Addr needs to be shifted <<2 to point #X value - //CPRI_FRAME_TX_HDR_DATA =Hdr_Data; - -// do_write(&CPRI_FRAME_TX_HDR_ADDR,0xF000000+(BF_X<<2)+BF_Ctrlword_wordnum); - do_write(&CPRI_FRAME_TX_HDR_ADDR,(Hdr_Data_en<<24)+(BF_X<<2)+BF_Ctrlword_wordnum); - do_write(&CPRI_FRAME_TX_HDR_DATA,Hdr_Data); -} - - -uint32_t HeaderRam_Rx(uint32_t BF_X,uint32_t BF_Ctrlword_wordnum) -{ - uint32_t Hdr_data =0; - - //CPRI_FRAME_RX_HDR_ADDR = (BF_X<<2)+BF_Ctrlword_wordnum*4;//Hdr_Addr needs to be shifted <<2 to point #X value,ie:X=16,Hdr_addr = 0x40; - //Hdr_data = CPRI_FRAME_RX_HDR_DATA; - - do_write(&CPRI_FRAME_RX_HDR_ADDR,(BF_X<<2)+BF_Ctrlword_wordnum); - __ucps2_synch(f_SM); - //do_write(&CPRI_FRAME_RX_HDR_ADDR,(BF_X<<2)+BF_Ctrlword_wordnum); - Hdr_data = do_read_volatile(&CPRI_FRAME_RX_HDR_DATA); - - if(BF_Ctrlword_wordnum == 3) - { - do_write(&CPRI_FRAME_RX_HDR_ADDR,(BF_X<<2)); - } - //if(BF_Ctrlword_wordnum <= 3) - { -// do_write(&CPRI_FRAME_RX_HDR_ADDR,3); - } - return Hdr_data; -} - - -uint32_t UCP_API_CPRI_GetHfnsyncFlag() -{ - uint32_t Flag =0; - //Flag = (AUX_INT_FLAG & BIT2);//Hfnsync - - Flag = ((do_read_volatile(&AUX_INT_FLAG)) & BIT2); - return Flag; -} - - -uint32_t UCP_API_CPRI_GetBuffer1FullFlag() -{ - uint32_t Flag =0; - //Flag = (AUX_INT_FLAG & BIT4);//buffer1 full - - Flag = ((do_read_volatile(&AUX_INT_FLAG)) & BIT4); - return Flag; -} - - -uint32_t UCP_API_CPRI_GetTxHfnCnt() -{ - uint32_t TxHfnCnt =0; - //Cnt = (AUX_CNT0 & 0xFF);// - TxHfnCnt = ((do_read_volatile(&AUX_CNT0)) & 0xFF); - return TxHfnCnt; -} - -uint32_t UCP_API_CPRI_GetTxXCnt() -{ - uint32_t TxXCnt =0; - //Cnt = ((AUX_CNT0 >>8) & 0xFF);// - TxXCnt = (((do_read_volatile(&AUX_CNT0)) >> 8) & 0xFF); - return TxXCnt; -} - -uint32_t UCP_API_CPRI_GetRxHfnCnt() -{ - uint32_t RxHfnCnt =0; - //Cnt = (AUX_CNT0 & 0xFF);// - RxHfnCnt = ((do_read_volatile(&AUX_CNT2)) & 0xFF); - return RxHfnCnt; - -} - -void HeaderTxRam_init(uint32_t vendor) -{ - uint32_t i,j; - HeaderRam_ins_disable(); - for(i=0;i<64;i++)//Ns - { - for(j=0;j<4;j++)// - { - HeaderRam_Tx(i+64*j,0,0,0);//vendor - HeaderRam_Tx(i+64*j,1,0,0);//vendor - HeaderRam_Tx(i+64*j,2,0,0);//vendor - HeaderRam_Tx(i+64*j,3,0,0);//vendor - } - } - do_write(&CPRI_FRAME_RX_HDR_ADDR,0); - __ucps2_synch(f_SM); - do_write(&gVendorFlag,vendor); -} -uint8_t SECTION_ALIGNED g_rru_msg_data[CPRI_RRU_MSG_LEN]; -uint8_t g_rru_msg_data[CPRI_RRU_MSG_LEN]; -int32_t set_cpri_rru_msg(CpriRruMsg_t rru_msg) -{ - if ((0 == rru_msg.msg_addr) || (0 == rru_msg.msg_len)) - { - return -1; - } - - for(int i=0; i<41; i++) - { - *((uint32_t *)&g_rru_msg_data[0] + i) = SWAP32(*((uint32_t *)rru_msg.msg_addr + i)); - } - -// memcpy_ucp(&g_rru_msg_data, (uint8_t*)rru_msg.msg_addr, rru_msg.msg_len); - return 0; -} -uint32_t get_cpri_rru_msg_addr() -{ - return (uint32_t)g_rru_msg_data; -} +#include "cpri_driver.h" + +#include "ucp_param.h" +#include "ucp_cpri.h" +#include "ucp_js_ctrl.h" +#include "ucp_js_subcrg.h" +#include "ucp_pet_ctrl.h" +#include "ucp_pma.h" +#include "dw_gmac.h" +#include "hw_cpri.h" +#include "cpri_csu.h" +#include "ucp_drv_common.h" +#include "ucp_printf.h" +#include "ucp_utility.h" +#include "mem_sections.h" +#include "ucp_sfr_c.h" +#include "phy_para.h" + +//#define CPRI_SPEED 8//option 8 + +//8 option8 10137.6Mbit/s 64B/66B +//7 option7 9830.4Mbit/s 8B/10B +//10 option10 24330.24Mbit/s 64B/66B +extern DDR0 uint32_t pma_fw[16384*2]; +//extern volatile int32_t gCpriSyncIntCnt; +extern volatile uint32_t gVendorFlag; + +uint32_t PLLSEL_temp = 0; +//切换xtal_clk时钟 +void Clk_To_XTAL() +{ + do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x121000); //暂停输出core时钟 + PLLSEL_temp = do_read_volatile(&JECS_CRG_PLLSEL); + do_write(&JECS_CRG_PLLSEL, (PLLSEL_temp&0xF87FFFF0)|(BIT23)|(BIT3));//ecs pll选择xtal_clk时钟输入并输出给cpri core div + do_write(&ESP_CLK_CFG_REG, 0x121000); //暂停apb时钟输出 + do_write(&CLK_CTL_REG1, ((do_read_volatile(&CLK_CTL_REG1))&(~BIT2))); //切换PLL2时钟源为xtal_clk时钟 + do_write(&ESP_CLK_CFG_REG, 0x521000); //使能apb时钟输出 + do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x520000); //使能输出core时钟 + +} + +//恢复正常 +void Clk_To_Normal() +{ + + do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x121000); //暂停输出core时钟 + do_write(&JECS_CRG_PLLSEL, PLLSEL_temp); //切换CORE时钟源为正常的PMA TX给cpri core div + do_write(&ESP_CLK_CFG_REG, 0x121000); //暂停apb时钟输出 + do_write(&CLK_CTL_REG1, do_read_volatile(&CLK_CTL_REG1) | BIT2);//切换PLL2时钟为PLL2输出时钟 + do_write(&ESP_CLK_CFG_REG, 0x524000); //使能apb时钟输出 + do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x520000); //使能输出core时钟 + +} +/***************************CPRI*************************/ +void Init_cpri_clk(uint32_t cpri_speed_sel) +{ + if(cpri_speed_sel <= 7)//8B/10B + { + //JECS_CRG_PLLSEL |= BIT24;//IP REC MODE + do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | BIT24); + //cdr div clk output divided by 4 + JECS_CRG_CPRI_CDR_CLK_CTRL = 0x523000; + //u_cpri_core_div div cfg + JECS_CRG_CPRI_CORE_CLK_CTRL = 0x521000; + //u_cpri_pcs_core_div div cfg + JECS_CRG_CPRI_PCS_CORE_CLK_CTRL = 0x520000; + } + else //64B/66B + { + // JECS_CRG_PLLSEL |= (BIT26|BIT24);//IP REC MODE + do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT26|BIT24)); + //cdr div clk output divided by 11 + do_write(&JECS_CRG_CPRI_CDR_CLK_CTRL, 0x52a000); + //u_cpri_core_div div cfg + //JECS_CRG_CPRI_CORE_CLK_CTRL = 0x520000; + do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x520000); + //u_cpri_pcs_core_div div cfg + // JECS_CRG_CPRI_PCS_CORE_CLK_CTRL = 0x521000; + do_write(&JECS_CRG_CPRI_PCS_CORE_CLK_CTRL, 0x521000); + } + ucp_nop(400); + //JECS_CRG_PLLSEL &= (~BIT4); //？？？ + do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) &(~BIT4)); + ucp_nop(400); + //(*((volatile uint32_t *)(JS_CRG_BASE + 4*11))) = 0x520000; + //JS_CRG_SAM3_CLK_CTRL = 0x520000; + do_write(&JS_CRG_SAM3_CLK_CTRL, 0x520000); + ucp_nop(400); +} + +#if 0 +void Init_config_cpri(uint32_t cpri_speed_sel) +{ + switch(cpri_speed_sel) + { + case 7: + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + CPRI_FRAME_RX_CFG = 0x10|BIT8;//bit9:Default 150 HF=10ms mode & bit0:7;cfg_frm_rate set & bit8:enable Extract Control AxC data to external port + CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 + CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 + CPRI_FRAME_TX_SCRAMBLER = 0x61cd; + break; + + case 8: + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + CPRI_FRAME_RX_CFG = 0x14|BIT8;//bit9:short frame mode & bit0:7;cfg_frm_rate set & bit8:enable Extract Control AxC data to external port + CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 + CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 + CPRI_FRAME_TX_SCRAMBLER = 0x0; + break; + + case 10: + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + CPRI_FRAME_RX_CFG = 0x30|BIT8;//bit9:short frame mode & bit0:7;cfg_frm_rate set & bit8:enable Extract Control AxC data to external port + CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 + CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 + CPRI_FRAME_TX_SCRAMBLER = 0x0; + break; + + default://option 8 + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + CPRI_FRAME_RX_CFG = 0x14|BIT8;//0x70 + CPRI_FRAME_TX_CM_CFG = 0x114; //ethernet pointer designate 20 + CPRI_FRAME_TX_PROT_VER = 0x2;//protocol version2 + CPRI_FRAME_TX_SCRAMBLER = 0x0; + break; + } +/***************move to finish map config + CPRI_MAP_CFG = BIT4|BIT0;//enable map Tx and Rx + CPRI_MAP_TOGGLE = BIT4|BIT0;//Activate config maps + ************************/ + CPRI_FRAME_TX_BFN_INIT = 0x10000;//initial TX BFN value 0,bit16：load BFN;bit11:0,BFN value + + CPRI_FRAME_TX_CFG = BIT2|BIT1;//Default 150 HF=10ms mode&master mode&tx enable&enable insertion of ctrl AxC + +} + +/***********************pcs******************************/ + +void Init_config_pcs(uint32_t cpri_speed_sel) +{ + //cancell cpri's rst + JECS_CRG_CPRI0_RST_CTRL |= BIT24; + JECS_CRG_CPRI1_RST_CTRL |= BIT24; + JECS_CRG_CPRI2_RST_CTRL |= BIT24; + JECS_CRG_CPRI3_RST_CTRL |= BIT24; + JECS_CRG_CPRI4_RST_CTRL |= BIT24; + JECS_CRG_CPRI5_RST_CTRL |= BIT24; + JECS_CRG_CPRI6_RST_CTRL |= BIT24; + ECPRI_RST_CFG_REG |= BIT24; + AUX_CTRL_REG &= (~BIT2); + //delay_us(1); + //ucp_nop(400); + + switch(cpri_speed_sel) + { + case 7: + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + + CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 + CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection + CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 + + CPRI_PCS_ADDR_CFG = 0x1C;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x1;//DATA_CFG + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xB8;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x14<<7|BIT5|BIT14;//DATA_CFG cpri_enable + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xBC;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x14<<7|BIT5|BIT14;//DATA_CFG cpri_enable + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR + CPRI_PCS_DATA_TX_CFG = 0; // RS-FEC disable + CPRI_PCS_CTRL_CFG = 0x2;//WR +// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x1E<<1;//bit8:1： Tx Buffer initial fill =8 +// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 +// +// CPRI_PCS_ADDR_CFG = 0xC4;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x1E<<1;//bit8:1： Rx Buffer initial fill =5 +// CPRI_PCS_CTRL_CFG = 0X2;//WR + break; + + case 8: + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + + CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 + CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection + CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 + + CPRI_PCS_ADDR_CFG = 0x1C;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x0;//DATA_CFG + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xB8;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xBC;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT15;//DATA_CFG with scramble enable + //CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT15;//DATA_CFG Bypass scrambler in 64b/66b decoder + CPRI_PCS_CTRL_CFG = 0x2;//WR + +// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x8<<1;//bit8:1： Tx Buffer initial fill =8 +// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 +#if 1 + CPRI_PCS_ADDR_CFG = 0xC4;//ADDR, CFG_RX + CPRI_PCS_DATA_TX_CFG = BIT10|(3<<1);//DATA_CFG serdes_loopback, bit8:1： Rx Buffer initial fill =3 + CPRI_PCS_CTRL_CFG = 0x2;//WR +#endif + CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR + CPRI_PCS_DATA_TX_CFG = (2<<1); // RS-FEC enable + CPRI_PCS_CTRL_CFG = 0x2;//WR + + break; + + case 10: + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + + CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 + CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection + CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 + + CPRI_PCS_ADDR_CFG = 0x1C;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x0;//DATA_CFG + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xB8;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xBC;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG with scramble enable + //CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT15;//DATA_CFG Bypass scrambler in 64b/66b decoder + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR + CPRI_PCS_DATA_TX_CFG = (2<<1); // RS-FEC enable + CPRI_PCS_CTRL_CFG = 0x2;//WR + +// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x8<<1;//bit8:1： Tx Buffer initial fill =8 +// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 +// +// CPRI_PCS_ADDR_CFG = 0xC4;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x5<<1;//bit8:1： Rx Buffer initial fill =5 +// CPRI_PCS_CTRL_CFG = 0X2;//WR + break; + default://option 8 + CPRI_PCS_64B66B_CFG = 0x0;//0x40 + + CPRI_PCS_ADDR_CFG = 0x0;//ADDR 0x48 + CPRI_PCS_DATA_TX_CFG = BIT13|BIT6;//DATA_CFG 0x4c pcs speed_selection + CPRI_PCS_CTRL_CFG = 0x2;//WR 0x44 + + CPRI_PCS_ADDR_CFG = 0x1C;//ADDR + CPRI_PCS_DATA_TX_CFG = 0x0;//DATA_CFG + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xB8;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable + CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG cpri_enable reser tx + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = 0xBC;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14;//DATA_CFG with scramble enable + CPRI_PCS_DATA_TX_CFG = 0x20<<7|BIT14|BIT0;//DATA_CFG Bypass scrambler in 64b/66b decoder + CPRI_PCS_CTRL_CFG = 0x2;//WR + + CPRI_PCS_ADDR_CFG = RSFEC_CTRL;//ADDR + CPRI_PCS_DATA_TX_CFG = (2<<1); // RS-FEC enable + CPRI_PCS_CTRL_CFG = 0x2;//WR + +// CPRI_PCS_ADDR_CFG = 0xC0;//ADDR +// CPRI_PCS_DATA_TX_CFG = 0x8<<1;//bit8:1： Tx Buffer initial fill =8 +// CPRI_PCS_CTRL_CFG = 0X2;//WR 0x44 +// + CPRI_PCS_ADDR_CFG = 0xC4;//ADDR + CPRI_PCS_DATA_TX_CFG = BIT10|(3<<1);//bit8:1： Rx Buffer initial fill =5 + CPRI_PCS_CTRL_CFG = 0X2;//WR + + } +#if 0 + UINT32 PCS_status; + + /**********配置PCS寄存器REG_RW_GENERAL_TX************/ + CPRI_PCS_ADDR_CFG = 0xB8;//ADDR + CPRI_PCS_DATA_TX_CFG &= 0xFFFE;//bit0:normal operate + CPRI_PCS_CTRL_CFG = 0x2;//WR + + /**********配置PCS寄存器REG_RW_GENERAL_RX************/ + CPRI_PCS_ADDR_CFG = 0xBC;//ADDR + CPRI_PCS_DATA_TX_CFG &= 0xFFFE;//bit0:normal operate + CPRI_PCS_CTRL_CFG = 0x2;//WR + + /**********读取PCS寄存器PCS_STATUS_2************/ + CPRI_PCS_ADDR_CFG = 0x20;//ADDR + CPRI_PCS_CTRL_CFG = 0x1;//Read + PCS_status = CPRI_PCS_DATA_RX_STAT; + while((PCS_status & (BIT10|BIT11)) != 0);//check no fault on Tx and Rx +#endif +// UCP_PRINT_LOG("PCS REG INIT DONE!\r\n"); +} +#endif +/**********************cpri_pma***********************/ + +void init_cpri_pma_rst(void){ +#if 0 + //cancell jecs pma rst + JECS_CRG_PMA16_RST_CTRL |= BIT24; + JECS_CRG_PMA0_RST_CTRL |= BIT24; + JECS_CRG_PMA1_RST_CTRL |= BIT24; + JECS_CRG_PMA2_RST_CTRL |= BIT24; + JECS_CRG_PMA3_RST_CTRL |= BIT24; + JECS_CRG_PMA8_RST_CTRL |= BIT24; + JECS_CRG_PMA9_RST_CTRL |= BIT24; + JECS_CRG_PMA10_RST_CTRL |= BIT24; + JECS_CRG_PMA11_RST_CTRL |= BIT24; + JECS_CRG_PMA12_RST_CTRL |= BIT24; + JECS_CRG_PMA13_RST_CTRL |= BIT24; + JECS_CRG_PMA14_RST_CTRL |= BIT24; + JECS_CRG_PMA15_RST_CTRL |= BIT24; + //cancell pet pma rst + PET_EQ0_RST_CFG |= BIT24; + PET_EQ1_RST_CFG |= BIT24; + PET_EQ2_RST_CFG |= BIT24; + PET_EQ3_RST_CFG |= BIT24; + PET_PAMRX0_RST_CFG |= BIT24; + PET_PAMRX1_RST_CFG |= BIT24; + PET_PAMRX2_RST_CFG |= BIT24; + PET_PAMRX3_RST_CFG |= BIT24; + PET_RX0_RST_CFG |= BIT24; + PET_RX1_RST_CFG |= BIT24; + PET_RX2_RST_CFG |= BIT24; + PET_RX3_RST_CFG |= BIT24; + PET_TX0_RST_CFG |= BIT24; + PET_TX1_RST_CFG |= BIT24; + PET_TX2_RST_CFG |= BIT24; + PET_TX3_RST_CFG |= BIT24; + PET_PWR_RST_CFG |= BIT24; +#endif + do_write(&JECS_CRG_PMA16_RST_CTRL, do_read_volatile(&JECS_CRG_PMA16_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA0_RST_CTRL, do_read_volatile(&JECS_CRG_PMA0_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA1_RST_CTRL, do_read_volatile(&JECS_CRG_PMA1_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA2_RST_CTRL, do_read_volatile(&JECS_CRG_PMA2_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA3_RST_CTRL, do_read_volatile(&JECS_CRG_PMA3_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA8_RST_CTRL, do_read_volatile(&JECS_CRG_PMA8_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA9_RST_CTRL, do_read_volatile(&JECS_CRG_PMA9_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA10_RST_CTRL, do_read_volatile(&JECS_CRG_PMA10_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA11_RST_CTRL, do_read_volatile(&JECS_CRG_PMA11_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA12_RST_CTRL, do_read_volatile(&JECS_CRG_PMA12_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA13_RST_CTRL, do_read_volatile(&JECS_CRG_PMA13_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA14_RST_CTRL, do_read_volatile(&JECS_CRG_PMA14_RST_CTRL) | BIT24); + do_write(&JECS_CRG_PMA15_RST_CTRL, do_read_volatile(&JECS_CRG_PMA15_RST_CTRL) | BIT24); + do_write(&PET_EQ0_RST_CFG, do_read_volatile(&PET_EQ0_RST_CFG) | BIT24); + do_write(&PET_EQ1_RST_CFG, do_read_volatile(&PET_EQ1_RST_CFG) | BIT24); + do_write(&PET_EQ2_RST_CFG, do_read_volatile(&PET_EQ2_RST_CFG) | BIT24); + do_write(&PET_EQ3_RST_CFG, do_read_volatile(&PET_EQ3_RST_CFG) | BIT24); + do_write(&PET_PAMRX0_RST_CFG, do_read_volatile(&PET_PAMRX0_RST_CFG) | BIT24); + do_write(&PET_PAMRX1_RST_CFG, do_read_volatile(&PET_PAMRX1_RST_CFG) | BIT24); + do_write(&PET_PAMRX2_RST_CFG, do_read_volatile(&PET_PAMRX2_RST_CFG) | BIT24); + do_write(&PET_PAMRX3_RST_CFG, do_read_volatile(&PET_PAMRX3_RST_CFG) | BIT24); + do_write(&PET_RX0_RST_CFG, do_read_volatile(&PET_RX0_RST_CFG) | BIT24); + do_write(&PET_RX1_RST_CFG, do_read_volatile(&PET_RX1_RST_CFG) | BIT24); + do_write(&PET_RX2_RST_CFG, do_read_volatile(&PET_RX2_RST_CFG) | BIT24); + do_write(&PET_RX3_RST_CFG, do_read_volatile(&PET_RX3_RST_CFG) | BIT24); + do_write(&PET_TX0_RST_CFG, do_read_volatile(&PET_TX0_RST_CFG) | BIT24); + do_write(&PET_TX1_RST_CFG, do_read_volatile(&PET_TX1_RST_CFG) | BIT24); + do_write(&PET_TX2_RST_CFG, do_read_volatile(&PET_TX2_RST_CFG) | BIT24); + do_write(&PET_TX3_RST_CFG, do_read_volatile(&PET_TX3_RST_CFG) | BIT24); + do_write(&PET_PWR_RST_CFG, do_read_volatile(&PET_PWR_RST_CFG) | BIT24); +} + +DDR0 uint32_t ate_tx_eq_pre[22] = {0, 0, 0, 0, 0, 8, 12, 10, 12, 16, 0, 0, 0, 0, 0, 0, 8, 8, 8, 10, 12, 0}; +DDR0 uint32_t ate_tx_eq_post[22] = {24,16,20,12, 0, 0, 0, 18, 12, 0, 32, 16, 12, 16, 8, 0, 0, 0, 12, 10, 0, 24}; +DDR0 uint32_t ate_tx_eq_main[22] = {18,20,19,21,24,22, 21, 17, 18, 20, 16, 14, 15, 14,16,18,16,16, 13, 13, 15, 12}; +void init_pma_commonconfig(uint32_t pma_sel,uint32_t cpri_speed_sel) +{ + uint32_t m=1; + uint32_t n=0; + uint32_t t=1; + uint32_t ate_ref_range = 0; + uint32_t ate_ref_clk_div2_en = 0; + uint32_t ate_ref_raw_clk_div2_en = 0; + uint32_t ate_ref_clk_mplla_div = 0; + uint32_t ate_lane_ref_sel = 0; + uint32_t ate_mplla_fb_clk_div4_en = 0; + uint32_t ate_mplla_multiplier = 0; + uint32_t ate_mplla_tx_clk_div = 0; + uint32_t ate_mplla_word_clk_div = 0; + uint32_t ate_mplla_ssc_en = 0; + uint32_t ate_mplla_ssc_up_spread = 0; + uint32_t ate_mplla_ssc_peak = 0; + uint32_t ate_mplla_ssc_step_size = 0; + uint32_t ate_mplla_frac_en = 0; + uint32_t ate_mplla_frac_quot = 0; + uint32_t ate_mplla_frac_den = 0; + uint32_t ate_mplla_frac_rem = 0; + uint32_t ate_refa_lane_clk_en = 0; + uint32_t ate_bs_rx_level = 0; + uint32_t ate_bs_tx_lowswing = 0; + uint32_t ate_bs_rx_bigswing = 0; + uint32_t ate_mplla_init_cal_disable = 0; + uint32_t ate_refa_dig_clk_sel = 0; + uint32_t ate_ref_dco_bypass = 0; + uint32_t ate_refa_dco_ld_val = 0; + uint32_t ate_ref_dco_target = 0; + uint32_t ate_ref_dco_dig_range = 0; + uint32_t ate_mplla_bw_threshold = 0; + uint32_t ate_mplla_bw_low = 0; + uint32_t ate_mplla_bw_high = 0; + uint32_t ate_mplla_ctl_buf_bypass = 0; + uint32_t ate_mplla_short_lock_en = 0; + uint32_t ate_rx_term_offset = 0; + uint32_t ate_txdn_term_offset = 0; + uint32_t ate_txup_term_offset = 0; + uint32_t ate_sup_misc = 0; + uint32_t ate_rx_vref_ctrl = 0; + uint32_t ate_rx_ref_ld_val = 0; + uint32_t ate_rx_vco_ld_val = 0; + uint32_t ate_rx_cdr_ppm_max = 0; + //lane + uint32_t ate_tx_misc = 0; + uint32_t ate_tx_dcc_ctrl_diff_range = 0; + uint32_t ate_tx_dcc_ctrl_cm_range = 0; + uint32_t ate_tx_width = 0; + uint32_t ate_tx_ropll_cp_ctl_intg = 0; + uint32_t ate_tx_ropll_cp_ctl_prop = 0; + uint32_t ate_tx_ropll_rc_filter = 0; + uint32_t ate_tx_ropll_v2i_mode = 0; + uint32_t ate_tx_ropll_vco_low_freq = 0; + uint32_t ate_tx_ropll_postdiv = 0; + uint32_t ate_tx_rate = 0; + uint32_t ate_tx_ropll_div16p5_clk_en = 0; + uint32_t ate_tx_ropll_125mhz_clk_en = 0; + uint32_t ate_tx_term_ctrl = 0; + uint32_t ate_tx_dly_cal_en = 0; + uint32_t ate_tx_pll_word_clk_freq = 0; + uint32_t ate_tx_dig_ropll_div_clk_sel = 0; + uint32_t ate_tx_dual_cntx_en = 0; + uint32_t ate_tx_ropll_bypass = 0; + uint32_t ate_tx_ropll_refdiv = 0; + uint32_t ate_tx_ropll_refsel = 0; + uint32_t ate_tx_ropll_fbdiv = 0; + uint32_t ate_tx_ropll_div_clk_en = 0; + uint32_t ate_tx_ropll_out_div = 0; + uint32_t ate_tx_ropll_word_clk_div_sel= 0; + uint32_t txX_ropll_word_clk_div_lte = 0; + uint32_t ate_tx_fastedge_en = 0; +// uint32_t ate_tx_eq_pre = 0; +// uint32_t ate_tx_eq_post = 0; +// uint32_t ate_tx_eq_main = 0; + uint32_t ate_tx_align_wide_xfer_en = 0; + uint32_t ate_rx_eq_att_lvl = 0; + uint32_t ate_rx_eq_ctle_boost = 0; + uint32_t ate_rx_eq_ctle_pole = 0; + uint32_t ate_rx_eq_afe_rate = 0; + uint32_t ate_rx_eq_vga_gain = 0; + uint32_t ate_rx_eq_afe_config = 0; + uint32_t ate_rx_eq_dfe_tap1 = 0; + uint32_t ate_rx_eq_dfe_tap2 = 0; + uint32_t ate_rx_delta_iq = 0; + uint32_t ate_rx_cdr_vco_config = 0; + uint32_t ate_rx_dcc_ctrl_diff_range = 0; + uint32_t ate_rx_dcc_ctrl_cm_range = 0; + uint32_t ate_rx_sigdet_lf_threshold = 0; + uint32_t ate_rx_sigdet_hf_threshold = 0; + uint32_t ate_rx_misc = 0; + uint32_t ate_rx_term_ctrl = 0; + uint32_t ate_rx_width = 0; + uint32_t ate_rx_dig_div_clk_sel = 0; + uint32_t ate_rx_div_clk_en = 0; + uint32_t ate_rx_div_clk_sel = 0; + uint32_t ate_rx_rate = 0; + uint32_t ate_rx_dfe_bypass = 0; + uint32_t ate_rx_offcan_cont = 0; + uint32_t ate_rx_adapt_cont = 0; + uint32_t ate_rx_eq_dfe_float_en = 0; + uint32_t ate_rx_div16p5_clk_en = 0; + uint32_t ate_rx_125mhz_clk_en = 0; + uint32_t ate_rx_cdr_ssc_en = 0; + uint32_t ate_rx_sigdet_hf_en = 0; + uint32_t ate_rx_sigdet_lfps_filter_en = 0; + uint32_t ate_rx_term_acdc = 0; + uint32_t ate_rx_adapt_sel = 0; + uint32_t ate_rx_adapt_mode = 0; + uint32_t ate_rx_adapt_en = 0; + + uint32_t ate_ref_clk_mpllb_div = 0; + uint32_t ate_mpllb_fb_clk_div4_en = 0; + uint32_t ate_mpllb_multiplier = 0; + uint32_t ate_mpllb_tx_clk_div = 0; + uint32_t ate_mpllb_word_clk_div = 0; + uint32_t ate_mpllb_ssc_en = 0; + uint32_t ate_mpllb_ssc_up_spread = 0; + uint32_t ate_mpllb_ssc_peak = 0; + uint32_t ate_mpllb_ssc_step_size = 0; + uint32_t ate_mpllb_frac_en = 0; + uint32_t ate_mpllb_frac_quot = 0; + uint32_t ate_mpllb_frac_den = 0; + uint32_t ate_mpllb_frac_rem = 0; + uint32_t ate_refb_lane_clk_en = 0; + uint32_t ate_mpllb_init_cal_disable = 0; + uint32_t ate_refb_dig_clk_sel = 0; + uint32_t ate_refb_dco_ld_val = 0; + uint32_t ate_mpllb_bw_high = 0; + uint32_t ate_mpllb_bw_low = 0; + uint32_t ate_mpllb_bw_threshold = 0; + uint32_t ate_mpllb_ctl_buf_bypass = 0; + uint32_t ate_mpllb_short_lock_en = 0; + + //const + uint32_t ate_mplla_force_en = 0;// + uint32_t ate_mpllb_force_en = 0;// + uint32_t ate_pcs_pwr_stable = 1;// + uint32_t ate_pg_mode_en = 0;// + uint32_t ate_pg_reset = 0;// + uint32_t ate_pma_pwr_stable = 1;// + uint32_t ate_refa_clk_en = 1;// + uint32_t ate_refb_clk_en = 0;// + uint32_t ate_ref_repeat_clk_en = 1;// + uint32_t ate_rx_pstate = 2;// + uint32_t ate_rx_invert = 0;// + uint32_t ate_rx_lpd = 0;// + uint32_t ate_rx_term_en = 1;// + uint32_t ate_tx_pstate = 2;// + uint32_t ate_tx_clk_rdy = 1;// + uint32_t ate_tx_invert = 0;// + uint32_t ate_tx_lpd = 0;// + uint32_t ate_tx_mpll_en = 1;// + +#if 0 + if(cpri_speed_sel == 2){ + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 1 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 17 ; + ate_rx_vco_ld_val = 1360; + ate_rx_cdr_ppm_max = 18 ; + //lane + ate_tx_misc = 128 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 3 ; + ate_tx_ropll_cp_ctl_intg = 91 ; + ate_tx_ropll_cp_ctl_prop = 91 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 3 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 4 ; + ate_tx_ropll_div16p5_clk_en = 0 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 0 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 9 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 16 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 3 ; + txX_ropll_word_clk_div_lte = 3 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 12 ; + ate_rx_eq_ctle_pole = 0 ; + ate_rx_eq_afe_rate = 7 ; + ate_rx_eq_vga_gain = 20 ; + ate_rx_eq_afe_config = 1300; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 1027; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 128 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 3 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + //ate_rx_rate = 3 ; + ate_rx_rate = 4 ;//different with pdf + ate_rx_dfe_bypass = 1 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 0 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 0 ; + ate_rx_adapt_en = 0 ; + } + if(cpri_speed_sel == 3){ + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 1 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 17 ; + ate_rx_vco_ld_val = 1360; + ate_rx_cdr_ppm_max = 18 ; + //lane + ate_tx_misc = 128 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 3 ; + ate_tx_ropll_cp_ctl_intg = 91 ; + ate_tx_ropll_cp_ctl_prop = 91 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 3 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 3 ; + ate_tx_ropll_div16p5_clk_en = 0 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + //ate_tx_pll_word_clk_freq = A ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 9 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 16 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 3 ; + txX_ropll_word_clk_div_lte = 3 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 12 ; + ate_rx_eq_ctle_pole = 0 ; + ate_rx_eq_afe_rate = 7 ; + ate_rx_eq_vga_gain = 20 ; + ate_rx_eq_afe_config = 1300; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 1027; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 128 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 3 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 3 ; + ate_rx_dfe_bypass = 1 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 0 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 0 ; + ate_rx_adapt_en = 0 ; + } + if(cpri_speed_sel == 4){ + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 1 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 14 ; + ate_rx_vco_ld_val = 1400; + ate_rx_cdr_ppm_max = 19 ; + //lane + ate_tx_misc = 128 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 3 ; + ate_tx_ropll_cp_ctl_intg = 105 ; + ate_tx_ropll_cp_ctl_prop = 99 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 2 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 3 ; + ate_tx_ropll_div16p5_clk_en = 0 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 9 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 20 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 3 ; + txX_ropll_word_clk_div_lte = 3 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 12 ; + ate_rx_eq_ctle_pole = 0 ; + ate_rx_eq_afe_rate = 7 ; + ate_rx_eq_vga_gain = 20 ; + ate_rx_eq_afe_config = 1300 ; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 34 ; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 128 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 3 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 3 ; + ate_rx_dfe_bypass = 1 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 0 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 0 ; + ate_rx_adapt_en = 0 ; + } + if(cpri_speed_sel == 5){ + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 1 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 17 ; + ate_rx_vco_ld_val = 1360; + ate_rx_cdr_ppm_max = 18 ; + //lane + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 3 ; + ate_tx_ropll_cp_ctl_intg = 91 ; + ate_tx_ropll_cp_ctl_prop = 91 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 3 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 2 ; + ate_tx_ropll_div16p5_clk_en = 0 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 4 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 9 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 16 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 3 ; + txX_ropll_word_clk_div_lte = 3 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 12 ; + ate_rx_eq_ctle_pole = 1 ; + ate_rx_eq_afe_rate = 6 ; + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = 1300 ; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 1027 ; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 3 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 2 ; + ate_rx_dfe_bypass = 1 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 0 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 0 ; + ate_rx_adapt_en = 0 ; + } + if(cpri_speed_sel == 6){ + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 1 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 14 ; + ate_rx_vco_ld_val = 1400; + ate_rx_cdr_ppm_max = 19 ; + //lane + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 3 ; + ate_tx_ropll_cp_ctl_intg = 105 ; + ate_tx_ropll_cp_ctl_prop = 99 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 2 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 2 ; + ate_tx_ropll_div16p5_clk_en = 1 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + //ate_tx_pll_word_clk_freq = NA ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 9 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 20 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 3 ; + txX_ropll_word_clk_div_lte = 3 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 12 ; + ate_rx_eq_ctle_pole = 1 ; + ate_rx_eq_afe_rate = 6 ; + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = 1300; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 34 ; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 3 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 2 ; + ate_rx_dfe_bypass = 1 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 0 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 0 ; + ate_rx_adapt_en = 0 ; + } + if(cpri_speed_sel == 7){ + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 1 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 17 ; + ate_rx_vco_ld_val = 1360; + ate_rx_cdr_ppm_max = 18 ; + //lane + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 3 ; + ate_tx_ropll_cp_ctl_intg = 91 ; + ate_tx_ropll_cp_ctl_prop = 91 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 3 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 1 ; + ate_tx_ropll_div16p5_clk_en = 1 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 6 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 9 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 16 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 3 ; + txX_ropll_word_clk_div_lte = 3 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 16 ; + ate_rx_eq_ctle_pole = 1 ; + ate_rx_eq_afe_rate = 5 ; + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = 332 ; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 1027; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 3 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 1 ; + ate_rx_dfe_bypass = 0 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 0 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 4 ; + ate_rx_adapt_en = 1 ; + } + if(cpri_speed_sel == 11){ + ate_ref_range = 4 ;//option7A + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 2 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 21 ; + ate_rx_vco_ld_val = 1386; + ate_rx_cdr_ppm_max = 18 ; + //lane + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 4 ; + ate_tx_ropll_cp_ctl_intg = 84 ; + ate_tx_ropll_cp_ctl_prop = 97 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 3 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 1 ; + ate_tx_ropll_div16p5_clk_en = 1 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 6 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 15 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 22 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 2 ; + txX_ropll_word_clk_div_lte = 2 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 16 ; + ate_rx_eq_ctle_pole = 1 ; + ate_rx_eq_afe_rate = 5 ; + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = 332 ; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 1027; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 4 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 1 ; + ate_rx_dfe_bypass = 0 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 1 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 4 ; + ate_rx_adapt_en = 1 ; + } + #endif + + if(cpri_speed_sel == 8) + { + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 2 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599 ; + ate_mplla_bw_high = 1599 ; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 17 ; + ate_rx_vco_ld_val = 1403 ; + ate_rx_cdr_ppm_max = 19 ; + //lane + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 4 ; + ate_tx_ropll_cp_ctl_intg = 79 ; + ate_tx_ropll_cp_ctl_prop = 79 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 2 ; + ate_tx_ropll_postdiv = 1 ; + ate_tx_rate = 1 ; + ate_tx_ropll_div16p5_clk_en = 1 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 6 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 6 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 11 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 2 ; + txX_ropll_word_clk_div_lte = 2 ; + ate_tx_fastedge_en = 0 ; + // ate_tx_eq_pre = 0 ; + // ate_tx_eq_post = 0 ; + // ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 16 ; + ate_rx_eq_ctle_pole = 1 ; + ate_rx_eq_afe_rate = 5 ; + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = 332 ; + ate_rx_eq_dfe_tap1 = 0 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 0 ; + ate_rx_cdr_vco_config = 1027 ; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 4 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 1 ; + ate_rx_dfe_bypass = 0 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 1 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 4 ; + ate_rx_adapt_en = 1 ; + } +#if 0 + if(cpri_speed_sel == 9){ + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 2 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 14 ; + ate_rx_vco_ld_val = 1386; + ate_rx_cdr_ppm_max = 18 ; + //lane + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 4 ; + ate_tx_ropll_cp_ctl_intg = 105 ; + ate_tx_ropll_cp_ctl_prop = 67 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 2 ; + ate_tx_ropll_postdiv = 0 ; + ate_tx_rate = 1 ; + ate_tx_ropll_div16p5_clk_en = 1 ; + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 4 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 5 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 11 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 2 ; + txX_ropll_word_clk_div_lte = 2 ; + ate_tx_fastedge_en = 0 ; + ate_tx_eq_pre = 0 ; + ate_tx_eq_post = 0 ; + ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 0 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 16 ; + ate_rx_eq_ctle_pole = 1 ; + ate_rx_eq_afe_rate = 4 ; + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = 396 ; + ate_rx_eq_dfe_tap1 = 10 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 6 ; + ate_rx_cdr_vco_config = 34 ; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 4 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 1 ; + ate_rx_dfe_bypass = 0 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 0 ; + ate_rx_div16p5_clk_en = 1 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 4 ; + ate_rx_adapt_en = 1 ; + } + #endif + if(cpri_speed_sel == 10) + { +#if 0 + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 2 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 14 ; + ate_rx_vco_ld_val = 1386; + ate_rx_cdr_ppm_max = 18 ; + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 4 ; + ate_tx_ropll_cp_ctl_intg = 105 ; + ate_tx_ropll_cp_ctl_prop = 67 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 2 ; + ate_tx_ropll_postdiv = 0 ; + ate_tx_rate = 0 ; + ate_tx_ropll_div16p5_clk_en = 1 ;//20220215 + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 6 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 5 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 11 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 2 ; + txX_ropll_word_clk_div_lte = 2 ; + ate_tx_fastedge_en = 0 ; + ate_tx_align_wide_xfer_en = 1 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 20 ; + ate_rx_eq_ctle_pole = 3 ; + ate_rx_eq_afe_rate = 2 ; + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = 2456; + ate_rx_eq_dfe_tap1 = 12 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 3 ; + ate_rx_cdr_vco_config = 34 ; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 0 ; + ate_rx_width = 4 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 0 ; + ate_rx_dfe_bypass = 0 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 1 ; + ate_rx_div16p5_clk_en = 1 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 4 ; + ate_rx_adapt_en = 1 ; +#endif + ate_ref_range = 4 ; + ate_ref_clk_div2_en = 0 ; + ate_ref_raw_clk_div2_en = 0 ; + ate_ref_clk_mplla_div = 1 ; + ate_lane_ref_sel = 0 ; + ate_mplla_fb_clk_div4_en = 0 ; + ate_mplla_multiplier = 180 ; + ate_mplla_tx_clk_div = 1 ; + ate_mplla_word_clk_div = 2 ; + ate_mplla_ssc_en = 0 ; + ate_mplla_ssc_up_spread = 0 ; + ate_mplla_ssc_peak = 0 ; + ate_mplla_ssc_step_size = 0 ; + ate_mplla_frac_en = 0 ; + ate_mplla_frac_quot = 0 ; + ate_mplla_frac_den = 0 ; + ate_mplla_frac_rem = 0 ; + ate_refa_lane_clk_en = 0 ; + ate_bs_rx_level = 7 ; + ate_bs_tx_lowswing = 0 ; + ate_bs_rx_bigswing = 1 ; + ate_mplla_init_cal_disable = 0 ; + ate_refa_dig_clk_sel = 0 ; + ate_ref_dco_bypass = 0 ; + ate_refa_dco_ld_val = 123 ; + ate_ref_dco_target = 150 ; + ate_ref_dco_dig_range = 6 ; + ate_mplla_bw_threshold = 75 ; + ate_mplla_bw_low = 1599; + ate_mplla_bw_high = 1599; + ate_mplla_ctl_buf_bypass = 0 ; + ate_mplla_short_lock_en = 0 ; + ate_rx_term_offset = 0 ; + ate_txdn_term_offset = 0 ; + ate_txup_term_offset = 0 ; + ate_sup_misc = 3 ; + ate_rx_vref_ctrl = 5 ; + ate_rx_ref_ld_val = 14 ; + ate_rx_vco_ld_val = 1386; + ate_rx_cdr_ppm_max = 18 ; + //lane + ate_tx_misc = 0 ; + ate_tx_dcc_ctrl_diff_range = 8 ; + ate_tx_dcc_ctrl_cm_range = 8 ; + ate_tx_width = 4 ; + ate_tx_ropll_cp_ctl_intg = 105 ; + ate_tx_ropll_cp_ctl_prop = 67 ; + ate_tx_ropll_rc_filter = 4 ; + ate_tx_ropll_v2i_mode = 3 ; + ate_tx_ropll_vco_low_freq = 2 ; + ate_tx_ropll_postdiv = 0 ; + ate_tx_rate = 0 ; + ate_tx_ropll_div16p5_clk_en = 1 ;//20220215 + ate_tx_ropll_125mhz_clk_en = 0 ; + ate_tx_term_ctrl = 0 ; + ate_tx_dly_cal_en = 0 ; + ate_tx_pll_word_clk_freq = 6 ; + ate_tx_dig_ropll_div_clk_sel = 0 ; + ate_tx_dual_cntx_en = 0 ; + ate_tx_ropll_bypass = 0 ; + ate_tx_ropll_refdiv = 5 ; + ate_tx_ropll_refsel = 0 ; + ate_tx_ropll_fbdiv = 11 ; + ate_tx_ropll_div_clk_en = 0 ; + ate_tx_ropll_out_div = 4 ; + ate_tx_ropll_word_clk_div_sel = 2 ; + txX_ropll_word_clk_div_lte = 2 ; + ate_tx_fastedge_en = 0 ; +// ate_tx_eq_pre = 0 ; +// ate_tx_eq_post = 0 ; +// ate_tx_eq_main = 24 ; + ate_tx_align_wide_xfer_en = 1 ; + ate_rx_eq_att_lvl = 0 ; + ate_rx_eq_ctle_boost = 20 ; + ate_rx_eq_ctle_pole = 3 ; + ate_rx_eq_afe_rate = 1 ;//24gtest 2 + ate_rx_eq_vga_gain = 16 ; + ate_rx_eq_afe_config = (9<<8)+(m<<6)+(n<<4)+(t<<2)+0;//24gtest 2456 + ate_rx_eq_dfe_tap1 = 12 ; + ate_rx_eq_dfe_tap2 = 128 ; + ate_rx_delta_iq = 3 ; + ate_rx_cdr_vco_config = 34 ; + ate_rx_dcc_ctrl_diff_range = 11 ; + ate_rx_dcc_ctrl_cm_range = 11 ; + ate_rx_sigdet_lf_threshold = 4 ; + ate_rx_sigdet_hf_threshold = 2 ; + ate_rx_misc = 0 ; + ate_rx_term_ctrl = 2 ;//24gtest 0 + ate_rx_width = 4 ; + ate_rx_dig_div_clk_sel = 0 ; + ate_rx_div_clk_en = 0 ; + ate_rx_div_clk_sel = 0 ; + ate_rx_rate = 0 ; + ate_rx_dfe_bypass = 0 ; + ate_rx_offcan_cont = 1 ; + ate_rx_adapt_cont = 1 ; + ate_rx_eq_dfe_float_en = 1 ; + ate_rx_div16p5_clk_en = 1 ; + ate_rx_125mhz_clk_en = 0 ; + ate_rx_cdr_ssc_en = 0 ; + ate_rx_sigdet_hf_en = 0 ; + ate_rx_sigdet_lfps_filter_en = 0 ; + ate_rx_term_acdc = 0 ; + ate_rx_adapt_sel = 0 ; + ate_rx_adapt_mode = 4 ; + ate_rx_adapt_en = 0 ; + } + + ate_tx_term_ctrl = ate_tx_term_ctrl +8; + ate_rx_term_ctrl = ate_rx_term_ctrl +8; + ate_ref_clk_mpllb_div = ate_ref_clk_mplla_div;// + ate_mpllb_fb_clk_div4_en = ate_mplla_fb_clk_div4_en;// + ate_mpllb_multiplier = ate_mplla_multiplier;// + ate_mpllb_tx_clk_div = ate_mplla_tx_clk_div;// + ate_mpllb_word_clk_div = ate_mplla_word_clk_div;// + ate_mpllb_ssc_en = ate_mplla_ssc_en;// + ate_mpllb_ssc_up_spread = ate_mplla_ssc_up_spread;// + ate_mpllb_ssc_peak = ate_mplla_ssc_peak;// + ate_mpllb_ssc_step_size = ate_mplla_ssc_step_size;// + ate_mpllb_frac_en = ate_mplla_frac_en;// + ate_mpllb_frac_quot = ate_mplla_frac_quot;// + ate_mpllb_frac_den = ate_mplla_frac_den;// + ate_mpllb_frac_rem = ate_mplla_frac_den;// + ate_refb_lane_clk_en = ate_refa_lane_clk_en;// + ate_mpllb_init_cal_disable = ate_mplla_init_cal_disable;// + ate_refb_dig_clk_sel = ate_refa_dig_clk_sel; + ate_refb_dco_ld_val = ate_refa_dco_ld_val; + ate_mpllb_bw_high = ate_mplla_bw_high ;// + ate_mpllb_bw_low = ate_mplla_bw_low ;// + ate_mpllb_bw_threshold = ate_mplla_bw_threshold;// + ate_mpllb_ctl_buf_bypass = ate_mplla_ctl_buf_bypass;// + ate_mpllb_short_lock_en = ate_mplla_short_lock_en;// + + //if(pma_sel ==0) + { +#if 0 + JECS_PHY_BS_CTRL = BIT4 + (7<<6); + + JECS_PMA1_REF_CLK_CTRL = 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12); + JECS_PMA1_REFB_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en; + JECS_PMA1_REFA_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en; + JECS_PMA1_BROADCAST_LANE_REFCLK_SEL = ate_lane_ref_sel; + JECS_PMA1_MPLLA_PARAM6 = (ate_mplla_fb_clk_div4_en<<4); + JECS_PMA1_MPLLB_PARAM6 = (ate_mpllb_fb_clk_div4_en<<4); + JECS_PMA1_MPLLA_PARAM5 = (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8); + JECS_PMA1_MPLLB_PARAM5 = (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8); + JECS_PMA1_REFA_CLK_CTRL1 = 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en; + JECS_PMA1_REFB_CLK_CTRL1 = 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en; + JECS_PMA1_MPLLA_SSC_CTRL2 = ate_mplla_ssc_peak; + JECS_PMA1_MPLLB_SSC_CTRL2 = ate_mpllb_ssc_peak; + JECS_PMA1_MPLLA_SSC_CTRL5 = ate_mplla_ssc_step_size; + JECS_PMA1_MPLLB_SSC_CTRL5 = ate_mpllb_ssc_step_size; + JECS_PMA1_MPLLA_FRAC_CTRL1 = ate_mplla_frac_den; + JECS_PMA1_MPLLB_FRAC_CTRL1 = ate_mpllb_frac_den; + JECS_PMA1_MPLLA_FRAC_CTRL2 = ate_mplla_frac_en; + JECS_PMA1_MPLLB_FRAC_CTRL2 = ate_mpllb_frac_en; + JECS_PMA1_MPLLA_FRAC_CTRL3 = ate_mplla_frac_quot; + JECS_PMA1_MPLLB_FRAC_CTRL3 = ate_mpllb_frac_quot; + JECS_PMA1_MPLLA_FRAC_CTRL4 = ate_mplla_frac_rem; + JECS_PMA1_MPLLB_FRAC_CTRL4 = ate_mpllb_frac_rem; + JECS_PMA1_MPLLA_PARAM3 = (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold; + JECS_PMA1_MPLLB_PARAM3 = (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold; + JECS_PMA1_MPLLA_SSC_CTRL1 = ate_mplla_ssc_en; + JECS_PMA1_MPLLB_SSC_CTRL1 = ate_mpllb_ssc_en; + JECS_PMA1_MPLLA_SSC_CTRL4 = ate_mplla_ssc_up_spread; + JECS_PMA1_MPLLB_SSC_CTRL4 = ate_mpllb_ssc_up_spread; + JECS_PMA1_SUP_MISC = ate_sup_misc; + JECS_PMA1_MPLLA_PARAM4 = ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12); + JECS_PMA1_MPLLB_PARAM4 = ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12); + JECS_PMA1_RTUNE_CTRL1 = ate_rx_term_offset; + JECS_PMA1_RTUNE_CTRL2 = ate_txdn_term_offset; + JECS_PMA1_RTUNE_CTRL3 = ate_txup_term_offset; + JECS_PMA1_MPLLA_PARAM1 = ate_mplla_bw_high; + JECS_PMA1_MPLLB_PARAM1 = ate_mpllb_bw_high; + JECS_PMA1_MPLLA_PARAM2 = ate_mplla_bw_low; + JECS_PMA1_MPLLB_PARAM2 = ate_mpllb_bw_low; + JECS_PMA1_RX_BIAS_CURRENT_CTRL = ate_rx_vref_ctrl+BIT8;//20220214 + JECS_PMA1_MPLLA_FORCE_EN = ate_mplla_force_en; + JECS_PMA1_MPLLB_FORCE_EN = ate_mpllb_force_en; + JECS_PMA1_POWER_GATING_SIGNAL1 = ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12); + + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7 = ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8); + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8 = ate_rx_vco_ld_val; + JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1 = ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12); + JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2 = ate_tx_misc + (ate_tx_term_ctrl<<8); + JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2 = (ate_tx_width<<4) + ate_tx_rate; + JECS_PMA1_BROADCAST_ETH_CLK_CTRL = (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en; + JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL = ate_tx_dig_ropll_div_clk_sel; + JECS_PMA1_BROADCAST_RECEIVER_CONTROL= (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8); + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4 = (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost; + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3 = (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass + (ate_rx_eq_att_lvl<<8); + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9 = ate_rx_width; + JECS_PMA1_BROADCAST_RX_EQ_CTRL2 = (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2; + JECS_PMA1_BROADCAST_RX_EQ_CTRL1 = (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config; + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2 = ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12); + JECS_PMA1_BROADCAST_RX_ADAPT_CTRL = ate_rx_adapt_sel; + JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING = (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8); + JECS_PMA1_BROADCAST_TRANSMITTER_EQ1 = ate_tx_eq_main; + JECS_PMA1_BROADCAST_TRANSMITTER_EQ2 = ate_tx_eq_post; + JECS_PMA1_BROADCAST_TRANSMITTER_EQ3 = ate_tx_eq_pre; + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6 = (ate_rx_misc<<8); + JECS_PMA1_BROADCAST_RX_DCC_CTRL = ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4); + JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5 = (ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1; + JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2 = (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en; + JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3 = ate_rx_sigdet_lfps_filter_en; + JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2 = ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7); + JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4 = ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14); + JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3 = ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7); + JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5 = ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100; + JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1 = (ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4); + JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY = ate_tx_clk_rdy; + JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING = ate_tx_align_wide_xfer_en + (ate_tx_invert<<4); + JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1 = ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8); + JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3 = ate_tx_dual_cntx_en; + JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL = ate_tx_dly_cal_en; + JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL = ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8); + #endif + do_write(&JECS_PHY_BS_CTRL, BIT4 + (7<<6)); + do_write(&JECS_PMA1_REF_CLK_CTRL, 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12)); + do_write(&JECS_PMA1_REFB_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en); + do_write(&JECS_PMA1_REFA_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en); + do_write(&JECS_PMA1_BROADCAST_LANE_REFCLK_SEL, ate_lane_ref_sel); + do_write(&JECS_PMA1_MPLLA_PARAM6, (ate_mplla_fb_clk_div4_en<<4)); + do_write(&JECS_PMA1_MPLLB_PARAM6, (ate_mpllb_fb_clk_div4_en<<4)); + do_write(&JECS_PMA1_MPLLA_PARAM5, (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8)); + do_write(&JECS_PMA1_MPLLB_PARAM5, (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8)); + do_write(&JECS_PMA1_REFA_CLK_CTRL1, 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en); + do_write(&JECS_PMA1_REFB_CLK_CTRL1, 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en); + do_write(&JECS_PMA1_MPLLA_SSC_CTRL2, ate_mplla_ssc_peak); + do_write(&JECS_PMA1_MPLLB_SSC_CTRL2, ate_mpllb_ssc_peak); + do_write(&JECS_PMA1_MPLLA_SSC_CTRL5, ate_mplla_ssc_step_size); + do_write(&JECS_PMA1_MPLLA_SSC_CTRL5, ate_mpllb_ssc_step_size); + do_write(&JECS_PMA1_MPLLA_FRAC_CTRL1, ate_mplla_frac_den); + do_write(&JECS_PMA1_MPLLB_FRAC_CTRL1, ate_mpllb_frac_den); + do_write(&JECS_PMA1_MPLLA_FRAC_CTRL2, ate_mplla_frac_en); + do_write(&JECS_PMA1_MPLLB_FRAC_CTRL2, ate_mpllb_frac_en); + do_write(&JECS_PMA1_MPLLA_FRAC_CTRL3, ate_mplla_frac_quot); + do_write(&JECS_PMA1_MPLLB_FRAC_CTRL3, ate_mpllb_frac_quot); + do_write(&JECS_PMA1_MPLLA_FRAC_CTRL4, ate_mplla_frac_rem); + do_write(&JECS_PMA1_MPLLB_FRAC_CTRL4, ate_mpllb_frac_rem); + do_write(&JECS_PMA1_MPLLA_PARAM3, (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold); + do_write(&JECS_PMA1_MPLLB_PARAM3, (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold); + do_write(&JECS_PMA1_MPLLA_SSC_CTRL1 , ate_mplla_ssc_en); + do_write(&JECS_PMA1_MPLLB_SSC_CTRL1 , ate_mpllb_ssc_en); + do_write(&JECS_PMA1_MPLLA_SSC_CTRL4 , ate_mplla_ssc_up_spread); + do_write(&JECS_PMA1_MPLLB_SSC_CTRL4 , ate_mpllb_ssc_up_spread); + do_write(&JECS_PMA1_SUP_MISC , ate_sup_misc); + do_write(&JECS_PMA1_MPLLA_PARAM4 , ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12)); + do_write(&JECS_PMA1_MPLLB_PARAM4 , ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12)); + do_write(&JECS_PMA1_RTUNE_CTRL1 , ate_rx_term_offset); + do_write(&JECS_PMA1_RTUNE_CTRL2 , ate_txdn_term_offset); + do_write(&JECS_PMA1_RTUNE_CTRL3 , ate_txup_term_offset); + do_write(&JECS_PMA1_MPLLA_PARAM1 , ate_mplla_bw_high); + do_write(&JECS_PMA1_MPLLB_PARAM1 , ate_mpllb_bw_high); + do_write(&JECS_PMA1_MPLLA_PARAM2 , ate_mplla_bw_low); + do_write(&JECS_PMA1_MPLLB_PARAM2 , ate_mpllb_bw_low); + do_write(&JECS_PMA1_RX_BIAS_CURRENT_CTRL , ate_rx_vref_ctrl+BIT8); + do_write(&JECS_PMA1_MPLLA_FORCE_EN , ate_mplla_force_en); + do_write(&JECS_PMA1_MPLLB_FORCE_EN , ate_mpllb_force_en); + do_write(&JECS_PMA1_POWER_GATING_SIGNAL1 , ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12)); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7, ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8)); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8, ate_rx_vco_ld_val); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1, ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12)); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2, ate_tx_misc + (ate_tx_term_ctrl<<8)); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2, (ate_tx_width<<4) + ate_tx_rate); + do_write(&JECS_PMA1_BROADCAST_ETH_CLK_CTRL, (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en); + do_write(&JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL, ate_tx_dig_ropll_div_clk_sel); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_CONTROL, (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8)); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4, (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3, (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass + (ate_rx_eq_att_lvl<<8)); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9, ate_rx_width); + do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL2, (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2); + do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL1, (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2,ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12)); + do_write(&JECS_PMA1_BROADCAST_RX_ADAPT_CTRL,ate_rx_adapt_sel ); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING, (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8)); + if(8 == cpri_speed_sel) + { + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, ate_tx_eq_main[4]); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, ate_tx_eq_post[4]); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, ate_tx_eq_pre[4]); + } + if(10 == cpri_speed_sel) + { + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, ate_tx_eq_main[4]); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, ate_tx_eq_post[4]); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, ate_tx_eq_pre[4]); + } + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6, (ate_rx_misc<<8)); + do_write(&JECS_PMA1_BROADCAST_RX_DCC_CTRL, ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4)); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5,(ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2, (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en); + do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3, ate_rx_sigdet_lfps_filter_en); + do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2,ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7)); + do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4 , ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14)); + do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3 , ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7)); + do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5 , ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1 ,(ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4)); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY ,ate_tx_clk_rdy); + do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING , ate_tx_align_wide_xfer_en + (ate_tx_invert<<4)); + do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1 , ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8)); + do_write(&JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3 , ate_tx_dual_cntx_en); + do_write(&JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL , ate_tx_dly_cal_en); + do_write(&JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL , ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8)); + } + + #if 0 + if(pma_sel ==1){ + + PET_PHY_BS_CTRL = BIT4 + (7<<6); + + PET_PMA3_BROADCAST_RECEIVER_REQ_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_RECEIVER_ADAPT_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_RECEIVER_DATAPATH_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_RECEIVER_CONTROL_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_RECEIVER_RECAL_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_TRANSMITTER_REQ_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_TRANSMITTER_CONTROL_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_TRANSMITTER_EQ_MUX_CTRL = 0x1; + PET_PMA3_BROADCAST_CONTEXT_RESTORE_MUX = 0x1; + PET_PMA3_BROADCAST_ETH_CLK_CTRL_MUX = 0x1; + PET_PMA3_BROADCAST_RECV_REQUEST_CTRL_MUX = 0x1; + PET_PMA3_BROADCAST_RX_COARSE_ADAPT_CTRL_MUX = 0x1; + PET_PMA3_BROADCAST_MULTI_CLK_CTRL_MUX = 0x1; + PET_PMA3_BROADCAST_TRANS_REQ_MUX = 0x1; + PET_PMA3_BROADCAST_TRANS_INTERFACE_MUX = 0x1; + PET_PMA3_BROADCAST_PLL_STATE_MUX = 0x1; + PET_PMA3_REF_CLK_MUX = 0x1; + PET_PMA3_MPLL_CTRL_MUX = BIT4|BIT8|BIT0;//20220214 + + PET_PMA3_REF_CLK_CTRL = 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12); + PET_PMA3_REFB_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en; + PET_PMA3_REFA_CLK_CTRL2 = (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en; + PET_PMA3_BROADCAST_LANE_REFCLK_SEL = ate_lane_ref_sel; + PET_PMA3_MPLLA_PARAM6 = (ate_mplla_fb_clk_div4_en<<4); + PET_PMA3_MPLLB_PARAM6 = (ate_mpllb_fb_clk_div4_en<<4); + PET_PMA3_MPLLA_PARAM5 = (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8); + PET_PMA3_MPLLB_PARAM5 = (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8); + PET_PMA3_REFA_CLK_CTRL1 = 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en; + PET_PMA3_REFB_CLK_CTRL1 = 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en; + PET_PMA3_MPLLA_SSC_CTRL2 = ate_mplla_ssc_peak; + PET_PMA3_MPLLB_SSC_CTRL2 = ate_mpllb_ssc_peak; + PET_PMA3_MPLLA_SSC_CTRL5 = ate_mplla_ssc_step_size; + PET_PMA3_MPLLB_SSC_CTRL5 = ate_mpllb_ssc_step_size; + PET_PMA3_MPLLA_FRAC_CTRL1 = ate_mplla_frac_den; + PET_PMA3_MPLLB_FRAC_CTRL1 = ate_mpllb_frac_den; + PET_PMA3_MPLLA_FRAC_CTRL2 = ate_mplla_frac_en; + PET_PMA3_MPLLB_FRAC_CTRL2 = ate_mpllb_frac_en; + PET_PMA3_MPLLA_FRAC_CTRL3 = ate_mplla_frac_quot; + PET_PMA3_MPLLB_FRAC_CTRL3 = ate_mpllb_frac_quot; + PET_PMA3_MPLLA_FRAC_CTRL4 = ate_mplla_frac_rem; + PET_PMA3_MPLLB_FRAC_CTRL4 = ate_mpllb_frac_rem; + PET_PMA3_MPLLA_PARAM3 = (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold; + PET_PMA3_MPLLB_PARAM3 = (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold; + PET_PMA3_MPLLA_SSC_CTRL1 = ate_mplla_ssc_en; + PET_PMA3_MPLLB_SSC_CTRL1 = ate_mpllb_ssc_en; + PET_PMA3_MPLLA_SSC_CTRL4 = ate_mplla_ssc_up_spread; + PET_PMA3_MPLLB_SSC_CTRL4 = ate_mpllb_ssc_up_spread; + PET_PMA3_SUP_MISC = ate_sup_misc; + PET_PMA3_MPLLA_PARAM4 = ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12); + PET_PMA3_MPLLB_PARAM4 = ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12); + PET_PMA3_RTUNE_CTRL1 = ate_rx_term_offset; + PET_PMA3_RTUNE_CTRL2 = ate_txdn_term_offset; + PET_PMA3_RTUNE_CTRL3 = ate_txup_term_offset; + PET_PMA3_MPLLA_PARAM1 = ate_mplla_bw_high; + PET_PMA3_MPLLB_PARAM1 = ate_mpllb_bw_high; + PET_PMA3_MPLLA_PARAM2 = ate_mplla_bw_low; + PET_PMA3_MPLLB_PARAM2 = ate_mpllb_bw_low; + PET_PMA3_RX_BIAS_CURRENT_CTRL = ate_rx_vref_ctrl+BIT8;//20220214 + PET_PMA3_MPLLA_FORCE_EN = ate_mplla_force_en; + PET_PMA3_MPLLB_FORCE_EN = ate_mpllb_force_en; + PET_PMA3_POWER_GATING_SIGNAL1 = ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12); + + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM7 = ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8); + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM8 = ate_rx_vco_ld_val; + PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING1 = ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12); + PET_PMA3_BROADCAST_TRANSMITTER_CONTROL2 = ate_tx_misc + (ate_tx_term_ctrl<<8); + PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM2 = (ate_tx_width<<4) + ate_tx_rate; + PET_PMA3_BROADCAST_ETH_CLK_CTRL = (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en; + PET_PMA3_BROADCAST_TX_DIV_CLK_CTRL = ate_tx_dig_ropll_div_clk_sel; + PET_PMA3_BROADCAST_RECEIVER_CONTROL= (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8); + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM4 = (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost; + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM3 = (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass + (ate_rx_eq_att_lvl<<8); + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM9 = ate_rx_width; + PET_PMA3_BROADCAST_RX_EQ_CTRL2 = (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2; + PET_PMA3_BROADCAST_RX_EQ_CTRL1 = (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config; + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM2 = ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12); + PET_PMA3_BROADCAST_RX_ADAPT_CTRL = ate_rx_adapt_sel; + PET_PMA3_BROADCAST_RECEIVER_ADAPT_SETTING = (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8); + PET_PMA3_BROADCAST_TRANSMITTER_EQ1 = ate_tx_eq_main; + PET_PMA3_BROADCAST_TRANSMITTER_EQ2 = ate_tx_eq_post; + PET_PMA3_BROADCAST_TRANSMITTER_EQ3 = ate_tx_eq_pre; + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM6 = (ate_rx_misc<<8); + PET_PMA3_BROADCAST_RX_DCC_CTRL = ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4); + PET_PMA3_BROADCAST_RECEIVER_REQ_PARAM5 = (ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1; + PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING2 = (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en; + PET_PMA3_BROADCAST_RECEIVER_DATAPATH_SETTING3 = ate_rx_sigdet_lfps_filter_en; + PET_PMA3_BROADCAST_TRANS_REQ_CTRL2 = ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7); + PET_PMA3_BROADCAST_TRANS_REQ_CTRL4 = ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14); + PET_PMA3_BROADCAST_TRANS_REQ_CTRL3 = ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7); + PET_PMA3_BROADCAST_TRANS_REQ_CTRL5 = ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100; + PET_PMA3_BROADCAST_TRANSMITTER_REQ_PARAM1 = (ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4); + PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY = ate_tx_clk_rdy; + PET_PMA3_BROADCAST_TRANSMITTER_DATAPATH_SETTING = ate_tx_align_wide_xfer_en + (ate_tx_invert<<4); + PET_PMA3_BROADCAST_TRANS_REQ_CTRL1 = ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8); + PET_PMA3_BROADCAST_CONTEXT_RESTORE_CTRL3 = ate_tx_dual_cntx_en; + PET_PMA3_BROADCAST_TRANS_INTERFACE_CTRL = ate_tx_dly_cal_en; + PET_PMA3_BROADCAST_RX_DIV_CLK_CTRL = ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8); + } + #endif +} + +void Init_jecspma(uint32_t cpri_speed_sel) +{ +#if 0 + JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | (BIT4); + //cancell jecs pma rst + JECS_CRG_PMA16_RST_CTRL |= BIT24; + JECS_CRG_PMA0_RST_CTRL |= BIT24; + JECS_CRG_PMA1_RST_CTRL |= BIT24; + JECS_CRG_PMA2_RST_CTRL |= BIT24; + JECS_CRG_PMA3_RST_CTRL |= BIT24; + JECS_CRG_PMA8_RST_CTRL |= BIT24; + JECS_CRG_PMA9_RST_CTRL |= BIT24; + JECS_CRG_PMA10_RST_CTRL |= BIT24; + JECS_CRG_PMA11_RST_CTRL |= BIT24; + JECS_CRG_PMA12_RST_CTRL |= BIT24; + JECS_CRG_PMA13_RST_CTRL |= BIT24; + JECS_CRG_PMA14_RST_CTRL |= BIT24; + JECS_CRG_PMA15_RST_CTRL |= BIT24; +#endif +#if 1 + uint32_t i =0; + uint32_t temp =0; + + //PCS Protocol Sel + // JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | (BIT2); + temp = do_read_volatile(&JECS_CTRL_PROTOCOL_SEL); + temp |= BIT2; + __ucps2_synch(0); + do_write(&JECS_CTRL_PROTOCOL_SEL, temp); + // JECS_PMA1_CPRI_PCS_STATUS_CTRL = 0; + do_write(&JECS_PMA1_CPRI_PCS_STATUS_CTRL, 0); + //PCS BIT REV + if(cpri_speed_sel<=7)//option~option7 + { + //JECS_PMA1_PCS_BIT_REV_CTRL = 0x211; + do_write(&JECS_PMA1_PCS_BIT_REV_CTRL, 0x211); + } + else + { + //JECS_PMA1_PCS_BIT_REV_CTRL = 0x111; + do_write(&JECS_PMA1_PCS_BIT_REV_CTRL, 0x111); + } + do_write(&JECS_PMA1_CPRI_SIGDET, (BIT4|BIT0)); + ucp_nop(400); + if(cpri_speed_sel==7) + { + // JECS_PMA1_TX_CLK_SEL = 0x0; + do_write(&JECS_PMA1_TX_CLK_SEL,0); + } + else if((cpri_speed_sel==3)| (cpri_speed_sel==9)) + { + //JECS_PMA1_TX_CLK_SEL = 0x2; + do_write(&JECS_PMA1_TX_CLK_SEL,0x2); + } + else if(cpri_speed_sel==2) + { + // JECS_PMA1_TX_CLK_SEL = 0x3; + do_write(&JECS_PMA1_TX_CLK_SEL,0x3); + } + else + { + //JECS_PMA1_TX_CLK_SEL = 0x1; + do_write(&JECS_PMA1_TX_CLK_SEL,0x1); + } + ucp_nop(400); + + init_pma_commonconfig(0,cpri_speed_sel); + ucp_nop(400); + + // JECS_PMA1_PHY_RESET = 0x1; + do_write(&JECS_PMA1_PHY_RESET,0x1); + ucp_nop(400); + //UARTPrintStr("JECS PHY RESET\n"); + //JECS_PMA1_SRAM_CTRL = 0x1; + //JECS_PMA1_PHY_RESET = 0x0; + //while((JECS_PMA1_SRAM_STATUS & BIT0)!=BIT0); + //init_fastjecspma();//to be changed + ////SRAM ECC DisEn and Init Done + //JECS_PMA1_SRAM_CTRL = 0x1001; + //UARTPrintStr("JECS SRAM EXTDONE\n"); + + // JECS_PMA1_SRAM_CTRL = 0x101; + do_write(&JECS_PMA1_SRAM_CTRL,0x101); + ucp_nop(400); + // JECS_PMA1_PHY_RESET = 0x0; + do_write(&JECS_PMA1_PHY_RESET,0); + //wait sram_load success + // while((JECS_PMA1_SRAM_STATUS&BIT0) != 1) ; + + __ucps2_synch(0); + while((do_read_volatile(&JECS_PMA1_SRAM_STATUS) & BIT0)!= 1){} + + for(i=0;i<16384;i++) + { + //(*((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4))) = pma_fw[i]; + + // do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4),pma_fw[i]); + + temp =do_read_volatile(&pma_fw[i]); + __ucps2_synch(0); + do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000*4+i*4),temp); + __ucps2_synch(0); + } + + // (*((volatile uint32_t *)(JECS_PMA1_CFG+0x101*4))) |= BIT1; + + do_write((volatile uint32_t *)(JECS_PMA1_CFG+0x101*4), do_read_volatile((volatile uint32_t *)(JECS_PMA1_CFG+0x101*4)) | BIT1); + __ucps2_synch(0); + for(i=0;i<16384;i++) + { + // (*((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4))) = pma_fw[i+16384]; + // do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000ul*4+i*4),pma_fw[i+16384]); + + temp =do_read_volatile(&pma_fw[i+16384]); + __ucps2_synch(0); + do_write((volatile uint32_t *)(JECS_PMA1_CFG+0xc000*4+i*4),temp); + __ucps2_synch(0); + } + do_write(&JECS_PMA1_SRAM_CTRL,0x1101); + __ucps2_synch(0); +#endif +} + + + +void init_jecspma_recrx(){ + //Disable Tx and Rx RST + //JECS_PMA1_LANE0_TRANSMITTER_CONTROL1 = 0x0; + //JECS_PMA1_LANE0_RECEIVER_RESET = 0x0; + + //Wait Ack Done + //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); + //while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); + //UARTPrintStr("JECS RX ACK DONE\n"); + + //Enable TX and RX Req + do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1); + + //Wait ACK and Disable Req + while(!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0)); + do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0); + do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); + + //Wait Ack Done + while(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0); + + //P0 PSTATE + do_write(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7) & 0xfff0); + do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1); + + //Wait ACK and Disable Req + while(!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0)); + do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0); + do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); + + //Wait Ack Done + while(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0); + + //Enable Data + do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, 0x1); + + //wait rx valid + while(do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) == 0){} + + //UARTPrintStr("RECMODE:JECS RX RX VALID\n"); + +} + +void init_jecspma_rectx(){ + //Disable Tx and Rx RST +#if 0 + JECS_PMA1_LANE0_TRANSMITTER_CONTROL1 = 0x0; + JECS_PMA1_LANE0_RECEIVER_RESET = 0x0; + JECS_PMA1_LANE1_TRANSMITTER_CONTROL1 = 0x0; + JECS_PMA1_LANE1_RECEIVER_RESET = 0x0; + JECS_PMA1_LANE2_TRANSMITTER_CONTROL1 = 0x0; + JECS_PMA1_LANE2_RECEIVER_RESET = 0x0; + JECS_PMA1_LANE3_TRANSMITTER_CONTROL1 = 0x0; + JECS_PMA1_LANE3_RECEIVER_RESET = 0x0; +#endif + + do_write(&JECS_PMA1_LANE0_TRANSMITTER_CONTROL1, 0x0); + do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, 0x0); + do_write(&JECS_PMA1_LANE1_TRANSMITTER_CONTROL1, 0x0); + do_write(&JECS_PMA1_LANE1_RECEIVER_RESET, 0x0); + do_write(&JECS_PMA1_LANE2_TRANSMITTER_CONTROL1, 0x0); + do_write(&JECS_PMA1_LANE2_RECEIVER_RESET, 0x0); + do_write(&JECS_PMA1_LANE3_TRANSMITTER_CONTROL1, 0x0); + do_write(&JECS_PMA1_LANE3_RECEIVER_RESET, 0x0); + ucp_nop(400); + //Wait Ack Done + //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); + //while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); + __ucps2_synch(0); + while(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0); + __ucps2_synch(0); + while(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0){} + //UARTPrintStr("RECMODE:JECS TX ACK DONE\n"); + + //Enable TX and RX Req + //JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x1; + do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1); + //JECS_PMA1_LANE0_RECEIVER_REQ = 0x1; + + //Wait ACK and Disable Req + //while(!((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0))); + + //while(!((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0))); + __ucps2_synch(0); + while(!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0)); + //JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x0; + do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0); + // JECS_PMA1_LANE0_RECEIVER_REQ = 0x0; + do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); + + //Wait Ack Done + //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); + + //while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); + __ucps2_synch(0); + while(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0); + //UARTPrintStr("RECMODE:JECS TX ACK DONE\n"); + + //P0 PSTATE + //JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7 = (JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7&0xfff0); + + + // JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1 = (JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1&0xff); + __ucps2_synch(0); + do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1, do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1) &0xff); + + + // JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x1; + do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1); + //JECS_PMA1_LANE0_RECEIVER_REQ = 0x1; + + //Wait ACK and Disable Req + //while(!((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0))); + + // while(!((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0))); + __ucps2_synch(f_SM); + while(!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0)); + // JECS_PMA1_LANE0_TRANSMITTER_REQ = 0x0; + do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x00); + //JECS_PMA1_LANE0_RECEIVER_REQ = 0x0; + do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0); + + //Wait Ack Done + //while((JECS_PMA1_LANE0_RECEIVER_REQ_ACK&BIT0)); + + // while((JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK&BIT0)); + __ucps2_synch(f_SM); + while(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0); + //UARTPrintStr("RECMODE:JECS TX ACK DONE\n"); + + //Enable Data + // JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN = 0x1; + do_write(&JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN, 0x1); + //JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN = 0x1; + + //P0 PSTATE + //while(JECS_PMA1_LANE0_TRANS_PLL_STATE == 0); + __ucps2_synch(f_SM); + while(do_read_volatile(&JECS_PMA1_LANE0_TRANS_PLL_STATE) == 0){} + //UARTPrintStr("RECMODE:JECS TX READY\n"); + +} + +void jecspma_recrx_eq() +{ + uint32_t i=0; + uint32_t j=0; + init_jecspma_recrx(); + //for(uint32_t i = 0;i<10 ; i++) + //while(1) + { + i++; + //rx adapt eq + //UARTPrintStr("PMA RX ADAPT EQ START"); + //De-assert rx_data_en + if((0 == (j % 100)) && (1< j)) + { + Clk_To_XTAL(); + do_write(&CPRI_PCS_ADDR_CFG, 0); + do_write(&CPRI_PCS_DATA_TX_CFG, BIT15|BIT13|BIT6); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0); + do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0x1C); + do_write(&CPRI_PCS_DATA_TX_CFG, 0); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xB8); + do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xBC); + do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + Clk_To_Normal(); + + } + + do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4); + + //Assert rx_adapt_in_prog to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); + + //Toggle rx_reset to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) | BIT4); + do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) & (~BIT4)); + __ucps2_synch(f_SM); + + //Wait for de-assertion of rx_ack from the PHY + while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & 0x1 )!= 0); + //Assert rx_data_en to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4|BIT0); + __ucps2_synch(f_SM); + + //Wait for assertion of rx_valid from the PHY + while((do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) & BIT0 )!= 0x1); + + //Perform an RX adaptation request and assert rx_adapt_req + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4|BIT0); + __ucps2_synch(f_SM); + + //Wait for assertion of rx_adapt_ack from the PHY + while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)&BIT0) != BIT0); + debug_write((DBG_DDR_IDX_CPRI_BASE), do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)); + + //UARTPrintStr_f("JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK",JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK); + //De-assert rx_adapt_req to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); + + //De-assert rx_adapt_in_prog to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, 0); +#if 0 + do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL) & (~BIT24)); + // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL) & (~BIT24)); + ucp_nop(400); + do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL)| BIT24); + // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL)| BIT24); + +#endif + debug_write((DBG_DDR_IDX_CPRI_BASE+1), i); + debug_write((DBG_DDR_IDX_CPRI_BASE+2), j); +#if 0 + //ucp_nop(400); + + //if(0xA0 < (((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK))>>8) & 0xFF)) + if(0x80 < (((do_read_volatile((DBG_DDR_IDX_CPRI_BASE<<2)+DBG_DDR_ADDR_BASE))>>8) & 0xFF)) + { + j++; + delay_us(10000); + //if((do_read_volatile(&AUX_INT_FLAG) & BIT2) == 0x4) + if(do_read_volatile(&CPRI_FRAME_RX_STAT) == 0x1E) + //if (1 < gCpriSyncIntCnt) + { + break; + } + } + +#endif + + } + + +} +void jecspma_recrx_reset() +{ + uint32_t i=0; + uint32_t j=0; + init_jecspma_recrx(); + while(1) + { + i++; + //rx adapt eq + //UARTPrintStr("PMA RX ADAPT EQ START"); + //De-assert rx_data_en + + if((0 == (j % 100)) && (1< j)) + { + Clk_To_XTAL(); + do_write(&CPRI_PCS_ADDR_CFG, 0); + do_write(&CPRI_PCS_DATA_TX_CFG, BIT15|BIT13|BIT6); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0); + do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0x1C); + do_write(&CPRI_PCS_DATA_TX_CFG, 0); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xB8); + do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xBC); + do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + Clk_To_Normal(); + + } + + do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4); + + //Assert rx_adapt_in_prog to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); + + //Toggle rx_reset to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) | BIT4); + do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) & (~BIT4)); + __ucps2_synch(f_SM); + + //Wait for de-assertion of rx_ack from the PHY + while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & 0x1 )!= 0); + //Assert rx_data_en to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4|BIT0); + __ucps2_synch(f_SM); + + //Wait for assertion of rx_valid from the PHY + while((do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) & BIT0 )!= 0x1); + + //Perform an RX adaptation request and assert rx_adapt_req + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4|BIT0); + __ucps2_synch(f_SM); + + //Wait for assertion of rx_adapt_ack from the PHY + while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)&BIT0) != BIT0); + debug_write((DBG_DDR_IDX_CPRI_BASE+4), do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)); + + //UARTPrintStr_f("JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK",JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK); + //De-assert rx_adapt_req to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4); + + //De-assert rx_adapt_in_prog to the PHY + do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, 0); +#if 0 + do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL) & (~BIT24)); + // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL) & (~BIT24)); + ucp_nop(400); + do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL)| BIT24); + // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL)| BIT24); + +#endif + debug_write((DBG_DDR_IDX_CPRI_BASE+5), i); + //debug_write((DBG_DDR_IDX_CPRI_BASE+4), j); +#if 1 + //ucp_nop(400); + + //if(0xA0 < (((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK))>>8) & 0xFF)) + if(0x80 < (((do_read_volatile(((DBG_DDR_IDX_CPRI_BASE+4)<<2)+DBG_DDR_ADDR_BASE))>>8) & 0xFF)) + { + j++; + debug_write((DBG_DDR_IDX_CPRI_BASE+6), j); + delay_us(10000); + //if((do_read_volatile(&AUX_INT_FLAG) & BIT2) == 0x4) + if(do_read_volatile(&CPRI_FRAME_RX_STAT) == 0x1E) + //if (1 < gCpriSyncIntCnt) + { + break; + } + } + + +#endif + + } + +#if 0 + uint32_t resynctimes = 0; + delay_us(10000); + for(uint32_t i=0;i<500;i++) + { + if(do_read_volatile(&CPRI_FRAME_RX_STAT) != 0x1E) + { + resynctimes++; + jecspma_recrx_eq(); + debug_write((DBG_DDR_IDX_CPRI_BASE+3), i); + debug_write((DBG_DDR_IDX_CPRI_BASE+7), resynctimes); + } + else + { + delay_us(1000); + } + } +#endif + +} +void init_cpri(uint32_t cpri_speed_sel) +{ +// uint32_t resynctimes = 0; + //JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | BIT4;//cpri tx pma sel jecs + do_write(&JECS_CTRL_PROTOCOL_SEL, do_read_volatile(&JECS_CTRL_PROTOCOL_SEL) | BIT4); + +#if 0 + /************************************ + 配置光模块使能：PD16/AP_GPIO0B29 + 低：光模块发射打开 + 高：光模块发射关闭 + *****************************************/ + // do_write((GPIO0_A29_PINMUX_REG_ADDR+0xc), (do_read_volatile((GPIO0_A29_PINMUX_REG_ADDR+0xc))|0x3)); + do_write((0x0445818c), (do_read_volatile(0x0445818c)|0x3));//pinmux + __ucps2_synch(f_SM); + do_write((0x04450010), (do_read_volatile(0x04450010)|(BIT29))); //dir:1:out;0:in + __ucps2_synch(f_SM); + do_write((0x0445000c), (do_read_volatile(0x0445000c)&(~(BIT29)))); // data:0 + __ucps2_synch(f_SM); + delay_us(1000); +#endif + + init_cpri_pma_rst(); + + Init_cpri_clk(cpri_speed_sel); + + Init_jecspma(cpri_speed_sel); + + init_jecspma_rectx(); + + do_write(SERDES_INIT_FLAG_ADDR, 1); // cpri serdes clk init finished + + do_write(&JECS_CRG_CPRI0_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI0_RST_CTRL) | BIT24); + do_write(&JECS_CRG_CPRI1_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI1_RST_CTRL) | BIT24); + do_write(&JECS_CRG_CPRI2_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI2_RST_CTRL) | BIT24); + do_write(&JECS_CRG_CPRI3_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI3_RST_CTRL) | BIT24); + do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL) | BIT24); + do_write(&JECS_CRG_CPRI5_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI5_RST_CTRL) | BIT24); + do_write(&JECS_CRG_CPRI6_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI6_RST_CTRL) | BIT24); + do_write(&ECPRI_RST_CFG_REG, do_read_volatile(&ECPRI_RST_CFG_REG) | BIT24); + do_write(&AUX_CTRL_REG, do_read_volatile(&AUX_CTRL_REG) & (~BIT2)); + ucp_nop(400); + if(8 == cpri_speed_sel)//option8 + { + do_write(&CPRI_PCS_64B66B_CFG, 0); + do_write(&CPRI_FRAME_RX_CFG, 0x14|BIT8); + Clk_To_XTAL(); + do_write(&CPRI_PCS_ADDR_CFG, 0); + do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0x1C); + do_write(&CPRI_PCS_DATA_TX_CFG, 0); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xB8); + do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xBC); + do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + +//恢复正常 + Clk_To_Normal(); + + do_write(&CPRI_FRAME_TX_CM_CFG, 0x114); + do_write(&CPRI_FRAME_TX_PROT_VER, 0x1); + do_write(&CPRI_FRAME_TX_BFN_INIT, 0x10000); + do_write(&CPRI_FRAME_TX_SCRAMBLER, 0x0); + do_write(&CPRI_FRAME_TX_CFG, BIT2|BIT1); + } + else if(10 == cpri_speed_sel)//option10 + { + do_write(&CPRI_PCS_64B66B_CFG, 0); + do_write(&CPRI_FRAME_RX_CFG, 0x30|BIT8); + Clk_To_XTAL(); + do_write(&CPRI_PCS_ADDR_CFG, 0); + do_write(&CPRI_PCS_DATA_TX_CFG, BIT13|BIT6); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0x1C); + do_write(&CPRI_PCS_DATA_TX_CFG, 0); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xB8); + do_write(&CPRI_PCS_DATA_TX_CFG,0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); + do_write(&CPRI_PCS_ADDR_CFG, 0xBC); + do_write(&CPRI_PCS_DATA_TX_CFG, 0x20<<7|BIT14); + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); +#if 1 + do_write(&CPRI_PCS_ADDR_CFG, 0x320); + do_write(&CPRI_PCS_DATA_TX_CFG, BIT2);//DATA_CFG Enable RS-FEC + do_write(&CPRI_PCS_CTRL_CFG, 0x2); + __ucps2_synch(f_SM); +#endif + Clk_To_Normal(); + do_write(&CPRI_FRAME_TX_CM_CFG, 0x114); + do_write(&CPRI_FRAME_TX_PROT_VER, 0x1); + do_write(&CPRI_FRAME_TX_BFN_INIT, 0x10000); + do_write(&CPRI_FRAME_TX_SCRAMBLER, 0x0); + do_write(&CPRI_FRAME_TX_CFG, BIT2|BIT1); + } + else + { + } + + + jecspma_recrx_eq(); +#if 0 + + delay_us(10000); + for(uint32_t i=0;i<3000;i++) + { + if(do_read_volatile(&CPRI_FRAME_RX_STAT) != 0x1E) + { + resynctimes++; + jecspma_recrx_eq(); + debug_write((DBG_DDR_IDX_CPRI_BASE+3), i); + debug_write((DBG_DDR_IDX_CPRI_BASE+7), resynctimes); + } + else + { + delay_us(10000); + } + } +#endif + do_write(&ALARM_FLAG,0x0); +} +DDR0 uint32_t ID_SIZE_buf[3][16] = { +{1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0}, +{1,1,8,8,8,8,2,2,1,0,0,0,0,0,0,0}, +{1,1,8,8,8,8,8,8,8,8,1,0,0,0,0,0} +}; +uint32_t ID_SIZE[16]={0}; + +void config_cpri_map_directed(uint32_t option,uint32_t MappingMode) +{ + uint64_t addr; + + + if(8 == option) + { + if(OTIC_MAP_FIGURE12 == MappingMode) + { + memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64); + } + else if(OTIC_MAP_FIGURE10 == MappingMode) + { + memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[1], 64); + } + } + else if(10 == option) + { + if(OTIC_MAP_FIGURE16 == MappingMode) + { + memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[2], 64); + } + } + else + { + memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64); + } + + //axc rx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< ID_SIZE[0]*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+0; //id 0 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+1; //id 1 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+2; //id 2 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+3; //id 3 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+4; //id 4 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+5; //id 5 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+6; //id 6 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+7; //id 7 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+8; //id 8 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+9; //id 9 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+10; //id 10 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+11; //id 11 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+12; //id 12 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+13; //id 13 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+14; //id 14 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14]+ID_SIZE[15])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+15; //id 15 + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = 0; + } + } + + //axc tx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< ID_SIZE[0]*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[0]<<16) + ((addr/4)<<8) + BIT7+0; //id 0 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[1]<<16) + ((addr/4)<<8) + BIT7+1; //id 1 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[2]<<16) + ((addr/4)<<8) + BIT7+2; //id 2 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[3]<<16) + ((addr/4)<<8) + BIT7+3; //id 3 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[4]<<16) + ((addr/4)<<8) + BIT7+4; //id 4 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[5]<<16) + ((addr/4)<<8) + BIT7+5; //id 5 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[6]<<16) + ((addr/4)<<8) + BIT7+6; //id 6 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[7]<<16) + ((addr/4)<<8) + BIT7+7; //id 7 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[8]<<16) + ((addr/4)<<8) + BIT7+8; //id 8 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[9]<<16) + ((addr/4)<<8) + BIT7+9; //id 9 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[10]<<16) + ((addr/4)<<8) + BIT7+10; //id 10 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[11]<<16) + ((addr/4)<<8) + BIT7+11; //id 11 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[12]<<16) + ((addr/4)<<8) + BIT7+12; //id 12 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[13]<<16) + ((addr/4)<<8) + BIT7+13; //id 13 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[14]<<16) + ((addr/4)<<8) + BIT7+14; //id 14 + } + else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14]+ID_SIZE[15])*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[15]<<16) + ((addr/4)<<8) + BIT7+15; //id 15 + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = 0; + } + } + + if(8 == option) + { + if(OTIC_MAP_FIGURE12 == MappingMode)//#ifdef CPRI_TIMING_7D2U_TEST + { + //map tx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< 5*4) + { + // op 0:pass 1:right 2:left 3:clr + //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64+8)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64+8+1)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + //(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0; + } + } + + //map rx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< 5*4) + { + // op 0:pass 1:right 2:left 3:clr + //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64+8)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64+8+1)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + //(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0; + } + } + } + if(OTIC_MAP_FIGURE10 == MappingMode) + { + //map tx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< 5*4) + { + // op 0:pass 1:right 2:left 3:clr + //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP + if(addr< 4*4) + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + else + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2)*4) + { + // (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (48<<8)+(1<<14)+(32<<16)+(1<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64+8)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + #if 0 + if(addr< (5+2+64+7)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else//获取NR AGC + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(0<<22)+(0<<24)+(3<<30); + } + #endif + } + else if(addr< (5+2+64+8+1)*4) + { + //(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (56<<8)+(1<<14)+(40<<16)+(1<<22)+(0<<24)+(3<<30); + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (40<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0; + } + } + + //map rx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< 5*4) + { + // op 0:pass 1:right 2:left 3:clr + //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + + } + else if(addr< (5+2)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(48<<16)+(2<<22)+(0<<24)+(3<<30); + + } + else if(addr< (5+2+64)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64+8)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); + } + else if(addr< (5+2+64+8+1)*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (40<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + // addr = addr +4; + // (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0 + BIT4 + BIT5 + (56<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0; + } + } + } + } + + if(10 == option) + { + if(OTIC_MAP_FIGURE16 == MappingMode) + { + //map tx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< 12*4) + { + // op 0:pass 1:right 2:left 3:clr + //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP + if(addr< 11*4) + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + } + else if(addr< (12+2)*4)//compress + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (48<<8)+(1<<14)+(32<<16)+(1<<22)+(0<<24)+(3<<30); //need to confirm location + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (12+2+64)*4)//NR小区0 + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (12+2+64+64)*4)//NR小区1 + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + } + else if(addr< (12+2+64+64+49)*4)//Reserve + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + } + else if(addr< (12+2+64+64+49+1)*4)//Agc + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0; + } + } + + //map rx cfg + for(addr = 0; addr<0x400;addr = addr +4) + { + if(addr< 12*4) + { // op 0:pass 1:right 2:left 3:clr + //EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + + } + else if(addr< (12+2)*4)//compress + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//Compress NR小区0 + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(48<<16)+(2<<22)+(0<<24)+(3<<30);//Compress NR小区1 + + } + else if(addr< (12+2+64)*4)//NR小区0 + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); + } + else if(addr< (12+2+64+64)*4)//NR小区1 + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30); + addr = addr +4; + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30); + } + else if(addr< (12+2+64+64+49)*4)//Reserve + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + } + else if(addr< (12+2+64+64+49+1)*4)//AGC + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location + } + else + { + (*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0; + } + } + + } + } + + CPRI_MAP_TOGGLE = BIT0; + //start_cpri_map(); +} + +void start_cpri_map(void) +{ +// CPRI_MAP_CFG = BIT4|BIT0;//enable map Tx and Rx + + do_write((&CPRI_MAP_CFG), (BIT4|BIT0)); +// do_write((&CPRI_MAP_CFG), BIT0); + +} + +void stop_cpri_map(void) +{ +// CPRI_MAP_CFG = BIT4|BIT0;//enable map Tx and Rx + + do_write((&CPRI_MAP_CFG), BIT0); + +} + +/*****************GMAC******************/ +/**************** + dma_ch:Queue0~7 + Tx_des_base:基地址 + Rx_des_base:基地址 +***********************/ +#if 0 +void init_cprigmac(uint32_t dma_ch,uint32_t Tx_des_base,uint32_t Rx_des_base) +{ + uint32_t i; + + JECS_CRG_CPRI1_CLK_CTRL = 0x527000;//for rx gmii 125M + JECS_CRG_CPRI2_CLK_CTRL = 0x527000;//for tx gmii 125M + //SET 1000M + GMAC2_MAC_Configuration = 0x00002003;//bit13:0代表全双工；bit14:15:1Gbps + //enable 4 rx q Queue enabled for DCB/Generic + GMAC2_MAC_RxQ_Ctrl0 = 0x000000aa; + // routing of multicast, broadcast, AV,DCB, and untagged packets to to the Rx queues + GMAC2_MAC_RxQ_Ctrl1 = 0x00000000+(dma_ch<<8)+(dma_ch<<4)+(dma_ch<<12)+(dma_ch<<16); + //set 4 rx q Priorities + GMAC2_MAC_RxQ_Ctrl2 = 0x08040201; + //VLAN Tag in Rx status is enabled and Always strip VLAN Tag + GMAC2_MAC_VLAN_Tag = 0x01600000; + //recv all packet Hash or Perfect Filter is enabled + GMAC2_MAC_Packet_Filter = 0x80000400; + //set mac for channel 0-3 + //GMAC2_MAC_Address0_High = 0x80000607; + //GMAC2_MAC_Address1_High = 0x80011607; + //GMAC2_MAC_Address2_High = 0x80022607; + //GMAC2_MAC_Address3_High = 0x80033607; + //GMAC2_MAC_Address0_Low = 0x08090a00; + //GMAC2_MAC_Address1_Low = 0x08090a00; + //GMAC2_MAC_Address2_Low = 0x08090a00; + //GMAC2_MAC_Address3_Low = 0x08090a00; + GMAC2_MAC_Ext_Configuration = 0; + GMAC2_MAC_Ext_Configuration = 0; + GMAC2_MAC_Ext_Configuration = 0; + GMAC2_MAC_Ext_Configuration = 0; + //SET Tran queue size 1 Transmit Queue Enable Transmit Store and Forward + //When this bit is set, the transmission starts when a full packet + //resides in the MTL Tx queue. + GMAC2_MTL_TxQ0_Operation_Mode = 0x0001000a; + GMAC2_MTL_TxQ1_Operation_Mode = 0x0001000a; + GMAC2_MTL_TxQ2_Operation_Mode = 0x0001000a; + GMAC2_MTL_TxQ3_Operation_Mode = 0x0001000a; + //set Quantum or Weights + GMAC2_MTL_TxQ0_Quantum_Weight = 0x5; + GMAC2_MTL_TxQ1_Quantum_Weight = 0x5; + GMAC2_MTL_TxQ2_Quantum_Weight = 0x14; + GMAC2_MTL_TxQ3_Quantum_Weight = 0x14; + //set0 + GMAC2_MTL_Operation_Mode = 0; + //set Receive Queue Threshold Control 128 bytes + //drop err packet recv less 64 packet + GMAC2_MTL_RxQ0_Operation_Mode = 0xf00033; + GMAC2_MTL_RxQ1_Operation_Mode = 0xf00033; + GMAC2_MTL_RxQ2_Operation_Mode = 0xf00033; + GMAC2_MTL_RxQ3_Operation_Mode = 0xf00033; + //rx q0 for dma0 q1 for dma1 q2 for dma2 q3 for dma3 + GMAC2_MTL_RxQ_DMA_Map0 = 0x03020100; + //GMAC2_MTL_RxQ_DMA_Map1 = 0x07060504; + //set Receive Queue Threshold Control 128 bytes + //drop err packet recv less 64 packet + //RQS 1 + GMAC2_MTL_RxQ0_Operation_Mode = 0x00f00033; + GMAC2_MTL_RxQ1_Operation_Mode = 0x00f00033; + GMAC2_MTL_RxQ2_Operation_Mode = 0x00f00033; + GMAC2_MTL_RxQ3_Operation_Mode = 0x00f00033; + //Receive Queue Overflow Interrupt Enable + //Transmit Queue Underflow Interrupt Enable + GMAC2_MTL_Q0_Interrupt_Control_Status = 0X01000100; + GMAC2_MTL_Q1_Interrupt_Control_Status = 0X01000100; + GMAC2_MTL_Q2_Interrupt_Control_Status = 0X01000100; + GMAC2_MTL_Q3_Interrupt_Control_Status = 0X01000100; + //Receive Queue Packet Arbitration is enable and weight 3 + GMAC2_MTL_RxQ0_Control = 0X00000007; + GMAC2_MTL_RxQ1_Control = 0X00000007; + GMAC2_MTL_RxQ2_Control = 0X00000007; + GMAC2_MTL_RxQ3_Control = 0X00000007; + //Transmit Programmable Burst Length = 16 Transmit Channel Weight = 3 + GMAC2_DMA_CH0_Tx_Control = 0x00100006; + GMAC2_DMA_CH1_Tx_Control = 0x00100006; + GMAC2_DMA_CH2_Tx_Control = 0x00100006; + GMAC2_DMA_CH3_Tx_Control = 0x00100006; + //DMA descriptor + GMAC2_DMA_CH0_TxDesc_List_Address = Tx_des_base ; + GMAC2_DMA_CH1_TxDesc_List_Address = Tx_des_base ; + GMAC2_DMA_CH2_TxDesc_List_Address = Tx_des_base ; + GMAC2_DMA_CH3_TxDesc_List_Address = Tx_des_base ; + //ring 1f + GMAC2_DMA_CH0_TxDesc_Ring_Length = 0x3ff; + GMAC2_DMA_CH1_TxDesc_Ring_Length = 0x3ff; + GMAC2_DMA_CH2_TxDesc_Ring_Length = 0x3ff; + GMAC2_DMA_CH3_TxDesc_Ring_Length = 0x3ff; + //set axi mode + GMAC2_DMA_SysBus_Mode = 0x0103000e + BIT11; + //set mode - + GMAC2_DMA_CH0_Control = 0; + GMAC2_DMA_CH1_Control = 0; + GMAC2_DMA_CH2_Control = 0; + GMAC2_DMA_CH3_Control = 0; + //Receive Programmable Burst Length 16 Receive Buffer size 4K + GMAC2_DMA_CH0_Rx_Control = 0x00101000; + GMAC2_DMA_CH1_Rx_Control = 0x00101000; + GMAC2_DMA_CH2_Rx_Control = 0x00101000; + GMAC2_DMA_CH3_Rx_Control = 0x00101000; + //DMA descriptor + GMAC2_DMA_CH0_RxDesc_List_Address = Rx_des_base ; + GMAC2_DMA_CH1_RxDesc_List_Address = Rx_des_base ; + GMAC2_DMA_CH2_RxDesc_List_Address = Rx_des_base ; + GMAC2_DMA_CH3_RxDesc_List_Address = Rx_des_base ; + //ring 1f + GMAC2_DMA_CH0_RxDesc_Ring_Length = 0X3Ff; + GMAC2_DMA_CH1_RxDesc_Ring_Length = 0X3Ff; + GMAC2_DMA_CH2_RxDesc_Ring_Length = 0X3Ff; + GMAC2_DMA_CH3_RxDesc_Ring_Length = 0X3Ff; + //int en + GMAC2_DMA_CH0_Interrupt_Enable = 0x0000f0df; + GMAC2_DMA_CH1_Interrupt_Enable = 0x0000f0df; + GMAC2_DMA_CH2_Interrupt_Enable = 0x0000f0df; + GMAC2_DMA_CH3_Interrupt_Enable = 0x0000f0df; + + GMAC2_DMA_Mode = 0; + + // sunny modify // +#if 0 + for(i=0;i<10;i++){ + //write descriptor + (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+0ul ))) = RX_DES_BASE + 0x08000000 + i*0x800;//4EE1 + (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+4ul ))) = 0 ; + (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+8ul ))) = RX_DES_BASE + 0x08000000 + i*0x800 + 0x40 ; + (*((volatile uint32_t *)(GMAC2_DMA_CH0_RxDesc_List_Address+/*dma_ch*0x80+*/i*16+12ul))) = 0xc1000000 ; + } +#endif + + switch(dma_ch){ + case 0x0 : GMAC2_DMA_CH0_RxDesc_Tail_Pointer = GMAC2_DMA_CH0_RxDesc_List_Address + 0x10*50; break; + case 0x1 : GMAC2_DMA_CH1_RxDesc_Tail_Pointer = GMAC2_DMA_CH1_RxDesc_List_Address + 0x10*50; break; + case 0x2 : GMAC2_DMA_CH2_RxDesc_Tail_Pointer = GMAC2_DMA_CH2_RxDesc_List_Address + 0x10*50; break; + case 0x3 : GMAC2_DMA_CH3_RxDesc_Tail_Pointer = GMAC2_DMA_CH3_RxDesc_List_Address + 0x10*50; break; + } + +// clean_all_cache(); + //start dma rx + switch(dma_ch){ + case 0x0 :GMAC2_DMA_CH0_Rx_Control |= BIT0; break; + case 0x1 :GMAC2_DMA_CH1_Rx_Control |= BIT0; break; + case 0x2 :GMAC2_DMA_CH2_Rx_Control |= BIT0; break; + case 0x3 :GMAC2_DMA_CH3_Rx_Control |= BIT0; break; + } + +} +#endif + +/***********************AUX interface**********************/ +void AUX_Rx_init(uint32_t Buffer0,uint32_t Buffer1,uint32_t Len0,uint32_t Len1) +{ + +// AWADDR0 = Buffer0;//axi首地址寄存器0 +// AXI_LEN0 = Len0; //axi长度寄存器0 +// AWADDR1 = Buffer1;//axi首地址寄存器1 +// AXI_LEN1 = Len1; //axi长度寄存器1 + do_write(&AWADDR0,Buffer0); + do_write(&AXI_LEN0,Len0); + do_write(&AWADDR1,Buffer1); + do_write(&AXI_LEN1,Len1); + +} +/************************************ +Axi_mode: + 01:写完第一块buffer停住 + 10：写完两块buffer停住 + 11:来回写两块buffer +*************************************/ +void AUX_Rx_enable(uint32_t Axi_mode) +{ + AUX_CTRL_REG |= (Axi_mode<<16);//bit17:16表示axi_mode:0x01:表示写完第一块buffer停住；0x10:写完两块buffer停住；0x11来回写两块buffer +} + +void AUX_Rx_Disable() +{ + + AUX_CTRL_REG &= 0xFFFCFFFF;//bit17:16 :0,axi disable，and aux_rx disable +} + + +void AUX_Tx_enable() +{ + + AUX_CTRL_REG |= BIT0;//bit0:aux_tx start +} + +void AUX_Tx_Disable() +{ + + AUX_CTRL_REG &= 0xFFFFFFFE;//bit0:aux_tx disable +} + + +/************************************** parameter description*************************** + uint32_t Num :tx aux插入点的个数，有效值为1~10; + uint32_t DATA_CNT[] :在一个Hyper Frame里，插入basic frame的位置，有效值为0~255; + uint32_t DATA_CNT_POS[] :在一个basic frame里，插入的位置，有效值根据速率而定（根据CPRI 6.1 IP手册,Table 7-7，Figure 7-10）; + //DATA_CNT_POS[] + //6:40; + //9:64; + //8:64; + //10:80; + //12:96; + //24:192; +***********************************************************************************/ + +void AUX_Data_insert(uint32_t Num,uint8_t DATA_CNT[],uint8_t DATA_CNT_POS[],uint32_t DATA_TX[],uint32_t DATA_EN[]) +{ + //AUX_CTRL_REG = BIT0;//enable aux tx + + AUX_INS_NUM = Num;//AUX_INS_NUM[3:0]:tx aux插入点的个数，有效值为1~10 + + /*******插入数据帧寄存器:DATA_CNT_X0/DATA_CNT_X1/DATA_CNT_X2*************** + DATA_CNT_X0[31:24]:插入帧3 aux_cnt_x3 + DATA_CNT_X0[23:16]:插入帧2 aux_cnt_x2 + DATA_CNT_X0[15:8] :插入帧1 aux_cnt_x1 + DATA_CNT_X0[7:0] :插入帧0 aux_cnt_x0 + + DATA_CNT_X1[31:24]:插入帧3 aux_cnt_x7 + DATA_CNT_X1[23:16]:插入帧2 aux_cnt_x6 + DATA_CNT_X1[15:8] :插入帧1 aux_cnt_x5 + DATA_CNT_X1[7:0] :插入帧0 aux_cnt_x4 + + DATA_CNT_X2[31:16]:reserved + DATA_CNT_X2[15:8] :插入帧1 aux_cnt_x1 + DATA_CNT_X2[7:0] :插入帧0 aux_cnt_x0 + *****************************************************************************/ + DATA_CNT_X0 = (DATA_CNT[3]<<24)+(DATA_CNT[2]<<16)+(DATA_CNT[1]<<8)+DATA_CNT[0]; + DATA_CNT_X1 = (DATA_CNT[7]<<24)+(DATA_CNT[6]<<16)+(DATA_CNT[5]<<8)+DATA_CNT[4]; + DATA_CNT_X2 = (DATA_CNT[9]<<8)+DATA_CNT[8]; + + /******插入数据位置寄存器:DATA_CNT_POS0/DATA_CNT_POS1/DATA_CNT_POS2******* + DATA_CNT_POS0[31:24]:插入位置3 aux_cnt_pos3 + DATA_CNT_POS0[23:16]:插入位置2 aux_cnt_pos2 + DATA_CNT_POS0[15:8] :插入位置1 aux_cnt_pos1 + DATA_CNT_POS0[7:0] :插入位置0 aux_cnt_pos0 + + DATA_CNT_POS1[31:24]:插入位置7 aux_cnt_pos7 + DATA_CNT_POS1[23:16]:插入位置6 aux_cnt_pos6 + DATA_CNT_POS1[15:8] :插入位置5 aux_cnt_pos5 + DATA_CNT_POS1[7:0] :插入位置4 aux_cnt_pos4 + + DATA_CNT_POS2[31:16]:reserved + DATA_CNT_POS2[15:8] :插入位置9 aux_cnt_pos9 + DATA_CNT_POS2[7:0] :插入位置8 aux_cnt_pos8 + *****************************************************************************/ + DATA_CNT_POS0 = (DATA_CNT_POS[3]<<24)+(DATA_CNT_POS[2]<<16)+(DATA_CNT_POS[1]<<8)+DATA_CNT_POS[0]; + DATA_CNT_POS1 = (DATA_CNT_POS[7]<<24)+(DATA_CNT_POS[6]<<16)+(DATA_CNT_POS[5]<<8)+DATA_CNT_POS[4]; + DATA_CNT_POS2 = (DATA_CNT_POS[9]<<8)+DATA_CNT_POS[8]; + + /* AUX_DATA_TX0~9[31:0]:插入data值 32bit*/ + AUX_DATA_TX0 = DATA_TX[0]; + AUX_DATA_TX1 = DATA_TX[1]; + AUX_DATA_TX2 = DATA_TX[2]; + AUX_DATA_TX3 = DATA_TX[3]; + AUX_DATA_TX4 = DATA_TX[4]; + AUX_DATA_TX5 = DATA_TX[5]; + AUX_DATA_TX6 = DATA_TX[6]; + AUX_DATA_TX7 = DATA_TX[7]; + AUX_DATA_TX8 = DATA_TX[8]; + AUX_DATA_TX9 = DATA_TX[9]; + + /* AUX_DATA_EN0~9:插入data按位使能 */ + AUX_DATA_EN0 = DATA_EN[0];//0xffffff00; + AUX_DATA_EN1 = DATA_EN[1];//0xffff00ff; + AUX_DATA_EN2 = DATA_EN[2];//0xff00ffff; + AUX_DATA_EN3 = DATA_EN[3];//0x00ffffff; + AUX_DATA_EN4 = DATA_EN[4];//0xffffffff; + AUX_DATA_EN5 = DATA_EN[5];//0xffffffff; + AUX_DATA_EN6 = DATA_EN[6];//0xffffffff; + AUX_DATA_EN7 = DATA_EN[7];//0xffffffff; + AUX_DATA_EN8 = DATA_EN[8];//0xffffffff; + AUX_DATA_EN9 = DATA_EN[9];//0xffffffff; + +} + + +/************************************** parameter description 同AUX_Data_insert()***************************/ + +void AUX_Ctrl_insert(uint32_t Num,uint8_t CTRL_CNT[],uint8_t CTRL_CNT_POS[],uint8_t CTRL_TX[],uint8_t CTRL_EN[]) +{ + /*************插入控制寄存器：CTRL_CNT_X0/CTRL_CNT_X1/CTRL_CNT_X2 + CTRL_CNT_X0[31:24]:插入控制帧3 ctrl_cnt_x3 + CTRL_CNT_X0[23:16]:插入控制帧2 ctrl_cnt_x2 + CTRL_CNT_X0[15:8] :插入控制帧1 ctrl_cnt_x1 + CTRL_CNT_X0[7:0] :插入控制帧0 ctrl_cnt_x0 + + CTRL_CNT_X1[31:24]:插入控制帧3 ctrl_cnt_x7 + CTRL_CNT_X1[23:16]:插入控制帧2 ctrl_cnt_x6 + CTRL_CNT_X1[15:8] :插入控制帧1 ctrl_cnt_x5 + CTRL_CNT_X1[7:0] :插入控制帧0 ctrl_cnt_x4 + + CTRL_CNT_X2[31:16]:reserved + CTRL_CNT_X2[15:8] :插入控制帧1 ctrl_cnt_x1 + CTRL_CNT_X2[7:0] :插入控制帧0 ctrl_cnt_x8 + *****************************************************************/ + CTRL_CNT_X0 = (CTRL_CNT[3]<<24)+(CTRL_CNT[2]<<16)+(CTRL_CNT[1]<<8)+CTRL_CNT[0]; + CTRL_CNT_X1 = (CTRL_CNT[7]<<24)+(CTRL_CNT[6]<<16)+(CTRL_CNT[5]<<8)+CTRL_CNT[4]; + CTRL_CNT_X2 = (CTRL_CNT[9]<<8)+CTRL_CNT[8]; + + /*************插入控制位置寄存器：CTRL_CNT_POS0/CTRL_CNT_POS1/CTRL_CNT_POS2 + CTRL_CNT_POS0[31:24]:插入控制位置3 ctrl_cnt_pos3 + CTRL_CNT_POS0[23:16]:插入控制位置2 ctrl_cnt_pos2 + CTRL_CNT_POS0[15:8] :插入控制位置1 ctrl_cnt_pos1 + CTRL_CNT_POS0[7:0] :插入控制位置0 ctrl_cnt_pos0 + + CTRL_CNT_POS1[31:24]:插入控制位置3 ctrl_cnt_pos7 + CTRL_CNT_POS1[23:16]:插入控制位置2 ctrl_cnt_pos6 + CTRL_CNT_POS1[15:8] :插入控制位置1 ctrl_cnt_pos5 + CTRL_CNT_POS1[7:0] :插入控制位置0 ctrl_cnt_pos4 + + CTRL_CNT_POS2[31:16]:reserved + CTRL_CNT_POS2[15:8] :插入控制位置1 ctrl_cnt_pos1 + CTRL_CNT_POS2[7:0] :插入控制位置0 ctrl_cnt_pos0 + *****************************************************************/ + CTRL_CNT_POS0 = (CTRL_CNT_POS[3]<<24)+(CTRL_CNT_POS[2]<<16)+(CTRL_CNT_POS[1]<<8)+CTRL_CNT_POS[0]; + CTRL_CNT_POS1 = (CTRL_CNT_POS[7]<<24)+(CTRL_CNT_POS[6]<<16)+(CTRL_CNT_POS[5]<<8)+CTRL_CNT_POS[4]; + CTRL_CNT_POS2 = (CTRL_CNT_POS[9]<<8)+CTRL_CNT_POS[8]; + + /* AUX_DATA_TX0~9[31:0]:插入控制值 4bit*/ + AUX_CTRL_TX0 = ((CTRL_TX[7]&0xf)<<28)+((CTRL_TX[6]&0xf)<<24)+((CTRL_TX[5]&0xf)<<20)+((CTRL_TX[4]&0xf)<<16)+((CTRL_TX[3]&0xf)<<12)+((CTRL_TX[2]&0xf)<<8)+((CTRL_TX[1]&0xf)<<4)+ (CTRL_TX[0]&0xf);//aux_ctrl_tx0~7,bit0:3,bit4:7,bit8:11,bit12:15,bit16:19,bit20:23,bit24:27,bit28:31 + AUX_CTRL_TX1 = ((CTRL_TX[9]&0xf)<<4)+ (CTRL_TX[8]&0xf);//aux_ctrl_tx8~9,bit0:3,bit4:7 + + /* AUX_DATA_TX0~9[31:0]:插入data值 4bit*/ + AUX_CTRL_EN_TX0 =((CTRL_EN[7]&0xf)<<28)+((CTRL_EN[6]&0xf)<<24)+((CTRL_EN[5]&0xf)<<20)+((CTRL_EN[4]&0xf)<<16)+((CTRL_EN[3]&0xf)<<12)+((CTRL_EN[2]&0xf)<<8)+((CTRL_EN[1]&0xf)<<4)+ (CTRL_EN[0]&0xf);//aux_ctrl_en_tx0~7,bit0:3,bit4:7,bit8:11,bit12:15,bit16:19,bit20:23,bit24:27,bit28:31 + AUX_CTRL_EN_TX1 = ((CTRL_EN[9]&0xf)<<4)+ (CTRL_EN[8]&0xf);//aux_ctrl_en_tx8~9,bit0:3,bit4:7 + +} + +/*******************HeaderRam************* +note:插入控制字，AUX优先级高于HeaderRam**/ + +void HeaderRam_ins_enable() +{ + //CPRI_FRAME_TX_CFG |= BIT5;//Enable TX CTRL HeaderRam insertion + + uint32_t val = do_read_volatile(&CPRI_FRAME_TX_CFG); + val |= BIT5; + do_write(&CPRI_FRAME_TX_CFG,val); +} +void HeaderRam_ins_disable() +{ + //CPRI_FRAME_TX_CFG &= (~BIT5);//disable TX CTRL HeaderRam insertion + + uint32_t val = do_read_volatile(&CPRI_FRAME_TX_CFG); + val &= (~BIT5); + do_write(&CPRI_FRAME_TX_CFG,val); +} + +//uint32_t BF_X:基本帧号 +//uint32_t BF_Ctrlword_wordnum:该基本帧的控制字的第几个32bit +//uint32_t Hdr_Data：要insert的数据 +void HeaderRam_Tx(uint32_t BF_X,uint32_t BF_Ctrlword_wordnum,uint32_t Hdr_Data,uint32_t Hdr_Data_en) +{ + //CPRI_FRAME_TX_HDR_ADDR = 0xF000000+(BF_X<<2)+BF_Ctrlword_wordnum*4;//bit27:24 每个bit位对应data的1个字节的插入使能 ;Hdr_Addr needs to be shifted <<2 to point #X value + //CPRI_FRAME_TX_HDR_DATA =Hdr_Data; + +// do_write(&CPRI_FRAME_TX_HDR_ADDR,0xF000000+(BF_X<<2)+BF_Ctrlword_wordnum); + do_write(&CPRI_FRAME_TX_HDR_ADDR,(Hdr_Data_en<<24)+(BF_X<<2)+BF_Ctrlword_wordnum); + do_write(&CPRI_FRAME_TX_HDR_DATA,Hdr_Data); +} + + +uint32_t HeaderRam_Rx(uint32_t BF_X,uint32_t BF_Ctrlword_wordnum) +{ + uint32_t Hdr_data =0; + + //CPRI_FRAME_RX_HDR_ADDR = (BF_X<<2)+BF_Ctrlword_wordnum*4;//Hdr_Addr needs to be shifted <<2 to point #X value,ie:X=16,Hdr_addr = 0x40; + //Hdr_data = CPRI_FRAME_RX_HDR_DATA; + + do_write(&CPRI_FRAME_RX_HDR_ADDR,(BF_X<<2)+BF_Ctrlword_wordnum); + __ucps2_synch(f_SM); + //do_write(&CPRI_FRAME_RX_HDR_ADDR,(BF_X<<2)+BF_Ctrlword_wordnum); + Hdr_data = do_read_volatile(&CPRI_FRAME_RX_HDR_DATA); + + if(BF_Ctrlword_wordnum == 3) + { + do_write(&CPRI_FRAME_RX_HDR_ADDR,(BF_X<<2)); + } + //if(BF_Ctrlword_wordnum <= 3) + { +// do_write(&CPRI_FRAME_RX_HDR_ADDR,3); + } + return Hdr_data; +} + + +uint32_t UCP_API_CPRI_GetHfnsyncFlag() +{ + uint32_t Flag =0; + //Flag = (AUX_INT_FLAG & BIT2);//Hfnsync + + Flag = ((do_read_volatile(&AUX_INT_FLAG)) & BIT2); + return Flag; +} + + +uint32_t UCP_API_CPRI_GetBuffer1FullFlag() +{ + uint32_t Flag =0; + //Flag = (AUX_INT_FLAG & BIT4);//buffer1 full + + Flag = ((do_read_volatile(&AUX_INT_FLAG)) & BIT4); + return Flag; +} + + +uint32_t UCP_API_CPRI_GetTxHfnCnt() +{ + uint32_t TxHfnCnt =0; + //Cnt = (AUX_CNT0 & 0xFF);// + TxHfnCnt = ((do_read_volatile(&AUX_CNT0)) & 0xFF); + return TxHfnCnt; +} + +uint32_t UCP_API_CPRI_GetTxXCnt() +{ + uint32_t TxXCnt =0; + //Cnt = ((AUX_CNT0 >>8) & 0xFF);// + TxXCnt = (((do_read_volatile(&AUX_CNT0)) >> 8) & 0xFF); + return TxXCnt; +} + +uint32_t UCP_API_CPRI_GetRxHfnCnt() +{ + uint32_t RxHfnCnt =0; + //Cnt = (AUX_CNT0 & 0xFF);// + RxHfnCnt = ((do_read_volatile(&AUX_CNT2)) & 0xFF); + return RxHfnCnt; + +} + +void HeaderTxRam_init(uint32_t vendor) +{ + uint32_t i,j; + HeaderRam_ins_disable(); + for(i=0;i<64;i++)//Ns + { + for(j=0;j<4;j++)// + { + HeaderRam_Tx(i+64*j,0,0,0);//vendor + HeaderRam_Tx(i+64*j,1,0,0);//vendor + HeaderRam_Tx(i+64*j,2,0,0);//vendor + HeaderRam_Tx(i+64*j,3,0,0);//vendor + } + } + do_write(&CPRI_FRAME_RX_HDR_ADDR,0); + __ucps2_synch(f_SM); + do_write(&gVendorFlag,vendor); +} + + +uint8_t SECTION_ALIGNED g_rru_msg_data[CPRI_RRU_MSG_LEN]; +int32_t set_cpri_rru_msg(CpriRruMsg_t rru_msg) +{ + if((0 == rru_msg.msg_addr) || (0 == rru_msg.msg_len)) + { + return -1; + } + + for(int i=0; i<41; i++) + { + *((uint32_t *)&g_rru_msg_data[0] + i) = SWAP32(do_read_volatile(rru_msg.msg_addr + i*4)); + } + + return 0; +} + + +uint32_t get_cpri_rru_msg_addr() +{ + return (uint32_t)g_rru_msg_data; +}