jinhong/YB_Platform
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1. add synch to spu_sw_queue.s.c

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2. change memcpy bu spu_shell.s.c
The above are possible problems found during the current process
This commit is contained in:
lishuang.xie 2023-07-24 09:43:59 +08:00
parent 7e2437c0d6
commit 0a4146be80
2 changed files with 7 additions and 2 deletions
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3
public/common/platform/src/spu_shell.s.c
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@ -119,7 +119,8 @@ void spu_insert_cmd_ext(char *name, OSP_FUNCPTR pfunc, char *desc, uint32_t argn
memcpy_ucp(tlb[num].cmd, name, strlen(name) + 1); memcpy_ucp(tlb[num].cmd, name, strlen(name) + 1);
memcpy_ucp(tlb[num].descption, desc, strlen(desc) + 1); memcpy_ucp(tlb[num].descption, desc, strlen(desc) + 1);
memcpy_ucp(tlb[num].wrapper, (OSP_FUNCPTR)spu_shell_wrapper, sizeof(OSP_FUNCPTR)); tlb[num].wrapper = (OSP_FUNCPTR)spu_shell_wrapper;
//memcpy_ucp(tlb[num].wrapper, (OSP_FUNCPTR)spu_shell_wrapper, sizeof(OSP_FUNCPTR));
//memcpy_ucp(tlb[num].routine, pfunc, sizeof(OSP_FUNCPTR)); //memcpy_ucp(tlb[num].routine, pfunc, sizeof(OSP_FUNCPTR));
tlb[num].routine = pfunc; tlb[num].routine = pfunc;
tlb[num].argnum = argnum; tlb[num].argnum = argnum;

4
public/common/platform/src/spu_sw_queue.s.c
View File

@ -520,11 +520,14 @@ uint8_t spu_sw_enque(spu_sw_queue_index_e emqueue_idx, int8_t *pi8addr)
u16enqueue_cnt++; u16enqueue_cnt++;
u32msg_addr = u32queue_share_addr + SPU_APE_RFM_MSG_OFFSET + SPU_APE_RFM_MSG_SIZE*u16enqueue_idx; u32msg_addr = u32queue_share_addr + SPU_APE_RFM_MSG_OFFSET + SPU_APE_RFM_MSG_SIZE*u16enqueue_idx;
__ucps2_synch(0);
do_write_short(u32msg_addr, u16enque_idx); do_write_short(u32msg_addr, u16enque_idx);
debug_write(DBG_DDR_COMMON_IDX(core_id, 124), u16enque_idx); debug_write(DBG_DDR_COMMON_IDX(core_id, 124), u16enque_idx);
//debug_write(DBG_DDR_COMMON_IDX(core_id, 125), u16enqueue_cnt); //debug_write(DBG_DDR_COMMON_IDX(core_id, 125), u16enqueue_cnt);
debug_write(DBG_DDR_COMMON_IDX(core_id, 126), u32msg_addr); debug_write(DBG_DDR_COMMON_IDX(core_id, 126), u32msg_addr);
debug_write(DBG_DDR_COMMON_IDX(core_id, 127), u32enque_addr); debug_write(DBG_DDR_COMMON_IDX(core_id, 127), u32enque_addr);
__ucps2_synch(0);
do_write_short(u32enque_addr, u16enqueue_cnt); do_write_short(u32enque_addr, u16enqueue_cnt);
return 0; return 0;
} }
@ -563,6 +566,7 @@ uint8_t spu_sw_deque(spu_sw_queue_index_e emqueue_idx, uint32_t **pu32value)
u16queue_msg_idx = do_read_short(u32msg_addr); u16queue_msg_idx = do_read_short(u32msg_addr);
*pu32value = (uint32_t *)(gst_sw_queue_mem[emqueue_idx].u32addr + (u16queue_msg_idx)*SPU_APE_RFM_QUE_SIG_SIZE); *pu32value = (uint32_t *)(gst_sw_queue_mem[emqueue_idx].u32addr + (u16queue_msg_idx)*SPU_APE_RFM_QUE_SIG_SIZE);
__ucps2_synch(0);
do_write_short(u32deque_addr, u16dequeue_cnt); do_write_short(u32deque_addr, u16dequeue_cnt);
return 0; return 0;