1.platform PCIE support 2.readme.txt update
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HUOHUO
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.gitignore
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.gitignore
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*.o
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*.d
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build/
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101
README.md
101
README.md
@ -1,92 +1,9 @@
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# UCP4008_PLATFORM_SPU
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## Getting started
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To make it easy for you to get started with GitLab, here's a list of recommended next steps.
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Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)!
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## Add your files
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- [ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files
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- [ ] [Add files using the command line](https://docs.gitlab.com/ee/gitlab-basics/add-file.html#add-a-file-using-the-command-line) or push an existing Git repository with the following command:
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```
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cd existing_repo
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git remote add origin http://gitlab.smartlogictech.com/ucp/driver/ucp4008_platform_spu.git
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git branch -M main
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git push -uf origin main
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```
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## Integrate with your tools
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- [ ] [Set up project integrations](http://gitlab.smartlogictech.com/ucp/driver/ucp4008_platform_spu/-/settings/integrations)
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## Collaborate with your team
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- [ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/)
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- [ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html)
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- [ ] [Automatically close issues from merge requests](https://docs.gitlab.com/ee/user/project/issues/managing_issues.html#closing-issues-automatically)
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- [ ] [Enable merge request approvals](https://docs.gitlab.com/ee/user/project/merge_requests/approvals/)
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- [ ] [Set auto-merge](https://docs.gitlab.com/ee/user/project/merge_requests/merge_when_pipeline_succeeds.html)
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## Test and Deploy
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Use the built-in continuous integration in GitLab.
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- [ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/index.html)
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- [ ] [Analyze your code for known vulnerabilities with Static Application Security Testing(SAST)](https://docs.gitlab.com/ee/user/application_security/sast/)
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- [ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html)
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- [ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/)
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- [ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html)
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***
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# Editing this README
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When you're ready to make this README your own, just edit this file and use the handy template below (or feel free to structure it however you want - this is just a starting point!). Thank you to [makeareadme.com](https://www.makeareadme.com/) for this template.
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## Suggestions for a good README
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Every project is different, so consider which of these sections apply to yours. The sections used in the template are suggestions for most open source projects. Also keep in mind that while a README can be too long and detailed, too long is better than too short. If you think your README is too long, consider utilizing another form of documentation rather than cutting out information.
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## Name
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Choose a self-explaining name for your project.
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## Description
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Let people know what your project can do specifically. Provide context and add a link to any reference visitors might be unfamiliar with. A list of Features or a Background subsection can also be added here. If there are alternatives to your project, this is a good place to list differentiating factors.
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## Badges
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On some READMEs, you may see small images that convey metadata, such as whether or not all the tests are passing for the project. You can use Shields to add some to your README. Many services also have instructions for adding a badge.
|
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|
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## Visuals
|
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Depending on what you are making, it can be a good idea to include screenshots or even a video (you'll frequently see GIFs rather than actual videos). Tools like ttygif can help, but check out Asciinema for a more sophisticated method.
|
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|
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## Installation
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Within a particular ecosystem, there may be a common way of installing things, such as using Yarn, NuGet, or Homebrew. However, consider the possibility that whoever is reading your README is a novice and would like more guidance. Listing specific steps helps remove ambiguity and gets people to using your project as quickly as possible. If it only runs in a specific context like a particular programming language version or operating system or has dependencies that have to be installed manually, also add a Requirements subsection.
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## Usage
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Use examples liberally, and show the expected output if you can. It's helpful to have inline the smallest example of usage that you can demonstrate, while providing links to more sophisticated examples if they are too long to reasonably include in the README.
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## Support
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Tell people where they can go to for help. It can be any combination of an issue tracker, a chat room, an email address, etc.
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||||
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## Roadmap
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If you have ideas for releases in the future, it is a good idea to list them in the README.
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## Contributing
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State if you are open to contributions and what your requirements are for accepting them.
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For people who want to make changes to your project, it's helpful to have some documentation on how to get started. Perhaps there is a script that they should run or some environment variables that they need to set. Make these steps explicit. These instructions could also be useful to your future self.
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You can also document commands to lint the code or run tests. These steps help to ensure high code quality and reduce the likelihood that the changes inadvertently break something. Having instructions for running tests is especially helpful if it requires external setup, such as starting a Selenium server for testing in a browser.
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## Authors and acknowledgment
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Show your appreciation to those who have contributed to the project.
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## License
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For open source projects, say how it is licensed.
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## Project status
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If you have run out of energy or time for your project, put a note at the top of the README saying that development has slowed down or stopped completely. Someone may choose to fork your project or volunteer to step in as a maintainer or owner, allowing your project to keep going. You can also make an explicit request for maintainers.
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compile:
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stage1:
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config ./public/make
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MaPU_TC_HOME := /home/ittc/Software/mcstudio/toolchain
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stage2:
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./build.sh --jesd --pcie --test 52 --mask 255
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stage3:
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build res path:
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./build
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@ -15,7 +15,7 @@
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#ifndef __MSG_TRANSFER_LAYER_H__
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#define __MSG_TRANSFER_LAYER_H__
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#define MAX_INSTANCE_NUM (4)
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#define MAX_INSTANCE_NUM (2)
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#define MAX_PORT_NUM (4)
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#define SUCCESS (0)
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@ -31,6 +31,8 @@
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#ifndef PCIE_BACKHAUL
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#define HANDSHKAE_MASK 0x00000e00//excluded APE cores
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#elif (defined(PCIE_WITH_JESD))
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#define HANDSHKAE_MASK 0x00000e00//excluded APE cores
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#else
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#define HANDSHKAE_MASK 0x00000f00//excluded APE cores
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#endif
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@ -41,13 +43,12 @@ typedef struct tUcpHandshake{
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uint32_t heartbeat[MAX_NUM_CORE];
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} UcpHandshake_t;
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UcpHandshake_t* get_handshake_info(void);
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//void handshake_with_host(void);
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void handshake_master_with_slave(uint32_t u32_core_mask);
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UcpHandshake_t * get_handshake_info(void);
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void handshake_master_with_slave(uint32_t core_mask);
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void handshake_slave_with_master(void);
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int32_t get_host_core_id(void);
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void handshake_request_from_host(int32_t core_id);
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void handshake_response_to_host(int32_t core_id);
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uint32_t get_host_core_mask(void);
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void handshake_request_from_host(uint32_t core_mask);
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void handshake_response_to_host(uint32_t core_mask);
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#endif
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@ -20,37 +20,57 @@
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#include "msg_transfer_mem.h"
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#include "pet_sm_mgt.h"
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UcpHandshake_t* get_handshake_info(void)
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UcpHandshake_t * get_handshake_info(void)
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{
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PetSmLocalMgt_t* pPetSmLocalMgt = get_pet_sm_local_mgt();
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return pPetSmLocalMgt->pHandshake;
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PetSmLocalMgt_t *pPetSmLocalMgt = get_pet_sm_local_mgt();
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return pPetSmLocalMgt->pHandshake;
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}
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int32_t get_host_core_id(void)
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uint32_t get_host_core_mask(void)
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{
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int32_t core_id;
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uint32_t core_mask = 0;
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#ifndef PCIE_BACKHAUL
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/*ARM A72 will call msg_transfer_init on TMAC_BACKHAUL mode*/
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core_id = NPU_CORE_ID;
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core_mask = (0x1 << NPU_CORE_ID);
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#elif (defined(PCIE_WITH_JESD))
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/*ARM A72 & PET RFM SPU0 will call msg_transfer_init on PCIE_WITH_JESD mode*/
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core_mask = (0x1 << NPU_CORE_ID) | (0x01 << PET_RFM_SPU0_CORE_ID);
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#else
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/*PET RFM SPU0 will call msg_transfer_init on PCIE_BACKHAUL mode*/
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core_id = PET_RFM_SPU0_CORE_ID;
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core_mask = (0x1 << PET_RFM_SPU0_CORE_ID);
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#endif
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return core_id;
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return core_mask;
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}
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//host is the core which called msg_transfer_init
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void handshake_request_from_host(int32_t core_id)
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void handshake_request_from_host(uint32_t core_mask)
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{
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volatile uint32_t request = 0;
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UcpHandshake_t* pHandshake = (UcpHandshake_t *)get_handshake_info();
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uint32_t core_ready_mask = 0;
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UcpHandshake_t *pHandshake = (UcpHandshake_t *)get_handshake_info();
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while(1) {
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request = do_read_volatile(&pHandshake->request[core_id]);
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if (request == (core_id + HANDSHKAE_REQ_VALUE)) {
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UCP_PRINT_EMPTY("Recieved handshake request message from core[0x%08x],value[0x%08x].",core_id,request);
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while (1)
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{
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for (uint32_t i = 0; i < MAX_NUM_CORE; i++)
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{
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if ((core_mask >> i) & 0x1)
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{
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request = do_read_volatile(&pHandshake->request[i]);
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if (request == (HANDSHKAE_REQ_VALUE + i))
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{
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UCP_PRINT_EMPTY("Recieved handshake request message from core[0x%08x], value[0x%08x].", i, request);
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core_ready_mask |= (1 << i);
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}
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}
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}
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if (core_mask == (core_ready_mask & core_mask))
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{
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UCP_PRINT_EMPTY("all cores are ready.");
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break;
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}
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}
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@ -59,31 +79,40 @@ void handshake_request_from_host(int32_t core_id)
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}
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//host is the core which called msg_transfer_init
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void handshake_response_to_host(int32_t core_id)
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void handshake_response_to_host(uint32_t core_mask)
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{
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uint32_t response= (core_id + HANDSHKAE_RESP_VALUE);
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UcpHandshake_t* pHandshake = (UcpHandshake_t *)get_handshake_info();
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volatile uint32_t response = 0;
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UcpHandshake_t *pHandshake = (UcpHandshake_t *)get_handshake_info();
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do_write(&pHandshake->response[core_id], response);
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UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x],value[0x%08x].",core_id,response);
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for (uint32_t i = 0; i < MAX_NUM_CORE; i++)
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{
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if ((core_mask >> i) & 0x1)
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{
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response = HANDSHKAE_RESP_VALUE + i;
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do_write(&pHandshake->response[i], response);
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UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x], value[0x%08x].", i, response);
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}
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}
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return;
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}
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//msgagent is the core which agented msg_transfer_init,PET_RFM_SPU1_CORE_ID
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void handshake_response_to_msgagent(int32_t core_id)
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void handshake_response_to_msgagent(uint32_t core_id)
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{
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volatile uint32_t request = 0;
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volatile uint32_t response = core_id + HANDSHKAE_RESP_VALUE;
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UcpHandshake_t* pHandshake = (UcpHandshake_t *)get_handshake_info();
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volatile uint32_t response = HANDSHKAE_RESP_VALUE + core_id;
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UcpHandshake_t *pHandshake = (UcpHandshake_t *)get_handshake_info();
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while(1) {
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while (1)
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{
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request = do_read_volatile(&pHandshake->request[core_id]);
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if (request == (core_id + HANDSHKAE_REQ_VALUE)) {
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UCP_PRINT_EMPTY("Recieved handshake request message from core[0x%08x],value[0x%08x].",core_id,request);
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if (request == (HANDSHKAE_REQ_VALUE + core_id))
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{
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UCP_PRINT_EMPTY("Recieved handshake request message from core[0x%08x], value[0x%08x].", core_id, request);
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do_write(&pHandshake->response[core_id], response);
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UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x],value[0x%08x].",core_id,response);
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do_write(&pHandshake->response[core_id], response);
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UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x], value[0x%08x].", core_id, response);
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break;
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}
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}
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@ -92,52 +121,43 @@ void handshake_response_to_msgagent(int32_t core_id)
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}
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//master is the core which controlled the handshake flow
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#if 0
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void handshake_with_host(void)
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{
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int32_t core_id = get_host_core_id();
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handshake_request_from_host(core_id);
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handshake_response_to_host(core_id);
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return;
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}
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#endif
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//master is the core which controlled the handshake flow
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void handshake_master_with_slave(uint32_t u32_core_mask)
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void handshake_master_with_slave(uint32_t core_mask)
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{
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uint32_t core_id = get_core_id();
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volatile uint32_t request = 0;
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uint32_t response;
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uint32_t core_id,coreReadyBitMap,coreMask;
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UcpHandshake_t* pHandshake = (UcpHandshake_t *)get_handshake_info();
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uint32_t ape_core_mask = u32_core_mask;
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uint32_t handshake_coremask = HANDSHKAE_MASK | ape_core_mask;
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volatile uint32_t response = 0;
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uint32_t handshake_core_mask = HANDSHKAE_MASK | core_mask;
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uint32_t core_ready_mask = 0;
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UcpHandshake_t *pHandshake = (UcpHandshake_t *)get_handshake_info();
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core_id = get_core_id();
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coreReadyBitMap = 1 << core_id;
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debug_write(DBG_DDR_COMMON_IDX(core_id,90), handshake_coremask);
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core_ready_mask = 1 << core_id;
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debug_write(DBG_DDR_COMMON_IDX(core_id, 90), handshake_core_mask);
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//msgagent need to run before other cores.
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handshake_response_to_msgagent(PET_RFM_SPU1_CORE_ID);
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while(1) {
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for(uint32_t i = 0; i < MAX_NUM_SPU; i++) {
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coreMask = (handshake_coremask >> i) & 0x1;
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if (coreMask) {
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while (1)
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{
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for (uint32_t i = 0; i < MAX_NUM_SPU; i++)
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{
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if ((handshake_core_mask >> i) & 0x1)
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{
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request = do_read_volatile(&pHandshake->request[i]);
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if (request == (i + HANDSHKAE_REQ_VALUE)) {
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UCP_PRINT_EMPTY("Recieved handshake request message from core[0x%08x],value[0x%08x].",core_id,request);
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if (request == (HANDSHKAE_REQ_VALUE + i))
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{
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UCP_PRINT_EMPTY("Recieved handshake request message from core[0x%08x], value[0x%08x].", i, request);
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response= (i + HANDSHKAE_RESP_VALUE);
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response= (HANDSHKAE_RESP_VALUE + i);
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do_write(&pHandshake->response[i], response);
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UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x],value[0x%08x].",core_id,response);
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UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x], value[0x%08x].", i, response);
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coreReadyBitMap |= (1 << i);
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core_ready_mask |= (1 << i);
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}
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}
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}
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if (handshake_coremask == (coreReadyBitMap & handshake_coremask)) {
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if (handshake_core_mask == (core_ready_mask & handshake_core_mask))
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{
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UCP_PRINT_EMPTY("all cores are ready.");
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break;
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}
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@ -150,20 +170,23 @@ void handshake_master_with_slave(uint32_t u32_core_mask)
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void handshake_slave_with_master(void)
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{
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uint32_t core_id = get_core_id();
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uint32_t request= (core_id + HANDSHKAE_REQ_VALUE);
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volatile uint32_t response;
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UcpHandshake_t* pHandshake = (UcpHandshake_t *)get_handshake_info();
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volatile uint32_t request = HANDSHKAE_REQ_VALUE + core_id;
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volatile uint32_t response = 0;
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UcpHandshake_t *pHandshake = (UcpHandshake_t *)get_handshake_info();
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do_write(&pHandshake->request[core_id], request);
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UCP_PRINT_EMPTY("core[0x%08x] sent handshake request message,value[0x%08x].",core_id,request);
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UCP_PRINT_EMPTY("core[0x%08x] sent handshake request message, value[0x%08x].", core_id, request);
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while(1) {
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while (1)
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{
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response = do_read_volatile(&pHandshake->response[core_id]);
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if (response == (core_id + HANDSHKAE_RESP_VALUE)) {
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UCP_PRINT_EMPTY("core[0x%08x] recieved handshake response message,value[0x%08x].",core_id,response);
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if (response == (HANDSHKAE_RESP_VALUE + core_id))
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{
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UCP_PRINT_EMPTY("core[0x%08x] recieved handshake response message, value[0x%08x].", core_id, response);
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break;
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}
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}
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return;
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}
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@ -17,7 +17,11 @@
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#include "typedef.h"
|
||||
|
||||
#define MAX_INSTANCE_NUM (4) //(2)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
#define MAX_INSTANCE_NUM (4)
|
||||
#else
|
||||
#define MAX_INSTANCE_NUM (2)
|
||||
#endif
|
||||
#define MAX_PORT_NUM (4)
|
||||
|
||||
#define SUCCESS (0)
|
||||
|
||||
@ -115,8 +115,10 @@ void msg_transfer_queue_init(void)
|
||||
MsgQueueCommonInfo_t* chCommon;
|
||||
|
||||
uint32_t i,j;
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++) {
|
||||
for (j = 0; j < UCP4008_TRAFFIC_MAX_NUM; j++) {
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
{
|
||||
for (j = 0; j < UCP4008_TRAFFIC_MAX_NUM; j++)
|
||||
{
|
||||
memcpy_ucp((void *)&pMsgQueueLocalMgt->localQueueCfg[i][j], (void *)pPetSmLocalMgt->pQueueCfg[i][j], sizeof(MsgQueueCfg_t));
|
||||
|
||||
ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localDlQueue[i][j];
|
||||
|
||||
@ -40,7 +40,7 @@ void pet_sm_alloc(void)
|
||||
|
||||
pPetSmLocalMgt->pHandshake = (UcpHandshake_t *)memSectionAlloc(pMemSection, sizeof(UcpHandshake_t), MEM_ALIGNED_4BYTES, "pHandshake");
|
||||
pPetSmLocalMgt->pSyncInfo = (SyncInfo_t *)memSectionAlloc(pMemSection, sizeof(SyncInfo_t), MEM_ALIGNED_4BYTES, "pSyncInfo");
|
||||
pPetSmLocalMgt->pBufIdxBase = (uint16_t *)memSectionAlloc(pMemSection, MAX_INSTANCE_NUM*UCP4008_TRAFFIC_MAX_NUM*MAX_M_BUFFER_NUM*sizeof(uint16_t), MEM_ALIGNED_4BYTES, "pBufIdxBase");
|
||||
pPetSmLocalMgt->pBufIdxBase = (uint16_t *)memSectionAlloc(pMemSection, MAX_INSTANCE_NUM * UCP4008_TRAFFIC_MAX_NUM * MAX_M_BUFFER_NUM * sizeof(uint16_t), MEM_ALIGNED_4BYTES, "pBufIdxBase");
|
||||
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++) {
|
||||
for (j = 0; j < UCP4008_TRAFFIC_MAX_NUM; j++) {
|
||||
|
||||
@ -34,8 +34,9 @@
|
||||
#define do_read_volatile_byte(a) __ucps2_load_ext_mem_v((void *)(a), f_B)
|
||||
#define do_read_volatile_short(a) __ucps2_load_ext_mem_v((void *)(a), f_S)
|
||||
|
||||
#define memcpy_ucp(d,s,l) memcpy_ext((void *__restrict)(d), (const void *__restrict)(s), (l))
|
||||
#define memset_ucp(d,v,l) memset_ext((void *)(d), (uint32_t)(v), (l))
|
||||
#define memcpy_ucp(d,s,l) memcpy_ext((void *__restrict)(d), (const void *__restrict)(s), (l))
|
||||
#define memset_ucp(d,v,l) memset_ext((void *)(d), (uint32_t)(v), (l))
|
||||
#define memcmp_ucp(s1,s2,l) memcmp((const void *)(s1), (const void *)(s2), (l))
|
||||
|
||||
//vector copy,sm address must align 64 bytes
|
||||
#define memcpy_ucp_dm2sm(d,s,l) vmemcpy_dm2sm((void *__restrict)(d), (const void *__restrict)(s), (l))
|
||||
|
||||
@ -23,25 +23,21 @@
|
||||
#define JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0xA380000 // SM5
|
||||
#define JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0xA290400 // SM4
|
||||
#else
|
||||
#define JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR 0x60F00000 // 0xF0000
|
||||
#define JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR 0x60FF0000 // 0xF0000
|
||||
#define JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR 0x61000000 // 0xF0000*4
|
||||
#define JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR 0x613C0000 // 0xF0000*4
|
||||
#endif
|
||||
|
||||
#define JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR 0x6BC00000 // 0xF0000
|
||||
#define JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR 0x6BCF0000 // 0xF0000
|
||||
#define JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR 0x6BC00000 // 0xF0000*4
|
||||
#define JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR 0x6BFC0000 // 0xF0000*4
|
||||
|
||||
#define JESD_15K_FDD_SUBFRAME_SAM_CNT 245760
|
||||
|
||||
|
||||
int32_t jesd_csu_init_lte_fdd();
|
||||
|
||||
int32_t jesd_csu_init_lte_fdd_slot0();
|
||||
|
||||
#if 0
|
||||
int32_t jesd_csu_init_nr_7ds2u_iomode();
|
||||
int32_t jesd_csu_init_nr_7ds2u_8t8r();
|
||||
int32_t jesd_csu_init_nr_7ds2u_4t4r_98();
|
||||
|
||||
int32_t jesd_csu_start_nr_7ds2u();
|
||||
int32_t jesd_csu_start_nr_7ds2u_8t8r();
|
||||
#endif
|
||||
int32_t jesd_csu_init_15K_fdd_1ant();
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -3,6 +3,8 @@
|
||||
|
||||
#include "typedef.h"
|
||||
|
||||
//#define JESD_SAMP_FREQ_245760K
|
||||
|
||||
// 4 ant, NR
|
||||
#define JESD_NRFDD_ANT_NUM 4 // 2 //
|
||||
#define JESD_NRFDD_MARGIN 5
|
||||
@ -11,7 +13,11 @@
|
||||
#define JESD_NRFDD_TX_NODENUM 10
|
||||
#define JESD_NRFDD_RX_NODENUM 10
|
||||
|
||||
#ifdef JESD_SAMP_FREQ_245760K /* Sample Freq: 245.76MHz */
|
||||
#define JESD_NRFDD_SLOT_SAM_CNT 122880
|
||||
#else /* Sample Freq: 122.88MHz */
|
||||
#define JESD_NRFDD_SLOT_SAM_CNT 61440
|
||||
#endif
|
||||
|
||||
#define JESD_NRFDD_TX_LIST_ADDR 0x8A000000 // 0x0a4f4000//
|
||||
#define JESD_NRFDD_RX_LIST_ADDR 0x8A008000 // 0x0a4f4800//
|
||||
|
||||
@ -66,27 +66,27 @@ int32_t jesd_csu_init_lte_fdd_slot0()
|
||||
if (0 == (i&0x1))
|
||||
{
|
||||
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR;
|
||||
txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
|
||||
txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
txCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
txCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
|
||||
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR;
|
||||
rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
|
||||
rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
rxCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
rxCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
}
|
||||
else if (1 == (i&0x1))
|
||||
{
|
||||
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR;
|
||||
txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
|
||||
txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
txCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
txCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
|
||||
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR;
|
||||
rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
|
||||
rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
rxCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
rxCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
|
||||
}
|
||||
}
|
||||
|
||||
jesd_csu_tx_cfg(txListAddr, 1, txCsuNode, JESD_CSU_CH0, 0);
|
||||
jesd_csu_rx_cfg(rxListAddr, 1, rxCsuNode, JESD_CSU_CH0, 0);
|
||||
jesd_csu_tx_cfg(txListAddr, 10, txCsuNode, JESD_CSU_CH0, 0);
|
||||
jesd_csu_rx_cfg(rxListAddr, 10, rxCsuNode, JESD_CSU_CH0, 0);
|
||||
#if 0
|
||||
jesd_csu_tx_list_init(txListAddr, JESD_LTEFDD_TX_NODENUM, txCsuNode);
|
||||
jesd_csu_tx_dmaReg_Cfg(JESD_CSU_CH0, txListAddr, JESD_LTEFDD_TX_NODENUM);
|
||||
@ -97,12 +97,46 @@ int32_t jesd_csu_init_lte_fdd_slot0()
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
int32_t jesd_csu_start_lte()
|
||||
int32_t jesd_csu_init_15K_fdd_1ant()
|
||||
{
|
||||
jesd_csu_start();
|
||||
jesd_csu_init(4, JESD_LTEFDD_MARGIN, FDD_MODE);
|
||||
stJesdCsuNodePara txCsuNode[JESD_LTEFDD_TX_NODENUM];
|
||||
stJesdCsuNodePara rxCsuNode[JESD_LTEFDD_RX_NODENUM];
|
||||
//tx的链表地址
|
||||
uint32_t txListAddr = JESD_LTEFDD_TX_LIST_ADDR; // 0x8A000000
|
||||
//rx的链表地址
|
||||
uint32_t rxListAddr = JESD_LTEFDD_RX_LIST_ADDR; // 0x8A008000
|
||||
int32_t i = 0;
|
||||
|
||||
// tx/rx, subframe 0~9
|
||||
for (i = 0; i < JESD_LTEFDD_TX_NODENUM; i++)
|
||||
{
|
||||
if (0 == (i&0x1))
|
||||
{
|
||||
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR;
|
||||
txCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
txCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*4;
|
||||
|
||||
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR;
|
||||
rxCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
rxCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*4;
|
||||
}
|
||||
else if (1 == (i&0x1))
|
||||
{
|
||||
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR;
|
||||
txCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
txCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*4;
|
||||
|
||||
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR;
|
||||
rxCsuNode[i].yStep = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2);
|
||||
rxCsuNode[i].allNum = (JESD_15K_FDD_SUBFRAME_SAM_CNT<<2)*4;
|
||||
}
|
||||
}
|
||||
|
||||
jesd_csu_tx_cfg(txListAddr, JESD_LTEFDD_TX_NODENUM, txCsuNode, JESD_CSU_CH0, 0);
|
||||
jesd_csu_rx_cfg(rxListAddr, JESD_LTEFDD_RX_NODENUM, rxCsuNode, JESD_CSU_CH0, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@ -483,7 +483,7 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
|
||||
#endif
|
||||
|
||||
//set_jesd_tx_slot_offset(nTmrId);
|
||||
set_jesd_tx_slot_offset(nTmrId);
|
||||
//set_jesd_rx_slot_offset(nTmrId);
|
||||
#ifdef PALLADIUM_TEST
|
||||
flag++;
|
||||
@ -551,7 +551,7 @@ int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
|
||||
|
||||
jesd_csu_clear_list();
|
||||
}
|
||||
clear_jesd_tx_slot_offset(nTmrId);
|
||||
//clear_jesd_tx_slot_offset(nTmrId);
|
||||
//clear_jesd_rx_slot_offset(nTmrId);
|
||||
|
||||
pMtimerSfn->cellSetup = 0;
|
||||
@ -569,6 +569,7 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
|
||||
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
|
||||
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
|
||||
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
|
||||
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
|
||||
int32_t nScsId = pMtimerPara->scsId;
|
||||
uint16_t runCore = pMtimerPara->runCoreId;
|
||||
uint32_t addr = (uint32_t)&(phyPara[nScsId].runCoreId);
|
||||
@ -586,12 +587,20 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
|
||||
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;
|
||||
|
||||
//if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
|
||||
if (0 != reCfgFlag) // no frame header offset, and the first cell
|
||||
//if (0 != reCfgFlag) // no frame header offset, and the first cell
|
||||
if (runCore == cellCore) // no frame header offset, and the first cell
|
||||
{
|
||||
pMtimerSfn->txSfnNum++;
|
||||
pMtimerSfn->txSfnNum &= 0x3FF;
|
||||
//pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
|
||||
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
|
||||
//pMtimerSfn->txSfnNum++;
|
||||
//pMtimerSfn->txSfnNum &= 0x3FF;
|
||||
if (pMtimerInt->sfnIntCnt & 0x1) // odd val
|
||||
{
|
||||
pMtimerSfn->txSfnNum = ((pMtimerSfn->txSfnNum>>1)<<1);
|
||||
}
|
||||
else // even val
|
||||
{
|
||||
pMtimerSfn->txSfnNum = ((pMtimerSfn->txSfnNum>>1)<<1)+1;
|
||||
}
|
||||
pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
|
||||
}
|
||||
addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
|
||||
do_write(addr, pMtimerSfn->txSfnNum);
|
||||
@ -628,7 +637,7 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
|
||||
}
|
||||
|
||||
reCfgFlag = 0; // 5;
|
||||
disable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // disable 10ms int
|
||||
//disable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // disable 10ms int
|
||||
pMtimerSfn->cellSetup = 1;
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum); // 0xE50
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT()); // 0xE54
|
||||
@ -647,18 +656,17 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
|
||||
{
|
||||
do_write((tmrBaseAddr+MTMR_PIN_CTRL_REG), 0x3); //CTRL_SEL
|
||||
do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), 0); //IO ctrl
|
||||
#if 0
|
||||
#if 1
|
||||
if (FDD_MODE == gJesdTFMode)
|
||||
{
|
||||
set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
|
||||
set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
|
||||
set_jesd_rf_state(JESD_ANT_TX, GPIO_ON); // TxOn();
|
||||
//set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF); // RxOn();
|
||||
//set_jesd_rf_state(JESD_RF_RX, GPIO_OFF); // RxOn();
|
||||
//set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF); // RxOn();
|
||||
set_jesd_rf_state(JESD_ANT_RX, GPIO_ON); // RxOn();
|
||||
set_jesd_rf_state(JESD_RF_RX, GPIO_ON); // RxOn();
|
||||
set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn();
|
||||
set_jesd_all_rf_state(0, GPIO_ON);
|
||||
//set_jesd_all_rf_state(1, GPIO_ON);
|
||||
//set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
|
||||
//set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
|
||||
//set_jesd_rf_state(JESD_ANT_TX, GPIO_ON); // TxOn();
|
||||
//set_jesd_rf_state(JESD_ANT_RX, GPIO_ON); // RxOn();
|
||||
//set_jesd_rf_state(JESD_RF_RX, GPIO_ON); // RxOn();
|
||||
//set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -716,7 +724,7 @@ void set_jesd_tmr_period(int32_t nTmrId)
|
||||
|
||||
set_mtimer_period(nTmrId, tempL, tempM, tempH);
|
||||
|
||||
//enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
|
||||
enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
|
||||
}
|
||||
|
||||
void jesd_1pps_src_init(uint8_t srcId)
|
||||
@ -803,7 +811,7 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
|
||||
txOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;
|
||||
rxOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;
|
||||
|
||||
enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
|
||||
//enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
|
||||
|
||||
uint32_t tmr3Point = SFN_PERIOD*1000 - txOffset; // ns
|
||||
uint32_t tmr4Point = SFN_PERIOD*1000 - txOffset; // ns
|
||||
@ -1256,6 +1264,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
|
||||
do_write((tmrBaseAddr+MTMR_CEVENT_REG), BIT17);
|
||||
do_write(cFlagAddr, BIT17); // clear int flag
|
||||
//uint32_t start = GET_STC_CNT();
|
||||
pMtimerInt->sfnIntCnt = 0;
|
||||
if (0 == pMtimerInt->pp1sIntCnt)
|
||||
{
|
||||
start_jesd_timer(nTmrId);
|
||||
@ -1313,7 +1322,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
|
||||
uint32_t start = GET_STC_CNT();
|
||||
pMtimerInt->sfnOffsetIntFlag = 1;
|
||||
pMtimerInt->sfnOffsetIntCnt++;
|
||||
if (0 == reCfgFlag)
|
||||
//if (0 == reCfgFlag)
|
||||
{
|
||||
pMtimerSfn->txSfnNum++;
|
||||
pMtimerSfn->txSfnNum &= 0x3FF;
|
||||
@ -1321,10 +1330,10 @@ uint32_t start = GET_STC_CNT();
|
||||
}
|
||||
#ifdef PALLADIUM_TEST
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C
|
||||
if (6 > gPP1sFlag)
|
||||
//if (6 > gPP1sFlag)
|
||||
{
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (1<<30))); // 0xD0
|
||||
gPP1sFlag++;
|
||||
//debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (1<<30))); // 0xD0
|
||||
//gPP1sFlag++;
|
||||
}
|
||||
#endif
|
||||
if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == (pMtimerInt->sfnOffsetIntCnt&0x3)))
|
||||
|
||||
@ -29,8 +29,13 @@
|
||||
typedef struct tSpuLogServerInfo {
|
||||
uint16_t isrFlag;
|
||||
uint16_t pingpong;
|
||||
uint16_t idx[MAX_INSTANCE_NUM][SPU_LOG_SERVER_RING_SIZE];
|
||||
uint32_t serverBufBase[MAX_INSTANCE_NUM][SPU_LOG_SERVER_RING_SIZE];
|
||||
#ifdef PCIE_WITH_JESD
|
||||
uint16_t idx[MAX_INSTANCE_NUM/2][SPU_LOG_SERVER_RING_SIZE];
|
||||
uint32_t serverBufBase[MAX_INSTANCE_NUM/2][SPU_LOG_SERVER_RING_SIZE];
|
||||
#else
|
||||
uint16_t idx[MAX_INSTANCE_NUM][SPU_LOG_SERVER_RING_SIZE];
|
||||
uint32_t serverBufBase[MAX_INSTANCE_NUM][SPU_LOG_SERVER_RING_SIZE];
|
||||
#endif
|
||||
uint32_t serverBufSize;
|
||||
uint32_t clientBufSize;
|
||||
uint32_t clientBufBase[MAX_NUM_SPU];
|
||||
|
||||
@ -42,8 +42,14 @@ void spu_log_server_init(void)
|
||||
}
|
||||
|
||||
uint32_t i,j;
|
||||
for (i=0; i<MAX_INSTANCE_NUM; i++) {
|
||||
for (j=0; j<SPU_LOG_SERVER_RING_SIZE; j++) {
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = 0; i< (MAX_INSTANCE_NUM / 2); i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
for (j=0; j<SPU_LOG_SERVER_RING_SIZE; j++)
|
||||
{
|
||||
pLogServerInfo->idx[i][j] = 0;
|
||||
pLogServerInfo->serverBufBase[i][j] = SPU_LOG_SERVER_BUF_BASE + (j*SPU_LOG_SERVER_BUF_SIZE*SPU_LOG_SERVER_BUF_DEPTH) + \
|
||||
(i*SPU_LOG_SERVER_RING_SIZE*SPU_LOG_SERVER_BUF_SIZE*SPU_LOG_SERVER_BUF_DEPTH);
|
||||
@ -144,7 +150,11 @@ static inline void spu_log_server_send(void)
|
||||
uint16_t pingpong = pLogServerInfo->pingpong;
|
||||
|
||||
uint32_t src_addr,size;
|
||||
for (uint32_t cell_id=0; cell_id<MAX_INSTANCE_NUM; cell_id++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (uint32_t cell_id = 0; cell_id < (MAX_INSTANCE_NUM / 2); cell_id++)
|
||||
#else
|
||||
for (uint32_t cell_id = 0; cell_id < MAX_INSTANCE_NUM; cell_id++)
|
||||
#endif
|
||||
{
|
||||
src_addr = pLogServerInfo->serverBufBase[cell_id][pingpong];
|
||||
size = pLogServerInfo->idx[cell_id][pingpong] * pLogServerInfo->serverBufSize;
|
||||
@ -152,7 +162,11 @@ static inline void spu_log_server_send(void)
|
||||
}
|
||||
|
||||
pLogServerInfo->pingpong = 1 - pLogServerInfo->pingpong;
|
||||
for (uint32_t cell_id=0; cell_id<MAX_INSTANCE_NUM; cell_id++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (uint32_t cell_id = 0; cell_id < (MAX_INSTANCE_NUM / 2); cell_id++)
|
||||
#else
|
||||
for (uint32_t cell_id = 0; cell_id < MAX_INSTANCE_NUM; cell_id++)
|
||||
#endif
|
||||
{
|
||||
pLogServerInfo->idx[cell_id][pLogServerInfo->pingpong] = 0;
|
||||
}
|
||||
|
||||
@ -55,17 +55,17 @@ void ecs_rfm_spu1_msg_transfer_init(void)
|
||||
{
|
||||
msg_transfer_mem_alloc();
|
||||
|
||||
int32_t core_id = get_host_core_id();
|
||||
handshake_request_from_host(core_id);
|
||||
//handshake_with_host();
|
||||
uint32_t host_core_mask = get_host_core_mask();
|
||||
handshake_request_from_host(host_core_mask);
|
||||
|
||||
msg_transfer_queue_init();//initialized local queuecfg from common queuecfg
|
||||
|
||||
uint32_t u32_core_mask = get_core_mask_by_phy();
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 3), u32_core_mask);
|
||||
handshake_master_with_slave(u32_core_mask);
|
||||
uint32_t slave_core_mask = get_core_mask_by_phy();
|
||||
uint32_t core_id = get_core_id();
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 3), slave_core_mask);
|
||||
handshake_master_with_slave(slave_core_mask);
|
||||
|
||||
handshake_response_to_host(core_id);
|
||||
handshake_response_to_host(host_core_mask);
|
||||
|
||||
phy_init();//phy application function:msg_transfer_cfg
|
||||
|
||||
|
||||
@ -55,8 +55,9 @@ int32_t phy_fh_drv_init()
|
||||
fhDrvPara.rateOption = JESD_OPTION_204C;
|
||||
#endif
|
||||
|
||||
#ifndef DISTRIBUTED_BS
|
||||
fronthaul_drv_cfg(&fhDrvPara);
|
||||
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -131,7 +132,7 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId, uint3
|
||||
phy_timer_config_ind_t my_cpritmr;
|
||||
|
||||
my_cpritmr.scsId = scsId;
|
||||
if ((0 <= cellId) || ((3 >= cellId)))
|
||||
if ((0 == cellId) || ((1 == cellId)))
|
||||
{
|
||||
my_cpritmr.runCoreId = coreId;
|
||||
}
|
||||
@ -186,7 +187,7 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId, uint3
|
||||
my_cpritmr.num_t_dl[0] =10;// 7; // dl slot num
|
||||
my_cpritmr.num_t_dl_symb[0] = 14;//6; // dl symbol num
|
||||
my_cpritmr.num_t_ul_symb[0] = 14;//4; // ul symbol num
|
||||
my_cpritmr.num_ants[0] = 2;
|
||||
my_cpritmr.num_ants[0] = 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -228,7 +229,7 @@ void ecs_rfm1_delete_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
|
||||
|
||||
stPhyDelCell myDelCell;
|
||||
myDelCell.scsId = scsId;
|
||||
if ((0 <= cellId) || (3 >= cellId))
|
||||
if ((0 == cellId) || (1 == cellId))
|
||||
{
|
||||
myDelCell.delCoreId = coreId;
|
||||
}
|
||||
|
||||
@ -22,6 +22,10 @@ DEFINES += SPU_BUILD_DATE=\"${spu_build_date}\"
|
||||
|
||||
ifeq ($(backhaul_option), pcie)
|
||||
DEFINES += PCIE_BACKHAUL
|
||||
|
||||
ifeq ($(fronthaul_option), jesd)
|
||||
DEFINES += PCIE_WITH_JESD
|
||||
endif
|
||||
endif
|
||||
|
||||
CC_FLAGS += $(foreach d,$(DEFINES),-D$(d))
|
||||
|
||||
@ -7,7 +7,8 @@
|
||||
# ==============================================================================
|
||||
|
||||
#MaPU_TC_HOME ?= /public/lixinxin/MaPUIDE/toolchain
|
||||
MaPU_TC_HOME := /public/share/tools/msdk/toolchain
|
||||
MaPU_TC_HOME := /home/ittc/Software/mcstudio/toolchain
|
||||
|
||||
$(info "MaPU_TC_HOME=" $(MaPU_TC_HOME))
|
||||
UCP_CC := $(MaPU_TC_HOME)/bin/ucp2
|
||||
UCP_INC := $(MaPU_TC_HOME)/include/ucp2
|
||||
|
||||
@ -95,15 +95,27 @@ typedef struct tPcieLinkStatus {
|
||||
|
||||
//RC和EP通信的counter结构体
|
||||
typedef struct tPcieTrafficCounter {
|
||||
uint32_t dlDescNum[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//通道描述符的个数，固定为128
|
||||
uint32_t dlTxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//由RC侧来填充，RC侧写下来的数据包的个数
|
||||
uint32_t dlRxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//EP侧接收到的数据包的个数
|
||||
//int8_t dlDescIdx[MAX_Q_NUM_DL_TRAFFIC][MAX_DESC_NUM];//该通道的DMA描述符的索引计数，最大128
|
||||
#ifdef PCIE_WITH_JESD
|
||||
uint32_t dlDescNum[MAX_INSTANCE_NUM/2][MAX_Q_NUM_DL_TRAFFIC];//通道描述符的个数，固定为128
|
||||
uint32_t dlTxCounter[MAX_INSTANCE_NUM/2][MAX_Q_NUM_DL_TRAFFIC];//由RC侧来填充，RC侧写下来的数据包的个数
|
||||
uint32_t dlRxCounter[MAX_INSTANCE_NUM/2][MAX_Q_NUM_DL_TRAFFIC];//EP侧接收到的数据包的个数
|
||||
//int8_t dlDescIdx[MAX_Q_NUM_DL_TRAFFIC][MAX_DESC_NUM];//该通道的DMA描述符的索引计数，最大128
|
||||
|
||||
uint32_t ulDescNum[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC];//通道描述符的个数，固定为12s8
|
||||
uint32_t ulTxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC];//EP侧发送出去的数据包个数
|
||||
uint32_t ulRxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC];//RC填充，RC接收到的数据包的个数
|
||||
//int8_t ulDescIdx[MAX_Q_NUM_UL_TRAFFIC][MAX_DESC_NUM];//该通道的DMA描述符的索引计数，最大128
|
||||
uint32_t ulDescNum[MAX_INSTANCE_NUM/2][MAX_Q_NUM_UL_TRAFFIC];//通道描述符的个数，固定为12s8
|
||||
uint32_t ulTxCounter[MAX_INSTANCE_NUM/2][MAX_Q_NUM_UL_TRAFFIC];//EP侧发送出去的数据包个数
|
||||
uint32_t ulRxCounter[MAX_INSTANCE_NUM/2][MAX_Q_NUM_UL_TRAFFIC];//RC填充，RC接收到的数据包的个数
|
||||
//int8_t ulDescIdx[MAX_Q_NUM_UL_TRAFFIC][MAX_DESC_NUM];//该通道的DMA描述符的索引计数，最大128
|
||||
#else
|
||||
uint32_t dlDescNum[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//通道描述符的个数，固定为128
|
||||
uint32_t dlTxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//由RC侧来填充，RC侧写下来的数据包的个数
|
||||
uint32_t dlRxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//EP侧接收到的数据包的个数
|
||||
//int8_t dlDescIdx[MAX_Q_NUM_DL_TRAFFIC][MAX_DESC_NUM];//该通道的DMA描述符的索引计数，最大128
|
||||
|
||||
uint32_t ulDescNum[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC];//通道描述符的个数，固定为12s8
|
||||
uint32_t ulTxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC];//EP侧发送出去的数据包个数
|
||||
uint32_t ulRxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC];//RC填充，RC接收到的数据包的个数
|
||||
//int8_t ulDescIdx[MAX_Q_NUM_UL_TRAFFIC][MAX_DESC_NUM];//该通道的DMA描述符的索引计数，最大128
|
||||
#endif
|
||||
} PcieTrafficCounter_t;
|
||||
|
||||
/*
|
||||
@ -123,8 +135,13 @@ typedef struct tPcieTraffiDescriptor {
|
||||
|
||||
//一共对传输描述符，用于9种业务，由收发task进行处理
|
||||
typedef struct tUcpTaskDescriptor{
|
||||
PcieTrafficDescriptor_t dl[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC][MAX_DESC_NUM];
|
||||
PcieTrafficDescriptor_t ul[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC][MAX_DESC_NUM];
|
||||
#ifdef PCIE_WITH_JESD
|
||||
PcieTrafficDescriptor_t dl[MAX_INSTANCE_NUM/2][MAX_Q_NUM_DL_TRAFFIC][MAX_DESC_NUM];
|
||||
PcieTrafficDescriptor_t ul[MAX_INSTANCE_NUM/2][MAX_Q_NUM_UL_TRAFFIC][MAX_DESC_NUM];
|
||||
#else
|
||||
PcieTrafficDescriptor_t dl[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC][MAX_DESC_NUM];
|
||||
PcieTrafficDescriptor_t ul[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC][MAX_DESC_NUM];
|
||||
#endif
|
||||
} UcpTaskDescriptor_t;
|
||||
|
||||
//pcie command enum
|
||||
@ -153,7 +170,11 @@ typedef enum pcieCommandType{
|
||||
typedef struct tPcieEpMemBarStruct {
|
||||
PcieLinkStatus_t status;//PCIE链路状态 地址 0x08740000 // 8字节
|
||||
SyncInfo_t trafficSyncInfo; // 0x08740000+8 //
|
||||
transfer_type_info_s traffic[MAX_INSTANCE_NUM][TRANSFER_TYPE_NUM];//业务配置下来的按照业务配置信息 0x08740000+ 0x18 //（8+16)字节
|
||||
#ifdef PCIE_WITH_JESD
|
||||
transfer_type_info_s traffic[MAX_INSTANCE_NUM/2][TRANSFER_TYPE_NUM];//业务配置下来的按照业务配置信息 0x08740000+ 0x18 //（8+16)字节
|
||||
#else
|
||||
transfer_type_info_s traffic[MAX_INSTANCE_NUM][TRANSFER_TYPE_NUM];//业务配置下来的按照业务配置信息 0x08740000+ 0x18 //（8+16)字节
|
||||
#endif
|
||||
PcieTrafficCounter_t cnt; //每个通道本次收发数据包状态结构体 //0x08740000+ 0x1F8 //(8+16+480)字节
|
||||
UcpTaskDescriptor_t desc;//RC和EP之间DMA任务收发数据的描述符，// 6*128*2= 1536字节// 0x08740000+ 0x288 (8+16+480+144)= 648
|
||||
uint32_t command[14];//RC和EP通信的command的命令, // 0x08740000+ 0x888 88A=(8+16+480+144+1536)= 2184
|
||||
@ -172,8 +193,13 @@ typedef struct tUcpPcieEpMemInfo {
|
||||
PcieDmaBuffer_t* pRdmaChains[MAX_CH_NUM_UCP_DMA];//读通道buffer，用于DMA传输的LL链表
|
||||
PcieDmaBuffer_t* pWdmaChains[MAX_CH_NUM_UCP_DMA];//写通道buffer，通道所服务的业务id
|
||||
|
||||
#ifdef PCIE_WITH_JESD
|
||||
UcpExtTraffic_t* pExtDlTraffic[MAX_INSTANCE_NUM/2][UCP4008_TRAFFIC_MAX_NUM];//[MAX_Q_NUM_DL_TRAFFIC]; //下行应用业务通信结构体
|
||||
UcpExtTraffic_t* pExtUlTraffic[MAX_INSTANCE_NUM/2][UCP4008_TRAFFIC_MAX_NUM];//[MAX_Q_NUM_UL_TRAFFIC]; //上行应用业务通信结构体
|
||||
#else
|
||||
UcpExtTraffic_t* pExtDlTraffic[MAX_INSTANCE_NUM][UCP4008_TRAFFIC_MAX_NUM];//[MAX_Q_NUM_DL_TRAFFIC]; //下行应用业务通信结构体
|
||||
UcpExtTraffic_t* pExtUlTraffic[MAX_INSTANCE_NUM][UCP4008_TRAFFIC_MAX_NUM];//[MAX_Q_NUM_UL_TRAFFIC]; //上行应用业务通信结构体
|
||||
#endif
|
||||
} UcpPcieEpMemInfo_t;
|
||||
|
||||
UcpPcieEpMemInfo_t* get_ucp_pcie_mem_info(void);
|
||||
|
||||
@ -83,8 +83,13 @@ void pcie_ep_mem_init(void)
|
||||
///pUcpPcieMemInfo->pWdmaChains[k]->used = 0;
|
||||
}
|
||||
//跟RC通信的线程， 读
|
||||
ptr = (uint8_t *)memSectionAlloc(pMemSection, MAX_INSTANCE_NUM*MAX_Q_NUM_DL_TRAFFIC*sizeof_aligned_4bytes(UcpExtTraffic_t), MEM_ALIGNED_4BYTES, "pExtDlTraffic");
|
||||
for(k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
ptr = (uint8_t *)memSectionAlloc(pMemSection, (MAX_INSTANCE_NUM / 2) * MAX_Q_NUM_DL_TRAFFIC * sizeof_aligned_4bytes(UcpExtTraffic_t), MEM_ALIGNED_4BYTES, "pExtDlTraffic");
|
||||
for (k = 0; k < (MAX_INSTANCE_NUM / 2); k++)
|
||||
#else
|
||||
ptr = (uint8_t *)memSectionAlloc(pMemSection, MAX_INSTANCE_NUM * MAX_Q_NUM_DL_TRAFFIC * sizeof_aligned_4bytes(UcpExtTraffic_t), MEM_ALIGNED_4BYTES, "pExtDlTraffic");
|
||||
for (k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < MAX_Q_NUM_DL_TRAFFIC; i++)
|
||||
{
|
||||
@ -93,8 +98,13 @@ void pcie_ep_mem_init(void)
|
||||
}
|
||||
}
|
||||
//跟应用通信的描述符，写
|
||||
ptr = (uint8_t *)memSectionAlloc(pMemSection, MAX_INSTANCE_NUM*MAX_Q_NUM_UL_TRAFFIC*sizeof_aligned_4bytes(UcpExtTraffic_t), MEM_ALIGNED_4BYTES, "pExtUlTraffic");
|
||||
for(k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
ptr = (uint8_t *)memSectionAlloc(pMemSection, (MAX_INSTANCE_NUM / 2) * MAX_Q_NUM_UL_TRAFFIC * sizeof_aligned_4bytes(UcpExtTraffic_t), MEM_ALIGNED_4BYTES, "pExtUlTraffic");
|
||||
for (k = 0; k < (MAX_INSTANCE_NUM / 2); k++)
|
||||
#else
|
||||
ptr = (uint8_t *)memSectionAlloc(pMemSection, MAX_INSTANCE_NUM * MAX_Q_NUM_UL_TRAFFIC * sizeof_aligned_4bytes(UcpExtTraffic_t), MEM_ALIGNED_4BYTES, "pExtUlTraffic");
|
||||
for (k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < MAX_Q_NUM_UL_TRAFFIC; i++)
|
||||
{
|
||||
|
||||
@ -26,7 +26,11 @@ static inline void ucp_variables_init()
|
||||
uint32_t i = 0;
|
||||
UcpPcieEpMemInfo_t* pUcpPcieMemInfo = get_ucp_pcie_mem_info();
|
||||
//UcpQueueMemInfo_t* pUcpQueueMemInfo = get_ucp_queue_mem_info();
|
||||
for(k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (k = 0; k < (MAX_INSTANCE_NUM / 2); k++)
|
||||
#else
|
||||
for (k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < UCP4008_TRAFFIC_MAX_NUM; i++) {
|
||||
memset(pUcpPcieMemInfo->pExtDlTraffic[k][i], 0, sizeof(UcpExtTraffic_t));
|
||||
@ -62,7 +66,11 @@ static inline void ucp_counter_setup(void)
|
||||
UcpPcieEpMemInfo_t* pUcpPcieMemInfo = get_ucp_pcie_mem_info();
|
||||
PcieTrafficCounter_t* pCounter = (PcieTrafficCounter_t *)&pUcpPcieMemInfo->pUcpMemBar->cnt;
|
||||
//pUcpPcieMemInfo->pUcpMemBar->traffic[][].queue_cplane_info.
|
||||
for(k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (k = 0; k < (MAX_INSTANCE_NUM / 2); k++)
|
||||
#else
|
||||
for (k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < UCP4008_TRAFFIC_MAX_NUM; i++) {
|
||||
//configure dl counter
|
||||
@ -135,7 +143,11 @@ static inline void ucp_variables_setup(void)
|
||||
UcpPcieEpMemInfo_t* pUcpPcieMemInfo = get_ucp_pcie_mem_info();
|
||||
UcpExtTraffic_t* pExtTraffic = NULL;
|
||||
uint32_t desc_mask = 0; //pUcpPcieMemInfo->pUcpMemBar->cnt.dlDescNum[][];
|
||||
for(k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (k = 0; k < (MAX_INSTANCE_NUM / 2); k++)
|
||||
#else
|
||||
for (k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < UCP4008_TRAFFIC_MAX_NUM; i++) {
|
||||
desc_mask = pUcpPcieMemInfo->pUcpMemBar->cnt.dlDescNum[k][i] - 1;
|
||||
@ -156,7 +168,11 @@ static inline void ucp_variables_setup(void)
|
||||
}
|
||||
}
|
||||
|
||||
for(k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (k = 0; k < (MAX_INSTANCE_NUM / 2); k++)
|
||||
#else
|
||||
for (k = 0; k < MAX_INSTANCE_NUM; k++)
|
||||
#endif
|
||||
{
|
||||
for (i = 0; i < UCP4008_TRAFFIC_MAX_NUM; i++) {
|
||||
desc_mask = pUcpPcieMemInfo->pUcpMemBar->cnt.ulDescNum[k][i] - 1;
|
||||
|
||||
@ -156,7 +156,12 @@ static inline int32_t ucp_pcie_dl_worker(uint32_t inst_id)
|
||||
//int ret = 0;
|
||||
uint32_t q_idx = 0;
|
||||
uint32_t k = 0;
|
||||
|
||||
#ifdef PCIE_WITH_JESD
|
||||
uint32_t dl_finished[MAX_INSTANCE_NUM/2][MAX_Q_NUM_DL_TRAFFIC] = {0};//局部变量用来记录，是哪个业务queue已经完成了传输
|
||||
#else
|
||||
uint32_t dl_finished[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC] = {0};//局部变量用来记录，是哪个业务queue已经完成了传输
|
||||
#endif
|
||||
memset(dl_finished, 0, sizeof(dl_finished));
|
||||
int32_t dma_idx = 0;//DMA服务的上行队列的队列号
|
||||
uint32_t dma_trc_inst_id = 0;//用于记录DMA服务的小区号
|
||||
@ -184,7 +189,11 @@ static inline int32_t ucp_pcie_dl_worker(uint32_t inst_id)
|
||||
UcpPcieDmaComplete_t* pCmplt = NULL;
|
||||
uint32_t num_rx_queues = MAX_Q_NUM_DL_TRAFFIC;//跟业务queue对应，共6个queue
|
||||
//按照传输队列判断，是否有队列已经传输完成，传输队列一共有6个
|
||||
for(i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = 0; i < (MAX_INSTANCE_NUM / 2); i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
for (k = 0; k < num_rx_queues; k++) {
|
||||
|
||||
@ -215,7 +224,11 @@ static inline int32_t ucp_pcie_dl_worker(uint32_t inst_id)
|
||||
if (extInc > 0) {
|
||||
pCnt->dlRxCounter[i][k] += extInc;//写入bar空间该通道接收到的数据包个数
|
||||
//ucp_queue_dl_put_done(k, intInc);//队列中保存接收数据包计数
|
||||
msg_queue_dl_put_done(i, k, intInc);
|
||||
#ifdef PCIE_WITH_JESD
|
||||
msg_queue_dl_put_done((MAX_INSTANCE_NUM / 2) + i, k, intInc);
|
||||
#else
|
||||
msg_queue_dl_put_done(i, k, intInc);
|
||||
#endif
|
||||
/*UCP_PRINT_LOG("DL After PutComplete int_dl_ch[%d][%d]: in = %d out = %d alloc = %d free = %d intInc = %d\n",
|
||||
i, k, pMsgQueueLocalMgt->localDlQueue[i][k].in, pMsgQueueLocalMgt->localDlQueue[i][k].out,
|
||||
pMsgQueueLocalMgt->localDlQueue[i][k].alloc, pMsgQueueLocalMgt->localDlQueue[i][k].free, intInc);*/
|
||||
@ -298,7 +311,11 @@ static inline int32_t ucp_pcie_dl_worker(uint32_t inst_id)
|
||||
#endif
|
||||
for (n = 0; n < N; n++)
|
||||
{
|
||||
ext_ch->buf = (uint32_t *)msg_queue_dl_put_buf(inst_id, k);//ucp_queue_dl_put_buf(k);
|
||||
#ifdef PCIE_WITH_JESD
|
||||
ext_ch->buf = (uint32_t *)msg_queue_dl_put_buf((MAX_INSTANCE_NUM / 2) + inst_id, k);//ucp_queue_dl_put_buf(k);
|
||||
#else
|
||||
ext_ch->buf = (uint32_t *)msg_queue_dl_put_buf(inst_id, k);//ucp_queue_dl_put_buf(k);
|
||||
#endif
|
||||
if (NULL != ext_ch->buf)
|
||||
{
|
||||
ext_ch->offset = 0;
|
||||
@ -393,7 +410,11 @@ static inline int32_t ucp_pcie_ul_worker(uint32_t inst_id)
|
||||
uint32_t q_idx = 0;
|
||||
uint32_t dma_trc_inst_id = 0;
|
||||
uint32_t k = 0;
|
||||
#ifdef PCIE_WITH_JESD
|
||||
uint32_t ul_finished[MAX_INSTANCE_NUM/2][MAX_Q_NUM_UL_TRAFFIC] = {0};
|
||||
#else
|
||||
uint32_t ul_finished[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC] = {0};
|
||||
#endif
|
||||
memset(ul_finished, 0, sizeof(ul_finished));
|
||||
int32_t dma_idx = 0;
|
||||
int32_t ret = 0;
|
||||
@ -421,7 +442,11 @@ static inline int32_t ucp_pcie_ul_worker(uint32_t inst_id)
|
||||
UcpPcieDmaComplete_t* pCmplt = NULL;
|
||||
uint32_t num_tx_queues = MAX_Q_NUM_UL_TRAFFIC;
|
||||
uint32_t i = 0;
|
||||
for(i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = 0; i < (MAX_INSTANCE_NUM / 2); i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
//如果有发送通道完成了DMA传输，则需要处理对应的数据包
|
||||
for (k = 0; k < num_tx_queues; k++)
|
||||
@ -429,7 +454,11 @@ static inline int32_t ucp_pcie_ul_worker(uint32_t inst_id)
|
||||
//首先检查该通道上的数据包是否被RC已经取走
|
||||
//ucp_queue_ul_check_free(k, pCnt->ulRxCounter[k]);
|
||||
//ucp_queue_ul_get_done(k, pCnt->ulRxCounter[k] - pMsgQueueLocalMgt->localUlQueue[k].free);
|
||||
msg_queue_ul_get_done(i, k, (pCnt->ulRxCounter[i][k] - pMsgQueueLocalMgt->localUlQueue[i][k].free));
|
||||
#ifdef PCIE_WITH_JESD
|
||||
msg_queue_ul_get_done((MAX_INSTANCE_NUM / 2) + i, k, (pCnt->ulRxCounter[i][k] - pMsgQueueLocalMgt->localUlQueue[(MAX_INSTANCE_NUM / 2) + i][k].free));
|
||||
#else
|
||||
msg_queue_ul_get_done(i, k, (pCnt->ulRxCounter[i][k] - pMsgQueueLocalMgt->localUlQueue[i][k].free));
|
||||
#endif
|
||||
//检查该通道的DMA传输是否完成
|
||||
if (0 == ul_finished[i][k])
|
||||
{
|
||||
@ -462,8 +491,8 @@ static inline int32_t ucp_pcie_ul_worker(uint32_t inst_id)
|
||||
pCnt->ulTxCounter[i][k] += extInc;//通知RC，数据包已经传输完成
|
||||
//ucp_queue_ul_get_done(k, intInc);//此处不应该立即去释放数据包，需要等对端取走后再去释放
|
||||
PCIE_DEBUG_LOG("UL After PutComplete int_ul_ch[%d][%d]: in = %d out = %d alloc = %d free = %d\n",
|
||||
i, k, pMsgQueueLocalMgt->localUlQueue[i][k].in, pMsgQueueLocalMgt->localUlQueue[i][k].out,
|
||||
pMsgQueueLocalMgt->localUlQueue[i][k].alloc, pMsgQueueLocalMgt->localUlQueue[i][k].free);
|
||||
i, k, pMsgQueueLocalMgt->localUlQueue[(MAX_INSTANCE_NUM / 2) + i][k].in, pMsgQueueLocalMgt->localUlQueue[(MAX_INSTANCE_NUM / 2) + i][k].out,
|
||||
pMsgQueueLocalMgt->localUlQueue[(MAX_INSTANCE_NUM / 2) + i][k].alloc, pMsgQueueLocalMgt->localUlQueue[(MAX_INSTANCE_NUM / 2) + i][k].free);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -489,9 +518,17 @@ static inline int32_t ucp_pcie_ul_worker(uint32_t inst_id)
|
||||
//检查是否有通道需要有数据发送，一共6个queue，逐个通道检查
|
||||
for (k = 0; k < num_tx_queues; k++, N = 0) {
|
||||
//ucp_queue_ul_update_in(k);
|
||||
msg_queue_ul_update_in(inst_id, k);
|
||||
#ifdef PCIE_WITH_JESD
|
||||
msg_queue_ul_update_in((MAX_INSTANCE_NUM / 2) + inst_id, k);
|
||||
#else
|
||||
msg_queue_ul_update_in(inst_id, k);
|
||||
#endif
|
||||
ext_ch = pUcpPcieMemInfo->pExtUlTraffic[inst_id][k];
|
||||
#ifdef PCIE_WITH_JESD
|
||||
int_ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localUlQueue[(MAX_INSTANCE_NUM / 2) + inst_id][k]; //从queue中获取需要传输的数据包的个数
|
||||
#else
|
||||
int_ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localUlQueue[inst_id][k]; //从queue中获取需要传输的数据包的个数
|
||||
#endif
|
||||
int_num = int_ch->in - int_ch->out;//本次要传输的数据包的个数
|
||||
if(0 == int_num)
|
||||
{
|
||||
@ -547,7 +584,11 @@ static inline int32_t ucp_pcie_ul_worker(uint32_t inst_id)
|
||||
}
|
||||
//将数据包的地址和size信息填充到DMA desc中
|
||||
for (n = 0; n < N; n++) {
|
||||
ext_ch->buf = (uint32_t *)msg_queue_ul_get_buf(inst_id, k);//ucp_queue_ul_get_buf(k); //每调用一次，自动加一，由queue保存当前的buffer地址
|
||||
#ifdef PCIE_WITH_JESD
|
||||
ext_ch->buf = (uint32_t *)msg_queue_ul_get_buf((MAX_INSTANCE_NUM / 2) + inst_id, k);//ucp_queue_ul_get_buf(k); //每调用一次，自动加一，由queue保存当前的buffer地址
|
||||
#else
|
||||
ext_ch->buf = (uint32_t *)msg_queue_ul_get_buf(inst_id, k);//ucp_queue_ul_get_buf(k); //每调用一次，自动加一，由queue保存当前的buffer地址
|
||||
#endif
|
||||
if (NULL != ext_ch->buf) {
|
||||
PCIE_DEBUG_LOG("UL After PreGet buf = 0x%x int_ul_ch[%d][%d].out = %d\n", (uint32_t)ext_ch->buf, inst_id, k, int_ch->out);
|
||||
} else {
|
||||
@ -640,24 +681,35 @@ void pcie_heart_beat(void)
|
||||
|
||||
void ucp_pcie_worker(void)
|
||||
{
|
||||
//ucp_pcie_reset();
|
||||
//ucp_pcie_reset();
|
||||
//pcie_heart_beat();
|
||||
for (uint32_t inst_id=0; inst_id<MAX_INSTANCE_NUM; inst_id++) {
|
||||
ucp_pcie_dl_worker(inst_id);
|
||||
ucp_pcie_ul_worker(inst_id);
|
||||
}
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (uint32_t inst_id = 0; inst_id < (MAX_INSTANCE_NUM / 2); inst_id++)
|
||||
#else
|
||||
for (uint32_t inst_id = 0; inst_id < MAX_INSTANCE_NUM; inst_id++)
|
||||
#endif
|
||||
{
|
||||
ucp_pcie_dl_worker(inst_id);
|
||||
ucp_pcie_ul_worker(inst_id);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void ucp_testSpeed_pcie_worker(void)
|
||||
{
|
||||
ucp_pcie_reset();
|
||||
for (uint32_t inst_id=0; inst_id<MAX_INSTANCE_NUM; inst_id++)
|
||||
{
|
||||
ucp_pcie_dl_worker(inst_id);
|
||||
ucp_pcie_ul_worker(inst_id);
|
||||
}
|
||||
return;
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (uint32_t inst_id = 0; inst_id < (MAX_INSTANCE_NUM / 2); inst_id++)
|
||||
#else
|
||||
for (uint32_t inst_id = 0; inst_id < MAX_INSTANCE_NUM; inst_id++)
|
||||
#endif
|
||||
{
|
||||
ucp_pcie_dl_worker(inst_id);
|
||||
ucp_pcie_ul_worker(inst_id);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -298,7 +298,12 @@ static inline int32_t msg_transfer_init(uint16_t port_index, uint16_t transfer_t
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
if (inst_id >= MAX_INSTANCE_NUM) {
|
||||
#ifdef PCIE_WITH_JESD
|
||||
if ((inst_id < (MAX_INSTANCE_NUM / 2)) || (inst_id >= MAX_INSTANCE_NUM))
|
||||
#else
|
||||
if (inst_id >= MAX_INSTANCE_NUM)
|
||||
#endif
|
||||
{
|
||||
PCIE_DEBUG_LOG("msg_transfer_init inst_id[%d] error.\n",inst_id);
|
||||
return FAILURE;
|
||||
}
|
||||
@ -441,19 +446,34 @@ void msg_transfer_cfg(void)
|
||||
|
||||
checkMsgTransferCfgFlag();
|
||||
|
||||
for (inst_id=0; inst_id<MAX_INSTANCE_NUM; inst_id++) {
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (inst_id = (MAX_INSTANCE_NUM / 2); inst_id < MAX_INSTANCE_NUM; inst_id++)
|
||||
#else
|
||||
for (inst_id = 0; inst_id < MAX_INSTANCE_NUM; inst_id++)
|
||||
#endif
|
||||
{
|
||||
/*********************************transfer_type = CU_SPLIT**********************************/
|
||||
transfer_type = CU_SPLIT;
|
||||
#ifdef PCIE_WITH_JESD
|
||||
get_msg_transfer_info(port_id,inst_id - (MAX_INSTANCE_NUM / 2),transfer_type, &transfer_type_info);
|
||||
handle_id = msg_transfer_init(port_id, transfer_type, inst_id, &transfer_type_info);
|
||||
#else
|
||||
get_msg_transfer_info(port_id,inst_id,transfer_type, &transfer_type_info);
|
||||
handle_id = msg_transfer_init(port_id, transfer_type, inst_id, &transfer_type_info);
|
||||
#endif
|
||||
if (handle_id < 0) {
|
||||
PCIE_ERROR_LOG("phy_cfg_init transfer_type:CU_SPLIT, handle_id[0x%08x] error.\n",handle_id);
|
||||
}
|
||||
|
||||
/*********************************transfer_type = OAM**********************************/
|
||||
transfer_type = OAM;
|
||||
#ifdef PCIE_WITH_JESD
|
||||
get_msg_transfer_info(port_id,inst_id - (MAX_INSTANCE_NUM / 2),transfer_type, &transfer_type_info);
|
||||
handle_id = msg_transfer_init(port_id, transfer_type, inst_id, &transfer_type_info);
|
||||
#else
|
||||
get_msg_transfer_info(port_id,inst_id,transfer_type, &transfer_type_info);
|
||||
handle_id = msg_transfer_init(port_id, transfer_type, inst_id, &transfer_type_info);
|
||||
#endif
|
||||
if (handle_id < 0) {
|
||||
PCIE_ERROR_LOG("phy_cfg_init transfer_type:OAM, handle_id[0x%08x] error.\n",handle_id);
|
||||
}
|
||||
|
||||
@ -21,6 +21,7 @@
|
||||
#include "testcase.h"
|
||||
#include "phy_para.h"
|
||||
#include "lib_debug_init.h"
|
||||
#include "ucp_heartbeat.h"
|
||||
|
||||
//#include "stc_timer.h"
|
||||
|
||||
@ -66,7 +67,7 @@ int32_t main(int32_t argc, char* argv[])
|
||||
/*********test code************/
|
||||
//test_case_recv_msg_pcie();
|
||||
/******************************/
|
||||
//heart_beat_write();
|
||||
heart_beat_write();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -71,14 +71,18 @@ uint32_t pcie_rx_callback_oam(const char* buf,uint32_t payloadSize)
|
||||
|
||||
void test_case_cfgpar_pcie()
|
||||
{
|
||||
int i = 0;
|
||||
int i = 0;
|
||||
|
||||
for(i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
{
|
||||
msg_transfer_callback_register(CU_SPLIT, i, C_PLANE, pcie_rx_callback_ctrl);
|
||||
msg_transfer_callback_register(CU_SPLIT, i, U_PLANE, pcie_rx_callback_data);
|
||||
msg_transfer_callback_register(OAM, i, C_PLANE, pcie_rx_callback_oam);
|
||||
}
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for(i = (MAX_INSTANCE_NUM / 2); i < MAX_INSTANCE_NUM; i++)
|
||||
#else
|
||||
for(i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
msg_transfer_callback_register(CU_SPLIT, i, C_PLANE, pcie_rx_callback_ctrl);
|
||||
msg_transfer_callback_register(CU_SPLIT, i, U_PLANE, pcie_rx_callback_data);
|
||||
msg_transfer_callback_register(OAM, i, C_PLANE, pcie_rx_callback_oam);
|
||||
}
|
||||
}
|
||||
|
||||
int8_t get_id(uint16_t type_id, uint16_t cu_flag)
|
||||
@ -130,7 +134,11 @@ void test_case_sendmsg_pcie()
|
||||
|
||||
|
||||
/****************************test code************************************************/
|
||||
for(i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = (MAX_INSTANCE_NUM / 2); i < MAX_INSTANCE_NUM; i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
handler.port_id = 0;
|
||||
handler.inst_id = i;
|
||||
@ -266,7 +274,12 @@ void test_case_recv_msg_pcie()
|
||||
uint32_t i = 0;
|
||||
|
||||
/****************************test code************************************************/
|
||||
for ( i = 0; i < MAX_INSTANCE_NUM; i++) {
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = (MAX_INSTANCE_NUM / 2); i < MAX_INSTANCE_NUM; i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
handler.port_id = port_id;
|
||||
handler.inst_id = i;
|
||||
handler.type_id = CU_SPLIT;
|
||||
|
||||
@ -94,10 +94,16 @@ void spu_oam_init(void)
|
||||
uint16_t cu_flag = C_PLANE;
|
||||
int32_t handle_id = 0;
|
||||
|
||||
for (inst_id=0; inst_id<MAX_INSTANCE_NUM; inst_id++) {
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (inst_id = 0; inst_id < (MAX_INSTANCE_NUM / 2); inst_id++)
|
||||
#else
|
||||
for (inst_id = 0; inst_id < MAX_INSTANCE_NUM; inst_id++)
|
||||
#endif
|
||||
{
|
||||
transfer_type = OAM;
|
||||
handle_id = msg_transfer_callback_register(transfer_type, inst_id,cu_flag, spu_rx_callback_oam);
|
||||
if (handle_id < 0) {
|
||||
if (handle_id < 0)
|
||||
{
|
||||
UCP_PRINT_ERROR("spu_oam_init transfer_type:OAM, handle_id[0x%08x] error.",handle_id);
|
||||
}
|
||||
}
|
||||
|
||||
@ -66,7 +66,12 @@ void msg_transfer_queue_polling(void)
|
||||
uint32_t len = 0;
|
||||
uint8_t* msg_ptr;
|
||||
|
||||
for (uint32_t i = 0; i < MAX_INSTANCE_NUM; i++) {
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (uint32_t i = 0; i < (MAX_INSTANCE_NUM / 2); i++)
|
||||
#else
|
||||
for (uint32_t i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
handler.port_id = port_id;
|
||||
handler.inst_id = i;
|
||||
handler.type_id = CU_SPLIT;
|
||||
|
||||
@ -283,216 +283,6 @@ uint32_t rx1_callback_ctrl(const char* buf,uint32_t payloadSize)
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
static uint32_t g_u32_rfm_2_alloc_err = 0; //(31) 0xB7E0147C
|
||||
static uint32_t g_u32_rfm_2_send_err = 0; //(32) 0xB7E01480
|
||||
static uint32_t g_u32_rfm_2_recv_num = 0; //(33) 0xB7E01484
|
||||
static uint32_t g_u32_rfm_2_send_ok = 0; //(34) 0xB7E01488
|
||||
|
||||
uint32_t rx2_callback_data(const char* buf,uint32_t payloadSize)
|
||||
{
|
||||
/* RFM0接收消息后发给APE0 */
|
||||
uint32_t core_id = get_core_id();
|
||||
int32_t ret = 0;
|
||||
char *addr = NULL;
|
||||
uint32_t u32_clock_tick = 0;
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+16), u32_clock_tick); //RFM receive tick
|
||||
g_u32_rfm_2_recv_num++;
|
||||
|
||||
addr = osp_alloc_msg(RFM_TEST_MSG_SIZE);
|
||||
if (NULL == addr)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 31), ++g_u32_rfm_2_alloc_err);
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
do_write(addr, (uint32_t)buf);
|
||||
do_write((addr+4), UCP4008_TRAFFIC_NR_eMBB_DATA);
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+20), u32_clock_tick); //RFM forward tick
|
||||
|
||||
ret = osp_send_msg((uint32_t)(addr),
|
||||
RFM_TEST_MSG_SIZE,
|
||||
RFM_MSG_TYPE,
|
||||
9, // src que id
|
||||
4, // dst que id
|
||||
40, // src task id
|
||||
40); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 32), ++g_u32_rfm_2_send_err);
|
||||
return payloadSize;
|
||||
}
|
||||
g_u32_rfm_2_send_ok++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 33), g_u32_rfm_2_recv_num);
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 34), g_u32_rfm_2_send_ok);
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
static uint32_t g_u32_rfm_2_alloc1_err = 0; //(35) 0xB7E0148C
|
||||
static uint32_t g_u32_rfm_2_send1_err = 0; //(36) 0xB7E01490
|
||||
static uint32_t g_u32_rfm_2_recv1_num = 0; //(37) 0xB7E01494
|
||||
static uint32_t g_u32_rfm_2_send1_ok = 0; //(38) 0xB7E01498
|
||||
|
||||
uint32_t rx2_callback_ctrl(const char* buf,uint32_t payloadSize)
|
||||
{
|
||||
int32_t ret = cell_setup_msg_forward((char*)buf, payloadSize);
|
||||
if (0 == ret) {
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
/* RFM0接收消息后发给APE1 */
|
||||
uint32_t core_id = get_core_id();
|
||||
char *addr = NULL;
|
||||
uint32_t u32_clock_tick = 0;
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+16), u32_clock_tick); //RFM receive tick
|
||||
g_u32_rfm_2_recv1_num++;
|
||||
|
||||
addr = osp_alloc_msg(RFM_TEST_MSG_SIZE);
|
||||
if (NULL == addr)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 35), ++g_u32_rfm_2_alloc1_err);
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
do_write(addr, (uint32_t)buf);
|
||||
do_write((addr+4), UCP4008_TRAFFIC_NR_eMBB_CTRL);
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+20), u32_clock_tick); //RFM forward tick
|
||||
|
||||
ret = osp_send_msg((uint32_t)(addr),
|
||||
RFM_TEST_MSG_SIZE,
|
||||
RFM_MSG_TYPE,
|
||||
9, // src que id
|
||||
5, // dst que id
|
||||
40, // src task id
|
||||
40); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 36), ++g_u32_rfm_2_send1_err);
|
||||
return payloadSize;
|
||||
}
|
||||
g_u32_rfm_2_send1_ok++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 37), g_u32_rfm_2_recv1_num);
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 38), g_u32_rfm_2_send1_ok);
|
||||
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
static uint32_t g_u32_rfm_3_alloc_err = 0; //(39) 0xB7E0149C
|
||||
static uint32_t g_u32_rfm_3_send_err = 0; //(40) 0xB7E014A0
|
||||
static uint32_t g_u32_rfm_3_recv_num = 0; //(41) 0xB7E014A4
|
||||
static uint32_t g_u32_rfm_3_send_ok = 0; //(42) 0xB7E014A8
|
||||
|
||||
uint32_t rx3_callback_data(const char* buf,uint32_t payloadSize)
|
||||
{
|
||||
/* RFM0接收消息后发给APE0 */
|
||||
uint32_t core_id = get_core_id();
|
||||
int32_t ret = 0;
|
||||
char *addr = NULL;
|
||||
uint32_t u32_clock_tick = 0;
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+16), u32_clock_tick); //RFM receive tick
|
||||
g_u32_rfm_3_recv_num++;
|
||||
|
||||
addr = osp_alloc_msg(RFM_TEST_MSG_SIZE);
|
||||
if (NULL == addr)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 39), ++g_u32_rfm_3_alloc_err);
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
do_write(addr, (uint32_t)buf);
|
||||
do_write((addr+4), UCP4008_TRAFFIC_NR_eMBB_DATA);
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+20), u32_clock_tick); //RFM forward tick
|
||||
|
||||
ret = osp_send_msg((uint32_t)(addr),
|
||||
RFM_TEST_MSG_SIZE,
|
||||
RFM_MSG_TYPE,
|
||||
9, // src que id
|
||||
6, // dst que id
|
||||
40, // src task id
|
||||
40); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 40), ++g_u32_rfm_3_send_err);
|
||||
return payloadSize;
|
||||
}
|
||||
g_u32_rfm_3_send_ok++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 41), g_u32_rfm_3_recv_num);
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 42), g_u32_rfm_3_send_ok);
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
static uint32_t g_u32_rfm_3_alloc1_err = 0; //(43) 0xB7E014AC
|
||||
static uint32_t g_u32_rfm_3_send1_err = 0; //(44) 0xB7E014B0
|
||||
static uint32_t g_u32_rfm_3_recv1_num = 0; //(45) 0xB7E014B4
|
||||
static uint32_t g_u32_rfm_3_send1_ok = 0; //(46) 0xB7E014B8
|
||||
|
||||
uint32_t rx3_callback_ctrl(const char* buf,uint32_t payloadSize)
|
||||
{
|
||||
int32_t ret = cell_setup_msg_forward((char*)buf, payloadSize);
|
||||
if (0 == ret) {
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
/* RFM0接收消息后发给APE1 */
|
||||
uint32_t core_id = get_core_id();
|
||||
char *addr = NULL;
|
||||
uint32_t u32_clock_tick = 0;
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+16), u32_clock_tick); //RFM receive tick
|
||||
g_u32_rfm_3_recv1_num++;
|
||||
|
||||
addr = osp_alloc_msg(RFM_TEST_MSG_SIZE);
|
||||
if (NULL == addr)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 43), ++g_u32_rfm_3_alloc1_err);
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
do_write(addr, (uint32_t)buf);
|
||||
do_write((addr+4), UCP4008_TRAFFIC_NR_eMBB_CTRL);
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
do_write((buf+20), u32_clock_tick); //RFM forward tick
|
||||
|
||||
ret = osp_send_msg((uint32_t)(addr),
|
||||
RFM_TEST_MSG_SIZE,
|
||||
RFM_MSG_TYPE,
|
||||
9, // src que id
|
||||
7, // dst que id
|
||||
40, // src task id
|
||||
40); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 44), ++g_u32_rfm_3_send1_err);
|
||||
return payloadSize;
|
||||
}
|
||||
g_u32_rfm_3_send1_ok++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 45), g_u32_rfm_3_recv1_num);
|
||||
debug_write(DBG_DDR_COMMON_IDX(core_id, 46), g_u32_rfm_3_send1_ok);
|
||||
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
void phy_init(void)
|
||||
{
|
||||
//uint8_t port_id = get_ucp_port_id();
|
||||
@ -502,7 +292,11 @@ void phy_init(void)
|
||||
int32_t handle_id = 0;
|
||||
//transfer_type_info_s transfer_type_info;
|
||||
|
||||
for (inst_id=0; inst_id<MAX_INSTANCE_NUM; inst_id++)
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (inst_id = 0; inst_id < (MAX_INSTANCE_NUM / 2); inst_id++)
|
||||
#else
|
||||
for (inst_id = 0; inst_id < MAX_INSTANCE_NUM; inst_id++)
|
||||
#endif
|
||||
{
|
||||
transfer_type = OAM;
|
||||
handle_id = msg_transfer_callback_register(transfer_type,inst_id,cu_flag,rx_callback_oam);
|
||||
@ -538,32 +332,6 @@ void phy_init(void)
|
||||
UCP_PRINT_EMPTY("msg_transfer_cfg transfer_type:CU_SPLIT, handle_id[0x%08x] error.",handle_id);
|
||||
}
|
||||
|
||||
transfer_type = CU_SPLIT;
|
||||
cu_flag = C_PLANE;
|
||||
handle_id = msg_transfer_callback_register(transfer_type, 2, cu_flag, rx2_callback_ctrl);
|
||||
if (handle_id < 0) {
|
||||
UCP_PRINT_EMPTY("msg_transfer_cfg transfer_type:CU_SPLIT, handle_id[0x%08x] error.",handle_id);
|
||||
}
|
||||
|
||||
cu_flag = U_PLANE;
|
||||
handle_id = msg_transfer_callback_register(transfer_type, 2, cu_flag, rx2_callback_data);
|
||||
if (handle_id < 0) {
|
||||
UCP_PRINT_EMPTY("msg_transfer_cfg transfer_type:CU_SPLIT, handle_id[0x%08x] error.",handle_id);
|
||||
}
|
||||
|
||||
transfer_type = CU_SPLIT;
|
||||
cu_flag = C_PLANE;
|
||||
handle_id = msg_transfer_callback_register(transfer_type, 3, cu_flag, rx3_callback_ctrl);
|
||||
if (handle_id < 0) {
|
||||
UCP_PRINT_EMPTY("msg_transfer_cfg transfer_type:CU_SPLIT, handle_id[0x%08x] error.",handle_id);
|
||||
}
|
||||
|
||||
cu_flag = U_PLANE;
|
||||
handle_id = msg_transfer_callback_register(transfer_type, 3, cu_flag, rx3_callback_data);
|
||||
if (handle_id < 0) {
|
||||
UCP_PRINT_EMPTY("msg_transfer_cfg transfer_type:CU_SPLIT, handle_id[0x%08x] error.",handle_id);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
245760
public/test/testcases/case121/fronthaul/DATA/tone_24576.dat
Normal file
245760
public/test/testcases/case121/fronthaul/DATA/tone_24576.dat
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,45 @@
|
||||
#ifndef _JESD_TEST_CASE121_H_
|
||||
#define _JESD_TEST_CASE121_H_
|
||||
|
||||
#if 0
|
||||
#define JESD_CASE44_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
|
||||
#define JESD_CASE44_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
|
||||
#define JESD_CASE44_RX_SLOTD_DATA_LEN 0xF0000
|
||||
|
||||
#define JESD_CASE44_TDD_DATA_LEN 0x960000
|
||||
|
||||
#define JESD_CASE44_RX1_DUMMY_DATA_ADDR 0xB4BA4800
|
||||
#define JESD_CASE44_RX1_SLOTS_DATA_ADDR ((JESD_CASE44_RX1_DUMMY_DATA_ADDR)+(JESD_CASE44_RX_DUMMY_DATA_LEN))
|
||||
#define JESD_CASE44_RX1_SLOT8_DATA_ADDR ((JESD_CASE44_RX1_SLOTS_DATA_ADDR)+(JESD_CASE44_RX_SLOTS_DATA_LEN))
|
||||
#define JESD_CASE44_RX1_SLOT9_DATA_ADDR ((JESD_CASE44_RX1_SLOT8_DATA_ADDR)+(JESD_CASE44_RX_SLOTD_DATA_LEN))
|
||||
|
||||
#define JESD_CASE44_RX2_DUMMY_DATA_ADDR 0xB5504800
|
||||
#define JESD_CASE44_RX2_SLOTS_DATA_ADDR ((JESD_CASE44_RX2_DUMMY_DATA_ADDR)+(JESD_CASE44_RX_DUMMY_DATA_LEN))
|
||||
#define JESD_CASE44_RX2_SLOT8_DATA_ADDR ((JESD_CASE44_RX2_SLOTS_DATA_ADDR)+(JESD_CASE44_RX_SLOTS_DATA_LEN))
|
||||
#define JESD_CASE44_RX2_SLOT9_DATA_ADDR ((JESD_CASE44_RX2_SLOT8_DATA_ADDR)+(JESD_CASE44_RX_SLOTD_DATA_LEN))
|
||||
|
||||
|
||||
#define JESD_CASE44_TX_SLOT_EVEN_F7SYMBOL_TAG 0
|
||||
#define JESD_CASE44_TX_SLOT_ODD_F7SYMBOL_TAG 1
|
||||
#define JESD_CASE44_TX_SLOT_EVEN_B7SYMBOL_TAG 2
|
||||
#define JESD_CASE44_TX_SLOT_ODD_B7SYMBOL_TAG 3
|
||||
|
||||
#define JESD_CASE44_RX_SLOT_EVEN_F7SYMBOL_TAG 4
|
||||
#define JESD_CASE44_RX_SLOT_ODD_F7SYMBOL_TAG 5
|
||||
#define JESD_CASE44_RX_SLOT_EVEN_B7SYMBOL_TAG 6
|
||||
#define JESD_CASE44_RX_SLOT_ODD_B7SYMBOL_TAG 7
|
||||
#endif
|
||||
int32_t fh_data_init(void);
|
||||
|
||||
int32_t fh_drv_init(void);
|
||||
|
||||
int32_t fh_csu_test_init(void);
|
||||
|
||||
void fh_test_case();
|
||||
|
||||
void jesd_tx_data_init();
|
||||
|
||||
void jesd_csu_config();
|
||||
|
||||
#endif
|
||||
|
||||
1
public/test/testcases/case121/fronthaul/note.txt
Normal file
1
public/test/testcases/case121/fronthaul/note.txt
Normal file
@ -0,0 +1 @@
|
||||
NR15K，245.76M采样率，发单音信号，频偏10M
|
||||
@ -0,0 +1,125 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : cpri_test_case44.c
|
||||
// Author : xinxin.li
|
||||
// Created On : 2023-03-22s
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
|
||||
#include "typedef.h"
|
||||
#include "ucp_printf.h"
|
||||
#include "ucp_utility.h"
|
||||
#include "ape_csu.h"
|
||||
#include "jesd_csu.h"
|
||||
#include "jesd_timer.h"
|
||||
#include "jesd_csu_lte_fdd.h"
|
||||
#include "jesd_test.h"
|
||||
#include "jesd_test_case121.h"
|
||||
#include "rfm1_drv.h"
|
||||
|
||||
extern uint32_t antDataLte[245760]; // 256QAM, NR15K, 245.76M
|
||||
|
||||
extern uint32_t gJesdTestMode;
|
||||
extern uint32_t gJesdIOMode;
|
||||
extern uint32_t gJesdTFMode;
|
||||
|
||||
int32_t fh_data_init(void)
|
||||
{
|
||||
gJesdTestMode = JESD_TEST_MODE;
|
||||
gJesdIOMode = JESD_CSU_CTRL;
|
||||
gJesdTFMode = FDD_MODE;
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
|
||||
|
||||
jesd_tx_data_init();//init tx data
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t fh_drv_init(void)
|
||||
{
|
||||
stFrontHaulDrvPara fhDrvPara;
|
||||
memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));
|
||||
|
||||
fhDrvPara.protocolSel = PROTOCOL_JESD;
|
||||
fhDrvPara.rateOption = JESD_OPTION_204B;
|
||||
|
||||
fronthaul_drv_cfg(&fhDrvPara);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t fh_csu_test_init(void)
|
||||
{
|
||||
jesd_csu_init_15K_fdd_1ant();
|
||||
|
||||
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
|
||||
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fh_test_case()
|
||||
{
|
||||
}
|
||||
|
||||
void fh_data_check(uint32_t times)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void jesd_tx_data_init()
|
||||
{
|
||||
uint8_t antNum = 1;
|
||||
uint8_t idAnt = 0;
|
||||
uint8_t idSlot = 0;
|
||||
uint32_t srcAddr = 0;
|
||||
uint32_t dstAddr = 0;
|
||||
uint32_t dataLen = 0;
|
||||
uint16_t samByteCnt = 4;
|
||||
uint32_t slotSamCnt = JESD_15K_FDD_SUBFRAME_SAM_CNT;
|
||||
|
||||
uint32_t cpyCnt = 0;
|
||||
|
||||
memset_ucp((void*)JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
memset_ucp((void*)JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
// valid data
|
||||
// IQ data
|
||||
samByteCnt = 4;
|
||||
for (idAnt = 0; idAnt < antNum; idAnt++)
|
||||
{
|
||||
for (idSlot = 0; idSlot <= 1; idSlot++)
|
||||
{
|
||||
if (0 == idSlot) // even slot
|
||||
{
|
||||
dataLen = samByteCnt * slotSamCnt;
|
||||
srcAddr = (uint32_t)(&antDataLte[0]); // + idAnt*slotSamCnt;
|
||||
dstAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
|
||||
}
|
||||
else if (1 == idSlot) // odd slot
|
||||
{
|
||||
dataLen = samByteCnt * slotSamCnt;
|
||||
srcAddr = (uint32_t)(&antDataLte[0]); // + idAnt*slotSamCnt;
|
||||
dstAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
|
||||
}
|
||||
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
|
||||
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
|
||||
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
|
||||
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
|
||||
cpyCnt++;
|
||||
}
|
||||
}
|
||||
memset((void*)JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
memset((void*)JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
}
|
||||
|
||||
|
||||
|
||||
245766
public/test/testcases/case121/fronthaul/src/jesd_test_case121_antdata.s.c
Normal file
245766
public/test/testcases/case121/fronthaul/src/jesd_test_case121_antdata.s.c
Normal file
File diff suppressed because it is too large
Load Diff
60
public/test/testcases/case121/osp/src/ape_test_case121.s.c
Normal file
60
public/test/testcases/case121/osp/src/ape_test_case121.s.c
Normal file
@ -0,0 +1,60 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : ape_test_case1.s.c
|
||||
// Author :
|
||||
// Created On : 2022-10-26
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
|
||||
#include "typedef.h"
|
||||
#include "osp_task.h"
|
||||
#include "osp_timer.h"
|
||||
#include "ucp_printf.h"
|
||||
|
||||
|
||||
void ape0_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape1_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape2_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape3_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape4_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape5_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape6_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape7_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
#include "jesd_test_case46.h"
|
||||
#include "rfm1_drv.h"
|
||||
|
||||
extern uint32_t antDataNr[245760];
|
||||
extern uint32_t antDataNr[JESD_NRFDD_SLOT_SAM_CNT];
|
||||
|
||||
extern uint32_t gJesdTestMode;
|
||||
extern uint32_t gJesdIOMode;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -17,9 +17,18 @@
|
||||
#include "osp_timer.h"
|
||||
#include "ucp_printf.h"
|
||||
|
||||
/************************************************************************/
|
||||
void ape0_event_task(uint32_t addr, uint32_t size);
|
||||
void ape0_event_task_del(uint32_t addr, uint32_t size);
|
||||
|
||||
void ape0_test_task_reg(void)
|
||||
{
|
||||
osp_task_info_ex ape0_event_task_info = {50, (int8_t*)"ape0_event_task", 50, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event_task};
|
||||
osp_task_info_ex ape0_event_task_info_del = {51, (int8_t*)"ape0_event_task_del", 51, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event_task_del};
|
||||
|
||||
osp_task_create(&ape0_event_task_info);
|
||||
osp_task_create(&ape0_event_task_info_del);
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
|
||||
449
public/test/testcases/case46/osp/src/case46_ape0_task.s.c
Normal file
449
public/test/testcases/case46/osp/src/case46_ape0_task.s.c
Normal file
@ -0,0 +1,449 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : case46_ape0_task.s.c
|
||||
// Author :
|
||||
// Created On : 2024-10-08
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
#include "ucp_utility.h"
|
||||
#include "ucp_tick.h"
|
||||
#include "ucp_printf.h"
|
||||
#include "phy_para.h"
|
||||
#include "osp_msg.h"
|
||||
#include "ucp_testcase.h"
|
||||
#include "msg_transfer_layer.h"
|
||||
#include "ucp_port.h"
|
||||
#include "ape_mtimer.h"
|
||||
#include "osp_task.h"
|
||||
#include "osp_timer.h"
|
||||
|
||||
/***************************************************************/
|
||||
/* 事件任务相关打点 */
|
||||
static uint32_t g_u32_case46_ape0_event1_rev_num = 0; // 30 0xB7E00078
|
||||
static uint32_t g_u32_case46_ape0_event1_rev_ok = 0; // 31 0xB7E0007C
|
||||
static uint32_t g_u32_case46_ape0_event1_addr_err = 0; // 32 0xB7E00080
|
||||
static uint32_t g_u32_case46_ape0_event1_tick = 0;
|
||||
static uint32_t g_u32_case46_ape0_event1_tick_err = 0; // 33 0xB7E00084
|
||||
static uint32_t g_u32_case46_ape0_event1_sfn_slot_err = 0; // 35 0xB7E0008C
|
||||
static uint32_t g_u32_case46_ape0_event1_alloc1_err = 0; // 40 0xB7E000A0
|
||||
static uint32_t g_u32_case46_ape0_event1_send1_err = 0; // 41 0xB7E000A4
|
||||
static uint32_t g_u32_case46_ape0_event1_alloc2_err = 0; // 42 0xB7E000A8
|
||||
static uint32_t g_u32_case46_ape0_event1_send2_err = 0; // 43 0xB7E000AC
|
||||
static uint32_t g_u32_case46_ape0_event1_send_ok = 0; // 44 0xB7E000B0
|
||||
|
||||
static uint32_t g_u32_case46_ape0_event2_num = 0; // 45 0xB7E000B4
|
||||
static uint32_t g_u32_case46_ape0_event3_num = 0; // 46 0xB7E000B8
|
||||
|
||||
/* 收到ARM侧发来的消息（通过RFM转发） */
|
||||
void ape0_event1_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
uint32_t msg_addr = 0;
|
||||
uint32_t que_num = 0;
|
||||
uint32_t value = 0;
|
||||
uint16_t scs = NR_SCS_30K;
|
||||
uint16_t sfn = 0;
|
||||
uint16_t slot = 0;
|
||||
uint16_t sfn_l = 0;
|
||||
uint16_t slot_l = 0;
|
||||
uint32_t u32_clock_offset = 0;
|
||||
uint32_t u32_clock_tick = 0;
|
||||
char *paddr = NULL;
|
||||
int ret = 0;
|
||||
|
||||
g_u32_case46_ape0_event1_rev_num++;
|
||||
if (0 == addr)
|
||||
{
|
||||
g_u32_case46_ape0_event1_addr_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 32), g_u32_case46_ape0_event1_addr_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
msg_addr = do_read(addr);
|
||||
que_num = do_read(addr+4);
|
||||
|
||||
value = *(uint32_t*)msg_addr;
|
||||
sfn = value >> 16;
|
||||
slot = value & 0xffff;
|
||||
//msg_transfer_free_msg(TEST_QUE_PORT_ID, que_num, 0, (char*)msg_addr);
|
||||
g_u32_case46_ape0_event1_rev_ok++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 30), g_u32_case46_ape0_event1_rev_num);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 31), g_u32_case46_ape0_event1_rev_ok);
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
|
||||
if (0 == g_u32_case46_ape0_event1_tick)
|
||||
{
|
||||
g_u32_case46_ape0_event1_tick = u32_clock_tick;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (u32_clock_tick > g_u32_case46_ape0_event1_tick)
|
||||
{
|
||||
u32_clock_offset = u32_clock_tick - g_u32_case46_ape0_event1_tick;
|
||||
if ((u32_clock_offset > TIMER_OFFSET_MAX) || (u32_clock_offset < TIMER_OFFSET_MIN))
|
||||
{
|
||||
g_u32_case46_ape0_event1_tick_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 33), g_u32_case46_ape0_event1_tick_err);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 34), u32_clock_offset);
|
||||
}
|
||||
}
|
||||
g_u32_case46_ape0_event1_tick = u32_clock_tick;
|
||||
}
|
||||
|
||||
sfn_l = get_tx_nr_sfn(scs);
|
||||
slot_l = get_tx_nr_slot(scs);
|
||||
if ((sfn != sfn_l) || (slot != slot_l))
|
||||
{
|
||||
g_u32_case46_ape0_event1_sfn_slot_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 35), g_u32_case46_ape0_event1_sfn_slot_err);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 36), sfn);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 37), sfn_l);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 38), slot);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 39), slot_l);
|
||||
}
|
||||
|
||||
/* 给本核event3发消息 */
|
||||
paddr = osp_alloc_msg(TEST_MSG_SIZE);
|
||||
if (NULL == paddr)
|
||||
{
|
||||
g_u32_case46_ape0_event1_alloc1_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 40), g_u32_case46_ape0_event1_alloc1_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
do_write(paddr, g_u32_case46_ape0_event1_rev_num);
|
||||
do_write((paddr+4), 0xA001B002);
|
||||
|
||||
ret = osp_send_msg((uint32_t)(paddr),
|
||||
TEST_MSG_SIZE,
|
||||
UCP4008_KERNEL_INNER,
|
||||
ape_id, // src que id
|
||||
ape_id, // dst que id
|
||||
40, // src task id
|
||||
42); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
g_u32_case46_ape0_event1_send1_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 41), g_u32_case46_ape0_event1_send1_err);
|
||||
//return ;
|
||||
}
|
||||
|
||||
/* 给其核event2发消息 */
|
||||
paddr = osp_alloc_msg(TEST_MSG_SIZE);
|
||||
if (NULL == paddr)
|
||||
{
|
||||
g_u32_case46_ape0_event1_alloc2_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 42), g_u32_case46_ape0_event1_alloc2_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
do_write(paddr, g_u32_case46_ape0_event1_rev_num);
|
||||
do_write((paddr+4), 0xA001B002);
|
||||
|
||||
ret = osp_send_msg((uint32_t)(paddr),
|
||||
TEST_MSG_SIZE,
|
||||
UCP4008_KERNEL_INTER,
|
||||
ape_id, // src que id
|
||||
ape_id+1, // dst que id
|
||||
40, // src task id
|
||||
41); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
g_u32_case46_ape0_event1_send2_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 43), g_u32_case46_ape0_event1_send2_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 44), ++g_u32_case46_ape0_event1_send_ok);
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
/* 收到他核event1发来的消息 */
|
||||
void ape0_event2_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
g_u32_case46_ape0_event2_num++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 45), g_u32_case46_ape0_event2_num);
|
||||
return ;
|
||||
}
|
||||
|
||||
/* 收到本核event1发来的消息 */
|
||||
void ape0_event3_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
g_u32_case46_ape0_event3_num++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 46), g_u32_case46_ape0_event3_num);
|
||||
return ;
|
||||
}
|
||||
|
||||
/***************************************************************/
|
||||
/* 定时时任务相关打点 */
|
||||
static uint32_t g_u32_case46_ape0_timer1_slot_no_continuous = 0; // 50 0xB7E000C8
|
||||
static uint32_t g_u32_case46_ape0_timer1_sfn_no_continuous = 0; // 51 0xB7E000CC
|
||||
static uint32_t g_u32_case46_ape0_timer1_slot_indication = 0; // 52 0xB7E000D0
|
||||
static uint32_t g_u32_case46_ape0_timer1_update_sfn_slot = 0; // 53 0xB7E000D4
|
||||
static uint32_t g_u32_case46_ape0_timer1_process_cnt = 0; // 54 0xB7E000D8
|
||||
static uint32_t g_u32_case46_ape0_timer1_process_tick = 0; // 55 0xB7E000DC
|
||||
static uint32_t g_u32_case46_ape0_timer1_process_tick_err = 0; // 56 0xB7E000E0
|
||||
static uint32_t g_u32_case46_ape0_timer2_process_cnt = 0; // 57 0xB7E000E4
|
||||
static uint32_t g_u32_case46_ape0_timer2_process_tick = 0; // 58 0xB7E000E8
|
||||
static uint32_t g_u32_case46_ape0_timer2_process_tick_err = 0; // 59 0xB7E000EC
|
||||
static uint32_t g_u32_case46_ape0_timer2_tx_slot_max = 0; // 64 0xB7E00100
|
||||
static uint32_t g_u32_case46_ape0_timer2_tx_slot_min = 0x32000;//65 0xB7E00104
|
||||
static uint32_t g_u32_case46_ape0_timer2_tx_slot_cur = 0; // 66 0xB7E00108
|
||||
static uint32_t g_u32_case46_ape0_timer2_rx_slot_max = 0; // 67 0xB7E0010C
|
||||
static uint32_t g_u32_case46_ape0_timer2_rx_slot_min = 0x32000; // 68 0xB7E00110
|
||||
static uint32_t g_u32_case46_ape0_timer2_rx_slot_cur = 0; // 69 0xB7E00114
|
||||
|
||||
static uint16_t gPreviousSlot = 0;
|
||||
static uint16_t gCurrentSlot = 0;
|
||||
static uint8_t gSlotFlagInit = 1;
|
||||
static uint8_t gSfnFlagInit = 1;
|
||||
static uint16_t gPreviousSfn = 0;
|
||||
static uint16_t gCurrentSfn = 0;
|
||||
|
||||
static inline void check_continuous_slot(uint16_t slot)
|
||||
{
|
||||
uint16_t delta = 0;
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
if (gSlotFlagInit == 1)
|
||||
{
|
||||
gSlotFlagInit = 0;
|
||||
gCurrentSlot = slot;
|
||||
}
|
||||
else
|
||||
{
|
||||
gPreviousSlot = gCurrentSlot;
|
||||
gCurrentSlot = slot;
|
||||
delta = (SFN_SLOT_NUM + gCurrentSlot - gPreviousSlot) % SFN_SLOT_NUM;
|
||||
if (delta != 1)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 50), ++g_u32_case46_ape0_timer1_slot_no_continuous);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void check_continuous_sfn(uint16_t sfn)
|
||||
{
|
||||
uint16_t delta = 0;
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
if (gSfnFlagInit == 1)
|
||||
{
|
||||
gSfnFlagInit = 0;
|
||||
gCurrentSfn = sfn;
|
||||
}
|
||||
else
|
||||
{
|
||||
gPreviousSfn = gCurrentSfn;
|
||||
gCurrentSfn = sfn;
|
||||
delta = (1024 + gCurrentSfn - gPreviousSfn) % 1024;
|
||||
if (delta != 1) {
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 51), ++g_u32_case46_ape0_timer1_sfn_no_continuous);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t gu32_ape0_send_cnt = 0;
|
||||
static inline void send_slot_indication(void)
|
||||
{
|
||||
uint16_t scs = NR_SCS_30K;
|
||||
uint16_t sfn = get_tx_nr_sfn(scs);
|
||||
uint16_t slot = get_tx_nr_slot(scs);
|
||||
uint32_t value = (sfn << 16) + slot;
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
uint32_t size = 8;
|
||||
char* buf;
|
||||
uint32_t availableSize,offset;
|
||||
|
||||
uint16_t cu_flag = U_PLANE;
|
||||
HandleId_t handler;
|
||||
handler.port_id = get_ucp_port_id();
|
||||
handler.inst_id = 0;
|
||||
handler.type_id = CU_SPLIT;
|
||||
int32_t ret = msg_transfer_send_start(handler.value);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 60), handler.value);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 61), ++gu32_ape0_send_cnt);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 62), slot);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 63), 0xffff);
|
||||
|
||||
ret = msg_transfer_alloc_msg(handler.value, cu_flag, size, &buf, &availableSize, &offset);
|
||||
if (SUCCESS != ret)
|
||||
{
|
||||
UCP_PRINT_ERROR("send_slot_indication C_PLANE ret[0x%08x]", ret);
|
||||
return;
|
||||
}
|
||||
uint32_t clockBegin;
|
||||
rdmcycle(&clockBegin);
|
||||
do_write(buf, value);
|
||||
do_write(buf+4, clockBegin);
|
||||
ret = msg_transfer_send_msg(handler.value, cu_flag, (uint8_t *)buf, offset, size);
|
||||
|
||||
ret = msg_transfer_send_end(handler.value);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 52), ++g_u32_case46_ape0_timer1_slot_indication);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void update_sfn_slot(void)
|
||||
{
|
||||
uint32_t clockBegin;
|
||||
rdmcycle(&clockBegin);
|
||||
|
||||
uint16_t scs = NR_SCS_30K;
|
||||
uint16_t sfn = get_tx_nr_sfn(scs);
|
||||
uint16_t slot = get_tx_nr_slot(scs);
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 53), ++g_u32_case46_ape0_timer1_update_sfn_slot);
|
||||
|
||||
UCP_PRINT_ERROR("ape[0x%x]:enter[%d], sfn[%d], slot[%d].", ape_id, g_u32_case46_ape0_timer1_update_sfn_slot, sfn, slot);
|
||||
|
||||
check_continuous_slot(slot);
|
||||
|
||||
if (slot == 0) {
|
||||
check_continuous_sfn(sfn);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* 定时点任务 */
|
||||
void ape0_timer1_task(void)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
uint32_t clockTick = 0;
|
||||
uint32_t clockOffset = 0;
|
||||
rdmcycle(&clockTick);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 54), ++g_u32_case46_ape0_timer1_process_cnt);
|
||||
|
||||
update_sfn_slot();
|
||||
|
||||
send_slot_indication();
|
||||
|
||||
if (0 == g_u32_case46_ape0_timer1_process_tick)
|
||||
{
|
||||
g_u32_case46_ape0_timer1_process_tick = clockTick;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (clockTick > g_u32_case46_ape0_timer1_process_tick)
|
||||
{
|
||||
clockOffset = clockTick - g_u32_case46_ape0_timer1_process_tick;
|
||||
if ((clockOffset > TIMER_OFFSET_MAX) || (clockOffset < TIMER_OFFSET_MIN))
|
||||
{
|
||||
g_u32_case46_ape0_timer1_process_tick_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 55), clockOffset);
|
||||
}
|
||||
}
|
||||
g_u32_case46_ape0_timer1_process_tick = clockTick;
|
||||
}
|
||||
//debug_write(DBG_DDR_COMMON_IDX(ape_id, 55), g_u32_case46_ape0_timer1_process_tick);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 56), g_u32_case46_ape0_timer1_process_tick_err);
|
||||
return;
|
||||
}
|
||||
|
||||
void ape0_timer2_task(void)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
uint32_t clockTick = 0;
|
||||
uint32_t clockOffset = 0;
|
||||
rdmcycle(&clockTick);
|
||||
|
||||
g_u32_case46_ape0_timer2_tx_slot_cur = get_tx_nr_slot_cycle();
|
||||
g_u32_case46_ape0_timer2_rx_slot_cur = get_rx_nr_slot_cycle();
|
||||
|
||||
g_u32_case46_ape0_timer2_tx_slot_max = get_max(g_u32_case46_ape0_timer2_tx_slot_cur, g_u32_case46_ape0_timer2_tx_slot_max);
|
||||
g_u32_case46_ape0_timer2_tx_slot_min = get_min(g_u32_case46_ape0_timer2_tx_slot_cur, g_u32_case46_ape0_timer2_tx_slot_min);
|
||||
|
||||
g_u32_case46_ape0_timer2_rx_slot_max = get_max(g_u32_case46_ape0_timer2_rx_slot_cur, g_u32_case46_ape0_timer2_rx_slot_max);
|
||||
g_u32_case46_ape0_timer2_rx_slot_min = get_min(g_u32_case46_ape0_timer2_rx_slot_cur, g_u32_case46_ape0_timer2_rx_slot_min);
|
||||
|
||||
g_u32_case46_ape0_timer2_process_cnt++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 57), g_u32_case46_ape0_timer2_process_cnt);
|
||||
|
||||
if (0 == g_u32_case46_ape0_timer2_process_tick)
|
||||
{
|
||||
g_u32_case46_ape0_timer2_process_tick = clockTick;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (clockTick > g_u32_case46_ape0_timer2_process_tick)
|
||||
{
|
||||
clockOffset = clockTick - g_u32_case46_ape0_timer2_process_tick;
|
||||
if ((clockOffset > TIMER_OFFSET_MAX) || (clockOffset < TIMER_OFFSET_MIN))
|
||||
{
|
||||
g_u32_case46_ape0_timer2_process_tick_err++;
|
||||
}
|
||||
}
|
||||
g_u32_case46_ape0_timer2_process_tick = clockTick;
|
||||
}
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 58), g_u32_case46_ape0_timer2_process_tick);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 59), g_u32_case46_ape0_timer2_process_tick_err);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 64), g_u32_case46_ape0_timer2_tx_slot_max);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 65), g_u32_case46_ape0_timer2_tx_slot_min);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 66), g_u32_case46_ape0_timer2_tx_slot_cur);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 67), g_u32_case46_ape0_timer2_rx_slot_max);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 68), g_u32_case46_ape0_timer2_rx_slot_min);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 69), g_u32_case46_ape0_timer2_rx_slot_cur);
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
/*************************************************************************/
|
||||
/* 收到消息后创建任务 */
|
||||
void ape0_event_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x01010101);
|
||||
|
||||
osp_task_info_ex ape0_task_event1 = {40, (int8_t*)"ape0_task_event1", 40, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event1_task};
|
||||
osp_task_info_ex ape0_task_event2 = {41, (int8_t*)"ape0_task_event2", 41, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event2_task};
|
||||
osp_task_info_ex ape0_task_event3 = {42, (int8_t*)"ape0_task_event3", 42, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event3_task};
|
||||
osp_task_info_ex ape0_task_timer1 = {43, (int8_t*)"ape0_task_timer1", 43, 2048, OSP_TIMER_TYPE, 0, 0x3ff, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_timer1_task};
|
||||
osp_task_info_ex ape0_task_timer2 = {44, (int8_t*)"ape0_task_timer2", 44, 2048, OSP_TIMER_TYPE, 0, 0x3ff, 200, NULL, (OSP_TASKENTRY_FUNC)ape0_timer2_task};
|
||||
|
||||
osp_task_create(&ape0_task_event1);
|
||||
osp_task_create(&ape0_task_event2);
|
||||
osp_task_create(&ape0_task_event3);
|
||||
osp_task_create(&ape0_task_timer1);
|
||||
osp_task_create(&ape0_task_timer2);
|
||||
|
||||
osp_timer_sync(NR_SCS_30K);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x03030303);
|
||||
return;
|
||||
}
|
||||
|
||||
/* 收到消息后删除任务 */
|
||||
void ape0_event_task_del(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
|
||||
|
||||
//osp_del_task_all(NR_SCS_30K);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -30,7 +30,7 @@ int32_t fh_data_init(void)
|
||||
int32_t fh_drv_init()
|
||||
{
|
||||
#ifdef DISTRIBUTED_BS
|
||||
cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
|
||||
//cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
|
||||
#endif
|
||||
#ifdef ECPRI_DISTRIBUTED_BS
|
||||
ecpri_init(ECPRI_OPTION_10G);
|
||||
|
||||
@ -0,0 +1,45 @@
|
||||
#ifndef _JESD_TEST_CASE52_H_
|
||||
#define _JESD_TEST_CASE52_H_
|
||||
|
||||
#if 0
|
||||
#define JESD_CASE41_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
|
||||
#define JESD_CASE41_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
|
||||
#define JESD_CASE41_RX_SLOTD_DATA_LEN 0xF0000
|
||||
|
||||
#define JESD_CASE41_TDD_DATA_LEN 0x960000
|
||||
|
||||
#define JESD_CASE41_RX1_DUMMY_DATA_ADDR 0xB4BA4800
|
||||
#define JESD_CASE41_RX1_SLOTS_DATA_ADDR ((JESD_CASE41_RX1_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
|
||||
#define JESD_CASE41_RX1_SLOT8_DATA_ADDR ((JESD_CASE41_RX1_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
|
||||
#define JESD_CASE41_RX1_SLOT9_DATA_ADDR ((JESD_CASE41_RX1_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
|
||||
|
||||
#define JESD_CASE41_RX2_DUMMY_DATA_ADDR 0xB5504800
|
||||
#define JESD_CASE41_RX2_SLOTS_DATA_ADDR ((JESD_CASE41_RX2_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
|
||||
#define JESD_CASE41_RX2_SLOT8_DATA_ADDR ((JESD_CASE41_RX2_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
|
||||
#define JESD_CASE41_RX2_SLOT9_DATA_ADDR ((JESD_CASE41_RX2_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
|
||||
|
||||
|
||||
#define JESD_CASE41_TX_SLOT_EVEN_F7SYMBOL_TAG 0
|
||||
#define JESD_CASE41_TX_SLOT_ODD_F7SYMBOL_TAG 1
|
||||
#define JESD_CASE41_TX_SLOT_EVEN_B7SYMBOL_TAG 2
|
||||
#define JESD_CASE41_TX_SLOT_ODD_B7SYMBOL_TAG 3
|
||||
|
||||
#define JESD_CASE41_RX_SLOT_EVEN_F7SYMBOL_TAG 4
|
||||
#define JESD_CASE41_RX_SLOT_ODD_F7SYMBOL_TAG 5
|
||||
#define JESD_CASE41_RX_SLOT_EVEN_B7SYMBOL_TAG 6
|
||||
#define JESD_CASE41_RX_SLOT_ODD_B7SYMBOL_TAG 7
|
||||
#endif
|
||||
int32_t fh_data_init(void);
|
||||
|
||||
int32_t fh_drv_init(void);
|
||||
|
||||
int32_t fh_csu_test_init(void);
|
||||
|
||||
void fh_test_case();
|
||||
|
||||
void jesd_tx_data_init();
|
||||
|
||||
void jesd_csu_config();
|
||||
|
||||
#endif
|
||||
|
||||
2
public/test/testcases/case52/fronthaul/note.txt
Normal file
2
public/test/testcases/case52/fronthaul/note.txt
Normal file
@ -0,0 +1,2 @@
|
||||
NR FDD，发单音
|
||||
JESD+PCIE
|
||||
126
public/test/testcases/case52/fronthaul/src/jesd_test_case52.s.c
Normal file
126
public/test/testcases/case52/fronthaul/src/jesd_test_case52.s.c
Normal file
@ -0,0 +1,126 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : jesd_test_case52.c
|
||||
// Author : xinxin.li
|
||||
// Created On : 2024-12-11
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
|
||||
#include "typedef.h"
|
||||
#include "ucp_printf.h"
|
||||
#include "ucp_utility.h"
|
||||
#include "ape_csu.h"
|
||||
#include "jesd_csu.h"
|
||||
#include "jesd_timer.h"
|
||||
#include "jesd_csu_nr_fdd.h"
|
||||
#include "jesd_csu_nr_7ds2u.h"
|
||||
#include "jesd_test.h"
|
||||
#include "jesd_test_case52.h"
|
||||
#include "rfm1_drv.h"
|
||||
|
||||
extern uint32_t antDataNr[JESD_NRFDD_SLOT_SAM_CNT];
|
||||
|
||||
extern uint32_t gJesdTestMode;
|
||||
extern uint32_t gJesdIOMode;
|
||||
extern uint32_t gJesdTFMode;
|
||||
|
||||
int32_t fh_data_init(void)
|
||||
{
|
||||
gJesdTestMode = JESD_TEST_MODE;
|
||||
gJesdIOMode = JESD_CSU_CTRL; // JESD_IO_CTRL;
|
||||
gJesdTFMode = FDD_MODE;
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
|
||||
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
|
||||
|
||||
jesd_tx_data_init();//init tx data
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t fh_drv_init(void)
|
||||
{
|
||||
stFrontHaulDrvPara fhDrvPara;
|
||||
memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));
|
||||
|
||||
fhDrvPara.protocolSel = PROTOCOL_JESD;
|
||||
fhDrvPara.rateOption = JESD_OPTION_204B;
|
||||
|
||||
fronthaul_drv_cfg(&fhDrvPara);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t fh_csu_test_init(void)
|
||||
{
|
||||
jesd_csu_init_nr_fdd();
|
||||
//jesd_csu_init_nr_7d2u_slot0();
|
||||
|
||||
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
|
||||
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fh_test_case()
|
||||
{
|
||||
//jesd_csu_start_nr_7ds2u();
|
||||
}
|
||||
|
||||
void fh_data_check(uint32_t times)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void jesd_tx_data_init()
|
||||
{
|
||||
uint8_t antNum = JESD_NRFDD_ANT_NUM;
|
||||
uint8_t idAnt = 0;
|
||||
uint8_t idSlot = 0;
|
||||
uint32_t srcAddr = 0;
|
||||
uint32_t dstAddr = 0;
|
||||
uint32_t dataLen = 0;
|
||||
uint16_t samByteCnt = 4;
|
||||
uint32_t slotSamCnt = JESD_NRFDD_SLOT_SAM_CNT;
|
||||
|
||||
uint32_t cpyCnt = 0;
|
||||
memset_ucp((void*)JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
memset_ucp((void*)JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
// valid data
|
||||
// IQ data
|
||||
samByteCnt = 4;
|
||||
for (idAnt = 0; idAnt < antNum; idAnt++)
|
||||
{
|
||||
for (idSlot = 0; idSlot <= 1; idSlot++)
|
||||
{
|
||||
if (0 == idSlot) // even slot
|
||||
{
|
||||
dataLen = samByteCnt * slotSamCnt;
|
||||
srcAddr = (uint32_t)(&antDataNr[0]); // + idAnt*slotSamCnt;
|
||||
dstAddr = JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
|
||||
}
|
||||
else if (1 == idSlot) // odd slot
|
||||
{
|
||||
dataLen = samByteCnt * slotSamCnt;
|
||||
srcAddr = (uint32_t)(&antDataNr[0]); // + idAnt*slotSamCnt;
|
||||
dstAddr = JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
|
||||
}
|
||||
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
|
||||
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
|
||||
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
|
||||
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
|
||||
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
|
||||
cpyCnt++;
|
||||
}
|
||||
}
|
||||
memset((void*)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
memset((void*)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
|
||||
}
|
||||
|
||||
|
||||
184336
public/test/testcases/case52/fronthaul/src/jesd_test_case52_antdata.s.c
Normal file
184336
public/test/testcases/case52/fronthaul/src/jesd_test_case52_antdata.s.c
Normal file
File diff suppressed because it is too large
Load Diff
29
public/test/testcases/case52/osp/inc/pcie_testcase.h
Normal file
29
public/test/testcases/case52/osp/inc/pcie_testcase.h
Normal file
@ -0,0 +1,29 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : ucp_pcie_traffic.h
|
||||
// Author : xianfeng.du
|
||||
// Created On : 2022-06-25
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
#ifndef __PCIE_TESTCASE_H__
|
||||
#define __PCIE_TESTCASE_H__
|
||||
|
||||
|
||||
uint32_t pcie_rx_callback_data(const char* buf,uint32_t payloadSize);
|
||||
uint32_t pcie_rx_callback_ctrl(const char* buf,uint32_t payloadSize);
|
||||
uint32_t pcie_rx_callback_oam(const char* buf,uint32_t payloadSize);
|
||||
void test_case_cfgpar_pcie();
|
||||
void test_case_sendmsg_pcie();
|
||||
void test_case_recv_msg_pcie();
|
||||
void test_speed_sendmsg_pcie();
|
||||
void test_speed_recv_msg_pcie();
|
||||
void pcie_test_task_func(void);
|
||||
#endif
|
||||
|
||||
|
||||
74
public/test/testcases/case52/osp/src/ape_test_case52.s.c
Normal file
74
public/test/testcases/case52/osp/src/ape_test_case52.s.c
Normal file
@ -0,0 +1,74 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : ape_test_case52.s.c
|
||||
// Author :
|
||||
// Created On : 2024-12-11
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
|
||||
#include "typedef.h"
|
||||
#include "osp_task.h"
|
||||
#include "osp_timer.h"
|
||||
#include "ucp_printf.h"
|
||||
#include "pcie_testcase.h"
|
||||
|
||||
/************************************************************************/
|
||||
void ape0_event_task(uint32_t addr, uint32_t size);
|
||||
void ape0_event_task_del(uint32_t addr, uint32_t size);
|
||||
|
||||
void ape0_test_task_reg(void)
|
||||
{
|
||||
test_case_cfgpar_pcie();
|
||||
|
||||
osp_task_info_ex ape0_event_task_info = {50, (int8_t*)"ape0_event_task", 50, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event_task};
|
||||
osp_task_info_ex ape0_event_task_info_del = {51, (int8_t*)"ape0_event_task_del", 51, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event_task_del};
|
||||
osp_task_info_ex pcie_normal_task_info = {52, (int8_t*)"pcie_normal_task", 52, 4096, OSP_NORMAL_TYPE, 1, 0, 0, NULL, (OSP_TASKENTRY_FUNC)pcie_test_task_func};
|
||||
|
||||
osp_task_create(&ape0_event_task_info);
|
||||
osp_task_create(&ape0_event_task_info_del);
|
||||
osp_task_create(&pcie_normal_task_info);
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape1_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape2_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape3_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape4_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape5_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape6_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
void ape7_test_task_reg(void)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
449
public/test/testcases/case52/osp/src/case52_ape0_task.s.c
Normal file
449
public/test/testcases/case52/osp/src/case52_ape0_task.s.c
Normal file
@ -0,0 +1,449 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : case52_ape0_task.s.c
|
||||
// Author :
|
||||
// Created On : 2024-12-11
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
#include "ucp_utility.h"
|
||||
#include "ucp_tick.h"
|
||||
#include "ucp_printf.h"
|
||||
#include "phy_para.h"
|
||||
#include "osp_msg.h"
|
||||
#include "ucp_testcase.h"
|
||||
#include "msg_transfer_layer.h"
|
||||
#include "ucp_port.h"
|
||||
#include "ape_mtimer.h"
|
||||
#include "osp_task.h"
|
||||
#include "osp_timer.h"
|
||||
|
||||
/***************************************************************/
|
||||
/* 事件任务相关打点 */
|
||||
static uint32_t g_u32_case52_ape0_event1_rev_num = 0; // 30 0xB7E00078
|
||||
static uint32_t g_u32_case52_ape0_event1_rev_ok = 0; // 31 0xB7E0007C
|
||||
static uint32_t g_u32_case52_ape0_event1_addr_err = 0; // 32 0xB7E00080
|
||||
static uint32_t g_u32_case52_ape0_event1_tick = 0;
|
||||
static uint32_t g_u32_case52_ape0_event1_tick_err = 0; // 33 0xB7E00084
|
||||
static uint32_t g_u32_case52_ape0_event1_sfn_slot_err = 0; // 35 0xB7E0008C
|
||||
static uint32_t g_u32_case52_ape0_event1_alloc1_err = 0; // 40 0xB7E000A0
|
||||
static uint32_t g_u32_case52_ape0_event1_send1_err = 0; // 41 0xB7E000A4
|
||||
static uint32_t g_u32_case52_ape0_event1_alloc2_err = 0; // 42 0xB7E000A8
|
||||
static uint32_t g_u32_case52_ape0_event1_send2_err = 0; // 43 0xB7E000AC
|
||||
static uint32_t g_u32_case52_ape0_event1_send_ok = 0; // 44 0xB7E000B0
|
||||
|
||||
static uint32_t g_u32_case52_ape0_event2_num = 0; // 45 0xB7E000B4
|
||||
static uint32_t g_u32_case52_ape0_event3_num = 0; // 46 0xB7E000B8
|
||||
|
||||
/* 收到ARM侧å<C2A7>‘æ<E28098>¥çš„消æ<CB86>¯ï¼ˆé€šè¿‡RFM转å<C2AC>‘ï¼?*/
|
||||
void ape0_event1_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
uint32_t msg_addr = 0;
|
||||
uint32_t que_num = 0;
|
||||
uint32_t value = 0;
|
||||
uint16_t scs = NR_SCS_30K;
|
||||
uint16_t sfn = 0;
|
||||
uint16_t slot = 0;
|
||||
uint16_t sfn_l = 0;
|
||||
uint16_t slot_l = 0;
|
||||
uint32_t u32_clock_offset = 0;
|
||||
uint32_t u32_clock_tick = 0;
|
||||
char *paddr = NULL;
|
||||
int ret = 0;
|
||||
|
||||
g_u32_case52_ape0_event1_rev_num++;
|
||||
if (0 == addr)
|
||||
{
|
||||
g_u32_case52_ape0_event1_addr_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 32), g_u32_case52_ape0_event1_addr_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
msg_addr = do_read(addr);
|
||||
que_num = do_read(addr+4);
|
||||
|
||||
value = *(uint32_t*)msg_addr;
|
||||
sfn = value >> 16;
|
||||
slot = value & 0xffff;
|
||||
//msg_transfer_free_msg(TEST_QUE_PORT_ID, que_num, 0, (char*)msg_addr);
|
||||
g_u32_case52_ape0_event1_rev_ok++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 30), g_u32_case52_ape0_event1_rev_num);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 31), g_u32_case52_ape0_event1_rev_ok);
|
||||
|
||||
rdmcycle(&u32_clock_tick);
|
||||
|
||||
if (0 == g_u32_case52_ape0_event1_tick)
|
||||
{
|
||||
g_u32_case52_ape0_event1_tick = u32_clock_tick;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (u32_clock_tick > g_u32_case52_ape0_event1_tick)
|
||||
{
|
||||
u32_clock_offset = u32_clock_tick - g_u32_case52_ape0_event1_tick;
|
||||
if ((u32_clock_offset > TIMER_OFFSET_MAX) || (u32_clock_offset < TIMER_OFFSET_MIN))
|
||||
{
|
||||
g_u32_case52_ape0_event1_tick_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 33), g_u32_case52_ape0_event1_tick_err);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 34), u32_clock_offset);
|
||||
}
|
||||
}
|
||||
g_u32_case52_ape0_event1_tick = u32_clock_tick;
|
||||
}
|
||||
|
||||
sfn_l = get_tx_nr_sfn(scs);
|
||||
slot_l = get_tx_nr_slot(scs);
|
||||
if ((sfn != sfn_l) || (slot != slot_l))
|
||||
{
|
||||
g_u32_case52_ape0_event1_sfn_slot_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 35), g_u32_case52_ape0_event1_sfn_slot_err);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 36), sfn);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 37), sfn_l);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 38), slot);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 39), slot_l);
|
||||
}
|
||||
|
||||
/* ç»™æœ¬æ ¸event3å<33>‘消æ<CB86>?*/
|
||||
paddr = osp_alloc_msg(TEST_MSG_SIZE);
|
||||
if (NULL == paddr)
|
||||
{
|
||||
g_u32_case52_ape0_event1_alloc1_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 40), g_u32_case52_ape0_event1_alloc1_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
do_write(paddr, g_u32_case52_ape0_event1_rev_num);
|
||||
do_write((paddr+4), 0xA001B002);
|
||||
|
||||
ret = osp_send_msg((uint32_t)(paddr),
|
||||
TEST_MSG_SIZE,
|
||||
UCP4008_KERNEL_INNER,
|
||||
ape_id, // src que id
|
||||
ape_id, // dst que id
|
||||
40, // src task id
|
||||
42); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
g_u32_case52_ape0_event1_send1_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 41), g_u32_case52_ape0_event1_send1_err);
|
||||
//return ;
|
||||
}
|
||||
|
||||
/* ç»™å…¶æ ¸event2å<32>‘消æ<CB86>?*/
|
||||
paddr = osp_alloc_msg(TEST_MSG_SIZE);
|
||||
if (NULL == paddr)
|
||||
{
|
||||
g_u32_case52_ape0_event1_alloc2_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 42), g_u32_case52_ape0_event1_alloc2_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
do_write(paddr, g_u32_case52_ape0_event1_rev_num);
|
||||
do_write((paddr+4), 0xA001B002);
|
||||
|
||||
ret = osp_send_msg((uint32_t)(paddr),
|
||||
TEST_MSG_SIZE,
|
||||
UCP4008_KERNEL_INTER,
|
||||
ape_id, // src que id
|
||||
ape_id+1, // dst que id
|
||||
40, // src task id
|
||||
41); // dst task id
|
||||
|
||||
if (0 != ret)
|
||||
{
|
||||
g_u32_case52_ape0_event1_send2_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 43), g_u32_case52_ape0_event1_send2_err);
|
||||
return ;
|
||||
}
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 44), ++g_u32_case52_ape0_event1_send_ok);
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
/* æ”¶åˆ°ä»–æ ¸event1å<31>‘æ<E28098>¥çš„消æ<CB86>?*/
|
||||
void ape0_event2_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
g_u32_case52_ape0_event2_num++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 45), g_u32_case52_ape0_event2_num);
|
||||
return ;
|
||||
}
|
||||
|
||||
/* æ”¶åˆ°æœ¬æ ¸event1å<31>‘æ<E28098>¥çš„消æ<CB86>?*/
|
||||
void ape0_event3_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
g_u32_case52_ape0_event3_num++;
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 46), g_u32_case52_ape0_event3_num);
|
||||
return ;
|
||||
}
|
||||
|
||||
/***************************************************************/
|
||||
/* 定时时任务相关打� */
|
||||
static uint32_t g_u32_case52_ape0_timer1_slot_no_continuous = 0; // 50 0xB7E000C8
|
||||
static uint32_t g_u32_case52_ape0_timer1_sfn_no_continuous = 0; // 51 0xB7E000CC
|
||||
static uint32_t g_u32_case52_ape0_timer1_slot_indication = 0; // 52 0xB7E000D0
|
||||
static uint32_t g_u32_case52_ape0_timer1_update_sfn_slot = 0; // 53 0xB7E000D4
|
||||
static uint32_t g_u32_case52_ape0_timer1_process_cnt = 0; // 54 0xB7E000D8
|
||||
static uint32_t g_u32_case52_ape0_timer1_process_tick = 0; // 55 0xB7E000DC
|
||||
static uint32_t g_u32_case52_ape0_timer1_process_tick_err = 0; // 56 0xB7E000E0
|
||||
static uint32_t g_u32_case52_ape0_timer2_process_cnt = 0; // 57 0xB7E000E4
|
||||
static uint32_t g_u32_case52_ape0_timer2_process_tick = 0; // 58 0xB7E000E8
|
||||
static uint32_t g_u32_case52_ape0_timer2_process_tick_err = 0; // 59 0xB7E000EC
|
||||
static uint32_t g_u32_case52_ape0_timer2_tx_slot_max = 0; // 64 0xB7E00100
|
||||
static uint32_t g_u32_case52_ape0_timer2_tx_slot_min = 0x32000;//65 0xB7E00104
|
||||
static uint32_t g_u32_case52_ape0_timer2_tx_slot_cur = 0; // 66 0xB7E00108
|
||||
static uint32_t g_u32_case52_ape0_timer2_rx_slot_max = 0; // 67 0xB7E0010C
|
||||
static uint32_t g_u32_case52_ape0_timer2_rx_slot_min = 0x32000; // 68 0xB7E00110
|
||||
static uint32_t g_u32_case52_ape0_timer2_rx_slot_cur = 0; // 69 0xB7E00114
|
||||
|
||||
static uint16_t gPreviousSlot = 0;
|
||||
static uint16_t gCurrentSlot = 0;
|
||||
static uint8_t gSlotFlagInit = 1;
|
||||
static uint8_t gSfnFlagInit = 1;
|
||||
static uint16_t gPreviousSfn = 0;
|
||||
static uint16_t gCurrentSfn = 0;
|
||||
|
||||
static inline void check_continuous_slot(uint16_t slot)
|
||||
{
|
||||
uint16_t delta = 0;
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
if (gSlotFlagInit == 1)
|
||||
{
|
||||
gSlotFlagInit = 0;
|
||||
gCurrentSlot = slot;
|
||||
}
|
||||
else
|
||||
{
|
||||
gPreviousSlot = gCurrentSlot;
|
||||
gCurrentSlot = slot;
|
||||
delta = (SFN_SLOT_NUM + gCurrentSlot - gPreviousSlot) % SFN_SLOT_NUM;
|
||||
if (delta != 1)
|
||||
{
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 50), ++g_u32_case52_ape0_timer1_slot_no_continuous);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void check_continuous_sfn(uint16_t sfn)
|
||||
{
|
||||
uint16_t delta = 0;
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
if (gSfnFlagInit == 1)
|
||||
{
|
||||
gSfnFlagInit = 0;
|
||||
gCurrentSfn = sfn;
|
||||
}
|
||||
else
|
||||
{
|
||||
gPreviousSfn = gCurrentSfn;
|
||||
gCurrentSfn = sfn;
|
||||
delta = (1024 + gCurrentSfn - gPreviousSfn) % 1024;
|
||||
if (delta != 1) {
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 51), ++g_u32_case52_ape0_timer1_sfn_no_continuous);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t gu32_ape0_send_cnt = 0;
|
||||
static inline void send_slot_indication(void)
|
||||
{
|
||||
uint16_t scs = NR_SCS_30K;
|
||||
uint16_t sfn = get_tx_nr_sfn(scs);
|
||||
uint16_t slot = get_tx_nr_slot(scs);
|
||||
uint32_t value = (sfn << 16) + slot;
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
uint32_t size = 8;
|
||||
char* buf;
|
||||
uint32_t availableSize,offset;
|
||||
|
||||
uint16_t cu_flag = U_PLANE;
|
||||
HandleId_t handler;
|
||||
handler.port_id = get_ucp_port_id();
|
||||
handler.inst_id = 0;
|
||||
handler.type_id = CU_SPLIT;
|
||||
int32_t ret = msg_transfer_send_start(handler.value);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 60), handler.value);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 61), ++gu32_ape0_send_cnt);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 62), slot);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 63), 0xffff);
|
||||
|
||||
ret = msg_transfer_alloc_msg(handler.value, cu_flag, size, &buf, &availableSize, &offset);
|
||||
if (SUCCESS != ret)
|
||||
{
|
||||
UCP_PRINT_ERROR("send_slot_indication C_PLANE ret[0x%08x]", ret);
|
||||
return;
|
||||
}
|
||||
uint32_t clockBegin;
|
||||
rdmcycle(&clockBegin);
|
||||
do_write(buf, value);
|
||||
do_write(buf+4, clockBegin);
|
||||
ret = msg_transfer_send_msg(handler.value, cu_flag, (uint8_t *)buf, offset, size);
|
||||
|
||||
ret = msg_transfer_send_end(handler.value);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 52), ++g_u32_case52_ape0_timer1_slot_indication);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static inline void update_sfn_slot(void)
|
||||
{
|
||||
uint32_t clockBegin;
|
||||
rdmcycle(&clockBegin);
|
||||
|
||||
uint16_t scs = NR_SCS_30K;
|
||||
uint16_t sfn = get_tx_nr_sfn(scs);
|
||||
uint16_t slot = get_tx_nr_slot(scs);
|
||||
uint32_t ape_id = get_core_id();
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 53), ++g_u32_case52_ape0_timer1_update_sfn_slot);
|
||||
|
||||
UCP_PRINT_ERROR("ape[0x%x]:enter[%d], sfn[%d], slot[%d].", ape_id, g_u32_case52_ape0_timer1_update_sfn_slot, sfn, slot);
|
||||
|
||||
check_continuous_slot(slot);
|
||||
|
||||
if (slot == 0) {
|
||||
check_continuous_sfn(sfn);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* 定时点任�*/
|
||||
void ape0_timer1_task(void)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
uint32_t clockTick = 0;
|
||||
uint32_t clockOffset = 0;
|
||||
rdmcycle(&clockTick);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 54), ++g_u32_case52_ape0_timer1_process_cnt);
|
||||
|
||||
update_sfn_slot();
|
||||
|
||||
send_slot_indication();
|
||||
|
||||
if (0 == g_u32_case52_ape0_timer1_process_tick)
|
||||
{
|
||||
g_u32_case52_ape0_timer1_process_tick = clockTick;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (clockTick > g_u32_case52_ape0_timer1_process_tick)
|
||||
{
|
||||
clockOffset = clockTick - g_u32_case52_ape0_timer1_process_tick;
|
||||
if ((clockOffset > TIMER_OFFSET_MAX) || (clockOffset < TIMER_OFFSET_MIN))
|
||||
{
|
||||
g_u32_case52_ape0_timer1_process_tick_err++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 55), clockOffset);
|
||||
}
|
||||
}
|
||||
g_u32_case52_ape0_timer1_process_tick = clockTick;
|
||||
}
|
||||
//debug_write(DBG_DDR_COMMON_IDX(ape_id, 55), g_u32_case52_ape0_timer1_process_tick);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 56), g_u32_case52_ape0_timer1_process_tick_err);
|
||||
return;
|
||||
}
|
||||
|
||||
void ape0_timer2_task(void)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
uint32_t clockTick = 0;
|
||||
uint32_t clockOffset = 0;
|
||||
rdmcycle(&clockTick);
|
||||
|
||||
g_u32_case52_ape0_timer2_tx_slot_cur = get_tx_nr_slot_cycle();
|
||||
g_u32_case52_ape0_timer2_rx_slot_cur = get_rx_nr_slot_cycle();
|
||||
|
||||
g_u32_case52_ape0_timer2_tx_slot_max = get_max(g_u32_case52_ape0_timer2_tx_slot_cur, g_u32_case52_ape0_timer2_tx_slot_max);
|
||||
g_u32_case52_ape0_timer2_tx_slot_min = get_min(g_u32_case52_ape0_timer2_tx_slot_cur, g_u32_case52_ape0_timer2_tx_slot_min);
|
||||
|
||||
g_u32_case52_ape0_timer2_rx_slot_max = get_max(g_u32_case52_ape0_timer2_rx_slot_cur, g_u32_case52_ape0_timer2_rx_slot_max);
|
||||
g_u32_case52_ape0_timer2_rx_slot_min = get_min(g_u32_case52_ape0_timer2_rx_slot_cur, g_u32_case52_ape0_timer2_rx_slot_min);
|
||||
|
||||
g_u32_case52_ape0_timer2_process_cnt++;
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 57), g_u32_case52_ape0_timer2_process_cnt);
|
||||
|
||||
if (0 == g_u32_case52_ape0_timer2_process_tick)
|
||||
{
|
||||
g_u32_case52_ape0_timer2_process_tick = clockTick;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (clockTick > g_u32_case52_ape0_timer2_process_tick)
|
||||
{
|
||||
clockOffset = clockTick - g_u32_case52_ape0_timer2_process_tick;
|
||||
if ((clockOffset > TIMER_OFFSET_MAX) || (clockOffset < TIMER_OFFSET_MIN))
|
||||
{
|
||||
g_u32_case52_ape0_timer2_process_tick_err++;
|
||||
}
|
||||
}
|
||||
g_u32_case52_ape0_timer2_process_tick = clockTick;
|
||||
}
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 58), g_u32_case52_ape0_timer2_process_tick);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 59), g_u32_case52_ape0_timer2_process_tick_err);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 64), g_u32_case52_ape0_timer2_tx_slot_max);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 65), g_u32_case52_ape0_timer2_tx_slot_min);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 66), g_u32_case52_ape0_timer2_tx_slot_cur);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 67), g_u32_case52_ape0_timer2_rx_slot_max);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 68), g_u32_case52_ape0_timer2_rx_slot_min);
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 69), g_u32_case52_ape0_timer2_rx_slot_cur);
|
||||
|
||||
return ;
|
||||
}
|
||||
|
||||
/*************************************************************************/
|
||||
/* 收到消æ<CB86>¯å<C2AF>Žåˆ›å»ºä»»åŠ?*/
|
||||
void ape0_event_task(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x01010101);
|
||||
|
||||
osp_task_info_ex ape0_task_event1 = {40, (int8_t*)"ape0_task_event1", 40, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event1_task};
|
||||
osp_task_info_ex ape0_task_event2 = {41, (int8_t*)"ape0_task_event2", 41, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event2_task};
|
||||
osp_task_info_ex ape0_task_event3 = {42, (int8_t*)"ape0_task_event3", 42, 2048, OSP_EVENT_TYPE, 0, 0, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_event3_task};
|
||||
osp_task_info_ex ape0_task_timer1 = {43, (int8_t*)"ape0_task_timer1", 43, 2048, OSP_TIMER_TYPE, 0, 0x3ff, 0, NULL, (OSP_TASKENTRY_FUNC)ape0_timer1_task};
|
||||
osp_task_info_ex ape0_task_timer2 = {44, (int8_t*)"ape0_task_timer2", 44, 2048, OSP_TIMER_TYPE, 0, 0x3ff, 200, NULL, (OSP_TASKENTRY_FUNC)ape0_timer2_task};
|
||||
|
||||
osp_task_create(&ape0_task_event1);
|
||||
osp_task_create(&ape0_task_event2);
|
||||
osp_task_create(&ape0_task_event3);
|
||||
osp_task_create(&ape0_task_timer1);
|
||||
osp_task_create(&ape0_task_timer2);
|
||||
|
||||
osp_timer_sync(NR_SCS_30K);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x03030303);
|
||||
return;
|
||||
}
|
||||
|
||||
/* 收到消æ<CB86>¯å<C2AF>Žåˆ 除任åŠ?*/
|
||||
void ape0_event_task_del(uint32_t addr, uint32_t size)
|
||||
{
|
||||
uint32_t ape_id = get_core_id();
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
|
||||
|
||||
//osp_del_task_all(NR_SCS_30K);
|
||||
|
||||
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
|
||||
return;
|
||||
}
|
||||
|
||||
436
public/test/testcases/case52/osp/src/pcie_testcase.c
Normal file
436
public/test/testcases/case52/osp/src/pcie_testcase.c
Normal file
@ -0,0 +1,436 @@
|
||||
// +FHDR------------------------------------------------------------
|
||||
// Copyright (c) 2022 SmartLogic.
|
||||
// ALL RIGHTS RESERVED
|
||||
// -----------------------------------------------------------------
|
||||
// Filename : main.c
|
||||
// Author : xianfeng.du
|
||||
// Created On : 2022-06-25
|
||||
// Last Modified :
|
||||
// -----------------------------------------------------------------
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// -FHDR------------------------------------------------------------
|
||||
#include "typedef.h"
|
||||
#include "osp_task.h"
|
||||
#include "osp_timer.h"
|
||||
#include "ucp_printf.h"
|
||||
#include "spu_log.h"
|
||||
|
||||
#include "ucp_drv_common.h"
|
||||
//#include "pet_rfm_spu0_top.h"
|
||||
//#include "msg_transfer_host.h"
|
||||
#include "msg_transfer_layer.h"
|
||||
//#include "ucp_pcie_traffic.h"
|
||||
#include "ucp_printf.h"
|
||||
#include "msg_transfer_mem.h"
|
||||
#include "msg_transfer_mbuffer.h"
|
||||
|
||||
uint32_t pcie_rx_callback_data(const char* buf,uint32_t payloadSize)
|
||||
{
|
||||
char tmplogbuf[1024] = {0};
|
||||
|
||||
if(payloadSize < 1024)
|
||||
{
|
||||
memcpy_ucp(tmplogbuf, buf, payloadSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
memcpy_ucp(tmplogbuf, buf, 1024);
|
||||
}
|
||||
|
||||
//UCP_PRINT_LOG("received buf : %s\n", tmplogbuf);
|
||||
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
uint32_t pcie_rx_callback_ctrl(const char* buf,uint32_t payloadSize)
|
||||
{
|
||||
char tmplogbuf[1024] = {0};
|
||||
|
||||
if(payloadSize < 1024)
|
||||
{
|
||||
memcpy_ucp(tmplogbuf, buf, payloadSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
memcpy_ucp(tmplogbuf, buf, 1024);
|
||||
}
|
||||
|
||||
//UCP_PRINT_LOG("received buf : %s\n", tmplogbuf);
|
||||
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
uint32_t pcie_rx_callback_oam(const char* buf,uint32_t payloadSize)
|
||||
{
|
||||
char tmplogbuf[1024] = {0};
|
||||
|
||||
if(payloadSize < 1024)
|
||||
{
|
||||
memcpy_ucp(tmplogbuf, buf, payloadSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
memcpy_ucp(tmplogbuf, buf, 1024);
|
||||
}
|
||||
|
||||
//UCP_PRINT_LOG("received buf : %s\n", tmplogbuf);
|
||||
|
||||
return payloadSize;
|
||||
}
|
||||
|
||||
void test_case_cfgpar_pcie()
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = (MAX_INSTANCE_NUM / 2); i < MAX_INSTANCE_NUM; i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
msg_transfer_callback_register(CU_SPLIT, i, C_PLANE, pcie_rx_callback_ctrl);
|
||||
msg_transfer_callback_register(CU_SPLIT, i, U_PLANE, pcie_rx_callback_data);
|
||||
msg_transfer_callback_register(OAM, i, C_PLANE, pcie_rx_callback_oam);
|
||||
}
|
||||
}
|
||||
|
||||
int8_t get_id(uint16_t type_id, uint16_t cu_flag)
|
||||
{
|
||||
int8_t que_id = -1;
|
||||
|
||||
switch (type_id) {
|
||||
case CU_SPLIT:
|
||||
if (cu_flag == U_PLANE) {
|
||||
que_id = UCP4008_TRAFFIC_NR_eMBB_DATA;
|
||||
} else {
|
||||
que_id = UCP4008_TRAFFIC_NR_eMBB_CTRL;
|
||||
}
|
||||
break;
|
||||
case OAM:
|
||||
que_id = UCP4008_TRAFFIC_OAM;
|
||||
break;
|
||||
default:
|
||||
UCP_PRINT_LOG("get_queue_id doesn't support transfer_type[%d] .",type_id);
|
||||
break;
|
||||
}
|
||||
|
||||
return que_id;
|
||||
}
|
||||
|
||||
//static uint32_t count = 0;
|
||||
|
||||
void test_case_sendmsg_pcie()
|
||||
{
|
||||
uint32_t size = 512-16;
|
||||
char* buf = NULL;
|
||||
uint32_t availableSize;
|
||||
|
||||
uint16_t cu_flag = C_PLANE;
|
||||
HandleId_t handler;
|
||||
handler.port_id = 0;
|
||||
handler.inst_id = 0;
|
||||
handler.type_id = CU_SPLIT;
|
||||
uint32_t slot_ind_flag = 1;
|
||||
int ret = 0;
|
||||
|
||||
uint32_t offset = 0;
|
||||
uint32_t i = 0;
|
||||
char templogbuf[256] = {0};
|
||||
|
||||
int8_t que_id = 0;
|
||||
MsgQueueLocalMgt_t* pMsgQueueLocalMgt = get_msg_queue_local_mgt();
|
||||
MsgQueueLocalInfo_t* ch;
|
||||
//uint32_t core_id = get_core_id();
|
||||
//uint32_t bufsize = ch->bufSize - MSG_MBUF_HEAD_SIZE;
|
||||
/****************************test code************************************************/
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = (MAX_INSTANCE_NUM / 2); i < MAX_INSTANCE_NUM; i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
//debug_write(DBG_DDR_COMMON_IDX(core_id, 2), ++count);
|
||||
handler.port_id = 0;
|
||||
handler.inst_id = i;
|
||||
handler.type_id = CU_SPLIT;
|
||||
if(1 == slot_ind_flag)
|
||||
{
|
||||
// slot_ind_flag = 0;
|
||||
ret = msg_transfer_send_start(handler.value);
|
||||
/************C_PLANE***************/
|
||||
cu_flag = C_PLANE;
|
||||
que_id = get_id(handler.type_id, cu_flag);
|
||||
ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localUlQueue[i][que_id];
|
||||
size = ch->bufSize-MSG_MBUF_HEAD_SIZE;
|
||||
ret = msg_transfer_alloc_msg(handler.value, cu_flag, size, &buf, &availableSize, &offset);
|
||||
//com_debug_log("alloc ctrl msg ulque[%d][%d] ch=0x%llx ch->bufSize=0x%x\n", i, que_id, (uint64_t)ch, ch->bufSize);
|
||||
if ( SUCCESS != ret) {
|
||||
com_debug_log("alloc ctrl msg failed! ulque[%d][%d] ch=0x%llx ch->bufSize=0x%x\n", i, que_id, (uint64_t)ch, ch->bufSize);
|
||||
continue;
|
||||
}
|
||||
//size = availableSize;
|
||||
//buf = *bufAddr;
|
||||
UCP_PRINT_LOG("msg transfer alloced ul msg C_PLANE buf = 0x%x!\n", buf);
|
||||
memset(templogbuf, 0x00, sizeof(templogbuf));
|
||||
sprintf(templogbuf, "%s", "this is test for ul CU_SPLIT ctrl transfer!\n");
|
||||
memcpy_ucp(buf, templogbuf, strlen(templogbuf)+1);
|
||||
/*
|
||||
*(uint32_t*)(ptr + 0) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 4) = 0x5a5a5a5a;
|
||||
*(uint32_t*)(ptr + 8) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 12) = 0xa5a5a5a5;
|
||||
*/
|
||||
//PCIE_DEBUG_LOG("start enter msg_transfer_send_msg\n");
|
||||
ret = msg_transfer_send_msg(handler.value, cu_flag, (uint8_t *)buf, offset, size);
|
||||
if(ret != SUCCESS)
|
||||
{
|
||||
com_debug_log("ul msg_transfer_send_msg CU_SPLIT ctrl failed! ret = %d inst_id=%d\n", ret, handler.inst_id);
|
||||
}
|
||||
|
||||
/************U_PLANE***************/
|
||||
cu_flag = U_PLANE;
|
||||
que_id = get_id(handler.type_id, cu_flag);
|
||||
ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localUlQueue[i][que_id];
|
||||
size = ch->bufSize-MSG_MBUF_HEAD_SIZE;
|
||||
ret = msg_transfer_alloc_msg(handler.value, cu_flag, size, &buf, &availableSize, &offset);
|
||||
//com_debug_log("alloc data msg ulque[%d][%d] ch=0x%llx ch->bufSize=0x%x\n", i, que_id, (uint64_t)ch, ch->bufSize);
|
||||
|
||||
if ( SUCCESS != ret) {
|
||||
com_debug_log("alloc data msg failed! ulque[%d][%d] ch=0x%llx ch->bufSize=0x%x\n", i, que_id, ch, ch->bufSize);
|
||||
continue;
|
||||
}
|
||||
//size = availableSize;
|
||||
//buf = *bufAddr;
|
||||
UCP_PRINT_LOG("msg transfer alloced ul U_PLANE msg buf = 0x%x!\n", buf);
|
||||
memset(templogbuf, 0x00, sizeof(templogbuf));
|
||||
sprintf(templogbuf, "%s", "this is test for ul CU_SPLIT data transfer!\n");
|
||||
memcpy_ucp(buf, templogbuf, strlen(templogbuf)+1);
|
||||
|
||||
/*
|
||||
ptr = (uint8_t *)buf;
|
||||
*(uint32_t*)(ptr + 0) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 4) = 0x5a5a5a5a;
|
||||
*(uint32_t*)(ptr + 8) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 12) = 0xa5a5a5a5;
|
||||
*/
|
||||
ret = msg_transfer_send_msg(handler.value, cu_flag, (uint8_t *)buf, offset, size);
|
||||
if(ret != SUCCESS)
|
||||
{
|
||||
com_debug_log("ul msg_transfer_send_msg CU_SPLIT data failed! ret = %d inst_id = %d\n", ret, handler.inst_id);
|
||||
}
|
||||
|
||||
ret = msg_transfer_send_end(handler.value);
|
||||
if(ret != SUCCESS)
|
||||
{
|
||||
com_debug_log("ul msg_transfer_send_end CU_SPLIT data failed! ret = %d inst_id = %d\n", ret, handler.inst_id);
|
||||
}
|
||||
}
|
||||
|
||||
handler.type_id = OAM;
|
||||
if(1 == slot_ind_flag)
|
||||
{
|
||||
// slot_ind_flag = 0;
|
||||
|
||||
ret = msg_transfer_send_start(handler.value);
|
||||
|
||||
/************C_PLANE***************/
|
||||
cu_flag = C_PLANE;
|
||||
que_id = get_id(handler.type_id, cu_flag);
|
||||
ch = (MsgQueueLocalInfo_t *)&pMsgQueueLocalMgt->localUlQueue[i][que_id];
|
||||
size = ch->bufSize-MSG_MBUF_HEAD_SIZE;
|
||||
ret = msg_transfer_alloc_msg(handler.value, cu_flag, size, &buf, &availableSize, &offset);
|
||||
//com_debug_log("alloc oam msg ulque[%d][%d] ch=0x%llx ch->bufSize=0x%x\n", i, que_id, (uint64_t)ch, ch->bufSize);
|
||||
|
||||
if ( SUCCESS != ret) {
|
||||
com_debug_log("oam alloc msg failed! ulque[%d][%d] ch=0x%llx ch->bufSize = 0x%x\n", i, que_id, ch, ch->bufSize);
|
||||
continue;
|
||||
}
|
||||
//size = availableSize;
|
||||
//buf = *bufAddr;
|
||||
UCP_PRINT_LOG("msg transfer alloced msg OAM buf = 0x%x!\n", buf);
|
||||
memset(templogbuf, 0x00, sizeof(templogbuf));
|
||||
sprintf(templogbuf, "%s", "this is test for ul OAM ctrl transfer!\n");
|
||||
memcpy_ucp(buf, templogbuf, strlen(templogbuf)+1);
|
||||
|
||||
/*
|
||||
*(uint32_t*)(ptr + 0) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 4) = 0x5a5a5a5a;
|
||||
*(uint32_t*)(ptr + 8) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 12) = 0xa5a5a5a5;
|
||||
*/
|
||||
ret = msg_transfer_send_msg(handler.value, cu_flag, (uint8_t *)buf, offset, size);
|
||||
if(ret != SUCCESS)
|
||||
{
|
||||
com_debug_log("ul msg_transfer_send_msg failed! CU_SPLIT oam ! ret = %d inst_id = %d\n", ret, handler.inst_id);
|
||||
continue;
|
||||
}
|
||||
|
||||
UCP_PRINT_LOG("msg_transfer_send_msg end!\n");
|
||||
ret = msg_transfer_send_end(handler.value);
|
||||
if(ret != SUCCESS)
|
||||
{
|
||||
com_debug_log("ul msg_transfer_send_end CU_SPLIT oam failed! ret = %d inst_id = %d\n", ret, handler.inst_id);
|
||||
}
|
||||
}
|
||||
}
|
||||
/*********************************************************************************/
|
||||
|
||||
}
|
||||
|
||||
void test_case_recv_msg_pcie()
|
||||
{
|
||||
uint16_t cu_flag = C_PLANE;
|
||||
HandleId_t handler;
|
||||
handler.port_id = 0;
|
||||
handler.inst_id = 0;
|
||||
handler.type_id = CU_SPLIT;
|
||||
|
||||
uint8_t port_id = 0;
|
||||
uint32_t offset = 0;
|
||||
uint32_t len = 0;
|
||||
uint8_t* msg_ptr;
|
||||
uint32_t i = 0;
|
||||
|
||||
/****************************test code************************************************/
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = (MAX_INSTANCE_NUM / 2); i < MAX_INSTANCE_NUM; i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
handler.port_id = port_id;
|
||||
handler.inst_id = i;
|
||||
handler.type_id = CU_SPLIT;
|
||||
cu_flag = C_PLANE;
|
||||
msg_transfer_receive(handler.value, cu_flag, offset, len, &msg_ptr);
|
||||
|
||||
cu_flag = U_PLANE;
|
||||
msg_transfer_receive(handler.value, cu_flag, offset, len, &msg_ptr);
|
||||
|
||||
handler.type_id = OAM;
|
||||
msg_transfer_receive(handler.value, cu_flag, offset, len, &msg_ptr);
|
||||
}
|
||||
/*********************************************************************************/
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
||||
void test_speed_sendmsg_pcie()
|
||||
{
|
||||
uint32_t size = 0;
|
||||
char* buf = NULL;
|
||||
uint32_t availableSize;
|
||||
|
||||
uint16_t cu_flag = C_PLANE;
|
||||
HandleId_t handler;
|
||||
handler.port_id = 0;
|
||||
handler.inst_id = 0;
|
||||
handler.type_id = CU_SPLIT;
|
||||
uint32_t slot_ind_flag = 1;
|
||||
int ret = 0;
|
||||
|
||||
uint32_t offset = 0;
|
||||
uint32_t i = 0;
|
||||
char templogbuf[1024] = {0};
|
||||
|
||||
MsgQueueLocalMgt_t* pMsgQueueLocalMgt = get_msg_queue_local_mgt();
|
||||
MsgQueueLocalInfo_t* ch = (MsgQueueLocalInfo_t*)&pMsgQueueLocalMgt->localUlQueue[0][1];
|
||||
size = ch->bufSize - MSG_MBUF_HEAD_SIZE;
|
||||
/****************************test code************************************************/
|
||||
for(i = 0; i < 2; i++)
|
||||
{
|
||||
handler.port_id = 0;
|
||||
handler.inst_id = i;
|
||||
handler.type_id = CU_SPLIT;
|
||||
if(1 == slot_ind_flag)
|
||||
{
|
||||
// slot_ind_flag = 0;
|
||||
ret = msg_transfer_send_start(handler.value);
|
||||
|
||||
/************C_PLANE***************/
|
||||
cu_flag = C_PLANE;
|
||||
ret = msg_transfer_alloc_msg(handler.value, cu_flag, size, &buf, &availableSize, &offset);
|
||||
if ( SUCCESS != ret) {
|
||||
UCP_PRINT_LOG("alloc msg failed!\n");
|
||||
continue;
|
||||
}
|
||||
//size = availableSize;
|
||||
//buf = *bufAddr;
|
||||
UCP_PRINT_LOG("msg transfer alloced ul msg C_PLANE buf = 0x%x!\n", buf);
|
||||
memset(templogbuf, 0x00, sizeof(templogbuf));
|
||||
sprintf(templogbuf, "%s", "this is test for ul CU_SPLIT ctrl transfer!\n");
|
||||
memcpy_ucp(buf, templogbuf, strlen(templogbuf)+1);
|
||||
/*
|
||||
*(uint32_t*)(ptr + 0) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 4) = 0x5a5a5a5a;
|
||||
*(uint32_t*)(ptr + 8) = 0x12345678;
|
||||
*(uint32_t*)(ptr + 12) = 0xa5a5a5a5;
|
||||
*/
|
||||
//PCIE_DEBUG_LOG("start enter msg_transfer_send_msg\n");
|
||||
ret = msg_transfer_send_msg(handler.value, cu_flag, (uint8_t *)buf, offset, size);
|
||||
if(ret != SUCCESS)
|
||||
{
|
||||
UCP_PRINT_LOG("ul msg_transfer_send_msg CU_SPLIT ctrl failed! ret = %d\n", ret);
|
||||
}
|
||||
|
||||
ret = msg_transfer_send_end(handler.value);
|
||||
}
|
||||
|
||||
}
|
||||
/*********************************************************************************/
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
void test_speed_recv_msg_pcie()
|
||||
{
|
||||
uint16_t cu_flag = C_PLANE;
|
||||
HandleId_t handler;
|
||||
handler.port_id = 0;
|
||||
handler.inst_id = 0;
|
||||
handler.type_id = CU_SPLIT;
|
||||
|
||||
uint8_t port_id = 0;
|
||||
uint32_t offset = 0;
|
||||
uint32_t len = 0;
|
||||
uint8_t* msg_ptr;
|
||||
uint32_t i = 0;
|
||||
|
||||
/****************************test code************************************************/
|
||||
#ifdef PCIE_WITH_JESD
|
||||
for (i = (MAX_INSTANCE_NUM / 2); i < MAX_INSTANCE_NUM; i++)
|
||||
#else
|
||||
for (i = 0; i < MAX_INSTANCE_NUM; i++)
|
||||
#endif
|
||||
{
|
||||
handler.port_id = port_id;
|
||||
handler.inst_id = i;
|
||||
handler.type_id = CU_SPLIT;
|
||||
cu_flag = C_PLANE;
|
||||
msg_transfer_receive(handler.value, cu_flag, offset, len, &msg_ptr);
|
||||
|
||||
cu_flag = U_PLANE;
|
||||
msg_transfer_receive(handler.value, cu_flag, offset, len, &msg_ptr);
|
||||
|
||||
handler.type_id = OAM;
|
||||
msg_transfer_receive(handler.value, cu_flag, offset, len, &msg_ptr);
|
||||
}
|
||||
/*********************************************************************************/
|
||||
}
|
||||
|
||||
|
||||
void pcie_test_task_func(void)
|
||||
{
|
||||
//uint32_t clockTick = 0;
|
||||
// uint32_t clockOffset = 0;
|
||||
test_case_sendmsg_pcie();
|
||||
test_speed_recv_msg_pcie();
|
||||
//delay_us(50);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user