jinhong/YB_Platform
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'dev_ck_v2.1_feature_UCP4008SL#1024' into 'dev_ck_v2.1'

Browse Source 
UCP4008_SL#1024# new feature;

See merge request ucp/driver/ucp4008_platform_spu!38
This commit is contained in:
Xianfeng Du 2023-09-27 11:40:05 +00:00
commit 273a7d8caf
53 changed files with 2706786 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
inc/drv_rfm.h
View File

@ -9,6 +9,15 @@
/**************************************************/
/* 前传接口驱动初始化相关 */
/**************************************************/
// 前传接口类型
typedef enum _tagProtocolID
{
PROTOCOL_NULL = 0,
PROTOCOL_CPRI = 1,
PROTOCOL_ECPRI,
PROTOCOL_JESD
}numProtoID;
// cpri option模式，决定接口速率
typedef enum _tagCpriOptionID
@ -33,36 +42,21 @@ typedef enum _tagEcpriOptionID
ECPRI_OPTION_10G = 10,
ECPRI_OPTION_25G = 25
}EcpriOptID;
/*
函数名称：cpri_init
函数入参：
uint32_t option : CPRI_OPTION_7 : option7
CPRI_OPTION_8 : option8
CPRI_OPTION_9 : option9
CPRI_OPTION_10: option10
uint32_t MappingMode : NR4T4R_7DS2U : 122.88M采样率，NR模式，4T4R
NR4T4R_LTE2T2R_FDD : 122.88+30.72M采样，1NR_4T4R+1LTE_2T2R
NR2_4T4R_7DS2U : 2
函数功能：cpri驱动初始化
*/
void cpri_init(uint32_t option,uint32_t MappingMode);
/*
函数名称：jesd_init
函数入参：无
函数功能：jesd驱动初始化
*/
void jesd_init();
/*
函数名称：ecpri_init
函数入参：uint32_t nOption : ECPRI_OPTION_10G : 10g速率模式,
ECPRI_OPTION_25G : 25g速率模式
函数功能：ecpri驱动初始化
*/
void ecpri_init(uint8_t nOption);
typedef struct _tagFrontHaulDrvPara
{
uint32_t protocolSel; // numProtoID
uint32_t rateOption; // CpriOptID/EcpriOptID
uint32_t mapOption; // CpriMapType
}stForntHaulDrvPara;
/*
函数名称：fronthaul_drv_cfg
函数入参：stForntHaulDrvPara* pFhDrvPara ：前传接口配置参数
函数功能：前传接口驱动配置
*/
int32_t fronthaul_drv_cfg(stForntHaulDrvPara* pFhDrvPara);
/*
函数名称：delay_us
函数入参：num：微秒

2
public/ape_spu/driver/src/ape_mtimer.s.c
View File

@ -202,7 +202,7 @@ void ape_slot_ctw_set(uint8_t nTmrId)
stc_timer_set_next_ctw(1);
stc_timer_ctwint_enable();
}
// debug_write(((DBG_DDR_IDX_DRV_BASE+13312) + (gSfnPara.txSlotIntCnt&0x1FF) + (apeId << 9)), GET_STC_CNT()); // 0xd000 // 设置完下一个stc点
debug_write(((DBG_DDR_IDX_DRV_BASE+15360) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x1FF) + (apeId << 9)), GET_STC_CNT()); // 0xd000 // 设置完下一个stc点
//osp_timer_call_task();
osp_timer_call_task_spe(gStcTimerPara.curSlotNum, 0); /* 定时点任务从首位开始 */

7
public/ape_spu/driver/src/ape_stc_timer.s.c
View File

@ -9,8 +9,7 @@
#include "smartos.h"
extern void osp_timer_call_task();
extern void osp_timer_call_task_spe(uint8_t u8slot, uint8_t u8taskidx); /* ?¡§¨º¡À¦Ì?¨¨???¡ä¨®¨º¡Á???a¨º? */
extern void osp_timer_call_task_spe(uint8_t u8slot, uint8_t u8taskidx);
stStcTimerPara gStcTimerPara;
extern stPhyScsPara* phyPara;
extern uint32_t gScsId;
@ -210,8 +209,8 @@ void isr_stc_timer_int()
#endif
stc_timer_ctwint_disable();
}
// debug_write(((DBG_DDR_IDX_DRV_BASE+10240) + ((gStcTimerPara.ctwIntCnt)&0x1FF) + (apeId<<9)), get_tx_nr_slot(1)); // 0xa000
//debug_write(((DBG_DDR_IDX_DRV_BASE+11264) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(&LTBG_TIME_BASE)); // 0xb000
//debug_write(((DBG_DDR_IDX_DRV_BASE+10240) + ((gStcTimerPara.ctwIntCnt)&0x1FF) + (apeId<<9)), get_tx_nr_slot(1)); // 0xa000
debug_write(((DBG_DDR_IDX_DRV_BASE+11264) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(&LTBG_TIME_BASE)); // 0xb000
osp_timer_call_task_spe(gStcTimerPara.curSlotNum, pointIdx);
//debug_write(((DBG_DDR_IDX_DRV_BASE+12288) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(&LTBG_TIME_BASE)); // 0xc000

11
public/common/driver/inc/phy_para.h
View File

@ -7,7 +7,7 @@
#define SFN_PERIOD 10000 // 10ms
#define SLOT_SYMBOL_NUM 14
#define SPU_DRV_SM_ADDR (0x0A4D7000)
#define SPU_DRV_SM_ADDR (0x0A4D7000) // (0x0A4F2000)
#define PROTO_SEL_ADDR (SPU_DRV_SM_ADDR+0x0)
#define PROTO_OPT_ADDR (SPU_DRV_SM_ADDR+0x4)
@ -142,7 +142,7 @@ typedef enum _tagEcpriOptionID
ECPRI_OPTION_10G = 10,
ECPRI_OPTION_25G = 25
}EcpriOptID;
typedef enum _tagScsID
{
LTE_SCS_ID = 0,
@ -187,6 +187,13 @@ typedef struct _tagPhyScsPara
// UINT64 rxSlotStcCnt;
// UINT64 txSlotStcCnt;
}stPhyScsPara;
typedef struct _tagFrontHaulDrvPara
{
uint32_t protocolSel; // numProtoID
uint32_t rateOption; // CpriOptID/EcpriOptID
uint32_t mapOption; // CpriMapType
}stForntHaulDrvPara;
typedef struct phy_timer_config_ind_t
{

1
public/common/driver/src/phy_para.s.c
View File

@ -46,6 +46,7 @@ void phy_para_init(int32_t protocol, int32_t option)
{
phy_scs_para_init(i);
}
__ucps2_synch(0);
}
void phy_scs_para_init(int32_t scsId)

3
public/ecs_rfm_spu1/driver/inc/rfm1_drv.h
View File

@ -9,5 +9,8 @@ void check_phy_cell(void);
void check_10ms_offset(void);
int32_t fronthaul_drv_cfg(stForntHaulDrvPara* pFhDrvPara);
#endif

10
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -365,9 +365,15 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
{
if (TDD_MODE == gJesdTFMode)
{
#if 1
set_jesd_rf_state(JESD_RF_RX, GPIO_OFF); // RxOff();
delay_us(5);
ucp_nop(100000);
set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
#else
set_jesd_rf_state(JESD_RF_TX, GPIO_OFF);
ucp_nop(100000);
set_jesd_rf_state(JESD_RF_RX, GPIO_ON);
#endif
}
else if (FDD_MODE == gJesdTFMode)
{
@ -993,7 +999,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
{
// uint32_t startTick = GET_STC_CNT();
jesd_csu_start();
if (FDD_MODE == gJesdTFMode)
if ((FDD_MODE == gJesdTFMode) || (JESD_IO_CTRL == gJesdIOMode))
{
jesd_csu_rx_start();
}

28
public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c
View File

@ -19,6 +19,10 @@
#include "stc_timer.h"
#include "cpri_timer.h"
#include "cpri_delay.h"
#include "hw_cpri.h"
#include "ecpri_driver.h"
#include "jesd_timer.h"
#ifdef TEST_ENABLE
#include "fh_test.h"
@ -161,3 +165,27 @@ void check_10ms_offset(void)
}
}
int32_t fronthaul_drv_cfg(stForntHaulDrvPara* pFhDrvPara)
{
if (PROTOCOL_CPRI == pFhDrvPara->protocolSel)
{
cpri_init(pFhDrvPara->rateOption, pFhDrvPara->mapOption);
}
else if (PROTOCOL_ECPRI == pFhDrvPara->protocolSel)
{
ecpri_init(pFhDrvPara->rateOption);
}
else if (PROTOCOL_JESD == pFhDrvPara->protocolSel)
{
jesd_init();
}
else
{
return -1;
}
return 0;
}

21
public/ecs_rfm_spu1/top/src/phy_init.s.c
View File

@ -16,9 +16,8 @@
#include "mtimer_cell.h"
#include "ucp_utility.h"
#include "app_interface.h"
#include "hw_cpri.h"
#include "ecpri_driver.h"
#include "jesd_timer.h"
#include "phy_para.h"
#include "rfm1_drv.h"
#define CELL_SETUP_TYPE_SIMULATION (0x5a6b7c8d)
@ -30,16 +29,24 @@ uint8_t gu8_send_del_task_cnt = 0;
int32_t phy_fh_drv_init()
{
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
#ifdef DISTRIBUTED_BS
cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
fhDrvPara.protocolSel = PROTOCOL_CPRI;
fhDrvPara.rateOption = CPRI_OPTION_8;
fhDrvPara.mapOption = OTIC_MAP_FIGURE12;
#endif
#ifdef ECPRI_DISTRIBUTED_BS
ecpri_init(ECPRI_OPTION_10G);
fhDrvPara.protocolSel = PROTOCOL_ECPRI;
fhDrvPara.rateOption = ECPRI_OPTION_10G;
#endif
#ifdef INTEGRATED_BS
jesd_init();
fhDrvPara.protocolSel = PROTOCOL_JESD;
#endif
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
@ -249,7 +256,7 @@ void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
uint32_t cell_id = do_read(msg_buf+20); // 0; //
uint32_t run_core = do_read(msg_buf+24);
memcpy_ucp(0x60000000, msg_buf, 32); // temp code
// memcpy_ucp(0x60000000, msg_buf, 32); // temp code
if (1 < msg_new_del)
{

4
public/test/testbench/fronthaul/inc/jesd_test.h
View File

@ -15,7 +15,7 @@
#ifndef __UCP_JESD_TESTCASE_H__
#define __UCP_JESD_TESTCASE_H__
#if 0
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x60F00000 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x60FF0400 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0x61380000 // SM5
@ -24,7 +24,7 @@
#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);

19
public/test/testcases/case14/fronthaul/src/ecs_rfm_spu1_test.s.c
View File

@ -15,7 +15,7 @@
#include "typedef.h"
#include "ucp_printf.h"
#include "phy_para.h"
#include "rfm1_drv.h"
/************************************************************************/
extern void cpri_init(uint32_t option,uint32_t MappingMode);
@ -29,15 +29,14 @@ int32_t fh_data_init(void)
int32_t fh_drv_init()
{
#ifdef DISTRIBUTED_BS
cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
#endif
#ifdef ECPRI_DISTRIBUTED_BS
ecpri_init(ECPRI_OPTION_10G);
#endif
#ifdef INTEGRATED_BS
jesd_init();
#endif
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_CPRI;
fhDrvPara.rateOption = CPRI_OPTION_8;
fhDrvPara.mapOption = OTIC_MAP_FIGURE12;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}

18
public/test/testcases/case20/fronthaul/src/ecs_rfm_spu1_test.s.c
View File

@ -15,6 +15,7 @@
#include "typedef.h"
#include "ucp_printf.h"
#include "phy_para.h"
#include "rfm1_drv.h"
/************************************************************************/
@ -29,15 +30,14 @@ int32_t fh_data_init(void)
int32_t fh_drv_init()
{
#ifdef DISTRIBUTED_BS
cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
#endif
#ifdef ECPRI_DISTRIBUTED_BS
ecpri_init(ECPRI_OPTION_10G);
#endif
#ifdef INTEGRATED_BS
jesd_init();
#endif
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_CPRI;
fhDrvPara.rateOption = CPRI_OPTION_8;
fhDrvPara.mapOption = OTIC_MAP_FIGURE12;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}

16
public/test/testcases/case21/fronthaul/src/fh_test_case21.s.c
View File

@ -15,7 +15,7 @@
#include "typedef.h"
#include "ucp_printf.h"
#include "phy_para.h"
#include "rfm1_drv.h"
/************************************************************************/
extern void cpri_init(uint32_t option,uint32_t MappingMode);
@ -29,16 +29,24 @@ int32_t fh_data_init(void)
int32_t fh_drv_init()
{
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
#ifdef DISTRIBUTED_BS
cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
fhDrvPara.protocolSel = PROTOCOL_CPRI;
fhDrvPara.rateOption = CPRI_OPTION_8;
fhDrvPara.mapOption = OTIC_MAP_FIGURE12;
#endif
#ifdef ECPRI_DISTRIBUTED_BS
ecpri_init(ECPRI_OPTION_10G);
fhDrvPara.protocolSel = PROTOCOL_ECPRI;
fhDrvPara.rateOption = ECPRI_OPTION_10G;
#endif
#ifdef INTEGRATED_BS
jesd_init();
fhDrvPara.protocolSel = PROTOCOL_JESD;
#endif
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}

10
public/test/testcases/case34/fronthaul/src/cpri_test_case34.s.c
View File

@ -24,6 +24,7 @@
#include "cpri_driver.h"
#include "phy_para.h"
#include "hw_cpri.h"
#include "rfm1_drv.h"
//#include "spu_hw_queue.h"
//#include "spu_log.h"
//#include "ecs_rfm_spu1_heap.h"
@ -62,7 +63,14 @@ int32_t fh_data_init(void)
int32_t fh_drv_init(void)
{
cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_CPRI;
fhDrvPara.rateOption = CPRI_OPTION_8;
fhDrvPara.mapOption = OTIC_MAP_FIGURE12;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}

45
public/test/testcases/case40/fronthaul/inc/jesd_test_case40.h Normal file
View File

@ -0,0 +1,45 @@
#ifndef _JESD_TEST_CASE43_H_
#define _JESD_TEST_CASE43_H_
#if 0
#define JESD_CASE43_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE43_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE43_RX_SLOTD_DATA_LEN 0xF0000
#define JESD_CASE43_TDD_DATA_LEN 0x960000
#define JESD_CASE43_RX1_DUMMY_DATA_ADDR 0xB4BA4800
#define JESD_CASE43_RX1_SLOTS_DATA_ADDR ((JESD_CASE43_RX1_DUMMY_DATA_ADDR)+(JESD_CASE43_RX_DUMMY_DATA_LEN))
#define JESD_CASE43_RX1_SLOT8_DATA_ADDR ((JESD_CASE43_RX1_SLOTS_DATA_ADDR)+(JESD_CASE43_RX_SLOTS_DATA_LEN))
#define JESD_CASE43_RX1_SLOT9_DATA_ADDR ((JESD_CASE43_RX1_SLOT8_DATA_ADDR)+(JESD_CASE43_RX_SLOTD_DATA_LEN))
#define JESD_CASE43_RX2_DUMMY_DATA_ADDR 0xB5504800
#define JESD_CASE43_RX2_SLOTS_DATA_ADDR ((JESD_CASE43_RX2_DUMMY_DATA_ADDR)+(JESD_CASE43_RX_DUMMY_DATA_LEN))
#define JESD_CASE43_RX2_SLOT8_DATA_ADDR ((JESD_CASE43_RX2_SLOTS_DATA_ADDR)+(JESD_CASE43_RX_SLOTS_DATA_LEN))
#define JESD_CASE43_RX2_SLOT9_DATA_ADDR ((JESD_CASE43_RX2_SLOT8_DATA_ADDR)+(JESD_CASE43_RX_SLOTD_DATA_LEN))
#define JESD_CASE43_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define JESD_CASE43_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define JESD_CASE43_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define JESD_CASE43_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define JESD_CASE43_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define JESD_CASE43_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE43_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE43_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case40/fronthaul/note.txt Normal file
View File

@ -0,0 +1 @@
常发单音，10个时隙都发一样的单音

148
public/test/testcases/case40/fronthaul/src/jesd_test_case40.s.c Normal file
View File

@ -0,0 +1,148 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case43.c
// Author : xinxin.li
// Created On : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case40.h"
#include "rfm1_drv.h"
extern uint32_t antDataPre7[123008];
extern uint32_t antDataPost7[122752];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_IO_CTRL;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x300
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
if (JESD_CSU_CTRL == gJesdIOMode)
{
jesd_csu_init_nr_7ds2u();
}
else if (JESD_IO_CTRL == gJesdIOMode)
{
jesd_csu_init_nr_7ds2u_iomode();
}
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
jesd_csu_start_nr_7ds2u();
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = 4;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
// uint32_t slotSamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*13;
uint32_t f7SamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6;
uint32_t b7SamCnt = SHORTCP_SAM_CNT*7;
uint32_t cpyCnt = 0;
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
}
memset((void*)JESD_NR7DS2U_RX_SLOTS_DATA_ADDR, 0, 4*8*SHORTCP_SAM_CNT*samByteCnt);
memset((void*)JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
memset((void*)JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
}

122758
public/test/testcases/case40/fronthaul/src/jesd_test_case40_antdata_post7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

123014
public/test/testcases/case40/fronthaul/src/jesd_test_case40_antdata_pre7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
public/test/testcases/case40/osp/src/ape_test_case40.s.c Normal file
View File

@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

45
public/test/testcases/case43/fronthaul/inc/jesd_test_case43.h Normal file
View File

@ -0,0 +1,45 @@
#ifndef _JESD_TEST_CASE43_H_
#define _JESD_TEST_CASE43_H_
#if 0
#define JESD_CASE43_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE43_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE43_RX_SLOTD_DATA_LEN 0xF0000
#define JESD_CASE43_TDD_DATA_LEN 0x960000
#define JESD_CASE43_RX1_DUMMY_DATA_ADDR 0xB4BA4800
#define JESD_CASE43_RX1_SLOTS_DATA_ADDR ((JESD_CASE43_RX1_DUMMY_DATA_ADDR)+(JESD_CASE43_RX_DUMMY_DATA_LEN))
#define JESD_CASE43_RX1_SLOT8_DATA_ADDR ((JESD_CASE43_RX1_SLOTS_DATA_ADDR)+(JESD_CASE43_RX_SLOTS_DATA_LEN))
#define JESD_CASE43_RX1_SLOT9_DATA_ADDR ((JESD_CASE43_RX1_SLOT8_DATA_ADDR)+(JESD_CASE43_RX_SLOTD_DATA_LEN))
#define JESD_CASE43_RX2_DUMMY_DATA_ADDR 0xB5504800
#define JESD_CASE43_RX2_SLOTS_DATA_ADDR ((JESD_CASE43_RX2_DUMMY_DATA_ADDR)+(JESD_CASE43_RX_DUMMY_DATA_LEN))
#define JESD_CASE43_RX2_SLOT8_DATA_ADDR ((JESD_CASE43_RX2_SLOTS_DATA_ADDR)+(JESD_CASE43_RX_SLOTS_DATA_LEN))
#define JESD_CASE43_RX2_SLOT9_DATA_ADDR ((JESD_CASE43_RX2_SLOT8_DATA_ADDR)+(JESD_CASE43_RX_SLOTD_DATA_LEN))
#define JESD_CASE43_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define JESD_CASE43_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define JESD_CASE43_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define JESD_CASE43_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define JESD_CASE43_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define JESD_CASE43_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE43_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE43_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case43/fronthaul/note.txt Normal file
View File

@ -0,0 +1 @@
7ds2u, 带收发切换，发单音，单音右偏中心频点20M

252
public/test/testcases/case43/fronthaul/src/jesd_test_case43.s.c Normal file
View File

@ -0,0 +1,252 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case43.c
// Author : xinxin.li
// Created On : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case43.h"
#include "rfm1_drv.h"
extern uint32_t antDataPre7[123008];
extern uint32_t antDataPost7[122752];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
#if 0
uint32_t srcImData[4*1024] = {0}; // 16KB
uint32_t srcImData[8*1024] = {0}; // 32KB
void jesd_tx_data_init()
{
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint8_t idSymbol = 0;
uint16_t idSample = 0;
uint32_t* pSrcAddr = NULL;
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t symbolSamCnt = 0;
uint16_t f7SamCnt = LONGCP_SAM_CNT + SHORTCP_SAM_CNT*6;
uint16_t b7SamCnt = SHORTCP_SAM_CNT*7;
// IQ data
// valid data
for (idAnt = 0; idAnt < JESD_NR7DS2U_ANT_NUM; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
pSrcAddr = srcImData;
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR;
dataLen = f7SamCnt<<2;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR;
dataLen = b7SamCnt<<2;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
dataLen = f7SamCnt<<2;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR;
dataLen = b7SamCnt<<2;
}
for (idSymbol = 0; idSymbol < 7; idSymbol++) // symbol
{
if ((0 == idSymbol) && (0 == idSymbolBlock))
{
symbolSamCnt = LONGCP_SAM_CNT;
}
else
{
symbolSamCnt = SHORTCP_SAM_CNT;
}
for (idSample = 0; idSample < symbolSamCnt; idSample++)
{
*pSrcAddr = (idAnt<<24) | (idSlot<<20) | ((idSymbol+idSymbolBlock*7)<<16) | (idSample);
pSrcAddr++;
}
}
memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
}
}
}
// dummy data
// IQ data
uint32_t tag = 0;
for (idAnt = 0; idAnt < JESD_NR7DS2U_ANT_NUM; idAnt++)
{
// S slot, symbol6, odd slot
srcAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (idAnt*(f7SamCnt<<2)) + ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*5)<<2);
dstAddr = JESD_NR7DS2U_TX_DUMMY_AXC1DATA_ADDR + idAnt*JESD_NR7DS2U_TX_DUMMY_AXCDATA_LEN;
dataLen = (SHORTCP_SAM_CNT)<<2;
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
// S slot, symbol7~13
srcAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (idAnt*(b7SamCnt<<2));
dstAddr += dataLen;
dataLen = b7SamCnt<<2;
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
// slot8, even slot, symbol0~6
srcAddr = JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + (idAnt*(f7SamCnt<<2));
dstAddr += dataLen;
dataLen = f7SamCnt<<2;
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
// slot8, even slot, symbol7~13
srcAddr = JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + (idAnt*(b7SamCnt<<2));
dstAddr += dataLen;
dataLen = b7SamCnt<<2;
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
// slot9, odd slot, symbol0~6
srcAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (idAnt*(f7SamCnt<<2));
dstAddr += dataLen;
dataLen = f7SamCnt<<2;
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
// slot9, odd slot, symbol7~13
srcAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (idAnt*(b7SamCnt<<2));
dstAddr += dataLen;
dataLen = b7SamCnt<<2;
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
}
}
#endif
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
if (JESD_CSU_CTRL == gJesdIOMode)
{
jesd_csu_init_nr_7ds2u();
}
else if (JESD_IO_CTRL == gJesdIOMode)
{
jesd_csu_init_nr_7ds2u_iomode();
}
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
jesd_csu_start_nr_7ds2u();
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = 4;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
// uint32_t slotSamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*13;
uint32_t f7SamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6;
uint32_t b7SamCnt = SHORTCP_SAM_CNT*7;
uint32_t cpyCnt = 0;
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
}
memset((void*)JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
memset((void*)JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
}

122758
public/test/testcases/case43/fronthaul/src/jesd_test_case43_antdata_post7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

123014
public/test/testcases/case43/fronthaul/src/jesd_test_case43_antdata_pre7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
public/test/testcases/case43/osp/src/ape_test_case43.s.c Normal file
View File

@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

4
public/test/testcases/case44/fronthaul/inc/jesd_test_case44.h
View File

@ -1,7 +1,7 @@
#ifndef _JESD_TEST_CASE44_H_
#define _JESD_TEST_CASE44_H_
#if 0
#define JESD_CASE44_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE44_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE44_RX_SLOTD_DATA_LEN 0xF0000
@ -28,7 +28,7 @@
#define JESD_CASE44_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE44_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE44_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);

12
public/test/testcases/case44/fronthaul/src/jesd_test_case44.s.c
View File

@ -21,6 +21,7 @@
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case44.h"
#include "rfm1_drv.h"
extern uint32_t antDataPre7[123008];
extern uint32_t antDataPost7[122752];
@ -43,7 +44,12 @@ int32_t fh_data_init(void)
int32_t fh_drv_init(void)
{
jesd_init();
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
@ -59,8 +65,8 @@ int32_t fh_csu_test_init(void)
jesd_csu_init_nr_7ds2u_iomode();
}
jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}

45
public/test/testcases/case47/fronthaul/inc/jesd_test_case47.h Normal file
View File

@ -0,0 +1,45 @@
#ifndef _JESD_TEST_CASE47_H_
#define _JESD_TEST_CASE47_H_
#if 0
#define JESD_CASE41_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE41_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE41_RX_SLOTD_DATA_LEN 0xF0000
#define JESD_CASE41_TDD_DATA_LEN 0x960000
#define JESD_CASE41_RX1_DUMMY_DATA_ADDR 0xB4BA4800
#define JESD_CASE41_RX1_SLOTS_DATA_ADDR ((JESD_CASE41_RX1_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
#define JESD_CASE41_RX1_SLOT8_DATA_ADDR ((JESD_CASE41_RX1_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
#define JESD_CASE41_RX1_SLOT9_DATA_ADDR ((JESD_CASE41_RX1_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
#define JESD_CASE41_RX2_DUMMY_DATA_ADDR 0xB5504800
#define JESD_CASE41_RX2_SLOTS_DATA_ADDR ((JESD_CASE41_RX2_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
#define JESD_CASE41_RX2_SLOT8_DATA_ADDR ((JESD_CASE41_RX2_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
#define JESD_CASE41_RX2_SLOT9_DATA_ADDR ((JESD_CASE41_RX2_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
#define JESD_CASE41_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define JESD_CASE41_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define JESD_CASE41_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define JESD_CASE41_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define JESD_CASE41_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define JESD_CASE41_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE41_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE41_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case47/fronthaul/note.txt Normal file
View File

@ -0,0 +1 @@
LTE FDD，发单音

118
public/test/testcases/case47/fronthaul/src/jesd_test_case47.s.c Normal file
View File

@ -0,0 +1,118 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case44.c
// Author : xinxin.li
// Created On : 2023-03-22s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_lte_fdd.h"
#include "jesd_test.h"
#include "jesd_test_case47.h"
#include "rfm1_drv.h"
extern uint32_t antDataLte[122880];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
extern uint32_t gJesdTFMode;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
jesd_csu_init_lte_fdd();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
//jesd_csu_start_nr_7ds2u();
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = 2;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
uint32_t slotSamCnt = JESD_LTEFDD_SUBFRAME_SAM_CNT;
uint32_t cpyCnt = 0;
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
if (0 == idSlot) // even slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataLte[0]) + idAnt*slotSamCnt;
dstAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
}
else if (1 == idSlot) // odd slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataLte[0]) + idAnt*slotSamCnt;
dstAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
memset((void*)JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset((void*)JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
}

245773
public/test/testcases/case47/fronthaul/src/jesd_test_case47_antdata.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
public/test/testcases/case47/osp/src/ape_test_case47.s.c Normal file
View File

@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

17
public/test/testcases/case48/fronthaul/inc/jesd_test_case48.h Normal file
View File

@ -0,0 +1,17 @@
#ifndef _JESD_TEST_CASE48_H_
#define _JESD_TEST_CASE48_H_
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case48/fronthaul/note.txt Normal file
View File

@ -0,0 +1 @@
7ds2u, 带收发切换，发256QAM, 245.76M 采样率

138
public/test/testcases/case48/fronthaul/src/jesd_test_case48.s.c Normal file
View File

@ -0,0 +1,138 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case43.c
// Author : xinxin.li
// Created On : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case48.h"
#include "rfm1_drv.h"
extern uint32_t antDataPre7[246016];
extern uint32_t antDataPost7[245504];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
jesd_csu_init_nr_7ds2u_4t4r_98();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
jesd_csu_start_nr_7ds2u();
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = 4;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
// uint32_t slotSamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*13;
uint32_t f7SamCnt = (LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6)*2;
uint32_t b7SamCnt = (SHORTCP_SAM_CNT*7)*2;
uint32_t cpyCnt = 0;
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
}
//memset((void*)JESD_NR7DS2U_RX_SLOTS_DATA_ADDR, 0, 4*8*SHORTCP_SAM_CNT*samByteCnt);
memset((void*)JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
memset((void*)JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
}

245510
public/test/testcases/case48/fronthaul/src/jesd_test_case48_antdata_post7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

246022
public/test/testcases/case48/fronthaul/src/jesd_test_case48_antdata_pre7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
public/test/testcases/case48/osp/src/ape_test_case48.s.c Normal file
View File

@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

8
public/test/testcases/case49/fronthaul/data/data_read.asv Normal file
View File

@ -0,0 +1,8 @@
fd_in = fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant_all.dat', 'r');
data_in = fscanf(fd_in, '%x');
fclose(fd_in);
size_datain = size(data_in);
ant0_data = data_in(1:(size_datain(1)/4));
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0.dat', 'w+');

24
public/test/testcases/case49/fronthaul/data/data_read.m Normal file
View File

@ -0,0 +1,24 @@
fd_in = fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant_all.dat', 'r');
data_in = fscanf(fd_in, '%x', Inf);
fclose(fd_in);
size_datain = size(data_in);
ant0_data = data_in(1:(size_datain(1)/4));
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0.dat', 'w+');
for i=1:1:(size_datain(1)/4)
fprintf(fd_out, '0x%08x\n', ant0_data(i));
end
fclose(fd_out);
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0_preSymbol.dat', 'w+');
for i=1:1:61504
fprintf(fd_out, '0x%08x\n', ant0_data(i));
end
fclose(fd_out);
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0_postSymbol.dat', 'w+');
for i=1:1:61376
fprintf(fd_out, '0x%08x\n', ant0_data(61504+i));
end
fclose(fd_out);

122880
public/test/testcases/case49/fronthaul/data/dl_ant0.dat Normal file
View File

File diff suppressed because it is too large Load Diff

61376
public/test/testcases/case49/fronthaul/data/dl_ant0_postSymbol.dat Normal file
View File

File diff suppressed because it is too large Load Diff

61504
public/test/testcases/case49/fronthaul/data/dl_ant0_preSymbol.dat Normal file
View File

File diff suppressed because it is too large Load Diff

491520
public/test/testcases/case49/fronthaul/data/dl_ant_all.dat Normal file
View File

File diff suppressed because it is too large Load Diff

245760
public/test/testcases/case49/fronthaul/data/dl_cpri_all.dat Normal file
View File

File diff suppressed because it is too large Load Diff

1920
public/test/testcases/case49/fronthaul/data/dl_cpri_comp.dat Normal file
View File

File diff suppressed because it is too large Load Diff

17
public/test/testcases/case49/fronthaul/inc/jesd_test_case49.h Normal file
View File

@ -0,0 +1,17 @@
#ifndef _JESD_TEST_CASE49_H_
#define _JESD_TEST_CASE49_H_
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

2
public/test/testcases/case49/fronthaul/note.txt Normal file
View File

@ -0,0 +1,2 @@
7ds2u, 带收发切换，发单音, 245.76M 采样率
双单音，左偏中心频点20MHz，右偏中心频点10MHz

138
public/test/testcases/case49/fronthaul/src/jesd_test_case49.s.c Normal file
View File

@ -0,0 +1,138 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case43.c
// Author : xinxin.li
// Created On : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case49.h"
#include "rfm1_drv.h"
extern uint32_t antDataPre7[246016];
extern uint32_t antDataPost7[245504];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stForntHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stForntHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
jesd_csu_init_nr_7ds2u_4t4r_98();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
jesd_csu_start_nr_7ds2u();
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = 4;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
// uint32_t slotSamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*13;
uint32_t f7SamCnt = (LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6)*2;
uint32_t b7SamCnt = (SHORTCP_SAM_CNT*7)*2;
uint32_t cpyCnt = 0;
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
}
//memset((void*)JESD_NR7DS2U_RX_SLOTS_DATA_ADDR, 0, 4*8*SHORTCP_SAM_CNT*samByteCnt);
memset((void*)JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
memset((void*)JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
}

245510
public/test/testcases/case49/fronthaul/src/jesd_test_case49_antdata_post7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

246023
public/test/testcases/case49/fronthaul/src/jesd_test_case49_antdata_pre7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

60
public/test/testcases/case49/osp/src/ape_test_case49.s.c Normal file
View File

@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}