From f87b9c5f369ff8f7a5387fbee2c0a99ba07f3397 Mon Sep 17 00:00:00 2001
From: "xinxin.li" <xinxin.li@263.com>
Date: Sun, 28 Apr 2024 13:50:24 +0800
Subject: [PATCH] 1. fix UCP4008-SL-EVB feature enhancement#1740; 2. modify rx
 slot cycle interface.

---
 public/ape_spu/driver/inc/ape_mtimer.h        |  1 +
 public/ape_spu/driver/src/ape_mtimer.s.c      | 35 +++++++++++++++++--
 .../case21/osp/src/case21_ape0_task.s.c       | 18 ++++++++++
 3 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/public/ape_spu/driver/inc/ape_mtimer.h b/public/ape_spu/driver/inc/ape_mtimer.h
index a958314..ea6818d 100644
--- a/public/ape_spu/driver/inc/ape_mtimer.h
+++ b/public/ape_spu/driver/inc/ape_mtimer.h
@@ -27,6 +27,7 @@ int32_t get_rx_lte_subframe();
 
 int32_t get_tx_nr_slot_cycle();
 int32_t get_tx_lte_subframe_cycle();
+int32_t get_rx_slot_cycle();
 int32_t get_rx_nr_slot_cycle();
 int32_t get_rx_lte_subframe_cycle();
 
diff --git a/public/ape_spu/driver/src/ape_mtimer.s.c b/public/ape_spu/driver/src/ape_mtimer.s.c
index 79bfbc7..0ed5af0 100644
--- a/public/ape_spu/driver/src/ape_mtimer.s.c
+++ b/public/ape_spu/driver/src/ape_mtimer.s.c
@@ -446,7 +446,7 @@ int32_t get_rx_lte_sfn()
 int32_t get_rx_nr_slot()
 {
 	int32_t rxSlotNum = 0;
-	int32_t offsetCycle = get_rx_nr_slot_cycle();
+	int32_t offsetCycle = get_rx_slot_cycle();
 	if (-1 != offsetCycle)
 	{
 	    if (0 <= offsetCycle)
@@ -473,7 +473,7 @@ int32_t get_rx_nr_slot()
 int32_t get_rx_lte_subframe()
 {
 	int32_t rxSlotNum = 0;
-	int32_t offsetCycle = get_rx_lte_subframe_cycle();
+	int32_t offsetCycle = get_rx_slot_cycle();
 	if (-1 != offsetCycle)
 	{
 	    if (0 <= offsetCycle)
@@ -525,6 +525,29 @@ int32_t get_tx_lte_subframe_cycle()
 	return offsetCycle;
 }
 
+int32_t get_rx_slot_cycle()
+{
+    int32_t interval = get_tx_rx_interval();
+	if (0 <= interval)
+	{
+		uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
+		__ucps2_synch(0);
+		int32_t offsetCycle = GET_STC_CNT() - txSlotTiming;
+		if (0 > offsetCycle)
+		{
+			uint32_t limitVal = 1000000000;
+			offsetCycle = (offsetCycle+limitVal)%limitVal;
+		}
+		offsetCycle -= interval;
+		
+		return offsetCycle;
+	}
+	else
+	{
+	    return -1;
+	}
+}
+
 int32_t get_rx_nr_slot_cycle()
 {
     int32_t interval = get_tx_rx_interval();
@@ -539,6 +562,10 @@ int32_t get_rx_nr_slot_cycle()
 			offsetCycle = (offsetCycle+limitVal)%limitVal;
 		}
 		offsetCycle -= interval;
+		if (0 > offsetCycle)
+		{
+		    offsetCycle += (gCellSfnPara[gMtimerId].slotPeriod*1000);
+		}
 		
 		return offsetCycle;
 	}
@@ -562,6 +589,10 @@ int32_t get_rx_lte_subframe_cycle()
 			offsetCycle = (offsetCycle+limitVal)%limitVal;
 		}
 		offsetCycle -= interval;
+		if (0 > offsetCycle)
+		{
+		    offsetCycle += (gCellSfnPara[gMtimerId].slotPeriod*1000);
+		}
 		
 		return offsetCycle;
 	}
diff --git a/public/test/testcases/case21/osp/src/case21_ape0_task.s.c b/public/test/testcases/case21/osp/src/case21_ape0_task.s.c
index 5d635e0..bcae207 100644
--- a/public/test/testcases/case21/osp/src/case21_ape0_task.s.c
+++ b/public/test/testcases/case21/osp/src/case21_ape0_task.s.c
@@ -359,6 +359,15 @@ void ape0_timer1_task(void)
     uint32_t ape_id = get_core_id();
     uint32_t clockTick   = 0;
     uint32_t clockOffset = 0;
+
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 72), get_tx_nr_sfn());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 73), get_tx_nr_slot());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 74), get_tx_nr_slot_cycle());
+	
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 76), get_rx_nr_sfn());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 77), get_rx_nr_slot());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 78), get_rx_nr_slot_cycle());
+	
     rdmcycle(&clockTick);
 
     debug_write(DBG_DDR_COMMON_IDX(ape_id, 54), ++g_u32_case21_ape0_timer1_process_cnt);
@@ -398,6 +407,15 @@ void ape0_timer2_task(void)
 	uint32_t txCycleEndTick = 0;
 	uint32_t rxCycleStartTick = 0;
 	uint32_t rxCycleEndTick = 0;
+	
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 80), get_tx_nr_sfn());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 81), get_tx_nr_slot());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 82), get_tx_nr_slot_cycle());
+	
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 84), get_rx_nr_sfn());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 85), get_rx_nr_slot());
+    debug_write(DBG_DDR_COMMON_IDX(ape_id, 86), get_rx_nr_slot_cycle());
+	
     rdmcycle(&clockTick);
 
 	rdmcycle(&txCycleStartTick);