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Merge branch 'dev_ck_v2.1_feature_enhance#1740#' into 'dev_ck_v2.1'

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UCP4008-SL-EVB feature enhancement#1740

See merge request ucp/driver/ucp4008_platform_spu!105
This commit is contained in:
Weihua Li 2024-04-28 06:42:01 +00:00
commit 281042f1ce
3 changed files with 52 additions and 2 deletions
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1
public/ape_spu/driver/inc/ape_mtimer.h
View File

@ -27,6 +27,7 @@ int32_t get_rx_lte_subframe();
int32_t get_tx_nr_slot_cycle();
int32_t get_tx_lte_subframe_cycle();
int32_t get_rx_slot_cycle();
int32_t get_rx_nr_slot_cycle();
int32_t get_rx_lte_subframe_cycle();

35
public/ape_spu/driver/src/ape_mtimer.s.c
View File

@ -446,7 +446,7 @@ int32_t get_rx_lte_sfn()
int32_t get_rx_nr_slot()
{
int32_t rxSlotNum = 0;
int32_t offsetCycle = get_rx_nr_slot_cycle();
int32_t offsetCycle = get_rx_slot_cycle();
if (-1 != offsetCycle)
{
if (0 <= offsetCycle)
@ -473,7 +473,7 @@ int32_t get_rx_nr_slot()
int32_t get_rx_lte_subframe()
{
int32_t rxSlotNum = 0;
int32_t offsetCycle = get_rx_lte_subframe_cycle();
int32_t offsetCycle = get_rx_slot_cycle();
if (-1 != offsetCycle)
{
if (0 <= offsetCycle)
@ -525,6 +525,29 @@ int32_t get_tx_lte_subframe_cycle()
return offsetCycle;
}
int32_t get_rx_slot_cycle()
{
int32_t interval = get_tx_rx_interval();
if (0 <= interval)
{
uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
__ucps2_synch(0);
int32_t offsetCycle = GET_STC_CNT() - txSlotTiming;
if (0 > offsetCycle)
{
uint32_t limitVal = 1000000000;
offsetCycle = (offsetCycle+limitVal)%limitVal;
}
offsetCycle -= interval;
return offsetCycle;
}
else
{
return -1;
}
}
int32_t get_rx_nr_slot_cycle()
{
int32_t interval = get_tx_rx_interval();
@ -539,6 +562,10 @@ int32_t get_rx_nr_slot_cycle()
offsetCycle = (offsetCycle+limitVal)%limitVal;
}
offsetCycle -= interval;
if (0 > offsetCycle)
{
offsetCycle += (gCellSfnPara[gMtimerId].slotPeriod*1000);
}
return offsetCycle;
}
@ -562,6 +589,10 @@ int32_t get_rx_lte_subframe_cycle()
offsetCycle = (offsetCycle+limitVal)%limitVal;
}
offsetCycle -= interval;
if (0 > offsetCycle)
{
offsetCycle += (gCellSfnPara[gMtimerId].slotPeriod*1000);
}
return offsetCycle;
}

18
public/test/testcases/case21/osp/src/case21_ape0_task.s.c
View File

@ -359,6 +359,15 @@ void ape0_timer1_task(void)
uint32_t ape_id = get_core_id();
uint32_t clockTick = 0;
uint32_t clockOffset = 0;
debug_write(DBG_DDR_COMMON_IDX(ape_id, 72), get_tx_nr_sfn());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 73), get_tx_nr_slot());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 74), get_tx_nr_slot_cycle());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 76), get_rx_nr_sfn());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 77), get_rx_nr_slot());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 78), get_rx_nr_slot_cycle());
rdmcycle(&clockTick);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 54), ++g_u32_case21_ape0_timer1_process_cnt);
@ -398,6 +407,15 @@ void ape0_timer2_task(void)
uint32_t txCycleEndTick = 0;
uint32_t rxCycleStartTick = 0;
uint32_t rxCycleEndTick = 0;
debug_write(DBG_DDR_COMMON_IDX(ape_id, 80), get_tx_nr_sfn());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 81), get_tx_nr_slot());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 82), get_tx_nr_slot_cycle());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 84), get_rx_nr_sfn());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 85), get_rx_nr_slot());
debug_write(DBG_DDR_COMMON_IDX(ape_id, 86), get_rx_nr_slot_cycle());
rdmcycle(&clockTick);
rdmcycle(&txCycleStartTick);