2. modify orx csu interrupt;
3. modify case48: 2cell, 160M data source;
4. test case: case21, case34, case44, case45, case48
This commit is contained in:
xinxin.li 2023-11-27 20:31:03 +08:00
parent c02dc790b8
commit 28a4a55b5a
22 changed files with 614702 additions and 1351719 deletions

View File

@ -15,6 +15,7 @@
#define JESD_CH_NUM 2 // rx0/rx1, tx0/tx1
#define JESD_LIST_NUM 2 // double 2.5ms, 2 lists for every ch
// 链表通道定义tx/rx各有两个通道小于等于4天线情况下只会启用通道0
typedef enum _tagJesdCsuCh
{
JESD_CSU_CH0 = 0,
@ -25,8 +26,8 @@ typedef struct _tagJesdCsuPara
{
uint8_t antNum; // 天线数
uint8_t cf;
uint8_t cs; // 控制字, =2
uint8_t n; // iq数据精度, = 12
uint8_t cs; // 控制字, =0
uint8_t n; // iq数据精度, = 16bit
uint8_t m; // 天线数*2
uint8_t nTotal; // n+cs+padding
uint8_t seq;
@ -34,19 +35,51 @@ typedef struct _tagJesdCsuPara
uint8_t reserved;
}stJesdCsuPara;
// 链表节点结构体定义
typedef struct _tagJesdCsuNodePara
{
uint32_t dataAddr;
uint32_t yStep;
uint32_t allNum;
uint32_t dataAddr; // 数据地址
uint32_t yStep; // 每个天线的数据总长度B为单位
uint32_t allNum; // 需要csu搬运的总的数据长度B为单位
}stJesdCsuNodePara;
/*******************************************************************************************************************
jesd_csu_init
uint8_t antNum: 线
uint8_t margin: jesd csu一次搬移的数据量xnum=(32*2^margin)Bmargin值allnum/xnum是个整数值
0 :
-1:
JESD CSU初始化
********************************************************************************************************************/
int32_t jesd_csu_init(uint8_t antNum, uint8_t margin);
/*******************************************************************************************************************
jesd_orx_csu_init
0 :
-1: jesd_csu_init
JESD ORX通道CSU初始化
********************************************************************************************************************/
int32_t jesd_orx_csu_init(void);
/*******************************************************************************************************************
jesd_csu_rx_inlatch_thres_cfg
uint8_t ch: rx通道IDJESD_CSU_CH0: rx0, JESD_CSU_CH1: rx1
uint32_t send_threshold: InLatch的阈值CSU暂停向总线发起写请求
uint32_t almostfull_threshold: InLatch的阈值CSU开始向总线发起写请求
0 :
-1:
JESD CSU初始化
********************************************************************************************************************/
int32_t jesd_csu_rx_inlatch_thres_cfg(uint8_t ch, uint32_t send_threshold, uint32_t almostfull_threshold);
// JESD CSU资源配置可以根据通道ID和list ID查询驱动所采用的tag号从而查询对应的通道任务是否完成
/***********************************************************************************
ch list RegGroup CmdFIFO tagId = RegGroupId
rx0 0/1/2/3 0/4/8/12 0 0/4/8/12
@ -55,11 +88,63 @@ int32_t jesd_csu_rx_inlatch_thres_cfg(uint8_t ch, uint32_t send_threshold, uint3
tx1 0/1/2/3 3/7/11/15 3 3/7/11/15
************************************************************************************/
/*******************************************************************************************************************
jesd_csu_rx_cfg
uint32_t listAddr:
uint32_t nodeNum:
stJesdCsuNodePara* pListNode:
uint8_t nChId: ID, JESD_CSU_CH0: rx0, JESD_CSU_CH1: rx1
uint8_t nListId: ID, 0~1, 22.5ms双小区配置
2.5ms采用list02.5ms采用list1
0 :
-1:
JESD RX通道CSU配置
********************************************************************************************************************/
int32_t jesd_csu_rx_cfg(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNodePara* pListNode, uint8_t nChId, uint8_t nListId);
/*******************************************************************************************************************
jesd_csu_tx_cfg
uint32_t listAddr:
uint32_t nodeNum:
stJesdCsuNodePara* pListNode:
uint8_t nChId: ID, JESD_CSU_CH0: tx0, JESD_CSU_CH1: tx1
uint8_t nListId: ID, 0~1, 22.5ms双小区配置
2.5ms采用list02.5ms采用list1
0 :
-1:
JESD TX通道CSU配置
********************************************************************************************************************/
int32_t jesd_csu_tx_cfg(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNodePara* pListNode, uint8_t nChId, uint8_t nListId);
/*******************************************************************************************************************
jesd_csu_orx_cfg
uint32_t listAddr:
uint32_t nodeNum:
stJesdCsuNodePara* pListNode:
uint8_t nListId: ID
0 :
-1:
JESD ORX通道CSU配置
********************************************************************************************************************/
int32_t jesd_csu_orx_cfg(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNodePara* pListNode, uint8_t nListId);
/*******************************************************************************************************************
jesd_csu_stat_lookup
uint8_t tag: tag号
0 :
1 :
-1:
tag号tag号对应的通道任务是否完成
********************************************************************************************************************/
int32_t jesd_csu_stat_lookup(uint8_t tag);
#endif

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@ -87,5 +87,7 @@ int32_t jesd_csu_tx_start(uint8_t nListId);
int32_t jesd_csu_orx_start(uint8_t nListId);
int32_t jesd_csu_stat_lookup(uint8_t tag);
#endif

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@ -66,7 +66,7 @@
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BE69000 // 0x1E0000 // 0x6c049000
#define JESD_ORX_DATA_ADDR 0x60000000
#define JESD_ORX_DATA_LEN 12288000
#define JESD_ORX_DATA_LEN (24576000*5) // 125ms
int32_t jesd_csu_init_nr_7ds2u();
int32_t jesd_csu_init_nr_7d2u_slot0();

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@ -3,6 +3,8 @@
#include "typedef.h"
#define SNIFFER_TMR_PERIOD 100000 // 100ms
int32_t jesd_orx_mtimer_init(int32_t nTmrId, int32_t nScsId);
int32_t jesd_orx_timer_init(void);

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@ -4,11 +4,31 @@
#include "ucp_csu.h"
#include "ucp_utility.h"
#include "ucp_drv_common.h"
#include "gpio_drv.h"
#include "inter_vector.h"
stJesdCsuPara gJesdCsuPara;
stJesdListPara gJesdTxListPara[JESD_CH_NUM][JESD_LIST_NUM];
stJesdListPara gJesdRxListPara[JESD_CH_NUM][JESD_LIST_NUM];
uint32_t gJesdOrxCsuIntCnt = 0;
void isr_jesd_orx_csu()
{
if (JS_CSU_ALLPENDEVENT1 & BIT14)
{
gJesdOrxCsuIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+122), gJesdOrxCsuIntCnt); // 0x1E8
JS_CSU_TAGMASK2 &= (~BIT2);
JS_CSU_EVENTINTCLEAR = 46;
debug_write((DBG_DDR_IDX_DRV_BASE+50), GET_STC_CNT()); // 0xc8
set_jesd_rf_state(JESD_ANT_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_RF_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_TRANS_ORX, GPIO_OFF);
}
}
int32_t jesd_csu_init(uint8_t antNum, uint8_t margin)
{
if ((0 == antNum) || (8 < antNum))
@ -75,7 +95,7 @@ int32_t jesd_csu_init(uint8_t antNum, uint8_t margin)
do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x80048010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write
do_write((&JS_CSU_EM_BS_SMSEL_PREDATANUM), ((0x3<<14) | (0x5<<5) | 0x8));
}
return 0;
}
@ -91,6 +111,13 @@ int32_t jesd_orx_csu_init(void)
do_write((&JS_CSU_JESDRX1SET), val);
do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x80048010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write
do_write((&JS_CSU_EM_BS_SMSEL_PREDATANUM), ((0x3<<14) | (0x5<<5) | 0x8));
int32_t ret = smart_irq_request(139, isr_jesd_orx_csu);
if (0 != ret)
{
debug_write((DBG_DDR_IDX_DRV_BASE+121), ret);
}
JS_CSU_INTMASK |= BIT14;
return 0;
}
@ -414,6 +441,8 @@ int32_t jesd_csu_orx_start(uint8_t nListId)
{
jesd_csu_rx_start_ch(1, nListId);
do_write(&(JS_CSU_TAGMASK2), BIT2);
return 0;
}

View File

@ -38,13 +38,11 @@ int32_t jesd_orx_mtimer_init(int32_t nTmrId, int32_t nScsId)
int32_t jesd_orx_timer_init(void)
{
jesd_orx_1pps_src_init(JESD_PP1S_SRC_STC);
mtimer_clear_all_event(MTIMER_JESD_RX1_ID);
set_jesd_orx_tmr_period();
//mtimer_clear_all_event(MTIMER_JESD_RX1_ID);
//set_jesd_orx_tmr_period();
set_jesd_orx_1pps_scratch();
set_jesd_orx_tmr_point(25000); // 25ms
//set_jesd_orx_tmr_point(25000); // 25ms
//set_jesd_orx_timer_int();
jesd_orx_pin_ctrl();
return 0;
@ -58,7 +56,7 @@ int32_t set_jesd_orx_tmr_period(void)
// 设置计数器溢出值
uint32_t tempL = pMtimerPara->tmrMsPeriod * pMtimerPara->slotPeriod / 1000;
uint32_t tempM = pMtimerPara->tddSlotNum;
uint32_t tempH = 10;
uint32_t tempH = SNIFFER_TMR_PERIOD / pMtimerPara->slotPeriod / pMtimerPara->tddSlotNum; // 10;
set_mtimer_period(MTIMER_JESD_RX1_ID, tempL, tempM, tempH);
//enable_mtimer_cevent_int(MTIMER_JESD_RX1_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
@ -120,7 +118,7 @@ int32_t set_jesd_orx_timer_int(void)
#endif
int32_t set_jesd_orx_tmr_point(int32_t usPoint)
{
if ((10*SFN_PERIOD) <= usPoint)
if ((SNIFFER_TMR_PERIOD) <= usPoint)
{
return -1;
}
@ -169,11 +167,14 @@ int32_t phy_sniffer_start()
{
//jesd_sniffer_orx_csu_init(); // test
jesd_orx_timer_init();
debug_write((DBG_DDR_IDX_DRV_BASE+64+7), 1); // 0x11c
//debug_write((DBG_DDR_IDX_DRV_BASE+64+7), 1); // 0x11c
}
set_jesd_rf_state(JESD_ANT_ORX, GPIO_ON);
set_jesd_rf_state(JESD_RF_ORX, GPIO_ON);
set_jesd_rf_state(JESD_TRANS_ORX, GPIO_ON);
orx_para_ptr->orx_start_flag = 1;
orx_para_ptr->orx_calldrv_cnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), orx_para_ptr->orx_calldrv_cnt); // 0x118
debug_write((DBG_DDR_IDX_DRV_BASE+64+8), orx_para_ptr->orx_calldrv_cnt); // 0x120
return 0;
}

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@ -368,8 +368,8 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
}
__ucps2_synch(0);
jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
jesd_timer_get_rf_point(nTmrId, my_jesdtmr);
//jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
//jesd_timer_get_rf_point(nTmrId, my_jesdtmr);
while (2 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))) // wait jesd serdes clk init finished
{
@ -424,19 +424,19 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
if ((JESD_CSU_CTRL == gJesdIOMode) && (MTIMER_JESD_RX0_ID == nTmrId))
if (JESD_CSU_CTRL == gJesdIOMode)
{
gCsuRxAdvanceNs = JESD_RX_ADVANCE_NS - do_read_volatile(CSU_RX_TD_SAMPLE);
gCsuTxAdvanceNs = do_read_volatile(CSU_TX_ADVANCE_SAMPLE);
#if 0
set_jesd_csu_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csu_point(MTIMER_JESD_TX0_ID, 0);
#else
jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
jesd_timer_get_rf_point(nTmrId, my_jesdtmr);
set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuoff_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
set_jesd_csuoff_point(MTIMER_JESD_TX0_ID, 0);
#endif
set_jesd_rxon_point(nTmrId, 0);
set_jesd_rxoff_point(nTmrId, 0);
set_jesd_txon_point(nTmrId, 0);
@ -1106,7 +1106,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
cEventFlag = do_read_volatile(cFlagAddr);
tEventFlag = do_read_volatile(tFlagAddr);
__ucps2_synch(0);
if ((cEventFlag & BIT17) || (cEventFlag & BIT2) || (tEventFlag & (1<<MTMR_10ms_OFFSET)))
if ((cEventFlag & BIT17) || (cEventFlag & BIT2) || (tEventFlag & (1<<MTMR_10ms_OFFSET)) || (tEventFlag & (1<<MTMR_TDD_OFFSET_10000)))
{
if (cEventFlag & BIT17) // 1pps int
{
@ -1169,7 +1169,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
do_write(cFlagAddr, (1<<MTMR_CEVENT_CNT14H)); // clear int flag
pMtimerInt->sfnIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+2), pMtimerInt->sfnIntCnt); // 0x108
debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(nTmrId<<2)), pMtimerInt->sfnIntCnt); // 0x108
#endif
uint16_t runCore = do_read_volatile_short(&(phyPara[gScsId].runCoreId));
if (((runCore & pMtimerPara->runCoreId) == pMtimerPara->runCoreId) && (4 == reCfgFlag))
@ -1191,7 +1191,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
pMtimerInt->sfnOffsetIntFlag = 1;
pMtimerInt->sfnOffsetIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+3), pMtimerInt->sfnOffsetIntCnt); // 0x10C
debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C
#endif
if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == (pMtimerInt->sfnOffsetIntCnt&0x3)))
{
@ -1204,11 +1204,17 @@ void jesd_10ms_callback(uint8_t nTmrId)
do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET_10000)); // clear int flag
pMtimerInt->insOffsetIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), pMtimerInt->insOffsetIntCnt); // 0x118
debug_write((DBG_DDR_IDX_DRV_BASE+64+9), pMtimerInt->insOffsetIntCnt); // 0x124
#endif
set_jesd_rf_state(JESD_ANT_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_RF_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_TRANS_ORX, GPIO_OFF);
//set_jesd_rf_state(JESD_ANT_ORX, GPIO_OFF);
//set_jesd_rf_state(JESD_RF_ORX, GPIO_OFF);
//set_jesd_rf_state(JESD_TRANS_ORX, GPIO_OFF);
debug_write((DBG_DDR_IDX_DRV_BASE+58), GET_STC_CNT()); // 0xc4
uint64_t rt_val = get_mtimer_rt_scr_value(MTIMER_JESD_RX1_ID);
debug_write((DBG_DDR_IDX_DRV_BASE+56), rt_val&0xFFFFFFFF); // 0xc0
debug_write((DBG_DDR_IDX_DRV_BASE+57), rt_val>>32); // 0xc4
stop_jesd_orx_timer();
// phy callback
phy_sniffer_data_proc();
@ -1320,12 +1326,12 @@ void jesd_tdd_callback(uint8_t nTmrId)
uint32_t startTick = 0;
uint32_t cost = 0;
//startTick = GET_STC_CNT();
startTick = GET_STC_CNT();
set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON);
set_jesd_rf_state(JESD_RF_TX, GPIO_ON);
set_jesd_rf_state(JESD_ANT_TX, GPIO_ON);
//cost = GET_STC_CNT() - startTick;
//debug_write((DBG_DDR_IDX_DRV_BASE+120), cost); // 0x1e0
cost = GET_STC_CNT() - startTick;
debug_write((DBG_DDR_IDX_DRV_BASE+120), cost); // 0x1e0
//jesd_csu_start();
#if 1
uint8_t nTddTxId = 0;
@ -1485,7 +1491,7 @@ void jesd_slot_callback(uint8_t nTmrId)
debug_write(((DBG_DDR_IDX_DRV_BASE+9728) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), (nowTxSlotStcCnt-lastTxSlotStcCnt)); // 0x9800
lastTxSlotStcCnt = nowTxSlotStcCnt;
#endif
#if 0
#if 1
nowTxSlotCnt = GET_STC_CNT();
if ((nowTxSlotCnt > lastTxSlotCnt) && (2 < pMtimerInt->txSlotIntCnt))
{

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@ -207,9 +207,6 @@ int32_t mtimer_orx_adjust(void)
if (1 == orx_para_ptr->orx_start_flag)
{
set_jesd_rf_state(JESD_ANT_ORX, GPIO_ON);
set_jesd_rf_state(JESD_RF_ORX, GPIO_ON);
set_jesd_rf_state(JESD_TRANS_ORX, GPIO_ON);
start_jesd_orx_timer();
jesd_csu_orx_start(0);
orx_para_ptr->orx_start_flag = 0;

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,128 @@
% pdsch test cases config
clear all
clc
common_TVSetting = [
...%仿
'simu_params.nBS = 2;',...
'simu_params.BS{1}.nUE = 1;', ...
'simu_params.BS{1}.UE{1}.type = ''active'';',...
'simu_params.nSlot = 100;', ...
'simu_params.firstSlotIdx = 1;', ...
'MAC_params.BS{1}.Bandwidth = 100;', ...
'MAC_params.BS{1}.allocatedVRB_index = [1:273];', ...%[1:273]
'MAC_params.BS{1}.nBWP = 1;',...
'MAC_params.BS{1}.BWP{1}.frame_struct.cyclicPrefix = ''Normal'';', ...
'MAC_params.BS{1}.BWP{1}.subcarrierSpacing = ''kHz30'';',...
'MAC_params.BS{1}.BWP{1}.BWPallocatedPRB_index = [1:273];',...
'MAC_params.BS{1}.UE{1}.ActiveBWP_ID = 1;', ...
'MAC_params.BS{1}.mu = 1;', ...
'MAC_params.BS{1}.cellID = 100;',...
'MAC_params.BS{1}.oversamplingTimes = 1;', ...
'MAC_params.constant.nMaxHARQRetransmission = 4;', ...
...%
'simu_params.BS{1}.is_DL= ''True'';',...
'simu_params.BS{1}.is_SSB = ''False'';', ...
'simu_params.BS{1}.is_CSIRS = ''False'';', ...%SINR,
'simu_params.BS{1}.UE{1}.is_PDCCH = ''False'';', ...
'simu_params.BS{1}.UE{1}.is_PDSCH = ''True'';', ...
...%
'simu_params.BS{1}.UE{1}.DL_Rx_process = ''DISABLED'';'...
...%
'simu_params.fixedPoint.is_SSB = ''True''; ' , ...% PDCCH TxTrue/False, by QY
'simu_params.fixedPoint.is_PDCCH = ''True''; ', ... % PDCCH TxTrue/False, by QY
'simu_params.fixedPoint.is_PDSCH = ''True'';' , ... % PDSCH TxTrue/False, by QY
'simu_params.fixedPoint.is_CSIRS = ''True'';' , ... % CSIRS TxTrue/False, by QY
'simu_params.fixedPoint.moduleSqnrsw = ''False''; ', ... % SQNRTrue/False, by QY
...%
'simu_params.BS{1}.is_UL = ''False'';',...
'simu_params.BS{1}.UE{1}.is_PRACH = ''False'';', ...
'simu_params.BS{1}.UE{1}.is_PUSCH = ''False'';' ,...
'simu_params.BS{1}.UE{1}.is_PUCCH = ''False'';' ,...
...%
'simu_params.SNR_Range = 50;', ...
'simu_params.BS{1}.CorfileTx = ''cor_low_tx1'';',...%
'simu_params.BS{1}.UE{1}.CorfileRx = ''cor_low_rx4'';',...
'MAC_params.BS{1}.nAntenna = 1;', ...
'MAC_params.BS{1}.nAntennaForPDSCH = 1;', ...
'MAC_params.BS{1}.nAntennaForPDCCH = 1;', ...
'MAC_params.BS{1}.nAntennaForCSIRS = 1;',...
'MAC_params.BS{1}.UE{1}.nAntenna = 4;', ...
'simu_params.channel.type = ''TDL-A'';',...
'simu_params.channel.new_channel = 1;', ...
'simu_params.BS{1}.UE{1}.channel.Fading_sw = +1;', ...% -1:, +1:
'simu_params.BS{1}.UE{1}.chmodel = ''chmodel_TDLA30'';',...
'simu_params.BS{1}.UE{1}.channel.Fd = 10;',... % maximum Dopplar freq.
...% 仿
'simu_params.BS{1}.UE{1}.cpri_compressed_sw = 0;'...
'simu_params.window = 0;', ...
'simu_params.window_rx = 0;', ...
'simu_params.deltaf_comp_sw = ''True'';',... % 'True' 'False'
'simu_params.TA = 0;',...
'simu_params.ADC = 0;',...
];
%% UEcase0
case0_UE0_PDSCH = ...
['simu_params.iTC = -1;', ...
'MAC_params.BS{1}.UE{1}.nPortForPDSCH = 1;', ...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.isTransmissionPTRS = 0;',...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.Beta_PDSCHDATA = 0;',... % -3000 -- -3dB
'MAC_params.BS{1}.UE{1}.PDSCH_Config.Beta_PDSCHDDMRS = 0;',...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.RNTI = 267;', ...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.BWPstart = 1;',...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.BWPsize = 273;',...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.mu = MAC_params.BS{1}.mu;',... % subcarrier spacing
'MAC_params.BS{1}.UE{1}.BWP{1}.frame_struct.cyclicPrefix = MAC_params.BS{1}.BWP{1}.frame_struct.cyclicPrefix;',...
...%
'MAC_params.BS{1}.UE{1}.nCodeWord = 1;',... %/
'MAC_params.BS{1}.UE{1}.PDSCH_Config.I_MCS = 27;', ... %I_MCS=1--Qm=2,
'MAC_params.BS{1}.UE{1}.PDSCH_Config.mcs_Table = ''qam256'';', ... %'qam256' / 'qam64LowSE'
'MAC_params.BS{1}.UE{1}.PDSCH_Config.RVid = 0;',...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.dmrsAntennaPort_index = [0];', ... %layer=4Port Index
'MAC_params.BS{1}.UE{1}.PDSCH_Config.iBS = MAC_params.BS{1}.cellID;', ... % nIdPdsch
'MAC_params.BS{1}.UE{1}.PDSCH_Config.PRGsize = 0;',... % 0/2/4, 0-wideband
'MAC_params.BS{1}.UE{1}.PDSCH_Config.VRB_to_PRBmappingType = 0;', ...%1/0/
'MAC_params.BS{1}.UE{1}.PDSCH_Config.RBG_BundleSize = 4;', ... % Li 2/4
'MAC_params.BS{1}.UE{1}.PDSCH_Config.Interleaver_size = 2;',... % R
... % PDSCH
'simu_params.BS{1}.UE{1}.symbol_pattern = [0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1];', ... % PDSCH
'MAC_params.BS{1}.UE{1}.allocatedVRB_index = [109:273];', ...% PDSCH%%RB
'MAC_params.BS{1}.UE{1}.PDSCH_Config.PDSCHmapType = ''A'';'...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.ResourceAllocateType = 1;'... % type 1
... % DMRS
'MAC_params.BS{1}.UE{1}.PDSCH_Config.TPMI = 0;', ...% Transmission Precoding Matrix indicator index
'MAC_params.BS{1}.UE{1}.PDSCH_Config.DMRSConfigType = ''1'';', ... % dmrsConfigType = 0
'MAC_params.BS{1}.UE{1}.PDSCH_Config.dmrsTypeAPos = 2;',... % l_0 = 2 dlDmrsSymbPos = 0x4
'MAC_params.BS{1}.UE{1}.PDSCH_Config.DMRSAddPos = 0;', ...%pos0,1,2,3DMRS,117+115+8+11
'MAC_params.BS{1}.UE{1}.PDSCH_Config.NumCDMGroupsWithoutData = 2;'...%1: DMRSDATA, 2: DMRSDATA
'MAC_params.BS{1}.UE{1}.PDCCH_Config.LdpcToolbox = 0;'... % 0toolbox1toolbox
'MAC_params.BS{1}.nSCID = 0;'... % nSCID
'MAC_params.BS{1}.UE{1}.N_nSCID_ID = 100;'...% dlDmrsScramblingId
'MAC_params.BS{1}.UE{1}.PDSCH_Config.nSymbolDMRS = 1;'... % maxlength = 1, 1/2,1 is single-symbol case, 2 is double-symbol case, never modify except for test, since the demod module of double-symbol case is not developed yet, though other modules are already
'MAC_params.BS{1}.UE{1}.PDSCH_Config.isDigitalBeamforming = 0;'...
'MAC_params.BS{1}.UE{1}.PDSCH_Config.DBindex = [1];',...%nAntennaForPDSCH
];
test_cases = {[common_TVSetting,case0_UE0_PDSCH,...
'simu_params.BS{1}.UE{1}.DL_Rx_process = ''ENABLED'';', ...
'simu_params.TwoCell_flag = ''True'';',...%
'simu_params.BS{2} = simu_params.BS{1};',...
'MAC_params.BS{2} = MAC_params.BS{1};',...
'MAC_params.BS{2}.UE{1}.allocatedVRB_index = [1:164];', ...% PDSCH%%RB
'simu_params.DFE_flag = ''False'';'... % True %False TwoCell_flag = ''True'' DFE_flag = ''False''使8192FFT30k
'simu_params.BS{1}.baseband_f0 = -50.01e06;',...
'simu_params.BS{2}.baseband_f0 = 49.98e06;'...
'MAC_params.BS{1}.PointAFrequency = 2493850e3;', ...% pointABandwidthCenterFrequency PointAFrequency = 2493850e3 12542990e3
'MAC_params.BS{1}.UE{1}.PointAFrequency = MAC_params.BS{1}.PointAFrequency;', ...
'MAC_params.BS{2}.PointAFrequency = MAC_params.BS{1}.PointAFrequency+99.99e6;', ... % 99.99M
'MAC_params.BS{2}.UE{1}.PointAFrequency = MAC_params.BS{2}.PointAFrequency;', ...
'simu_params.dBfs = -15;', ...
]};
% call 'NR_simu_main' to simulate the test cases
[simu_result_all] = NR_simu_main(test_cases);

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2.5ms双周期, 带收发切换发256QAM, 245.76M 采样率200M带宽
2.5ms双周期, 带收发切换发256QAM, 245.76M 采样率160M带宽
板卡中心频点2.593G
cell id100
RNTI267
cell0中心频点2.54299GRB offset108RB num165
cell1中心频点2.64298GRB offset0RB num164