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1. fix Bug#1061

Browse Source 
2. fix Bug#1081
3. fix Bug#1079
4. update New Feature#945
5. component debug_init call in spu_lib_debug_init() functon
6. testcase:
   6.1 spu(case34)+arm(case5): pass
   6.2 spu(case44)+arm(case5): pass
   6.3 spu(case21)+arm(case21):pass
   6.4 spu(case14)+arm(case3): pass
This commit is contained in:
lishuang.xie 2023-09-25 09:46:27 +08:00
parent 45932968f5
commit 295a44d46b
22 changed files with 1148 additions and 812 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
inc/drv_ape.h
View File

@ -49,7 +49,7 @@ void phy_para_init(int protocol, int option);
// stc timer初始化，该接口只需八个核中的一个核调用即可
void ape_stc_init();
// scs sm初始化，该接口只需八个核中的一个核调用即可，放在main函数的最前面
// pet sm初始化，该接口只需八个核中的一个核调用即可，放在main函数的最前面
void pet_sm_init();
/***************************************************************/
// 以下接口，为帕拉丁临时验证带OSP的版本使用，最好按声明的顺序依次调用。

4
inc/osp_ape.h
View File

@ -94,7 +94,7 @@ extern void osp_del_task(int prio, int scsId);
函数入参：无
函数功能：设置配置文件标识位
*/
void osp_var_init(void);
extern void osp_var_init(void);
/*
函数名称：smart_int_disable
@ -191,7 +191,6 @@ extern int osp_get_cfgfile(char* name, uint32_t *pbuf, int* psize);
/* 定时点相关接口 */
/************************************************************************************/
/*
函数名称：osp_timer_sync
函数功能：使能定时点任务
函数参数：int scsId:子载波ID号
@ -209,7 +208,6 @@ extern int osp_get_cfgfile(char* name, uint32_t *pbuf, int* psize);
extern void osp_timer_sync(int scsId); /* 使能任务定时点 */
/*
函数名称：osp_timer_unsync
函数功能：删小区时，用于定时点中断、任务及时隙中断
函数参数：int scsId:子载波ID号

22
public/ape_spu/osp/src/osp_init.s.c
View File

@ -264,31 +264,17 @@ start_hook_func osp_init_start_hook[] =
void osp_start()
{
int ret = 0;
int apeId = get_core_id();
int32_t core_id = get_core_id();
int32_t ret = 0;
g_ape_id = get_core_id();
g_que_id = g_ape_id;
#if 1
ret = smart_os_debug_init((DBG_DDR_OS_ADDR_BASE+apeId*DBG_DDR_OS_LEN), DBG_DDR_OS_LEN); // 推荐768, 实际1024
ret = smart_os_debug_init((DBG_DDR_OS_ADDR_BASE + core_id*DBG_DDR_OS_LEN), DBG_DDR_OS_LEN); // 推荐768, 实际1024
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 31), ret); // ape0: 0xb7e2407c
debug_write(DBG_DDR_ERR_IDX(core_id, 31), ret); // ape0: 0xb7e2407c
}
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+apeId*DBG_DDR_HW_LEN), DBG_DDR_HW_LEN); // 推荐384，实际512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 32), ret); // ape0: 0xb7e24080
}
#if 0
ret = smart_spin_debug_init((DBG_DDR_SPIN_ADDR_BASE+apeId*DBG_DDR_SPIN_LEN), DBG_DDR_SPIN_LEN); // 推荐36, 实际64
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 39), ret); // ape0: 0xb7e2407c
}
#endif
#endif
smart_kernel_init(osp_init_start_hook, g_ape_id);
}

4
public/ape_spu/osp/src/osp_msg.s.c
View File

@ -494,7 +494,7 @@ void osp_hw_que_irq(void)
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
uint8_t src_core_id = do_read_byte((char*)(&pmsg_head->src_core_id));
__ucps2_synch(0);
//__ucps2_synch(0);
switch (src_core_id)
{
@ -566,7 +566,7 @@ void osp_hw_que_irq(void)
#endif
dst_task_id = do_read_byte((char*)(&pmsg_head->dst_task_id));
__ucps2_synch(0);
//__ucps2_synch(0);
if (OSP_OK != osp_task_id_is_true(dst_task_id))
{

2
public/ape_spu/osp/src/osp_sw_queue.s.c
View File

@ -20,7 +20,7 @@ int osp_sw_queue_int(osp_sw_queue *p_sw_queue_head)
p_sw_queue_head->full_count = 0;
p_sw_queue_head->empty_count = 0;
p_sw_queue_head->mask = OSP_QUE_DEP-1;
p_sw_queue_head->msg_sem = osp_create_sem(1);
//p_sw_queue_head->msg_sem = osp_create_sem(1);
/*if (NULL == p_sw_queue_head->msg_sem)
{
return -OSP_PAR_ILL;

41
public/ape_spu/osp/src/osp_task.s.c
View File

@ -558,11 +558,25 @@ int osp_task_create(osp_task_info_ex *t_info_val)
if ((t_info_val->task_type == OSP_TIMER_TYPE) || (t_info_val->task_type == OSP_DRIVER_TYPE) || (t_info_val->task_type == OSP_OSP_TYPE))
{
tcb_handle->sem = osp_create_sem(0);
if (NULL == tcb_handle->sem)
{
UCP_PRINT_ERROR("task=%d, create sem error.\n\r", t_info_val->task_id);
FREE((stack_down-4));
FREE((char*)tcb_handle);
return -1;
}
}
//else if((t_attr_val->sem_value != 0) && (t_attr_val->task_type == OSP_EVENT_TYPE))
if (t_info_val->task_type == OSP_EVENT_TYPE)
{
tcb_handle->event_sem = osp_create_sem(0);
if (NULL == tcb_handle->event_sem)
{
UCP_PRINT_ERROR("task=%d, create sem error.\n\r", t_info_val->task_id);
FREE((stack_down-4));
FREE((char*)tcb_handle);
return -1;
}
tcb_handle->que_head = (osp_sw_queue*)osp_malloc(sizeof(osp_sw_queue));
if (NULL == tcb_handle->que_head)
{
@ -606,6 +620,9 @@ int osp_task_create(osp_task_info_ex *t_info_val)
debug_write(OSP_DEBUG_POT(g_ape_id, 29), t_info_val->task_id);
UCP_PRINT_ERROR("timer point is overflow\n\r");
UCP_PRINT_ERROR("timer cfg failed\n\r");
osp_delete_sem(tcb_handle->sem);
FREE((stack_down-4));
FREE((char*)tcb_handle);
return -1;
}
g_osp_timer_desc[g_osp_timer_desc_idx].task_id = t_info_val->task_id;
@ -667,7 +684,7 @@ int osp_task_create(osp_task_info_ex *t_info_val)
FREE((char*)tcb_handle);
return -1;
}
UCP_PRINT_LOG("smart_task_create return: 0x%08x, task_id = 0x%08x, task_pro = 0x%08x\r\n", ret, tcb_handle->task_id, tcb_handle->priority);
UCP_PRINT_LOG("smart_task_create return:%d, task_id=%d, num=%d", ret, tcb_handle->task_id, g_taskid_num);
debug_write(OSP_DEBUG_POT(g_ape_id, 30), ret);
debug_write(OSP_DEBUG_POT(g_ape_id, 31), t_info_val->task_id);
@ -718,6 +735,7 @@ void osp_del_timer_task(int task_id)
if(NULL == tcb_handle)
{
debug_write(OSP_DEBUG_POT(g_ape_id, 13), task_id);
UCP_PRINT_ERROR("osp_del_timer_task: no tcb_handle(task_id=%d)", task_id);
return ;
}
@ -725,9 +743,11 @@ void osp_del_timer_task(int task_id)
if (task_prio <= 0)
{
debug_write(OSP_DEBUG_POT(g_ape_id, 14), task_id);
UCP_PRINT_ERROR("osp_del_timer_task: no task_prio(task_id=%d)", task_id);
return ;
}
smart_task_del(task_prio); /* 删除任务 */
g_task_id_array[task_prio] = 0; /* 通过优先级清任务列表 */
g_prio_array[task_id] = 0; /* 通过任务ID清优先级列表 */
FREE((char*)((tcb_handle->stack_down)-4)); /* 释放栈空间 */
@ -745,7 +765,7 @@ void osp_del_timer_task(int task_id)
break;
}
}
smart_task_del(task_prio); /* 删除任务 */
//smart_task_del(task_prio); /* 删除任务 */
return ;
}
@ -783,7 +803,7 @@ void osp_del_task(int prio, int scsId)
tcb_handle = (osp_tcb*)g_tcb_handler_tbl[task_id];
/* 根据消息类型分别处理 */
#if 0
#if 0 /* osp_timer_unsync接口直接由物理层调用 */
if (OSP_TIMER_TYPE == tcb_handle->task_type)
{
/* 只要删除定时点任务，那就清空所有定时点任务相关信息 */
@ -791,20 +811,27 @@ void osp_del_task(int prio, int scsId)
osp_timer_unsync(scsId);
return ;
}
else
else
#endif
if (OSP_EVENT_TYPE == tcb_handle->task_type)
{
/* 删除任务 */
smart_task_del(prio);
/* 事件任务，删除事件信号量和软件队列 */
osp_delete_sem(tcb_handle->event_sem);
osp_free((char*)tcb_handle->que_head);
}
else if (OSP_NORMAL_TYPE == tcb_handle->task_type)
{
/* 无操作 */
/* 删除任务 */
smart_task_del(prio);
}
else
{
/* 删除任务 */
smart_task_del(prio);
/* 其他任务，删除信号量 */
osp_delete_sem(tcb_handle->sem);
}
@ -822,14 +849,14 @@ void osp_del_task(int prio, int scsId)
if (task_id == g_task_id_table[u8_loop])
{
g_task_id_table[u8_loop] = 0;
memcpy(&(g_task_id_table[u8_loop]), &(g_task_id_table[u8_loop+1]), (g_taskid_num-u8_loop-1));
memcpy(&(g_task_id_table[u8_loop]), &(g_task_id_table[u8_loop+1]), sizeof(int)*(g_taskid_num-u8_loop-1));
g_taskid_num--;
break;
}
}
/* 删除任务 */
smart_task_del(prio);
//smart_task_del(prio);
debug_write(OSP_DEBUG_POT(g_ape_id, 33), task_id);
#ifdef UCP_TICK_ENABLE

30
public/ape_spu/osp/src/osp_timer.s.c
View File

@ -7,7 +7,7 @@
#include "ucp_printf.h"
#include "ucp_tick.h"
osp_id_timer_t g_task_off_tbl[10][50] = {0}; /* 根据定时点任务，分解成时隙，偏移，任务ID */
osp_id_timer_t g_task_off_tbl[10][100] = {0}; /* 根据定时点任务，分解成时隙，偏移，任务ID */
osp_timer_desc g_osp_timer_desc[OSP_TIMER_TASK_MAX] ={0}; /* 定时点任务与定时点信息汇总 */
int g_osp_timer_desc_idx = 0;
@ -21,7 +21,7 @@ extern void stc_timer_set_tmrpoint(stStcTimerPoint *pTmrPoint);
//uint32_t g_task_timer_offset_forsoc[120] = {0};
char g_register_task_buf[OSP_TMR_POINT_MAX] = {0};
uint8_t gu8_register_task_group[10][50] = {0};
uint8_t gu8_register_task_group[10][100] = {0};
//char g_t_off_larger[50] = {0};
uint16_t g_reg_task_index = 0;
@ -43,13 +43,25 @@ void osp_timer_clear_stctimer()
void osp_timer_clear_task()
{
uint16_t u16_loop = 0;
for (u16_loop = 0; u16_loop < g_reg_task_index; u16_loop++)
for (u16_loop = 0; u16_loop < g_osp_timer_desc_idx; u16_loop++)
{
if (g_register_task_buf[g_reg_task_index] > 0)
if ((g_osp_timer_desc[u16_loop].task_id) > 0)
{
osp_del_timer_task(g_register_task_buf[g_reg_task_index]);
osp_del_timer_task(g_osp_timer_desc[u16_loop].task_id);
}
}
#if 0
for (u16_loop = 0; u16_loop < g_reg_task_index; u16_loop++)
{
//UCP_PRINT_ERROR("loop=%d, taskid=%d", u16_loop, g_register_task_buf[u16_loop]);
if (g_register_task_buf[u16_loop] > 0)
{
osp_del_timer_task(g_register_task_buf[u16_loop]);
}
}
#endif
}
/* OSP侧定时点任务初始化 */
@ -125,6 +137,7 @@ void osp_timer_sync(int scsId)
tmp_bitmap &= ~(1 << slot_id);
g_task_off_tbl[slot_id][tbl_index].task_id = ptr->task_id;
g_task_off_tbl[slot_id][tbl_index].t_offset = ptr->t_offset;
//UCP_PRINT_ERROR("i=%d,j=%d,taskid=%d,offset=%d", slot_id,tbl_index, ptr->task_id, ptr->t_offset);
}
tmp_cnt++;
ptr++;
@ -135,8 +148,13 @@ void osp_timer_sync(int scsId)
for(i = 0; i < 10;i++)
{
stc_timer_index = 0;
for(j = 0; j < 50;j++)
for(j = 0; j < 100;j++)
{
if (50 <= stc_timer_index)
{
UCP_PRINT_ERROR("one slot timer tasks overflow\n\r");
return ;
}
if (0 == j)
{
g_stcTimerPoint[i*50 + stc_timer_index].pointVal = 0;

167
public/ape_spu/top/src/ape_top.s.c
View File

@ -1,89 +1,82 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_top.c
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "smartos.h"
#include "ape_drv.h"
#include "ucp_handshake.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "msg_transfer_mem.h"
#include "msg_transfer_queue.h"
#include "pet_sm_mgt.h"
#include "osp_init.h"
static int32_t gCoreId = 0;
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_top.c
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "smartos.h"
#include "ape_drv.h"
#include "ucp_handshake.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "msg_transfer_mem.h"
#include "msg_transfer_queue.h"
#include "pet_sm_mgt.h"
#include "osp_init.h"
static int32_t gCoreId = 0;
ALWAYS_INLINE int32_t get_core_id(void)
{
return gCoreId;
}
void set_core_id(void)
{
__ucps2_iCacheConfig(f_DoubleEnable, f_BypassEnable);
{
return gCoreId;
}
void set_core_id(void)
{
__ucps2_iCacheConfig(f_DoubleEnable, f_BypassEnable);
gCoreId = smart_get_cpuid();
if (0 > gCoreId)
{
debug_write(DBG_DDR_ERR_IDX(0, 13), gCoreId);
}
UCP_PRINT_EMPTY("Hello world from APE,coreId[0x%x]", gCoreId);
__ucps2_synch(0);
return;
}
int32_t soc_drv_init()
{
int apeId = get_core_id();
if (0 == apeId)
{
pet_sm_init();
osp_var_init();
}
return 0;
}
void spu_drv_init(void)
{
pet_sm_alloc();
int32_t core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
UCP_PRINT_EMPTY("Hello world from APE[0x%08x]\r\n", core_id);
ape_drv_init();
UCP_PRINT_EMPTY("core_id[0x%08x] ape_drv_init OK\r\n", core_id);
return;
}
void spu_msg_transfer_init(void)//ape level
{
msg_transfer_mem_alloc();
handshake_slave_with_master();
msg_transfer_queue_init();
return;
}
if (0 > gCoreId)
{
debug_write(DBG_DDR_ERR_IDX(0, 13), gCoreId);
}
UCP_PRINT_EMPTY("Hello world from APE,coreId[0x%x]", gCoreId);
__ucps2_synch(0);
return;
}
int32_t soc_drv_init()
{
int apeId = get_core_id();
if (0 == apeId)
{
pet_sm_init();
osp_var_init();
}
return 0;
}
void spu_drv_init(void)
{
pet_sm_alloc();
ape_drv_init();
return;
}
void spu_msg_transfer_init(void)//ape level
{
msg_transfer_mem_alloc();
handshake_slave_with_master();
msg_transfer_queue_init();
return;
}

22
public/ape_spu/top/src/main.s.c
View File

@ -13,24 +13,24 @@
// -FHDR------------------------------------------------------------
#include "ape_top.h"
#include "osp_init.h"
#include "smartos.h"
#include "lib_debug_init.h"
#include "log_client.h"
#include "osp_init.h"
int32_t main(int32_t argc, char* argv[])
{
int32_t core_id = 0;
int32_t ret = 0;
set_core_id();
soc_drv_init();
#if 1
int32_t apeId = get_core_id();
core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
int32_t ret = smart_irq_debug_init(DBG_DDR_IRQ_ADDR_BASE+apeId*DBG_DDR_IRQ_LEN, DBG_DDR_IRQ_LEN);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 10), ret);
}
#endif
soc_drv_init();
ret = spu_lib_debug_init(core_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
spu_log_client_init();

280
public/common/app/src/app_interface.s.c
View File

@ -61,6 +61,19 @@ static uint32_t gu32_app_sendto_que8_ng = 0;
static uint32_t gu32_app_sendto_que9_ng = 0;
static uint32_t gu32_app_sendto_que10_ng = 0;
static uint32_t gu32_app_sendto_que11_ng = 0;
static uint32_t gu32_app_recv_que0 = 0; // #24
static uint32_t gu32_app_recv_que1 = 0;
static uint32_t gu32_app_recv_que2 = 0;
static uint32_t gu32_app_recv_que3 = 0;
static uint32_t gu32_app_recv_que4 = 0;
static uint32_t gu32_app_recv_que5 = 0;
static uint32_t gu32_app_recv_que6 = 0;
static uint32_t gu32_app_recv_que7 = 0;
static uint32_t gu32_app_recv_que8 = 0;
static uint32_t gu32_app_recv_que9 = 0;
static uint32_t gu32_app_recv_que10 = 0;
static uint32_t gu32_app_recv_que11 = 0;
#endif
#define APP_PALLADIUM_TEST
@ -210,62 +223,62 @@ int32_t osp_send_msg(uint32_t msg_addr,
{
case 0:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 12), ++gu32_app_sendto_que0_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 12), ++gu32_app_sendto_que0_ng);
break;
}
case 1:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 13), ++gu32_app_sendto_que1_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 13), ++gu32_app_sendto_que1_ng);
break;
}
case 2:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 14), ++gu32_app_sendto_que2_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 14), ++gu32_app_sendto_que2_ng);
break;
}
case 3:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 15), ++gu32_app_sendto_que3_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 15), ++gu32_app_sendto_que3_ng);
break;
}
case 4:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 16), ++gu32_app_sendto_que4_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 16), ++gu32_app_sendto_que4_ng);
break;
}
case 5:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 17), ++gu32_app_sendto_que5_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 17), ++gu32_app_sendto_que5_ng);
break;
}
case 6:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 18), ++gu32_app_sendto_que6_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 18), ++gu32_app_sendto_que6_ng);
break;
}
case 7:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 19), ++gu32_app_sendto_que7_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 19), ++gu32_app_sendto_que7_ng);
break;
}
case 8:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 20), ++gu32_app_sendto_que8_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 20), ++gu32_app_sendto_que8_ng);
break;
}
case 9:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 21), ++gu32_app_sendto_que9_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 21), ++gu32_app_sendto_que9_ng);
break;
}
case 10:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 22), ++gu32_app_sendto_que10_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 22), ++gu32_app_sendto_que10_ng);
break;
}
case 11:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 23), ++gu32_app_sendto_que11_ng);
debug_write(OSP_DEBUG_HW_POT(core_id, 23), ++gu32_app_sendto_que11_ng);
break;
}
default:
@ -284,62 +297,62 @@ int32_t osp_send_msg(uint32_t msg_addr,
{
case 0:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 0), ++gu32_app_sendto_que0_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 0), ++gu32_app_sendto_que0_ok);
break;
}
case 1:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 1), ++gu32_app_sendto_que1_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 1), ++gu32_app_sendto_que1_ok);
break;
}
case 2:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 2), ++gu32_app_sendto_que2_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 2), ++gu32_app_sendto_que2_ok);
break;
}
case 3:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 3), ++gu32_app_sendto_que3_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 3), ++gu32_app_sendto_que3_ok);
break;
}
case 4:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 4), ++gu32_app_sendto_que4_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 4), ++gu32_app_sendto_que4_ok);
break;
}
case 5:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 5), ++gu32_app_sendto_que5_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 5), ++gu32_app_sendto_que5_ok);
break;
}
case 6:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 6), ++gu32_app_sendto_que6_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 6), ++gu32_app_sendto_que6_ok);
break;
}
case 7:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 7), ++gu32_app_sendto_que7_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 7), ++gu32_app_sendto_que7_ok);
break;
}
case 8:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 8), ++gu32_app_sendto_que8_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 8), ++gu32_app_sendto_que8_ok);
break;
}
case 9:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 9), ++gu32_app_sendto_que9_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 9), ++gu32_app_sendto_que9_ok);
break;
}
case 10:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 10), ++gu32_app_sendto_que10_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 10), ++gu32_app_sendto_que10_ok);
break;
}
case 11:
{
debug_write(OSP_DEBUG_HW_POT(src_core_id, 11), ++gu32_app_sendto_que11_ok);
debug_write(OSP_DEBUG_HW_POT(core_id, 11), ++gu32_app_sendto_que11_ok);
break;
}
default:
@ -387,15 +400,154 @@ int32_t osp_send_msg_oam(uint32_t msg_addr,
debug_write(DBG_DDR_COMMON_IDX(core_id, 13), g_ecs_app_debug_info.ecs_msg_InQue_err);
debug_write(DBG_DDR_ERR_IDX(core_id, 19), ret_queue);
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
switch (dst_core_id)
{
case 0:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 12), ++gu32_app_sendto_que0_ng);
break;
}
case 1:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 13), ++gu32_app_sendto_que1_ng);
break;
}
case 2:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 14), ++gu32_app_sendto_que2_ng);
break;
}
case 3:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 15), ++gu32_app_sendto_que3_ng);
break;
}
case 4:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 16), ++gu32_app_sendto_que4_ng);
break;
}
case 5:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 17), ++gu32_app_sendto_que5_ng);
break;
}
case 6:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 18), ++gu32_app_sendto_que6_ng);
break;
}
case 7:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 19), ++gu32_app_sendto_que7_ng);
break;
}
case 8:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 20), ++gu32_app_sendto_que8_ng);
break;
}
case 9:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 21), ++gu32_app_sendto_que9_ng);
break;
}
case 10:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 22), ++gu32_app_sendto_que10_ng);
break;
}
case 11:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 23), ++gu32_app_sendto_que11_ng);
break;
}
default:
{
break;
}
}
#endif
}
#ifdef APP_PALLADIUM_TEST
#ifdef APP_PALLADIUM_TEST
debug_write(DBG_DDR_COMMON_IDX(core_id, 14), g_ecs_app_debug_info.ecs_msg_send_num);
#endif
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
switch (dst_core_id)
{
case 0:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 0), ++gu32_app_sendto_que0_ok);
break;
}
case 1:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 1), ++gu32_app_sendto_que1_ok);
break;
}
case 2:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 2), ++gu32_app_sendto_que2_ok);
break;
}
case 3:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 3), ++gu32_app_sendto_que3_ok);
break;
}
case 4:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 4), ++gu32_app_sendto_que4_ok);
break;
}
case 5:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 5), ++gu32_app_sendto_que5_ok);
break;
}
case 6:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 6), ++gu32_app_sendto_que6_ok);
break;
}
case 7:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 7), ++gu32_app_sendto_que7_ok);
break;
}
case 8:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 8), ++gu32_app_sendto_que8_ok);
break;
}
case 9:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 9), ++gu32_app_sendto_que9_ok);
break;
}
case 10:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 10), ++gu32_app_sendto_que10_ok);
break;
}
case 11:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 11), ++gu32_app_sendto_que11_ok);
break;
}
default:
{
break;
}
}
#endif
return ret_queue;
}
uint8_t ecs_hw_que_get_info(uint8_t que_id, uint32_t* pmsg_addr, uint32_t* pmsg_size)
{
int ret = -1;
@ -432,6 +584,80 @@ uint8_t ecs_hw_que_get_info(uint8_t que_id, uint32_t* pmsg_addr, uint32_t* pmsg_
*pmsg_addr = u32addr;
*pmsg_size = u32msg_size;
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
uint8_t src_core_id = do_read_byte((char*)(&pmsg_head->src_core_id));
//__ucps2_synch(0);
switch (src_core_id)
{
case 0:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 24), ++gu32_app_recv_que0);
break;
}
case 1:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 25), ++gu32_app_recv_que1);
break;
}
case 2:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 26), ++gu32_app_recv_que2);
break;
}
case 3:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 27), ++gu32_app_recv_que3);
break;
}
case 4:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 28), ++gu32_app_recv_que4);
break;
}
case 5:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 29), ++gu32_app_recv_que5);
break;
}
case 6:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 30), ++gu32_app_recv_que6);
break;
}
case 7:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 31), ++gu32_app_recv_que7);
break;
}
case 8:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 32), ++gu32_app_recv_que8);
break;
}
case 9:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 33), ++gu32_app_recv_que9);
break;
}
case 10:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 34), ++gu32_app_recv_que10);
break;
}
case 11:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 35), ++gu32_app_recv_que11);
break;
}
default:
{
break;
}
}
#endif
#ifdef APP_PALLADIUM_TEST
g_ecs_app_debug_info.ecs_msg_get_info_num++;
debug_write(DBG_DDR_COMMON_IDX(core_id, 17), g_ecs_app_debug_info.ecs_msg_get_info_num);

21
public/common/platform/inc/lib_debug_init.h Normal file
View File

@ -0,0 +1,21 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : lib_debug_init.h
// Author : xianfeng.du
// Created On : 2023-09-23
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#ifndef __SPU_LIB_DEBUG_INIT_H__
#define __SPU_LIB_DEBUG_INIT_H__
extern int32_t spu_lib_debug_init(uint8_t core_id);
#endif /* __SPU_LIB_DEBUG_INIT_H__ */

51
public/common/platform/src/lib_debug_init.s.c Normal file
View File

@ -0,0 +1,51 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : lib_debug_init.c
// Author : xianfeng.du
// Created On : 2023-09-23
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "lib_debug_init.h"
#include "ucp_utility.h"
#define SPU_APE_NUM (8)
extern int smart_irq_debug_init(uint32_t debug_base_addr, uint32_t len_bytes);
extern int smart_hq_debug_init( uint32_t debug_base_addr, uint32_t len_bytes);
/*
return : 0 -- OK
0x001 -- interrupt error
0x010 -- hw queue error
*/
int32_t spu_lib_debug_init(uint8_t core_id)
{
int32_t ret = 0;
int32_t ret_val = 0;
/* interrupt */
ret = smart_irq_debug_init((DBG_DDR_IRQ_ADDR_BASE + core_id*DBG_DDR_IRQ_LEN), DBG_DDR_IRQ_LEN);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 10), ret);
ret_val += 1;
}
/* hw queue */
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE + core_id*DBG_DDR_HW_LEN), DBG_DDR_HW_LEN); // 推荐384，实际512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 32), ret); // ape0: 0xb7e24080
ret_val += 1 << 1;
}
return ret_val;
}

689
public/common/platform/src/spu_hw_queue.s.c
View File

@ -1,15 +1,15 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : spu_hw_queue.s.c
// Author : lishuang.xie
// Created On : 2023-02-06
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : spu_hw_queue.s.c
// Author : lishuang.xie
// Created On : 2023-02-06
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "inter_vector.h"
#include "spu_hw_queue.h"
@ -17,355 +17,366 @@
#include "ucp_printf.h"
#include "hwque.h"
#define ECS_PALLADIUM_TEST
#ifdef ECS_PALLADIUM_TEST
typedef struct ECS_DEBUG_INFO_STRUCT
{
uint32_t ecs_msg_OutQue_err;
uint32_t ecs_msg_irq_num;
uint32_t ecs_msg_OutQue_num;
uint32_t ecs_msg_QutQue_ok;
uint32_t ecs_msg_QueIsEmpty_num;
}ecs_debug_info;
ecs_debug_info g_ecs_debug_info; /* ECS硬件队列调试信息 */
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
static uint32_t gu32_app_recv_que0 = 0; // #24
static uint32_t gu32_app_recv_que1 = 0;
static uint32_t gu32_app_recv_que2 = 0;
static uint32_t gu32_app_recv_que3 = 0;
static uint32_t gu32_app_recv_que4 = 0;
static uint32_t gu32_app_recv_que5 = 0;
static uint32_t gu32_app_recv_que6 = 0;
static uint32_t gu32_app_recv_que7 = 0;
static uint32_t gu32_app_recv_que8 = 0;
static uint32_t gu32_app_recv_que9 = 0;
static uint32_t gu32_app_recv_que10 = 0;
static uint32_t gu32_app_recv_que11 = 0;
#endif
ecs_hw_que_info_withirq_t g_ecs_hw_que_info; /* ECS带中断的硬件队列相关信息 */
ecs_hw_que_info_noirq_t gst_ecs_hw_que_info_noirq; /* ECS不带中断的硬件队列相关信息 */
#define ECS_PALLADIUM_TEST
#ifdef ECS_PALLADIUM_TEST
typedef struct ECS_DEBUG_INFO_STRUCT
{
uint32_t ecs_msg_OutQue_err;
uint32_t ecs_msg_irq_num;
uint32_t ecs_msg_OutQue_num;
uint32_t ecs_msg_QutQue_ok;
uint32_t ecs_msg_QueIsEmpty_num;
}ecs_debug_info;
ecs_debug_info g_ecs_debug_info; /* ECS¿¿¿¿¿¿¿¿ */
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
static uint32_t gu32_app_recv_que0 = 0; // #24
static uint32_t gu32_app_recv_que1 = 0;
static uint32_t gu32_app_recv_que2 = 0;
static uint32_t gu32_app_recv_que3 = 0;
static uint32_t gu32_app_recv_que4 = 0;
static uint32_t gu32_app_recv_que5 = 0;
static uint32_t gu32_app_recv_que6 = 0;
static uint32_t gu32_app_recv_que7 = 0;
static uint32_t gu32_app_recv_que8 = 0;
static uint32_t gu32_app_recv_que9 = 0;
static uint32_t gu32_app_recv_que10 = 0;
static uint32_t gu32_app_recv_que11 = 0;
#endif
ecs_hw_que_info_withirq_t g_ecs_hw_que_info; /* ECS¿¿¿¿¿¿¿¿¿¿¿¿ */
ecs_hw_que_info_noirq_t gst_ecs_hw_que_info_noirq; /* ECS¿¿¿¿¿¿¿¿¿¿¿¿¿ */
extern void ecs_hw_que_irq(void);
void ecs_hw_que_init(uint8_t core_id)
{
int32_t i32ret = 0;
/* communication init */
do
{
i32ret = smart_hq_init(core_id);
}
while(i32ret != 0);
UCP_PRINT_EMPTY("[ecs_hw_que_init]: smart_hq_init OK\r\n");
debug_write(DBG_DDR_COMMON_IDX(core_id, 28), core_id);
}
void ecs_hw_que_init_withirq(uint8_t core_id, uint8_t que_id)
{
int32_t ret = -1;
int32_t que_dep = -1;
int32_t que_width = -1;
int32_t que_used = -1;
int32_t que_cpuid = -1;
int32_t apeId = (int32_t)core_id;
memset(&g_ecs_hw_que_info, 0, sizeof(g_ecs_hw_que_info));
g_ecs_hw_que_info.ecs_hq_id = que_id;
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_hq_init OK\r\n");
debug_write(DBG_DDR_COMMON_IDX(core_id, 29), que_id);
/* Band */
ret = smart_que_bind(core_id, que_id);
if (0 != ret)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_que_bind error!!!!!(core_id = 0x%x, que_id= 0x%x)\r\n", core_id, que_id);
//#ifdef ECS_PALLADIUM_TEST
//debug_write((ECS_LOG_INDEX + 20), core_id);
//#endif
debug_write(DBG_DDR_ERR_IDX(apeId, 23), ret);
return ;
}
/* Get queue info*/
ret = smart_get_que_info(que_id, &que_dep, &que_width, &que_used, &que_cpuid);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 21), ret);
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 30), 0x1);
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: que_id(0x%08x),dep(0x%08x),width(0x%08x),used(0x%08x),cpuid(0x%08x) \r\n", que_id, que_dep,que_width,que_used,que_cpuid);
/* Get queue vector */
g_ecs_hw_que_info.ecs_hq_vector = smart_get_hq_vector(core_id, que_id);
if (0 >= g_ecs_hw_que_info.ecs_hq_vector)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_get_hq_vector error!!!!!(core_id = 0x%08x)....\r\n", core_id);
//#ifdef ECS_PALLADIUM_TEST
//debug_write((ECS_LOG_INDEX + 21), core_id);
//#endif
debug_write(DBG_DDR_ERR_IDX(apeId, 17), g_ecs_hw_que_info.ecs_hq_vector);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 31), g_ecs_hw_que_info.ecs_hq_vector);
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: hq_vector = 0x%x (coreid = 0x%x, queid = 0x%x)\r\n", g_ecs_hw_que_info.ecs_hq_vector, core_id, que_id);
/* Set req */
ret = smart_irq_request(g_ecs_hw_que_info.ecs_hq_vector, ecs_hw_que_irq);
if (0 != ret)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_irq_request error!!!!!(core_id = 0x%08x)....\r\n", core_id);
//#ifdef ECS_PALLADIUM_TEST
//debug_write((ECS_LOG_INDEX + 22), core_id);
//#endif
debug_write(DBG_DDR_ERR_IDX(apeId, 7), ret);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 30), 0x2);
smart_enable_q_nempty(que_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 30), 0x3);
//ecs_msg_que_init(que_id);
//debug_write(DBG_DDR_COMMON_IDX(core_id, 10), 0x4);
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: OK \r\n");
return ;
}
extern void ecs_hw_que_irq(void);
void ecs_hw_que_init(uint8_t core_id)
{
int32_t i32ret = 0;
/* communication init */
do
{
i32ret = smart_hq_init(core_id);
}
while(i32ret != 0);
UCP_PRINT_EMPTY("[ecs_hw_que_init]: smart_hq_init OK\r\n");
debug_write(DBG_DDR_COMMON_IDX(core_id, 28), core_id);
}
void ecs_hw_que_init_withirq(uint8_t core_id, uint8_t que_id)
{
int32_t ret = -1;
int32_t que_dep = -1;
int32_t que_width = -1;
int32_t que_used = -1;
int32_t que_cpuid = -1;
int32_t apeId = (int32_t)core_id;
memset(&g_ecs_hw_que_info, 0, sizeof(g_ecs_hw_que_info));
g_ecs_hw_que_info.ecs_hq_id = que_id;
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_hq_init OK\r\n");
debug_write(DBG_DDR_COMMON_IDX(core_id, 29), que_id);
/* Band */
ret = smart_que_bind(core_id, que_id);
if (0 != ret)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_que_bind error!!!!!(core_id = 0x%x, que_id= 0x%x)\r\n", core_id, que_id);
//#ifdef ECS_PALLADIUM_TEST
//debug_write((ECS_LOG_INDEX + 20), core_id);
//#endif
debug_write(DBG_DDR_ERR_IDX(apeId, 23), ret);
return ;
}
/* Get queue info*/
ret = smart_get_que_info(que_id, &que_dep, &que_width, &que_used, &que_cpuid);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 21), ret);
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 30), 0x1);
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: que_id(0x%08x),dep(0x%08x),width(0x%08x),used(0x%08x),cpuid(0x%08x) \r\n", que_id, que_dep,que_width,que_used,que_cpuid);
/* Get queue vector */
g_ecs_hw_que_info.ecs_hq_vector = smart_get_hq_vector(core_id, que_id);
if (0 >= g_ecs_hw_que_info.ecs_hq_vector)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_get_hq_vector error!!!!!(core_id = 0x%08x)....\r\n", core_id);
//#ifdef ECS_PALLADIUM_TEST
//debug_write((ECS_LOG_INDEX + 21), core_id);
//#endif
debug_write(DBG_DDR_ERR_IDX(apeId, 17), g_ecs_hw_que_info.ecs_hq_vector);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 31), g_ecs_hw_que_info.ecs_hq_vector);
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: hq_vector = 0x%x (coreid = 0x%x, queid = 0x%x)\r\n", g_ecs_hw_que_info.ecs_hq_vector, core_id, que_id);
/* Set req */
ret = smart_irq_request(g_ecs_hw_que_info.ecs_hq_vector, ecs_hw_que_irq);
if (0 != ret)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: smart_irq_request error!!!!!(core_id = 0x%08x)....\r\n", core_id);
//#ifdef ECS_PALLADIUM_TEST
//debug_write((ECS_LOG_INDEX + 22), core_id);
//#endif
debug_write(DBG_DDR_ERR_IDX(apeId, 7), ret);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 30), 0x2);
smart_enable_q_nempty(que_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 30), 0x3);
//ecs_msg_que_init(que_id);
//debug_write(DBG_DDR_COMMON_IDX(core_id, 10), 0x4);
UCP_PRINT_EMPTY("[ecs_hw_que_init_withirq]: OK \r\n");
return ;
}
void ecs_hw_que_init_noirq(uint8_t core_id, uint8_t que_id)
{
int32_t i32ret = 0;
int32_t i32que_dep = -1;
int32_t i32que_width = -1;
int32_t i32que_used = -1;
int32_t i32que_cpuid = -1;
int32_t i32que_dep = -1;
int32_t i32que_width = -1;
int32_t i32que_used = -1;
int32_t i32que_cpuid = -1;
memset(&gst_ecs_hw_que_info_noirq, 0, sizeof(gst_ecs_hw_que_info_noirq));
gst_ecs_hw_que_info_noirq.ecs_hq_id = que_id;
memset(&gst_ecs_hw_que_info_noirq, 0, sizeof(gst_ecs_hw_que_info_noirq));
gst_ecs_hw_que_info_noirq.ecs_hq_id = que_id;
/* Band */
i32ret = smart_que_bind(core_id, que_id);
if (0 != i32ret)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_noirq]: smart_que_bind error!!!!!(core_id = 0x%x, que_id= 0x%x)\r\n", core_id, que_id);
debug_write(DBG_DDR_ERR_IDX(core_id, 39), i32ret);
return ;
}
/* Band */
i32ret = smart_que_bind(core_id, que_id);
if (0 != i32ret)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_noirq]: smart_que_bind error!!!!!(core_id = 0x%x, que_id= 0x%x)\r\n", core_id, que_id);
debug_write(DBG_DDR_ERR_IDX(core_id, 39), i32ret);
return ;
}
/* Get queue info*/
i32ret = smart_get_que_info(que_id, &i32que_dep, &i32que_width, &i32que_used, &i32que_cpuid);
if (0 != i32ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 40), i32ret);
}
UCP_PRINT_EMPTY("[ecs_hw_que_init_noirq]: que_id(0x%08x),dep(0x%08x),width(0x%08x),used(0x%08x),cpuid(0x%08x) \r\n", que_id, i32que_dep, i32que_width, i32que_used, i32que_cpuid);
/* Get queue vector */
gst_ecs_hw_que_info_noirq.ecs_hq_vector = smart_get_hq_vector(core_id, que_id);
if (0 >= gst_ecs_hw_que_info_noirq.ecs_hq_vector)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_noirq]: smart_get_hq_vector error!!!!!(core_id = 0x%08x)....\r\n", core_id);
debug_write(DBG_DDR_ERR_IDX(core_id, 17), gst_ecs_hw_que_info_noirq.ecs_hq_vector);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 32), que_id);
/* Get queue info*/
i32ret = smart_get_que_info(que_id, &i32que_dep, &i32que_width, &i32que_used, &i32que_cpuid);
if (0 != i32ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 40), i32ret);
}
UCP_PRINT_EMPTY("[ecs_hw_que_init_noirq]: que_id(0x%08x),dep(0x%08x),width(0x%08x),used(0x%08x),cpuid(0x%08x) \r\n", que_id, i32que_dep, i32que_width, i32que_used, i32que_cpuid);
/* Get queue vector */
gst_ecs_hw_que_info_noirq.ecs_hq_vector = smart_get_hq_vector(core_id, que_id);
if (0 >= gst_ecs_hw_que_info_noirq.ecs_hq_vector)
{
UCP_PRINT_EMPTY("[ecs_hw_que_init_noirq]: smart_get_hq_vector error!!!!!(core_id = 0x%08x)....\r\n", core_id);
debug_write(DBG_DDR_ERR_IDX(core_id, 17), gst_ecs_hw_que_info_noirq.ecs_hq_vector);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 32), que_id);
return ;
}
uint32_t gu32_ecs_send_cnt = 0;
uint32_t gu32_ecs_recv_cnt = 0;
uint32_t gu32_ecs_send_cnt = 0;
uint32_t gu32_ecs_recv_cnt = 0;
ALWAYS_INLINE int32_t ecs_hw_que_send(uint8_t u8dst_que_id, uint32_t u32value)
{
int32_t i32ret = 0;
int32_t apeId = get_core_id();
int32_t apeId = get_core_id();
i32ret = smart_in_que(u8dst_que_id, u32value);
if (0 != i32ret)
{
UCP_PRINT_ERROR("[ecs_hw_que_send]: error(smart_in_que) que_id = 0x%08x addr = 0x%08x\r\n", u8dst_que_id, u32value);
debug_write(DBG_DDR_ERR_IDX(apeId, 41), i32ret);
return i32ret;
}
gu32_ecs_send_cnt++;
debug_write(DBG_DDR_ERR_IDX(apeId, 43), gu32_ecs_send_cnt);
i32ret = smart_in_que(u8dst_que_id, u32value);
if (0 != i32ret)
{
UCP_PRINT_ERROR("[ecs_hw_que_send]: error(smart_in_que) que_id = 0x%08x addr = 0x%08x\r\n", u8dst_que_id, u32value);
debug_write(DBG_DDR_ERR_IDX(apeId, 41), i32ret);
return i32ret;
}
gu32_ecs_send_cnt++;
debug_write(DBG_DDR_ERR_IDX(apeId, 43), gu32_ecs_send_cnt);
return 0;
}
ALWAYS_INLINE int32_t ecs_hw_que_recv(uint8_t u8dst_que_id, uint32_t *pu32value)
{
int32_t i32ret = 0;
int32_t apeId = get_core_id();
int32_t apeId = get_core_id();
i32ret = smart_out_que(u8dst_que_id, pu32value);
if (0 != i32ret)
{
UCP_PRINT_ERROR("[ecs_hw_que_recv]: smart_out_que error... que_id = 0x%08x \r\n", u8dst_que_id);
debug_write(DBG_DDR_ERR_IDX(apeId, 42), i32ret);
return i32ret;
}
gu32_ecs_recv_cnt++;
debug_write(DBG_DDR_ERR_IDX(apeId, 44), gu32_ecs_recv_cnt);
debug_write(DBG_DDR_ERR_IDX(apeId, 45), *pu32value);
/* is empty */
i32ret = smart_que_is_empty(u8dst_que_id);
if (0 != i32ret)
{
/* no message return */
#ifdef APP_PALLADIUM_TEST
debug_write(DBG_DDR_COMMON_IDX(core_id, 47), i32ret);
#endif
return 1;
}
i32ret = smart_out_que(u8dst_que_id, pu32value);
if (0 != i32ret)
{
UCP_PRINT_ERROR("[ecs_hw_que_recv]: smart_out_que error... que_id = 0x%08x \r\n", u8dst_que_id);
debug_write(DBG_DDR_ERR_IDX(apeId, 42), i32ret);
return i32ret;
}
gu32_ecs_recv_cnt++;
debug_write(DBG_DDR_ERR_IDX(apeId, 44), gu32_ecs_recv_cnt);
debug_write(DBG_DDR_ERR_IDX(apeId, 45), *pu32value);
return i32ret;
}
/*********************************************************/
/* irq */
void ecs_hw_que_irq(void)
{
int32_t ret = -1;
uint32_t idx = 0;
uint32_t len = 0;
ecs_msg_head *pmsg_head = NULL;
int32_t core_id = get_core_id();
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_irq_num++;
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
debug_write(OSP_DEBUG_HW_POT(core_id, 38), g_ecs_debug_info.ecs_msg_irq_num);
#endif
ret = smart_que_is_empty(g_ecs_hw_que_info.ecs_hq_id);
while(ret == 0)
{
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_OutQue_num++;
#endif
/* out queue */
ret = smart_out_que(g_ecs_hw_que_info.ecs_hq_id, &idx);
if (0 != ret)
{
UCP_PRINT_ERROR("[ecs_hw_que_irq]: smart_out_que error... que_id = 0x%08x \r\n", g_ecs_hw_que_info.ecs_hq_id);
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_OutQue_err++;
debug_write(DBG_DDR_COMMON_IDX(core_id, 33), g_ecs_debug_info.ecs_msg_OutQue_err);
debug_write(DBG_DDR_COMMON_IDX(core_id, 34), g_ecs_debug_info.ecs_msg_irq_num);
debug_write(DBG_DDR_COMMON_IDX(core_id, 35), g_ecs_debug_info.ecs_msg_OutQue_num);
#endif
debug_write(DBG_DDR_ERR_IDX(core_id, 28), ret);
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
debug_write(OSP_DEBUG_HW_POT(core_id, 40), g_ecs_debug_info.ecs_msg_OutQue_err);
#endif
return ;
}
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_QutQue_ok++;
#endif
UCP_PRINT_LOG("[ecs_hw_que_irq]: smart_out_que(0x%08x), addr = 0x%08x\r\n", g_ecs_hw_que_info.ecs_hq_id, idx);
if (NULL != g_ecs_hw_que_info.irq_entry)
{
pmsg_head = (ecs_msg_head*)((uint32_t)idx - (uint32_t)ECS_MSG_HEAD_LEN);
len = do_read((char*)(&pmsg_head->msg_size));
#ifdef ECS_PALLADIUM_TEST
debug_write(DBG_DDR_COMMON_IDX(core_id, 36), g_ecs_debug_info.ecs_msg_irq_num);
debug_write(DBG_DDR_COMMON_IDX(core_id, 37), g_ecs_debug_info.ecs_msg_OutQue_num);
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
uint8_t src_core_id = do_read_byte((char*)(&pmsg_head->src_core_id));
switch (src_core_id)
{
case 0:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 24), ++gu32_app_recv_que0);
break;
}
case 1:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 25), ++gu32_app_recv_que1);
break;
}
case 2:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 26), ++gu32_app_recv_que2);
break;
}
case 3:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 27), ++gu32_app_recv_que3);
break;
}
case 4:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 28), ++gu32_app_recv_que4);
break;
}
case 5:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 29), ++gu32_app_recv_que5);
break;
}
case 6:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 30), ++gu32_app_recv_que6);
break;
}
case 7:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 31), ++gu32_app_recv_que7);
break;
}
case 8:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 32), ++gu32_app_recv_que8);
break;
}
case 9:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 33), ++gu32_app_recv_que9);
break;
}
case 10:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 34), ++gu32_app_recv_que10);
break;
}
case 11:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 35), ++gu32_app_recv_que11);
break;
}
default:
{
break;
}
}
debug_write(OSP_DEBUG_HW_POT(core_id, 49), g_ecs_debug_info.ecs_msg_QutQue_ok);
#endif
g_ecs_hw_que_info.irq_entry(idx, len);
}
ret = smart_que_is_empty(g_ecs_hw_que_info.ecs_hq_id);
}
return ;
}
void ecs_hw_que_irq_callback(ECS_HWQUE_IRQ_FUNC func)
{
if (NULL == func)
{
#ifdef ECS_PALLADIUM_TEST
int32_t core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 38), 0xF0F0F0F0);
#endif
return ;
}
g_ecs_hw_que_info.irq_entry = func;
return ;
}
/*****************************************************/
/*********************************************************/
/* irq */
void ecs_hw_que_irq(void)
{
int32_t ret = -1;
uint32_t idx = 0;
uint32_t len = 0;
ecs_msg_head *pmsg_head = NULL;
int32_t core_id = get_core_id();
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_irq_num++;
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
debug_write(OSP_DEBUG_HW_POT(core_id, 38), g_ecs_debug_info.ecs_msg_irq_num);
#endif
ret = smart_que_is_empty(g_ecs_hw_que_info.ecs_hq_id);
while(ret == 0)
{
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_OutQue_num++;
#endif
/* out queue */
ret = smart_out_que(g_ecs_hw_que_info.ecs_hq_id, &idx);
if (0 != ret)
{
UCP_PRINT_ERROR("[ecs_hw_que_irq]: smart_out_que error... que_id = 0x%08x \r\n", g_ecs_hw_que_info.ecs_hq_id);
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_OutQue_err++;
debug_write(DBG_DDR_COMMON_IDX(core_id, 33), g_ecs_debug_info.ecs_msg_OutQue_err);
debug_write(DBG_DDR_COMMON_IDX(core_id, 34), g_ecs_debug_info.ecs_msg_irq_num);
debug_write(DBG_DDR_COMMON_IDX(core_id, 35), g_ecs_debug_info.ecs_msg_OutQue_num);
#endif
debug_write(DBG_DDR_ERR_IDX(core_id, 28), ret);
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
debug_write(OSP_DEBUG_HW_POT(core_id, 40), g_ecs_debug_info.ecs_msg_OutQue_err);
#endif
return ;
}
#ifdef ECS_PALLADIUM_TEST
g_ecs_debug_info.ecs_msg_QutQue_ok++;
#endif
UCP_PRINT_LOG("[ecs_hw_que_irq]: smart_out_que(0x%08x), addr = 0x%08x\r\n", g_ecs_hw_que_info.ecs_hq_id, idx);
if (NULL != g_ecs_hw_que_info.irq_entry)
{
pmsg_head = (ecs_msg_head*)((uint32_t)idx - (uint32_t)ECS_MSG_HEAD_LEN);
len = do_read((char*)(&pmsg_head->msg_size));
#ifdef ECS_PALLADIUM_TEST
debug_write(DBG_DDR_COMMON_IDX(core_id, 36), g_ecs_debug_info.ecs_msg_irq_num);
debug_write(DBG_DDR_COMMON_IDX(core_id, 37), g_ecs_debug_info.ecs_msg_OutQue_num);
#endif
#ifdef UCP_OSP_DBG_HW_CNT_ENABLE
uint8_t src_core_id = do_read_byte((char*)(&pmsg_head->src_core_id));
switch (src_core_id)
{
case 0:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 24), ++gu32_app_recv_que0);
break;
}
case 1:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 25), ++gu32_app_recv_que1);
break;
}
case 2:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 26), ++gu32_app_recv_que2);
break;
}
case 3:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 27), ++gu32_app_recv_que3);
break;
}
case 4:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 28), ++gu32_app_recv_que4);
break;
}
case 5:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 29), ++gu32_app_recv_que5);
break;
}
case 6:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 30), ++gu32_app_recv_que6);
break;
}
case 7:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 31), ++gu32_app_recv_que7);
break;
}
case 8:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 32), ++gu32_app_recv_que8);
break;
}
case 9:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 33), ++gu32_app_recv_que9);
break;
}
case 10:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 34), ++gu32_app_recv_que10);
break;
}
case 11:
{
debug_write(OSP_DEBUG_HW_POT(core_id, 35), ++gu32_app_recv_que11);
break;
}
default:
{
break;
}
}
debug_write(OSP_DEBUG_HW_POT(core_id, 49), g_ecs_debug_info.ecs_msg_QutQue_ok);
#endif
g_ecs_hw_que_info.irq_entry(idx, len);
}
ret = smart_que_is_empty(g_ecs_hw_que_info.ecs_hq_id);
}
return ;
}
void ecs_hw_que_irq_callback(ECS_HWQUE_IRQ_FUNC func)
{
if (NULL == func)
{
#ifdef ECS_PALLADIUM_TEST
int32_t core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 38), 0xF0F0F0F0);
#endif
return ;
}
g_ecs_hw_que_info.irq_entry = func;
return ;
}
/*****************************************************/

4
public/common/utility/inc/ucp_printf.h
View File

@ -27,9 +27,9 @@
#define PRINT_TICK 0x00000010
//#define UCP_PRINT_LEVEL (PRINT_OFF)
//#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_WARN |PRINT_LOG | PRINT_DEBUG | PRINT_TICK)
#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_WARN |PRINT_LOG | PRINT_DEBUG | PRINT_TICK)
//#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_DEBUG)
#define UCP_PRINT_LEVEL (PRINT_ERROR)
//#define UCP_PRINT_LEVEL (PRINT_ERROR)
#if (UCP_PRINT_LEVEL & PRINT_ERROR)

39
public/ecs_rfm_spu0/driver/src/rfm0_drv.s.c
View File

@ -24,17 +24,10 @@ void ecs_rfm0_drv_init(void)
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
int32_t ret = 0;
#if 1
ret = smart_irq_debug_init(DBG_DDR_IRQ_ADDR_BASE+apeId*DBG_DDR_IRQ_LEN, DBG_DDR_IRQ_LEN);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 11), ret);
}
#endif
ret = smart_irq_init(apeId);
if (0 != ret)
{
@ -43,21 +36,21 @@ void ecs_rfm0_drv_init(void)
UCP_PRINT_EMPTY("smart inter init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
ape_csu_init();
UCP_PRINT_EMPTY("ape csu init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
sfn_para_init();
UCP_PRINT_EMPTY("sfn para init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#if 1
@ -65,28 +58,28 @@ void ecs_rfm0_drv_init(void)
UCP_PRINT_EMPTY("ctc cal intr init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
rfm0_mtimer_int_init();
UCP_PRINT_EMPTY("set mtimer rfm0 int.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#endif
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* wait ecpri serdes clk init finished */
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR)));
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* wait ecpri serdes clk init finished */
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR)));
/* eCPRIÑ­»·¶ÓÁгõʼ»¯ */
ecpri_queue_init();
/* eCPRIÑ­»·¶ÓÁгõʼ»¯ */
ecpri_queue_init();
/* eCPRI CSU³õʼ»¯ */
ecpri_csu_init();
}
/* eCPRI CSU³õʼ»¯ */
ecpri_csu_init();
}
ecs_hw_que_init(apeId);
//ecs_hw_que_init_withirq(apeId, apeId);
@ -96,7 +89,7 @@ void ecs_rfm0_drv_init(void)
UCP_PRINT_EMPTY("[rfm0_drv_init]: OK \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
}

43
public/ecs_rfm_spu0/top/src/main.s.c
View File

@ -22,20 +22,21 @@
#include "phy_para.h"
#include "ecpri_queue_proc.h"
#include "ecpri_csu.h"
#include "lib_debug_init.h"
int32_t main(int32_t argc, char* argv[])
{
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU0,coreId[0x%x]", get_core_id());
debug_write(DBG_DDR_COMMON_IDX(get_core_id(), 0), PLATFORM_BUILD_DATA);
int32_t core_id = 0;
int32_t ret = 0;
/* hw_debug_init */
int32_t core_id = get_core_id();
int ret = 0;
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // 鎺ㄨ崘384锛屽疄闄?512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);
}
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU0,coreId[0x%x]", get_core_id());
core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
ret = spu_lib_debug_init(core_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
spu_log_client_init();
@ -47,19 +48,19 @@ int32_t main(int32_t argc, char* argv[])
while (1)
{
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* eCPRI循环队列轮询处理 */
ecpri_queue_proc();
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* eCPRI循环队列轮询处理 */
ecpri_queue_proc();
/* 手动触发eCPRI CSU发送数据测试 */
if (1 == do_read_volatile(ECPRI_DBG_BUF_ADDR + 0x0C))
{
ecpri_csu_send_test();
/* 手动触发eCPRI CSU发送数据测试 */
if (1 == do_read_volatile(ECPRI_DBG_BUF_ADDR + 0x0C))
{
ecpri_csu_send_test();
do_write(ECPRI_DBG_BUF_ADDR + 0x0C, 0x00);
}
}
do_write(ECPRI_DBG_BUF_ADDR + 0x0C, 0x00);
}
}
}
return 0;

120
public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c
View File

@ -31,19 +31,13 @@ void ecs_rfm1_drv_init(void)
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
SET_CLK_CFG_EMU();
SET_CLK_CFG_EMU();
//APC0_CSU_ELEVELMASK = 0xFFFFFFFF;
int32_t ret = 0;
#if 1
ret = smart_irq_debug_init(DBG_DDR_IRQ_ADDR_BASE+apeId*DBG_DDR_IRQ_LEN, DBG_DDR_IRQ_LEN);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 12), ret);
}
#endif
ret = smart_irq_init(apeId);
if (0 != ret)
{
@ -52,43 +46,43 @@ void ecs_rfm1_drv_init(void)
UCP_PRINT_EMPTY("interrupt init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
ape_csu_init();
UCP_PRINT_EMPTY("ape csu init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
sfn_para_init();
UCP_PRINT_EMPTY("sfn para init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
ctc_cal_intr_init();
UCP_PRINT_EMPTY("ctc cal intr init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
#if 1
gtimer2_init(0);
rfm1_gtimer2_1_set_int();
gtimer2_init(0);
rfm1_gtimer2_1_set_int();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
#endif
hw_gpio_init();
hw_gpio_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
ecs_hw_que_init(apeId);
@ -99,71 +93,71 @@ void ecs_rfm1_drv_init(void)
ecs_heap_mem_init(ECS_PHY_DDR_ADDR, ECS_PHY_DDR_SIZE);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
#ifdef TEST_ENABLE
fh_test_init();
fh_test_init();
#else
phy_fh_drv_init();
#endif
phy_fh_drv_init();
#endif
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
rfm_stc_init();
rfm_stc_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
}
void check_phy_cell(void)
{
//uint32_t clockBegin,clockEnd;
//int32_t clockCnt;
//uint32_t clockBegin,clockEnd;
//int32_t clockCnt;
volatile uint32_t phy_cell_flag = do_read_volatile(PHY_CELL_ADDR);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),1), phy_cell_flag);
__ucps2_synch(f_SM);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),2), 2);
if (PHY_CELL_FLAG == phy_cell_flag)
{
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),3), 3);
phy_timer_config_ind_t cellPara;
memcpy_ucp(&cellPara, (PHY_CELL_ADDR+4), sizeof(cellPara));
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),4), 4);
__ucps2_synch(f_SM);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),5), 5);
__ucps2_synch(f_SM);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),2), 2);
if (PHY_CELL_FLAG == phy_cell_flag)
{
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),3), 3);
phy_timer_config_ind_t cellPara;
memcpy_ucp(&cellPara, (PHY_CELL_ADDR+4), sizeof(cellPara));
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),4), 4);
__ucps2_synch(f_SM);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),5), 5);
//rdmcycle(&clockBegin);
// cpri_timer_reconfig(&cellPara);
int32_t ret = mtimer_reconfig(&cellPara);
//rdmcycle(&clockEnd);
//clockCnt = clockEnd - clockBegin;
//debug_write((DBG_DDR_IDX_DRV_BASE+900), clockCnt); // 0xe10
//rdmcycle(&clockBegin);
//cpri_timer_reconfig(&cellPara);
int32_t ret = mtimer_reconfig(&cellPara);
//rdmcycle(&clockEnd);
//clockCnt = clockEnd - clockBegin;
//debug_write((DBG_DDR_IDX_DRV_BASE+900), clockCnt); // 0xe10
if (-1 == ret)
{
UCP_PRINT_ERROR("mtimer_reconfig failed. \r\n");
return;
}
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),6), 6);
do_write(PHY_CELL_ADDR, 0);
__ucps2_synch(f_SM);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),7), 7);
}
if (-1 == ret)
{
UCP_PRINT_ERROR("mtimer_reconfig failed. \r\n");
return;
}
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),6), 6);
do_write(PHY_CELL_ADDR, 0);
__ucps2_synch(f_SM);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),7), 7);
}
}
void check_10ms_offset(void)
{
if (1 == get_sfnoffset_int_flag())
{
update_cpri_link_status();
cpri_delay_measurement_ck();
clear_sfnoffset_int_flag();
}
if (1 == get_sfnoffset_int_flag())
{
update_cpri_link_status();
cpri_delay_measurement_ck();
clear_sfnoffset_int_flag();
}
}

23
public/ecs_rfm_spu1/platform/src/ecs_rfm_spu1_oam.c
View File

@ -27,6 +27,8 @@
#define RFM_TEST_OAM_MSG_SIZE (8)
#define RFM_MSG_TYPE (0)
extern void phy_oam_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size);
OamMsgTransferHeader_t *g_oam_msg_ptr = NULL;
SpuOamBaseDelaySetRsp_t *g_oam_base_delay_set_rsp_ptr = NULL;
@ -55,17 +57,17 @@ void oam_msg_init(void)
void oam_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
{
uint32_t msg_type = 0;
uint32_t i = 0;
uint32_t msg_type = 0;
uint32_t i = 0;
uint32_t msg_buf = do_read(u32msg_addr);
uint32_t msg_size = do_read(u32msg_addr + 4);
uint32_t msg_size = do_read(u32msg_addr + 4);
uint8_t u8core_id = (uint8_t)get_core_id();
SpuOamBaseDelaySetReq_t *oam_base_delay_set_ptr = NULL;
SpuOamBaseDelayQryReq_t *oam_base_delay_qry_ptr = NULL;
SpuOamFiberDelayQryReq_t *oam_fiber_delay_qry_ptr = NULL;
debug_write(DBG_DDR_COMMON_IDX(u8core_id, 36), 0x12345678);
memset((void *)g_oam_msg_ptr, 0, sizeof(OamMsgTransferHeader_t));
memset((void *)g_oam_msg_ptr, 0, sizeof(OamMsgTransferHeader_t));
debug_write(DBG_DDR_COMMON_IDX(u8core_id, 38), msg_size);
ape_csu_dma_1D_G2L_ch2ch3_transfer(msg_buf, (uint64_t)((uint32_t)g_oam_msg_ptr - 0x100000), msg_size+12, 2, 1);
@ -95,10 +97,13 @@ void oam_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
oam_fiber_delay_qry_ptr = (SpuOamFiberDelayQryReq_t *)((uint8_t *)g_oam_msg_ptr + sizeof(OamMsgTransferHeader_t));
oam_fiber_delay_proc(oam_fiber_delay_qry_ptr, g_oam_msg_ptr);
break;
default:
phy_oam_msg_proc(u32msg_addr, u32msg_size);
break;
}
}
return;
return;
}
void oam_base_delay_proc(SpuOamBaseDelaySetReq_t *spu_oam_base_delay_set_ptr, OamMsgTransferHeader_t *spu_oam_msg_ptr)
@ -247,11 +252,11 @@ void oam_msg_proc_test(uint32_t u32msg_addr, uint32_t u32msg_size)
int32_t ret = 0;
char *addr = NULL;
uint32_t msg_buf = do_read(u32msg_addr);
uint32_t msg_size = do_read(u32msg_addr + 4);
uint32_t msg_size = do_read(u32msg_addr + 4);
uint8_t u8core_id = (uint8_t)get_core_id();
debug_write(DBG_DDR_COMMON_IDX(u8core_id, 36), 0x1234abcd);//0xb7e01690
memset((void *)g_oam_msg_ptr, 0, sizeof(OamMsgTransferHeader_t));
memset((void *)g_oam_msg_ptr, 0, sizeof(OamMsgTransferHeader_t));
debug_write(DBG_DDR_COMMON_IDX(u8core_id, 38), msg_size);
ape_csu_dma_1D_G2L_ch2ch3_transfer(msg_buf, (uint64_t)((uint32_t)g_oam_msg_ptr - 0x100000), msg_size+12, 2, 1);
@ -285,7 +290,7 @@ void oam_msg_proc_test(uint32_t u32msg_addr, uint32_t u32msg_size)
debug_write(DBG_DDR_COMMON_IDX(u8core_id, 44), 0x5678abcd);
return;
return;
}

60
public/ecs_rfm_spu1/top/src/main.s.c
View File

@ -28,6 +28,7 @@
#include "phy_para.h"
#include "hw_cpri.h"
#include "hwque.h"
#include "lib_debug_init.h"
#ifdef TEST_ENABLE
#include "fh_test.h"
@ -57,38 +58,37 @@ extern uint32_t gCpriCsuDummyFlag;
int32_t main(int32_t argc, char* argv[])
{
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU1,coreId[0x%x]", get_core_id());
debug_write(DBG_DDR_COMMON_IDX(get_core_id(), 0), PLATFORM_BUILD_DATA);
int32_t core_id = 0;
int32_t ret = 0;
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU1,coreId[0x%x]", get_core_id());
core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
ret = spu_lib_debug_init(core_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
/* hw_debug_init */
int32_t core_id = get_core_id();
#ifdef PALLADIUM_TEST
int flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
int flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
#endif
int ret = 0;
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // ÍƼö384£¬Êµ¼Ê512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);
}
spu_log_client_init();
spu_log_server_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
ecs_rfm_spu1_drv_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
ecs_rfm_spu1_msg_transfer_init();
spu_shell_init();
@ -96,24 +96,24 @@ int32_t main(int32_t argc, char* argv[])
spu_shell_cpri_cmd();
oam_msg_init();
while (1)
{
#ifdef TEST_ENABLE
do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
do_write(CSU_RX_TD_SAMPLE, 10000);
check_test_outcome(0);
do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
do_write(CSU_RX_TD_SAMPLE, 10000);
check_test_outcome(0);
#endif
phy_queue_polling();
if (PROTOCOL_CPRI == get_protocol_sel())
{
check_cpri();
if (PROTOCOL_CPRI == get_protocol_sel())
{
check_cpri();
check_10ms_offset();
}
check_10ms_offset();
}
spu_log_server_proc();
spu_shell_task();

303
public/ecs_rfm_spu1/top/src/phy_init.s.c
View File

@ -31,16 +31,16 @@ uint8_t gu8_send_del_task_cnt = 0;
int32_t phy_fh_drv_init()
{
#ifdef DISTRIBUTED_BS
cpri_init(CPRI_OPTION_8, NR4T4R_7DS2U);
cpri_init(CPRI_OPTION_8, NR4T4R_7DS2U);
#endif
#ifdef ECPRI_DISTRIBUTED_BS
ecpri_init(ECPRI_OPTION_10G);
ecpri_init(ECPRI_OPTION_10G);
#endif
#ifdef INTEGRATED_BS
jesd_init();
jesd_init();
#endif
return 0;
return 0;
}
void ecs_rfm1_send_create_task_info(uint8_t dst_core_id)
@ -55,7 +55,7 @@ void ecs_rfm1_send_create_task_info(uint8_t dst_core_id)
debug_write(DBG_DDR_COMMON_IDX(core_id, 59), dst_core_id);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 4), (uint32_t)addr);
debug_write(DBG_DDR_COMMON_IDX(core_id, 4), (uint32_t)addr);
do_write(addr, 0xa1a2a3a4);
do_write((addr+4), 0xb1b2b3b4);
ret = osp_send_msg((uint32_t)(addr),
@ -65,7 +65,7 @@ void ecs_rfm1_send_create_task_info(uint8_t dst_core_id)
dst_core_id, // dst que id
50, // src task id
50); // dst task id
if (0 != ret)
{
debug_write(DBG_DDR_COMMON_IDX(core_id, 58), 0xa2);
@ -88,7 +88,7 @@ void ecs_rfm1_send_del_task_info(uint8_t dst_core_id)
debug_write(DBG_DDR_COMMON_IDX(core_id, 62), dst_core_id);
return ;
}
debug_write(DBG_DDR_COMMON_IDX(core_id, 4), (uint32_t)addr);
debug_write(DBG_DDR_COMMON_IDX(core_id, 4), (uint32_t)addr);
do_write(addr, 0xa1a2a3a4);
do_write((addr+4), 0xb1b2b3b4);
ret = osp_send_msg((uint32_t)(addr),
@ -98,7 +98,7 @@ void ecs_rfm1_send_del_task_info(uint8_t dst_core_id)
dst_core_id, // dst que id
51, // src task id
51); // dst task id
if (0 != ret)
{
debug_write(DBG_DDR_COMMON_IDX(core_id, 61), 0xa2);
@ -111,176 +111,181 @@ void ecs_rfm1_send_del_task_info(uint8_t dst_core_id)
void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
{
phy_timer_config_ind_t my_cpritmr;
phy_timer_config_ind_t my_cpritmr;
my_cpritmr.scsId = scsId;
if ((0 == cellId) || ((1 == cellId)))
{
my_cpritmr.runCoreId = coreId;
}
else
{
my_cpritmr.runCoreId = 0;
}
if (NR_SCS_30K == scsId)
{
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 20;
my_cpritmr.num_t_dl[0] = 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 4; // ul symbol num
my_cpritmr.num_ants[0] = 4;
}
else if (LTE_SCS_ID == scsId)
{
my_cpritmr.t_period = 10000;
my_cpritmr.t_us = 1000;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 10;
my_cpritmr.num_t_dl[0] =10;// 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 14;//6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 14;//4; // ul symbol num
my_cpritmr.num_ants[0] = 2;
}
else
{
return;
}
my_cpritmr.scsId = scsId;
if ((0 == cellId) || ((1 == cellId)))
{
my_cpritmr.runCoreId = coreId;
}
else
{
my_cpritmr.runCoreId = 0;
}
mtimer_init4phy(&my_cpritmr);
if (NR_SCS_30K == scsId)
{
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 20;
uint32_t apeId = 0;
uint32_t runCore = my_cpritmr.runCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
while (h1Pos != 32)
{
apeId = 31 - h1Pos;
if (8 <= apeId)
{
return;
}
my_cpritmr.num_t_dl[0] = 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 4; // ul symbol num
my_cpritmr.num_ants[0] = 4;
}
else if (LTE_SCS_ID == scsId)
{
my_cpritmr.t_period = 10000;
my_cpritmr.t_us = 1000;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 10;
ecs_rfm1_send_create_task_info(apeId);
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
}
my_cpritmr.num_t_dl[0] =10;// 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 14;//6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 14;//4; // ul symbol num
my_cpritmr.num_ants[0] = 2;
}
else
{
return;
}
//for (int32_t coreId = 0; coreId < 4; coreId++)
{
//ecs_rfm1_send_create_task_info(coreId);
}
mtimer_init4phy(&my_cpritmr);
uint32_t apeId = 0;
uint32_t runCore = my_cpritmr.runCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
while (h1Pos != 32)
{
apeId = 31 - h1Pos;
if (8 <= apeId)
{
return;
}
ecs_rfm1_send_create_task_info(apeId);
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
}
//for (int32_t coreId = 0; coreId < 4; coreId++)
{
//ecs_rfm1_send_create_task_info(coreId);
}
}
void ecs_rfm1_delete_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
{
int32_t ret = 0;
int32_t ret = 0;
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+52), flag); // 0xb7e060d0
#endif
stPhyDelCell myDelCell;
myDelCell.scsId = scsId;
if ((0 == cellId) || (1 == cellId))
{
myDelCell.delCoreId = coreId;
}
else
{
myDelCell.delCoreId = 0;
}
uint32_t apeId = 0;
uint32_t runCore = myDelCell.delCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
while (h1Pos != 32)
{
apeId = 31 - h1Pos;
if (8 <= apeId)
{
return;
}
ecs_rfm1_send_del_task_info(apeId);
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+52), flag); // 0xb7e060d0
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+52), flag); // 0xb7e060d0
#endif
ret = mtimer_del_cell_cfg(&myDelCell);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+52), flag); // 0xb7e060d0
#endif
}
stPhyDelCell myDelCell;
myDelCell.scsId = scsId;
if ((0 == cellId) || (1 == cellId))
{
myDelCell.delCoreId = coreId;
}
else
{
myDelCell.delCoreId = 0;
}
volatile uint32_t gCellFlag = 0;
void phy_init(void)
{
gCellFlag = 0;
return;
}
uint32_t apeId = 0;
uint32_t runCore = myDelCell.delCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
while (h1Pos != 32)
{
apeId = 31 - h1Pos;
if (8 <= apeId)
{
return;
}
ecs_rfm1_send_del_task_info(apeId);
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+52), flag); // 0xb7e060d0
#endif
ret = mtimer_del_cell_cfg(&myDelCell);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+52), flag); // 0xb7e060d0
#endif
}
volatile uint32_t gCellFlag = 0;
void phy_init(void)
{
gCellFlag = 0;
return;
}
void phy_oam_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
{
return ;
}
void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
{
uint32_t msg_buf = do_read(u32msg_addr);
uint32_t msg_type = do_read(msg_buf);
uint32_t msg_buf = do_read(u32msg_addr);
uint32_t msg_type = do_read(msg_buf);
if (CELL_SETUP_TYPE_SIMULATION == msg_type)
{
uint32_t msg_new_del = do_read(msg_buf+12); // 0; //
uint32_t scs_id = do_read(msg_buf+16); // 1; //
uint32_t cell_id = do_read(msg_buf+20); // 0; //
uint32_t run_core = do_read(msg_buf+24);
memcpy_ucp(0x60000000, msg_buf, 32); // temp code
if (1 < msg_new_del)
{
return;
}
if (NR_SCS_120K < scs_id)
{
return;
}
{
uint32_t msg_new_del = do_read(msg_buf+12); // 0; //
uint32_t scs_id = do_read(msg_buf+16); // 1; //
uint32_t cell_id = do_read(msg_buf+20); // 0; //
uint32_t run_core = do_read(msg_buf+24);
if (0 == msg_new_del)
{
ecs_rfm1_build_cell(scs_id, cell_id, run_core);
}
else
{
ecs_rfm1_delete_cell(scs_id, cell_id, run_core);
}
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),1), 0x12345678);
}
memcpy_ucp(0x60000000, msg_buf, 32); // temp code
return;
if (1 < msg_new_del)
{
return;
}
if (NR_SCS_120K < scs_id)
{
return;
}
if (0 == msg_new_del)
{
ecs_rfm1_build_cell(scs_id, cell_id, run_core);
}
else
{
ecs_rfm1_delete_cell(scs_id, cell_id, run_core);
}
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),1), 0x12345678);
}
return;
}
uint32_t gDdrCallCnt = 0;
void ddr_wr_callback()
{
gDdrCallCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+127), gDdrCallCnt); // 0x1fc
gDdrCallCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+127), gDdrCallCnt); // 0x1fc
}
uint32_t gFapiCallCnt = 0;
void rfm1_fapi_callback()
{
gFapiCallCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+123), gFapiCallCnt); // 0x1ec
{
gFapiCallCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+123), gFapiCallCnt); // 0x1ec
}

13
public/pet_rfm_spu0/top/src/main.s.c
View File

@ -20,15 +20,22 @@
#include "ucp_printf.h"
#include "testcase.h"
#include "phy_para.h"
#include "lib_debug_init.h"
//#include "stc_timer.h"
int32_t main(int32_t argc, char* argv[])
{
//SET_CLK_CFG_EMU();
int ret = FAILURE;
int32_t core_id = 0;
int ret = FAILURE;
UCP_PRINT_LOG("Hello world from PET RFM SPU0,coreId[0x%x]", get_core_id());
debug_write(DBG_DDR_COMMON_IDX(get_core_id(), 0), PLATFORM_BUILD_DATA);
core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
ret = spu_lib_debug_init(core_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
pet_rfm_spu0_drv_init();

20
public/pet_rfm_spu1/top/src/main.s.c
View File

@ -20,20 +20,20 @@
#include "spu_shell.h"
#include "pet_rfm_spu1_oam.h"
#include "hwque.h"
#include "lib_debug_init.h"
int32_t main(int32_t argc, char* argv[])
{
UCP_PRINT_EMPTY("Hello world from PET RFM SPU1,coreId[0x%x]", get_core_id());
debug_write(DBG_DDR_COMMON_IDX(get_core_id(), 0), PLATFORM_BUILD_DATA);
int32_t core_id = 0;
int32_t ret = 0;
/* hw_debug_init */
int32_t core_id = get_core_id();
int ret = 0;
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // ÍƼö384£¬Êµ¼Ê512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);
}
UCP_PRINT_EMPTY("Hello world from PET RFM SPU1,coreId[0x%x]", get_core_id());
core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
ret = spu_lib_debug_init(core_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
spu_log_client_init();