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Merge branch 'dev_ck_v2.1_EVB_feature#1214#' into 'dev_ck_v2.1'

Browse Source 
UCP4008_SL_EVB feature enhancement#1214#

See merge request ucp/driver/ucp4008_platform_spu!51
This commit is contained in:
Xianfeng Du 2023-10-26 00:11:46 +00:00
commit 41fa8df011
68 changed files with 294 additions and 743052 deletions
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15
inc/drv_rfm.h
View File

@ -162,6 +162,12 @@ typedef struct _tagPhyDelCell
uint32_t scsId;
uint32_t delCoreId; // 此次需要删除小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。
}stPhyDelCell;
typedef struct CpriRruMsg
{
uint32_t msg_addr;
uint32_t msg_len;
}CpriRruMsg_t;
/*
函数名称：mtimer_init4phy
@ -193,6 +199,15 @@ void get_cpri_delay(uint32_t* delay);
函数功能：获取cpri的发送提前量
*/
void get_cpri_advance(uint32_t* advance);
/*
函数名称：set_cpri_rru_msg
函数入参：
CpriRruMsg_t rru_msg: 透传的消息信息结构体
函数功能：物理层通过cpri headerram向rru透传消息的接口
*/
int32_t set_cpri_rru_msg(CpriRruMsg_t rru_msg);
/**************************************************/
/* ape csu相关 */

2
public/ape_spu/driver/src/ape_cpri_timer.s.c
View File

@ -37,7 +37,7 @@ int32_t clr_cpri_timer_ape_int(void)
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
UCP_PRINT_ERROR("detach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;

4
public/ape_spu/driver/src/ape_ecpri_timer.s.c
View File

@ -39,7 +39,7 @@ int32_t clr_ecpri_timer_ape_int(void)
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
UCP_PRINT_ERROR("detach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;
@ -51,4 +51,4 @@ int32_t clr_ecpri_timer_ape_int(void)
void isr_ecpri_ape_slot_offset(void)
{
mtimer_ape_slot_callback(MTIMER_ECPRI_ID);
}
}

2
public/ape_spu/driver/src/ape_jesd_timer.s.c
View File

@ -63,7 +63,7 @@ int32_t clr_jesd_timer_ape_int(int32_t nTmrId)
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
UCP_PRINT_ERROR("detach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;

7
public/ape_spu/driver/src/ape_mtimer.s.c
View File

@ -127,12 +127,7 @@ int32_t mtimer_sfn_para_init(int32_t nTmrId, int32_t nScsId)
gCellSfnPara[nTmrId].txSfnNum = 0; // 1023;
gCellSfnPara[nTmrId].rxSlotNum = gCellSfnPara[nTmrId].slotMaxNum - 1;
gCellSfnPara[nTmrId].rxSfnNum = 1023;
#if 0
debug_write((DBG_DDR_IDX_DRV_BASE+48), gCellSfnPara[nTmrId].scsId); // 0xC0
debug_write((DBG_DDR_IDX_DRV_BASE+49), do_read_volatile_short(&(phyPara[gScsId].slotPeriod))); // 0xC4
debug_write((DBG_DDR_IDX_DRV_BASE+50), do_read_volatile_short(&(phyPara[gScsId].slotNumOfTdd))); // 0xC8
debug_write((DBG_DDR_IDX_DRV_BASE+51), do_read_volatile_short(&(phyPara[gScsId].slotNumOfSfn))); // 0xCC
#endif
return 0;
}

3
public/common/driver/inc/phy_para.h
View File

@ -56,6 +56,9 @@
#define DDR_MONITOR_ENABLE (SPU_DRV_SM_ADDR+0x270) // 开始监测ddr性能
#define DDR_MONITOR_CNT (SPU_DRV_SM_ADDR+0x274)
#define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // us as unit
#define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C)
// GPIO JESD TX/RX/ORX bit
#define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280)
#define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0)

7
public/common/driver/src/ctc_intr.s.c
View File

@ -75,13 +75,6 @@ void isr_ctc_cal(void)
{
do_write(((uint32_t*)(&SYSC_CTC28_REG)+apeId), 0); // clear int
gCellSfnPara[type-1].ctcIntFlag = 1;
#if 0
int32_t scsId = gCellSfnPara[gMtimerId].scsId;
gCellSfnPara[gMtimerId].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));
gCellSfnPara[gMtimerId].rxSfnNum = do_read_volatile(&(phyPara[scsId].rxSfnNum));
gCellSfnPara[gMtimerId].txSlotNum = do_read_volatile(&(phyPara[scsId].txSlotNum));
gCellSfnPara[gMtimerId].rxSlotNum = do_read_volatile(&(phyPara[scsId].rxSlotNum));
#endif
}
}

4
public/common/ecs_dm/inc/ecs_rfm_dm_mgt.h
View File

@ -38,11 +38,15 @@ typedef struct tEcsRfmDmLocalMgt {
stCpriGetRndDelay* pOamFiberDelayQryRspPtr ;
stCpriFrameHeadOffsetRsp* pOamFrameHeadOffsetRspPtr ;
stCpriGetFrameHeadOffset* pOamFrameHeadOffsetQryRspPtr;
stCpriCsuCmdFifoInfo* tx_cmd_fifo_ptr;
stCpriCsuCmdFifoInfo* rx_cmd_fifo_ptr;
} EcsRfmDmLocalMgt_t;
EcsRfmDmLocalMgt_t* get_ecs_rfm_dm_local_mgt(void);
int32_t ecs_rfm_dm_alloc(void);
int32_t ecs_rfm1_dm_init(void);
#endif

19
public/common/ecs_dm/inc/hw_cpri.h
View File

@ -61,6 +61,25 @@ typedef struct _tagCpriIntStat
//uint32_t gScrRxRfpValH;
}stCpriIntStat;
typedef struct
{
uint32_t cmd32l;
uint32_t cmd14h;
}stCpriCsuCmd;
typedef struct
{
uint32_t cmd_num;
stCpriCsuCmd cmd[10];
}stCpriCsuCmdFifo;
typedef struct
{
uint32_t cmdFifo_num;
stCpriCsuCmdFifo cmdFifo[8];
}stCpriCsuCmdFifoInfo;
void cpri_init(uint32_t option,uint32_t MappingMode);
void cpri_ecprimode_init();

104
public/common/ecs_dm/src/ecs_rfm_dm_mgt.s.c
View File

@ -97,6 +97,110 @@ int32_t ecs_rfm_dm_alloc(void)
}
}
pEcsDmLocalMgt->tx_cmd_fifo_ptr = (stCpriCsuCmdFifoInfo*)memSectionAlloc(pMemSection, sizeof(stCpriCsuCmdFifoInfo), MEM_ALIGNED_4BYTES, "tx_cmd_fifo");
if (NULL == pEcsDmLocalMgt->tx_cmd_fifo_ptr)
{
return -1;
}
pEcsDmLocalMgt->rx_cmd_fifo_ptr = (stCpriCsuCmdFifoInfo*)memSectionAlloc(pMemSection, sizeof(stCpriCsuCmdFifoInfo), MEM_ALIGNED_4BYTES, "rx_cmd_fifo");
if (NULL == pEcsDmLocalMgt->rx_cmd_fifo_ptr)
{
return -1;
}
return 0;
}
int32_t ecs_rfm1_dm_init(void)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
if (NULL == pEcsDmLocalMgt)
{
return -1;
}
if (NULL == pEcsDmLocalMgt->pCpriPara)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pCpriPara, 0, sizeof(stCpriPara));
if (NULL == pEcsDmLocalMgt->pCpriDelay)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pCpriDelay, 0, sizeof(stCpriDelayMeasure));
if (NULL == pEcsDmLocalMgt->pGpioInfo)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pGpioInfo, 0, sizeof(stGpioOnBoard));
if (NULL == pEcsDmLocalMgt->pAlarmStatus)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pAlarmStatus, 0, sizeof(stFhAlarmStat));
if (NULL == pEcsDmLocalMgt->pOamMsgPtr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pOamMsgPtr, 0, sizeof(stOamMsgTransferHeader));
if (NULL == pEcsDmLocalMgt->pOamBaseDelaySetRspPtr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pOamBaseDelaySetRspPtr, 0, sizeof(stCpriSetLinkDelay));
if (NULL == pEcsDmLocalMgt->pOamBaseDelayQryRspPtr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pOamBaseDelayQryRspPtr, 0, sizeof(stCpriGetLinkDelay));
if (NULL == pEcsDmLocalMgt->pOamFiberDelayQryRspPtr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pOamFiberDelayQryRspPtr, 0, sizeof(stCpriGetRndDelay));
if (NULL == pEcsDmLocalMgt->pOamFrameHeadOffsetRspPtr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pOamFrameHeadOffsetRspPtr, 0, sizeof(stCpriFrameHeadOffsetRsp));
for (int i = 0; i < MTIMER_INTEGRATED_MAX_NUM; i++)
{
if (NULL == pEcsDmLocalMgt->pMtimerPara[i])
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pMtimerPara[i], 0, sizeof(stMtimerPara));
}
if (NULL == pEcsDmLocalMgt->pOamFrameHeadOffsetQryRspPtr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->pOamFrameHeadOffsetQryRspPtr, 0, sizeof(stCpriGetFrameHeadOffset));
if (NULL == pEcsDmLocalMgt->tx_cmd_fifo_ptr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->tx_cmd_fifo_ptr, 0, sizeof(stCpriCsuCmdFifoInfo));
if (NULL == pEcsDmLocalMgt->rx_cmd_fifo_ptr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->rx_cmd_fifo_ptr, 0, sizeof(stCpriCsuCmdFifoInfo));
return 0;
}

20
public/ecs_rfm_spu0/driver/src/rfm0_mtimer.s.c
View File

@ -28,25 +28,7 @@ int32_t rfm0_mtimer_int_init(void)
return 0;
}
#if 0
void phy_cell_para_init(int32_t nScsId)
{
memset_ext((void*)pPhyCellPara, 0, sizeof(stPhyCellPara));
__ucps2_synch(f_SMW);
memset(&gCellSfnPara[gMtimerId], 0, sizeof(stSfnPara));
gScsId = nScsId;
gCellSfnPara[gMtimerId].scsId = gScsId;
gCellSfnPara[gMtimerId].slotPeriod = do_read_volatile_short(&(phyPara[gScsId].slotPeriod)); // 500; //
gCellSfnPara[gMtimerId].tddSlotNum = do_read_volatile_short(&(phyPara[gScsId].slotNumOfTdd)); // 10; //
gCellSfnPara[gMtimerId].slotMaxNum = do_read_volatile_short(&(phyPara[gScsId].slotNumOfSfn)); // 20; //
__ucps2_synch(f_SMR);
gCellSfnPara[gMtimerId].txSlotNum = gCellSfnPara[gMtimerId].slotMaxNum - 1;
gCellSfnPara[gMtimerId].txSfnNum = 1023;
gCellSfnPara[gMtimerId].rxSlotNum = gCellSfnPara[gMtimerId].slotMaxNum - 1;
gCellSfnPara[gMtimerId].rxSfnNum = 1023;
}
#endif
int32_t gRfm0CalFlag = 0;
int32_t gRfm0CalCnt = 0;
int32_t ecs_rfm0_cal_sfn(uint8_t nTmrId)

22
public/ecs_rfm_spu1/driver/inc/cpri_csu_api.h
View File

@ -16,6 +16,7 @@
#include <typedef.h>
#include "ucp_csu.h"
#include "ape_csu.h"
#include "hw_cpri.h"
//#define CPRI_API_TEST 1 // 定义测试宏开关
@ -50,25 +51,6 @@ typedef enum _tagCpriCsuLatchFlushID
CPRI_CSU_RX1_LATCH_FLUSH_ID
}numCpriCsuLatchFlushID;
typedef struct
{
uint32_t cmd32l;
uint32_t cmd14h;
}stCpriCsuCmd;
typedef struct
{
uint32_t cmd_num;
stCpriCsuCmd cmd[10];
}stCpriCsuCmdFifo;
typedef struct
{
uint32_t cmdFifo_num;
stCpriCsuCmdFifo cmdFifo[8];
}stCpriCsuCmdFifoInfo;
extern uint32_t UCP_API_CPRI_CSU_Init(uint32_t Cfg_BusRegNum, uint32_t Clr_CpriDmaRegGroup, uint32_t DmaTagMask);
extern void UCP_API_CPRI_CSU_RxInLatch_Cfg(uint32_t AxcIdNum,
@ -162,7 +144,7 @@ uint32_t UCP_API_CPRI_CSU_Get_LatchNum();
extern void UCP_API_CPRI_CSU_Get_CmdFIFO(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo);
void UCP_API_CPRI_CSU_START(stCpriCsuCmdFifoInfo tx_cmdfifo, stCpriCsuCmdFifoInfo rx_cmdfifo);
void UCP_API_CPRI_CSU_START(void);
void UCP_API_CPRI_CSU_STOP();

54
public/ecs_rfm_spu1/driver/src/cpri_csu_api.s.c
View File

@ -19,15 +19,13 @@
#include "cpri_csu.h"
#include "phy_para.h"
#include "mtimer_com.h"
#include "ecs_rfm_dm_mgt.h"
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
//extern stSfnPara gCellSfnPara[2];
extern uint32_t* gCpriCsuStopCmd;
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
uint32_t CsuStopFlag;
uint32_t gCpriCsuCmdCnt = 0;
uint32_t gCpriAxcIdNum = 0;
@ -845,16 +843,22 @@ uint32_t UCP_API_CPRI_CSU_Get_LatchNum()
void UCP_API_CPRI_CSU_Get_CmdFIFO(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo)
{
memcpy_ucp(&txCmdFifo, pTxCmdFifo, sizeof(stCpriCsuCmdFifoInfo));
memcpy_ucp(&rxCmdFifo, pRxCmdFifo, sizeof(stCpriCsuCmdFifoInfo));
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stCpriCsuCmdFifoInfo* tx_cmd_fifo_ptr = pEcsDmLocalMgt->tx_cmd_fifo_ptr;
stCpriCsuCmdFifoInfo* rx_cmd_fifo_ptr = pEcsDmLocalMgt->rx_cmd_fifo_ptr;
memcpy_ucp(tx_cmd_fifo_ptr, pTxCmdFifo, sizeof(stCpriCsuCmdFifoInfo));
memcpy_ucp(rx_cmd_fifo_ptr, pRxCmdFifo, sizeof(stCpriCsuCmdFifoInfo));
}
void UCP_API_CPRI_CSU_START(stCpriCsuCmdFifoInfo tx_cmdfifo, stCpriCsuCmdFifoInfo rx_cmdfifo)
void UCP_API_CPRI_CSU_START(void)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stCpriCsuCmdFifoInfo* pTxCmdFifo = pEcsDmLocalMgt->tx_cmd_fifo_ptr;
stCpriCsuCmdFifoInfo* pRxCmdFifo = pEcsDmLocalMgt->rx_cmd_fifo_ptr;
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
uint32_t slotId = pMtimerSfn->txSlotNum; // get_tx_nr_slot(NR_SCS_30K);
// uint32_t slotIdMax = gCellSfnPara[MTIMER_CPRI_ID].slotMaxNum-1;
uint32_t cmdId = 0;
if (1 == *gCpriCsuStopCmd)
@ -862,44 +866,22 @@ void UCP_API_CPRI_CSU_START(stCpriCsuCmdFifoInfo tx_cmdfifo, stCpriCsuCmdFifoInf
CsuStopFlag = 1;
return;
}
#if 0
if (slotId == 19) // first 2.5ms int
{
cmdId = 0;
}
else if (slotId == 4) // second 2.5ms int
{
cmdId = 1;
}
else if (slotId == 9) // third 2.5ms int
{
cmdId = 2;
}
else if (slotId == 14) // fourth 2.5ms int
{
cmdId = 3;
}
else
{
return;
}
#else
cmdId = pMtimerInt->csuEnCnt & 0x3; //gCpriCsuCmdCnt & 0x3;
#endif
debug_write(((DBG_DDR_IDX_DRV_BASE+704) + ((pMtimerInt->csuEnCnt<<2)&0x7F)), slotId); // 0xb00
debug_write(((DBG_DDR_IDX_DRV_BASE+704) + (((pMtimerInt->csuEnCnt<<2)+1)&0x7F)), UCP_API_CPRI_GetTxHfnCnt()); // 0xb00
debug_write(((DBG_DDR_IDX_DRV_BASE+704) + (((pMtimerInt->csuEnCnt<<2)+2)&0x7F)), tx_cmdfifo.cmdFifo[cmdId].cmd_num); // 0xb00
debug_write(((DBG_DDR_IDX_DRV_BASE+704) + (((pMtimerInt->csuEnCnt<<2)+3)&0x7F)), rx_cmdfifo.cmdFifo[cmdId].cmd_num); // 0xb00
debug_write(((DBG_DDR_IDX_DRV_BASE+704) + (((pMtimerInt->csuEnCnt<<2)+2)&0x7F)), pTxCmdFifo->cmdFifo[cmdId].cmd_num); // 0xb00
debug_write(((DBG_DDR_IDX_DRV_BASE+704) + (((pMtimerInt->csuEnCnt<<2)+3)&0x7F)), pRxCmdFifo->cmdFifo[cmdId].cmd_num); // 0xb00
//debug_write(((DBG_DDR_IDX_DRV_BASE+832) + (gCpriCsuCmdCnt&0x3F)), GET_STC_CNT()); // 0xd00
gCpriCsuCmdCnt++;
for (uint8_t i = 0; i < rx_cmdfifo.cmdFifo[cmdId].cmd_num; i++)
for (uint8_t i = 0; i < pRxCmdFifo->cmdFifo[cmdId].cmd_num; i++)
{
UCP_API_CPRI_CSU_RxAxcData_Fifo0Cmd(rx_cmdfifo.cmdFifo[cmdId].cmd[i].cmd14h, rx_cmdfifo.cmdFifo[cmdId].cmd[i].cmd32l);
UCP_API_CPRI_CSU_RxAxcData_Fifo0Cmd(pRxCmdFifo->cmdFifo[cmdId].cmd[i].cmd14h, pRxCmdFifo->cmdFifo[cmdId].cmd[i].cmd32l);
}
for (uint8_t i = 0; i < tx_cmdfifo.cmdFifo[cmdId].cmd_num; i++)
for (uint8_t i = 0; i < pTxCmdFifo->cmdFifo[cmdId].cmd_num; i++)
{
UCP_API_CPRI_CSU_TxAxcData_Fifo1Cmd(tx_cmdfifo.cmdFifo[cmdId].cmd[i].cmd14h, tx_cmdfifo.cmdFifo[cmdId].cmd[i].cmd32l);
UCP_API_CPRI_CSU_TxAxcData_Fifo1Cmd(pTxCmdFifo->cmdFifo[cmdId].cmd[i].cmd14h, pTxCmdFifo->cmdFifo[cmdId].cmd[i].cmd32l);
}
#if 0
if (1 == gCpriCsuCmdCnt)

6
public/ecs_rfm_spu1/driver/src/cpri_test_mode.s.c
View File

@ -23,8 +23,6 @@ DDR0 uint32_t test_srcImData[4*1024] = {0};
// uint32_t test_srcImData[4*1024] = {0};
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern volatile uint32_t CsuStopFlag ;
extern uint32_t gCpriCsuCmdCnt;
extern stCpriIntStat gCpriIntStatus;
@ -60,8 +58,8 @@ void Axc_data_test_init()
//uint32_t* srcImData = dmalloc(10240, DM0);
debug_write((DBG_DDR_IDX_CPRI_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
debug_write((DBG_DDR_IDX_CPRI_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304
//debug_write((DBG_DDR_IDX_CPRI_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
//debug_write((DBG_DDR_IDX_CPRI_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304
uint32_t cpyCnt = 0;
debug_write((DBG_DDR_IDX_CPRI_BASE+196+(cpyCnt<<2)), (uint32_t)test_srcImData); // 0x310

27
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -34,10 +34,7 @@
extern stPhyScsPara* phyPara;
//extern stSfnPara gCellSfnPara[2];
extern uint32_t gScsId;
extern uint32_t gMtimerId;
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern stCpriIntStat gCpriIntStatus;
//stCpriTimerPara gCpriTimerPara;
@ -748,7 +745,7 @@ void isr_cpri_10ms(void)
#endif
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+1), pMtimerInt->pp1sIntCnt); // 0x104
#ifdef PALLADIUM_TEST
#if 0//def PALLADIUM_TEST
//debug_write((DBG_DDR_IDX_DRV_BASE+576+(gCpriTimerPara.pp1sIntCnt&0x3f)), get_tx_nr_slot(1)); // 0xB7E06900
uint32_t val = 0;
@ -1001,22 +998,6 @@ void isr_cpri_slot_offset(void)
{
reCfgFlag = 0;
}
#if 0
if (0 == pMtimerInt->txSlotIntCnt)
{
// init cal
pMtimerCal->sfnCalFinished = 0;
uint32_t lockFlag = do_read_volatile(ARM_LOCK_FLAG_ADDR);
if (0 == lockFlag)
{
do_write(ARM_SFN_VALID_ADDR, ARM_SFN_VALID_FLAG);
do_write(ARM_SFN_NUM_ADDR, 0x1);
do_write(ARM_SFN_FLIP_ADDR, 0x1);
//do_write(ARM_LOCK_FLAG_ADDR, 0x1);
}
__ucps2_synch(f_SMW);
}
#endif
pMtimerSfn->txSlotTiming = GET_STC_CNT();
pMtimerSfn->txSlotNum++;
__ucps2_synch(0);
@ -1031,7 +1012,7 @@ void isr_cpri_slot_offset(void)
{
set_trigger_state(GPIO_OFF);
}
__ucps2_synch(0);
//__ucps2_synch(0);
#if 0
uint32_t readFlag = do_read_volatile(0x0A4D7248);
__ucps2_synch(0);
@ -1111,7 +1092,7 @@ void isr_cpri_slot_offset(void)
pMtimerSfn->rxSfnNum &= 0x3FF;
pMtimerSfn->rxSlotNum = 0;
}
__ucps2_synch(0);
//__ucps2_synch(0);
#ifdef PALLADIUM_TEST
if (8 > pMtimerInt->rxSlotIntCnt)
@ -1188,7 +1169,7 @@ void cpri_tdd_start_csu_7ds2u()
#endif
{
// start csu
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
pMtimerInt->csuEnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), pMtimerInt->csuEnCnt); // 0x118
}

8
public/ecs_rfm_spu1/driver/src/gpio_drv.s.c
View File

@ -75,8 +75,8 @@ int32_t hw_gpio_init()
}
else
{
do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x000F0000)); // pinmux, GPIO1B25 and GPIO1B24, gpio func, 0x3
do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25))); // GPIO1B25, output, 10ms trigger for phy
do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x030C0000)); // pinmux, GPIO1B25 and GPIO1B28, gpio func, 0x3
do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25)|(BIT28))); // GPIO1B25, output, 10ms trigger for phy
}
return 0;
@ -175,11 +175,11 @@ int32_t set_trigger_state(uint8_t nState)
{
if (GPIO_ON == nState)
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT25)); // GPIO1B25, high
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT25|BIT28)); // GPIO1B25 and GPIO1B28, high
}
else
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT25)))); // GPIO1B25, low
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT25))&(~(BIT28)))); // GPIO1B25 and GPIO1B28, low
}
}

3
public/ecs_rfm_spu1/driver/src/hw_cpri.s.c
View File

@ -21,9 +21,6 @@ volatile stCpriIntStat gCpriIntStatus;
extern uint32_t reCfgFlag;
extern volatile uint32_t gVendorFlag;
stCpriCsuCmdFifoInfo txCmdFifo;
stCpriCsuCmdFifoInfo rxCmdFifo;
void cpri_init(uint32_t option, uint32_t MappingMode)
{
#ifdef PALLADIUM_TEST

173
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -21,17 +21,14 @@
#include "gtimer_drv.h"
#include "gpio_drv.h"
//#ifdef INTEGRATED_BS
#ifdef TEST_ENABLE
#include "jesd_test.h"
#endif
//#endif
//stJesdTimerPara gJesdTmrPara[2];
extern stPhyScsPara* phyPara;
extern stSfnPara gCellSfnPara[2];
extern uint32_t gScsId;
extern uint32_t gMtimerId;
uint32_t gJesdTestMode = 0;
uint32_t gJesdIOMode = JESD_CSU_CTRL;
@ -50,9 +47,6 @@ int32_t gCsuRxAdvanceNs = JESD_RX_ADVANCE_NS - JESD_RRU_TD;
extern void rfm1_fapi_callback();
//#ifdef INTEGRATED_BS
//volatile uint32_t reCfgFlag = 0;
extern uint32_t reCfgFlag;
void jesd_init()
@ -64,6 +58,9 @@ void jesd_init()
#endif
phy_para_init(PROTOCOL_JESD, PROTO_OPTION_NULL);
do_write(JESD_RF_TXOFF2RXON, JESD_TXRX_CHANGE_GAP);
do_write(JESD_RF_TXON2PP1S, JESD_RF_ON_GAP);
do_write(CSU_RX_TD_SAMPLE, JESD_RRU_TD);
do_write(CSU_TX_ADVANCE_SAMPLE, gCsuTxAdvanceNs);
@ -170,7 +167,7 @@ int32_t get_jesd_timer_point_para(int32_t nTmrId, int32_t tmrPoint, uint32_t* te
if (tmrPoint < 0)
{
tmrPoint += SFN_PERIOD;
tmrPoint += pMtimerPara->tddPeriod; //SFN_PERIOD;
}
*tempL = pMtimerPara->tmrMsPeriod * (tmrPoint % pMtimerPara->slotPeriod) / 1000;
@ -277,7 +274,7 @@ int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdt
dlSlotCnt = my_jesdtmr->num_t_dl[0];
dlSymbolCnt = my_jesdtmr->num_t_dl_symb[0];
}
pMtimerPara->txRfOn[i].timerPoint = tdd - JESD_RF_ON_GAP; // tdd-8us
pMtimerPara->txRfOn[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXON2PP1S); //JESD_RF_ON_GAP; // tdd-8us
get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOn[i].timerPoint, &pMtimerPara->txRfOn[i].pointL,
&pMtimerPara->txRfOn[i].pointM, &pMtimerPara->txRfOn[i].pointH);
@ -285,18 +282,18 @@ int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdt
get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOff[i].timerPoint, &pMtimerPara->txRfOff[i].pointL,
&pMtimerPara->txRfOff[i].pointM, &pMtimerPara->txRfOff[i].pointH);
pMtimerPara->rxRfOn[i].timerPoint = pMtimerPara->txRfOff[i].timerPoint + JESD_TXRX_CHANGE_GAP;
pMtimerPara->rxRfOn[i].timerPoint = pMtimerPara->txRfOff[i].timerPoint + do_read_volatile(JESD_RF_TXOFF2RXON); //JESD_TXRX_CHANGE_GAP;
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxRfOn[i].timerPoint, &pMtimerPara->rxRfOn[i].pointL,
&pMtimerPara->rxRfOn[i].pointM, &pMtimerPara->rxRfOn[i].pointH);
pMtimerPara->rxRfOff[i].timerPoint = tdd - JESD_TXRX_CHANGE_GAP; // tdd-13us
pMtimerPara->rxRfOff[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXOFF2RXON); //JESD_TXRX_CHANGE_GAP; // tdd-13us
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxRfOff[i].timerPoint, &pMtimerPara->rxRfOff[i].pointL,
&pMtimerPara->rxRfOff[i].pointM, &pMtimerPara->rxRfOff[i].pointH);
debug_write((DBG_DDR_IDX_DRV_BASE+100+(i<<2)), pMtimerPara->txRfOn[i].timerPoint); // 0x190
debug_write((DBG_DDR_IDX_DRV_BASE+101+(i<<2)), pMtimerPara->txRfOff[i].timerPoint); // 0x194
debug_write((DBG_DDR_IDX_DRV_BASE+101+(i<<2)), pMtimerPara->txRfOff[i].timerPoint);// 0x194
debug_write((DBG_DDR_IDX_DRV_BASE+102+(i<<2)), pMtimerPara->rxRfOn[i].timerPoint); // 0x198
debug_write((DBG_DDR_IDX_DRV_BASE+103+(i<<2)), pMtimerPara->rxRfOff[i].timerPoint); // 0x19c
debug_write((DBG_DDR_IDX_DRV_BASE+103+(i<<2)), pMtimerPara->rxRfOff[i].timerPoint);// 0x19c
}
return 0;
@ -709,127 +706,7 @@ int32_t clear_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
return 0;
}
#if 0
int32_t set_jesd_csu_point(int32_t nTmrId, uint8_t nPointId)
{
if ((MTIMER_JESD_RX0_ID != nTmrId) && (MTIMER_JESD_TX0_ID != nTmrId))
{
return -1;
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
uint32_t val = 0;
uint32_t tempL = 0; //pMtimerPara->tmrMsPeriod * (nTmrPoint % pMtimerPara->slotPeriod) / 1000;
uint32_t tempM = 0; //(nTmrPoint / pMtimerPara->slotPeriod) % periodM;
if (MTIMER_JESD_RX0_ID == nTmrId)
{
/* rx */
val = do_read_volatile(tmrBaseAddr+MTMR_CMSK_REG);
val |= ((1<<16) | (1<<18));
do_write(tmrBaseAddr+MTMR_CMSK_REG, val);
tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->rxCsuOn[nPointId].timerPoint % pMtimerPara->slotPeriod) / 1000; // rx start point
tempM = pMtimerPara->rxCsuOn[nPointId].timerPoint / pMtimerPara->slotPeriod;
if (0 == tempL)
{
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
do_write((tmrBaseAddr+MTMR_RXEN2CSU0L_REG), tempL); /* csu RxOn */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+116+(nTmrId<<2)), tempL); // 0x1D0
#endif
val = 0xC0000000 | tempM; // special slot
do_write((tmrBaseAddr+MTMR_RXEN2CSU0H_REG), val); /* enable jesd rxdma */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+117+(nTmrId<<2)), val); // 0x1D4
#endif
__ucps2_synch(0);
while (do_read_volatile(tmrBaseAddr+MTMR_RXEN2CSU0H_REG)&BIT31);
tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->rxCsuOff[nPointId].timerPoint % pMtimerPara->slotPeriod) / 1000;
tempM = pMtimerPara->rxCsuOff[nPointId].timerPoint / pMtimerPara->slotPeriod;
if (0 == tempL)
{
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
do_write((tmrBaseAddr+MTMR_RXEN2CSU1L_REG), tempL); // -g_rfc_1us*(13-2)+RX_DELAY-OFFSET;//+CSU_RX_DELAY-OFFSET; /* csu RxOff */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+118+(nTmrId<<2)), tempL); // 0x1D8
#endif
val = 0x80000000 | tempM; // last slot of tdd
do_write((tmrBaseAddr+MTMR_RXEN2CSU1H_REG), val);
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+119+(nTmrId<<2)), val); // 0x1DC
#endif
__ucps2_synch(0);
while (do_read_volatile(tmrBaseAddr+MTMR_RXEN2CSU1H_REG)&BIT31);
#if 0
val = do_read_volatile(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2));
val |= (BIT11|BIT12);
do_write((tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2)), val);
#endif
}
else
{
/* tx */
val = do_read_volatile(tmrBaseAddr+MTMR_CMSK_REG);
val = ((1<<20) | (1<<22));
do_write(tmrBaseAddr+MTMR_CMSK_REG, val);
tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->txCsuOff[nPointId].timerPoint % pMtimerPara->slotPeriod) / 1000; // -TX_DELAY+g_rfc_1us*(1)-OFFSET;
tempM = pMtimerPara->txCsuOff[nPointId].timerPoint / pMtimerPara->slotPeriod;
if (0 == tempL)
{
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
do_write((tmrBaseAddr+MTMR_TXEN2CSU0L_REG), tempL); /* csu TxOff */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+116+(nTmrId<<2)), tempL); // 0x1F0
#endif
val = 0x80000000 | tempM; // special slot
do_write((tmrBaseAddr+MTMR_TXEN2CSU0H_REG), val);
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+117+(nTmrId<<2)), val); // 0x1f4
#endif
__ucps2_synch(0);
while (do_read_volatile(tmrBaseAddr+MTMR_TXEN2CSU0H_REG)&BIT31);
tempL = pMtimerPara->tmrMsPeriod * (pMtimerPara->txCsuOn[nPointId].timerPoint % pMtimerPara->slotPeriod) / 1000;
tempM = pMtimerPara->txCsuOn[nPointId].timerPoint / pMtimerPara->slotPeriod;
if (0 == tempL)
{
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
do_write((tmrBaseAddr+MTMR_TXEN2CSU1L_REG), tempL); // -TX_DELAY-OFFSET; /* csu TxOn */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+118+(nTmrId<<2)), tempL); // 0x1f8
#endif
val = 0xC0000000|tempM; // last slot of tdd
do_write((tmrBaseAddr+MTMR_TXEN2CSU1H_REG), val); /* enable jesd txdma */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+119+(nTmrId<<2)), val); // 0x1fC
#endif
__ucps2_synch(0);
while (do_read_volatile(tmrBaseAddr+MTMR_TXEN2CSU1H_REG)&BIT31);
#if 0
val = do_read_volatile(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2));
val |= (BIT13|BIT14);
do_write(tmrBaseAddr+MTMR_CINTE0_REG+2*(MTMR_INT_TDD_OFFSET<<2), val);
#endif
}
return 0;
}
#endif
int32_t set_jesd_csuon_point(int32_t nTmrId, uint8_t nPointId)
{
if ((MTIMER_JESD_RX0_ID != nTmrId) && (MTIMER_JESD_TX0_ID != nTmrId))
@ -1200,10 +1077,13 @@ void jesd_10ms_callback(uint8_t nTmrId)
}
#ifdef ENABLE_SFNCAL
mtimer_1pps_func(nTmrId);
if (MTIMER_JESD_RX0_ID == nTmrId)
{
mtimer_1pps_func(nTmrId);
}
#endif
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+1), pMtimerInt->pp1sIntCnt); // 0x104
debug_write((DBG_DDR_IDX_DRV_BASE+64+1+(nTmrId<<2)), pMtimerInt->pp1sIntCnt); // 0x104, 0x114
#if 0 //def PALLADIUM_TEST
uint32_t val = 0;
@ -1234,7 +1114,6 @@ void jesd_10ms_callback(uint8_t nTmrId)
#endif
uint16_t runCore = do_read_volatile_short(&(phyPara[gScsId].runCoreId));
if (((runCore & pMtimerPara->runCoreId) == pMtimerPara->runCoreId) && (4 == reCfgFlag))
//if ((runCore == pMtimerPara->runCoreId) && (3 == reCfgFlag))
{
debug_write((DBG_DDR_IDX_DRV_BASE+907), GET_STC_CNT()); // 0xe2c // timer restart finished
//uint32_t start = GET_STC_CNT();
@ -1479,22 +1358,6 @@ void jesd_slot_callback(uint8_t nTmrId)
{
reCfgFlag = 0;
}
#if 0
if (0 == pMtimerInt->txSlotIntCnt)
{
// init cal
pMtimerCal->sfnCalFinished = 0;
uint32_t lockFlag = do_read_volatile(ARM_LOCK_FLAG_ADDR);
if (0 == lockFlag)
{
do_write(ARM_SFN_VALID_ADDR, ARM_SFN_VALID_FLAG);
do_write(ARM_SFN_NUM_ADDR, 0x1);
do_write(ARM_SFN_FLIP_ADDR, 0x1);
do_write(ARM_LOCK_FLAG_ADDR, 0x1);
}
__ucps2_synch(f_SMW);
}
#endif
pMtimerSfn->txSlotTiming = GET_STC_CNT();
pMtimerSfn->txSlotNum++;
__ucps2_synch(0);
@ -1513,11 +1376,13 @@ void jesd_slot_callback(uint8_t nTmrId)
{
set_trigger_state(GPIO_OFF);
}
__ucps2_synch(0);
//__ucps2_synch(0);
#ifdef PALLADIUM_TEST
if (8 > pMtimerInt->txSlotIntCnt)
{
debug_write((DBG_DDR_IDX_DRV_BASE+576+(5<<3)+pMtimerInt->txSlotIntCnt), (GET_STC_CNT())); // -gRfm0LastTxTiming)); // 0x900
}
#endif
pMtimerInt->txSlotIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+80), pMtimerInt->txSlotIntCnt); // 0x140
@ -1571,7 +1436,7 @@ void jesd_slot_callback(uint8_t nTmrId)
pMtimerSfn->rxSfnNum &= 0x3FF;
pMtimerSfn->rxSlotNum = 0;
}
__ucps2_synch(0);
//__ucps2_synch(0);
#ifdef PALLADIUM_TEST
if (8 > pMtimerInt->rxSlotIntCnt)

29
public/ecs_rfm_spu1/driver/src/mtimer_cal.s.c
View File

@ -13,22 +13,19 @@
#include "mtimer_drv.h"
#include "gtimer_drv.h"
#include "ucp_handshake.h"
//#ifdef DISTRIBUTED_BS
#include "ucp_cpri.h"
#include "HeaderRam.h"
#include "cpri_timer.h"
#include "ecpri_timer.h"
#include "jesd_timer.h"
#include "jesd_csu.h"
extern stCpriIntStat gCpriIntStatus;
//#endif
//#ifdef INTEGRATED_BS
#include "jesd_timer.h"
//#endif
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];
extern stPhyScsPara* phyPara;
extern uint32_t gScsId;
void mtimer_1pps_resync(uint8_t nTmrId)
{
@ -47,18 +44,24 @@ void mtimer_1pps_resync(uint8_t nTmrId)
gtimer2_stop(0);
if (PROTOCOL_JESD == nBsType)
{
stop_jesd_timer(MTIMER_JESD_RX0_ID);
stop_jesd_timer(MTIMER_JESD_TX0_ID);
start_jesd_timer(MTIMER_JESD_RX0_ID);
start_jesd_timer(MTIMER_JESD_TX0_ID);
stop_jesd_timer(nTmrId);
stop_jesd_timer(nTmrId+1);
stop_jesd_timer(nTmrId+2);
stop_jesd_timer(nTmrId+3);
start_jesd_timer(nTmrId);
start_jesd_timer(nTmrId+1);
start_jesd_timer(nTmrId+2);
start_jesd_timer(nTmrId+3);
}
else // if (DISTRIBUTED_BS == nBsType)
{
gCpriIntStatus.cpriSyncFlag = 0;
stop_cpri_timer();
stop_ecpri_timer();
//set_cpri_tx_rfp();
set_cpri_tmr_ctrl();
start_cpri_timer();
start_ecpri_timer();
stCpriDelayMeasure* pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
n10msOffset = pCpriDelay->cpri10msOffset;
}

19
public/ecs_rfm_spu1/driver/src/mtimer_cell.s.c
View File

@ -18,25 +18,6 @@ extern uint32_t reCfgFlag;
extern void check_phy_cell(void);
#if 0
void phy_cell_para_init(int32_t nScsId)
{
memset_ext((void*)pPhyCellPara, 0, sizeof(stPhyCellPara));
__ucps2_synch(f_SMW);
memset(&gCellSfnPara[gMtimerId], 0, sizeof(stSfnPara));
gScsId = nScsId;
gCellSfnPara[gMtimerId].scsId = gScsId;
gCellSfnPara[gMtimerId].slotPeriod = do_read_volatile_short(&(phyPara[gScsId].slotPeriod)); // 500; //
gCellSfnPara[gMtimerId].tddSlotNum = do_read_volatile_short(&(phyPara[gScsId].slotNumOfTdd)); // 10; //
gCellSfnPara[gMtimerId].slotMaxNum = do_read_volatile_short(&(phyPara[gScsId].slotNumOfSfn)); // 20; //
__ucps2_synch(f_SMR);
gCellSfnPara[gMtimerId].txSlotNum = gCellSfnPara[gMtimerId].slotMaxNum - 1;
gCellSfnPara[gMtimerId].txSfnNum = 1023;
gCellSfnPara[gMtimerId].rxSlotNum = gCellSfnPara[gMtimerId].slotMaxNum - 1;
gCellSfnPara[gMtimerId].rxSfnNum = 1023;
}
#endif
void mtimer_init4phy(phy_timer_config_ind_t *mtmr)
{
uint8_t nBsType = get_protocol_sel();

4
public/ecs_rfm_spu1/driver/src/mtimer_drv.s.c
View File

@ -45,6 +45,10 @@ int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
{
return -1;
}
if (0 == coreClk)
{
return -1;
}
pMtimerPara->tmrClk = coreClk;
pMtimerPara->tmrMsPeriod = coreClk / 1000;

10
public/ecs_rfm_spu1/driver/src/stc_timer.s.c
View File

@ -10,7 +10,6 @@
stStcTimerPara gStcTimerPara;
extern stPhyScsPara* phyPara;
extern uint32_t gScsId;
void rfm_stc_init()
{
@ -136,7 +135,14 @@ uint32_t stc_pclk_init()
uint8_t paraL = jesdPara & 0xFF;
uint8_t paraM = (jesdPara >> 8) & 0xFF;
uint8_t paraN = (jesdPara >> 16) & 0xFF;
pClk = (uint64_t)(samClk/paraL/40)*paraM*paraN*10/8; // (uint64_t)(122880000/4/40)*8*16*10/8;
if ((0 == samClk) || (0 == jesdPara))
{
pClk = 0;
}
else
{
pClk = (uint64_t)(samClk/paraL/40)*paraM*paraN*10/8; // (uint64_t)(122880000/4/40)*8*16*10/8;
}
}
else
{

1
public/ecs_rfm_spu1/top/src/ecs_rfm_spu1_top.s.c
View File

@ -37,6 +37,7 @@ ALWAYS_INLINE int32_t get_core_id(void)
void ecs_rfm_spu1_drv_init(void)
{
ecs_rfm_dm_alloc();
ecs_rfm1_dm_init();
pet_sm_alloc();

4
public/ecs_rfm_spu1/top/src/main.s.c
View File

@ -106,8 +106,8 @@ int32_t main(int32_t argc, char* argv[])
check_10ms_offset();
}
#ifdef TEST_ENABLE
//do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
//do_write(CSU_RX_TD_SAMPLE, 10000);
do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
do_write(CSU_RX_TD_SAMPLE, 10000);
check_test_outcome(0);
#endif

7
public/test/testcases/case21/osp/src/case21_ape0_task.s.c
View File

@ -478,7 +478,12 @@ void ape0_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

7
public/test/testcases/case21/osp/src/case21_ape1_task.s.c
View File

@ -495,7 +495,12 @@ void ape1_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

7
public/test/testcases/case21/osp/src/case21_ape2_task.s.c
View File

@ -443,7 +443,12 @@ void ape2_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

7
public/test/testcases/case21/osp/src/case21_ape3_task.s.c
View File

@ -438,7 +438,12 @@ void ape3_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

7
public/test/testcases/case21/osp/src/case21_ape4_task.s.c
View File

@ -469,7 +469,12 @@ void ape4_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

7
public/test/testcases/case21/osp/src/case21_ape5_task.s.c
View File

@ -495,7 +495,12 @@ void ape5_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

7
public/test/testcases/case21/osp/src/case21_ape6_task.s.c
View File

@ -443,7 +443,12 @@ void ape6_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

7
public/test/testcases/case21/osp/src/case21_ape7_task.s.c
View File

@ -438,7 +438,12 @@ void ape7_event_task_del(uint32_t addr, uint32_t size)
uint32_t ape_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x05050505);
osp_del_task_all(NR_SCS_30K);
//osp_del_task_all(NR_SCS_30K);
osp_del_task(40, NR_SCS_30K);
osp_del_task(41, NR_SCS_30K);
osp_del_task(42, NR_SCS_30K);
osp_timer_unsync(NR_SCS_30K);
debug_write(DBG_DDR_COMMON_IDX(ape_id, 29), 0x06060606);
return;

4
public/test/testcases/case34/fronthaul/src/cpri_test_case34.s.c
View File

@ -34,8 +34,6 @@
uint32_t srcImData[4*1024] = {0}; // 16KB
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
@ -89,7 +87,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
uint32_t gCompWordCnt = 0;

0
public/test/testcases/case38/fronthaul/note.txt → public/test/testcases/case37/fronthaul/note.txt
View File

3
public/test/testcases/case37/fronthaul/readme.txt
View File

@ -1,3 +0,0 @@
CK的自研rru：
OTIC协议中图12，10g速率下4T4R单NR小区 模式：NR TDD 256QAM测试

4
public/test/testcases/case37/fronthaul/src/cpri_test_case37.s.c
View File

@ -33,8 +33,6 @@ extern uint32_t antData3[61440];
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
@ -80,7 +78,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}

122752
public/test/testcases/case38/fronthaul/DATA/265_slot0/dl_ant_post7.dat
View File

File diff suppressed because it is too large Load Diff

123008
public/test/testcases/case38/fronthaul/DATA/265_slot0/dl_ant_pre7.dat
View File

File diff suppressed because it is too large Load Diff

961
public/test/testcases/case38/fronthaul/DATA/265_slot0/dl_cpri_comp.dat
View File

@ -1,961 +0,0 @@
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0x00050005,
0x00040005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050004,
0x00050004,
0x00050005,
0x00050004,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050004,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00040005,
0x00050005,
0x00050005,
0x00050004,
0x00050004,
0x00050005,
0x00050005,
0x00040005,
0x00050005,
0x00050005,
0x00050005,
0x00050004,
0x00040004,
0x00050005,
0x00050005,
0x00050006,
0x00050005,
0x00050005,
0x00050006,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050006,
0x00050005,
0x00050005,
0x00050005,
0x00050006,
0x00040005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00040005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050004,
0x00050005,
0x00050005,
0x00040005,
0x00050005,
0x00050005,
0x00050004,
0x00050004,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050006,
0x00050005,
0x00050004,
0x00050004,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050004,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00040005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050005,
0x00050004,
0x00050005,
0x00050005,
0x00040005,
,

61377
public/test/testcases/case38/fronthaul/DATA/265_slot0/dl_cpri_post7.dat
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public/test/testcases/case38/fronthaul/DATA/265_slot0/dl_cpri_pre7.dat
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public/test/testcases/case38/fronthaul/inc/cpri_test_case38.h
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#ifndef _CPRI_TEST_CASE38_H_
#define _CPRI_TEST_CASE38_H_
// 4 ant, 7DS2U
#define CPRI_CASE38_IDNUM 6
#define CPRI_CASE38_SLOT_NUM 20
#define LONGCP_BF_CNT 139
#define SHORTCP_BF_CNT 137
#if 0
#define CPRI_CASE38_ID0_SIZE 1
#define CPRI_CASE38_ID1_SIZE 8
#define CPRI_CASE38_ID2_SIZE 8
#define CPRI_CASE38_ID3_SIZE 8
#define CPRI_CASE38_ID4_SIZE 8
#define CPRI_CASE38_ID5_SIZE 1
#define CPRI_CASE38_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define CPRI_CASE38_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define CPRI_CASE38_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define CPRI_CASE38_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define CPRI_CASE38_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define CPRI_CASE38_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define CPRI_CASE38_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define CPRI_CASE38_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
void cpri_csu_test_init();
void Cpri_data_init();
void Get_Cpri_OptionId();
void HeaderTxRam_data_init();
//void HeaderTxRam_init();
void Axc_data_init();
void cpri_csu_config();
void cpri_test_case();
void cpri_test_move_data();
void AxC_data_check(uint32_t times);
void cpri_check_slot_data(uint32_t slotNum);
#endif

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public/test/testcases/case38/fronthaul/rxData/rxPruData.dat
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public/test/testcases/case38/fronthaul/rxData/rxPruData.dat7.dat
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public/test/testcases/case38/fronthaul/rxData/rxPruData.dat8.dat
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public/test/testcases/case38/fronthaul/rxData/rxPruData.dat9.dat
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public/test/testcases/case38/fronthaul/rxData/rxPruData_ant0.dat
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public/test/testcases/case38/fronthaul/src/cpri_test_case38.s.c
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// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case35.c
// Author : xinxin.li
// Created On : 2023-01-12s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_utility.h"
#include "cpri_csu_nr_7ds2u.h"
#include "cpri_test_case38.h"
#include "cpri_timer.h"
#include "ape_csu.h"
#include "cpri_test.h"
#include "ucp_printf.h"
#include "HeaderRam.h"
#include "cpri_driver.h"
#include "phy_para.h"
#include "hw_cpri.h"
extern uint32_t compressData[1920];
extern uint32_t antData0[61440];
extern uint32_t antData1[61440];
extern uint32_t antData2[61440];
extern uint32_t antData3[61440];
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
extern volatile uint32_t gVendorFlag;
#define HeaderTestCnt 10
int32_t fh_data_init(void)
{
gCpriTestMode = CPRI_TEST_MODE;
gCpriCsuDummyFlag = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
//Get_Cpri_OptionId();//get cpri option value
//debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
Axc_data_init();//init axc data
UCP_PRINT_LOG("Axc data init.\r\n");
HeaderTxRam_data_init();
//HeaderTxRam_init();
return 0;
}
int32_t fh_drv_init(void)
{
cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
return 0;
}
int32_t fh_csu_test_init(void)
{
stCpriCsuCmdFifoInfo txTestCmdFifo;
stCpriCsuCmdFifoInfo rxTestCmdFifo;
cpri_csu_axc_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
cpri_csu_axcctrl_init_timing();
UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
return 0;
}
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
}
void HeaderTxRam_data_init()
{
#if 0
for(int i=0;i<16*HeaderTestCnt;i++)//NS=3,each BF only bit[127:0]
{
do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
}
#endif
for(int i=0;i<48*2;i++)//NS=8~19,each BF only bit[31:0]
{
do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
}
#if 0
for(int i=0;i<16*HeaderTestCnt;i++)
{
do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
}
#endif
}
void Axc_data_init()
{
uint8_t idID = 0;
uint8_t idSlot = 0; // even slot, odd slot
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t bfByteCnt = 0;
uint32_t slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
uint32_t f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;
uint32_t b7BfCnt = SHORTCP_BF_CNT*7;
uint32_t cpyCnt = 0;
// valid data
// compress factor
for (idSlot = 0; idSlot <= 1; idSlot++)
{
bfByteCnt = 2;
if (0 == idSlot) // even slot
{
srcAddr = (uint32_t)(&compressData[0]);
dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
}
else // odd slot
{
srcAddr = (uint32_t)(&compressData[1920>>1]);
dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
}
dataLen = (bfByteCnt*slotBfCnt);
debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
cpyCnt++;
memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
}
// IQ data
for (idID = 1; idID < 5; idID++)
// for (idID = 1; idID < 2; idID++)
{
bfByteCnt = 64;
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dataLen = bfByteCnt * f7BfCnt;
switch(idID)
{
case 1:
srcAddr = (uint32_t)(&antData0[0]);break;
case 2:
srcAddr = (uint32_t)(&antData1[0]);break;
case 3:
srcAddr = (uint32_t)(&antData2[0]);break;
case 4:
srcAddr = (uint32_t)(&antData3[0]);break;
}
//srcAddr = (uint32_t)(&antData[0]);
dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + (idID-1)*dataLen;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dataLen = bfByteCnt * b7BfCnt;
switch(idID)
{
case 1:
srcAddr = (uint32_t)(&antData0[15376]);break;
case 2:
srcAddr = (uint32_t)(&antData1[15376]);break;
case 3:
srcAddr = (uint32_t)(&antData2[15376]);break;
case 4:
srcAddr = (uint32_t)(&antData3[15376]);break;
}
//srcAddr = (uint32_t)(&antData[15376]);
dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + (idID-1)*dataLen;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dataLen = bfByteCnt * f7BfCnt;
switch(idID)
{
case 1:
srcAddr = (uint32_t)(&antData0[30720]);break;
case 2:
srcAddr = (uint32_t)(&antData1[30720]);break;
case 3:
srcAddr = (uint32_t)(&antData2[30720]);break;
case 4:
srcAddr = (uint32_t)(&antData3[30720]);break;
}
//srcAddr = (uint32_t)(&antData[30720]);
dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (idID-1)*dataLen;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dataLen = bfByteCnt * b7BfCnt;
switch(idID)
{
case 1:
srcAddr = (uint32_t)(&antData0[30720+15376]);break;
case 2:
srcAddr = (uint32_t)(&antData1[30720+15376]);break;
case 3:
srcAddr = (uint32_t)(&antData2[30720+15376]);break;
case 4:
srcAddr = (uint32_t)(&antData3[30720+15376]);break;
}
//srcAddr = (uint32_t)(&antData[30720+15376]);
dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (idID-1)*dataLen;
}
debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
cpyCnt++;
memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
}
}
}
}
uint32_t gCompWordCnt = 0;
uint32_t gErrSlotIdCnt = 0;
uint32_t gCompSlotIdCnt = 0;
void cpri_check_slot_data(uint32_t slotNum)
{
uint32_t slotId = 0;
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint8_t bitOffset = 0;
uint32_t totalSlotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
uint32_t slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
uint8_t bfWordCnt = 0;
uint8_t slotVal = 0;
uint8_t idVal = 0;
uint32_t bfStart = 0;
uint32_t compVal = 0;
uint32_t recvVal = 0;
uint32_t recvAddr = 0;
uint32_t *pAntData = antData0;
for (uint32_t i = 0; i < 5; i++)
{
gCompSlotIdCnt++;
slotId = slotNum; // get_tx_nr_slot(NR_SCS_30K);
idVal = i;
bfStart = 0;
switch(i)
{
case 1:
pAntData = antData0;break;
case 2:
pAntData = antData1;break;
case 3:
pAntData = antData2;break;
case 4:
pAntData = antData3;break;
}
if ((slotId >=0) && (slotId <= 6))
{
slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
slotVal = slotId & 0x1;
if (0 == i)
{
bitOffset = 1; // one BF, 2B
bfWordCnt = 1;
srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
}
else
{
bitOffset = 6; // one BF, 64B
bfWordCnt = 64>>2;
srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
}
dataLen = slotBfCnt << bitOffset;
}
else if (7 == slotId) // compare S slot, odd slot
{
bfStart = 0;
slotBfCnt = LONGCP_BF_CNT + 5 * SHORTCP_BF_CNT;
slotVal = 1;
if (0 == i)
{
bitOffset = 1; // one BF, 2B
bfWordCnt = 1;
srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset);
}
else
{
bitOffset = 6; // one BF, 64B
bfWordCnt = (64>>2);
srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset);
}
dataLen = slotBfCnt << bitOffset;
}
if (0 == i) // compress factor
{
for (uint32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
{
for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
{
if (7 == slotId)
{
dstAddr = 960 + idBf*bfWordCnt + idWord;
}
else
{
dstAddr = slotVal*(1920>>1) + idBf*bfWordCnt + idWord;
}
recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
recvVal = *((uint32_t*)recvAddr);
compVal = compressData[dstAddr];
if ((recvVal != compVal) || (recvVal != compVal))
{
// debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr); // 0x320
// debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr); // 0x324
// debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8))); // 0x328
// debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal); // 0x32c
// gErrSlotIdCnt++;
// break;
// break;
}
// do_write(a, gCompSlotIdCnt); // addr
// do_write(a, gErrSlotIdCnt);
}
}
}
else // axc data
{
for (uint32_t idBf = 0; idBf < slotBfCnt; idBf++)
{
for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
{
if (7 == slotId)
{
dstAddr = 30720 +idBf*bfWordCnt + idWord;
}
else
{
dstAddr = slotVal*30720 + idBf*bfWordCnt + idWord;
}
// recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord + 0x10);
//recvVal = *((uint32_t*)recvAddr);
recvVal = do_read_volatile(recvAddr);
//compVal = pAntData[dstAddr];
compVal = do_read_volatile(pAntData+dstAddr);
if (recvVal != compVal)
{
//debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr); // 0x320
//debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr); // 0x324
//debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8))); // 0x328
//debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal); // 0x32c
if (gErrSlotIdCnt < 0x100)
{
debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal); // 0x320
debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal); // 0x324
debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr); // 0x32c
debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), srcAddr); // 0x32c
debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); // 0x328
debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), dstAddr); // 0x328
debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); // 0x328
}
gErrSlotIdCnt++;
// break;
// break;
}
}
}
}
debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt); // 0x310
debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt); // 0x314
}
}
void Cpri_Header_Rx(void)
{
}
void fh_data_check(uint32_t times)
{
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
if (40 <= pMtimerInt->csuEnCnt)
{
#if 0
if (64 == gCpriTimerPara.csuEnCnt)
{
AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
//AUX_Rx_enable(0x2);
}
#endif
gCompWordCnt = 0;
for (int i = 0; i < 7; i++)
{
cpri_check_slot_data(i);
}
Cpri_Header_Rx();
}
}

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public/test/testcases/case38/fronthaul/src/cpri_test_case38_antdata.s.c
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public/test/testcases/case38/fronthaul/src/cpri_test_case38_antdata0.s.c
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public/test/testcases/case38/fronthaul/src/cpri_test_case38_antdata1.s.c
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public/test/testcases/case38/fronthaul/src/cpri_test_case38_antdata2.s.c
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public/test/testcases/case38/fronthaul/src/cpri_test_case38_antdata3.s.c
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public/test/testcases/case38/fronthaul/src/cpri_test_case38_comfactor.s.c
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public/test/testcases/case38/osp/src/ape_test_case38.s.c
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// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

4
public/test/testcases/case39/fronthaul/src/cpri_test_case39.s.c
View File

@ -34,8 +34,6 @@ extern uint32_t antData3[61440];
extern uint32_t gCpriTestMode;
//extern stCpriTimerPara gCpriTimerPara;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
@ -81,7 +79,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}

5
public/test/testcases/case60/fronthaul/src/cpri_test_case60.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -75,7 +72,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
void HeaderTxRam_data_init()

5
public/test/testcases/case61/fronthaul/src/cpri_test_case61.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -82,7 +79,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}

5
public/test/testcases/case66/fronthaul/src/cpri_test_case66.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -82,7 +79,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}

5
public/test/testcases/case68/fronthaul/src/cpri_test_case68.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -82,7 +79,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
void HeaderTxRam_data_init()

4
public/test/testcases/case70/fronthaul/src/cpri_test_case70.s.c
View File

@ -33,8 +33,6 @@
//DDR0 uint32_t srcImData[5*1024] = {0}; // 16KB
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
@ -75,7 +73,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
void HeaderTxRam_data_init()

4
public/test/testcases/case71/fronthaul/src/cpri_test_case71.s.c
View File

@ -40,8 +40,6 @@ extern uint32_t antData3[122880];
//DDR0 uint32_t srcImData[5*1024] = {0}; // 16KB
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
@ -82,7 +80,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
void HeaderTxRam_data_init()

4
public/test/testcases/case72/fronthaul/src/cpri_test_case72.s.c
View File

@ -40,8 +40,6 @@ extern uint32_t antData3[122880];
//DDR0 uint32_t srcImData[5*1024] = {0}; // 16KB
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
@ -82,7 +80,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}

5
public/test/testcases/case80/fronthaul/src/cpri_test_case80.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -79,7 +76,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
void HeaderTxRam_data_init()

5
public/test/testcases/case81/fronthaul/src/cpri_test_case81.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -79,7 +76,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
void HeaderTxRam_data_init()

5
public/test/testcases/case82/fronthaul/src/cpri_test_case82.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -79,7 +76,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}
void HeaderTxRam_data_init()

5
public/test/testcases/case83/fronthaul/src/cpri_test_case83.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -79,7 +76,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}

5
public/test/testcases/case84/fronthaul/src/cpri_test_case84.s.c
View File

@ -33,9 +33,6 @@
extern uint32_t gCpriTestMode;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern uint32_t gCpriTestMode;
//extern uint32_t CPRI_OPTION;
extern uint32_t gCpriCsuDummyFlag;
@ -79,7 +76,7 @@ int32_t fh_csu_test_init(void)
void fh_test_case()
{
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
UCP_API_CPRI_CSU_START();
}