1.delete the test code for cell build/delete in ECS_RFM1 main function;

2.move check_phy_cell to mtimer_init4phy function;
3.delete jesd rx1 timer init;
4.delete some test code in the cpri/jesd timer isr function;
5.add some necessary function declaration in the interface folder;
6.test case: case21(cpri and jesd), case34, case44.
This commit is contained in:
xinxin.li 2023-09-05 11:10:46 +08:00
parent 5f6630f8f6
commit 430c98b59a
7 changed files with 51 additions and 93 deletions

View File

@ -102,98 +102,26 @@ typedef struct phy_timer_config_ind_t
uint8_t num_ants; //天线个数
}phy_timer_config_ind_t;
typedef struct _tagPhyDelCell
{
uint32_t scsId;
uint32_t delCoreId; // 此次需要删除小区的ape core idbitmap方式bit0对应ape0bit1对应ape1。。。
}stPhyDelCell;
/*
cpri_timer_init4buildcell_c0
mtimer_init4phy
my_cpritmr
ecs rfm1的建小区流程APE建小区
*/
void mtimer_init4phy(phy_timer_config_ind_t *my_mtmr);
//void cpri_timer_init4buildcell_c0(phy_timer_config_ind_t *my_cpritmr);
//void jesd_timer_init4buildcell_c0(phy_timer_config_ind_t *my_cpritmr);
int32_t mtimer_init4phy(phy_timer_config_ind_t *my_mtmr);
/*
get_tx_nr_sfn
scs
mtimer_del_cell_cfg
delCell
APE删除任务和定时点ecs rfm1的删小区流程
*/
int get_tx_nr_sfn(uint8_t scs);
int32_t mtimer_del_cell_cfg(stPhyDelCell* delCell);
/*
get_tx_lte_sfn
*/
int get_tx_lte_sfn();
/*
get_tx_slot
scs
*/
int get_tx_nr_slot(uint8_t scs);
/*
get_tx_subframe
*/
int get_tx_lte_subframe();
/*
get_rx_nr_sfn
scs
*/
int get_rx_nr_sfn(uint8_t scs);
/*
get_rx_nr_sfn
*/
int get_rx_lte_sfn();
/*
get_rx_slot
scs
*/
int get_rx_nr_slot(uint8_t scs);
/*
get_rx_subframe
*/
int get_rx_lte_subframe();
/*
get_tx_nr_slot_cycle
scs
ns
*/
int get_tx_nr_slot_cycle(uint8_t scs);
/*
get_tx_lte_slot_cycle
scs
ns
*/
int get_tx_lte_subframe_cycle();
/*
get_rx_nr_slot_cycle
scs
ns
*/
int get_rx_nr_slot_cycle(uint8_t scs);
/*
get_rx_lte_slot_cycle
scs
ns
*/
int get_rx_lte_subframe_cycle();
/*
get_cpri_delay

View File

@ -84,9 +84,17 @@ extern int osp_task_create(osp_task_info_ex *);
/*
osp_del_task
prio :
scsId: scs id
*/
extern void osp_del_task(int prio);
osp_del_task(int prio, int scsId);
/*
osp_var_init
*/
void osp_var_init(void);
/*
smart_int_disable

View File

@ -2510,7 +2510,7 @@ void jecspma_recrx_reset()
}
void init_cpri(uint32_t cpri_speed_sel)
{
//uint32_t resynctimes = 0;
uint32_t resynctimes = 0;
//JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | BIT4;//cpri tx pma sel jecs
do_write(&JECS_CTRL_PROTOCOL_SEL, do_read_volatile(&JECS_CTRL_PROTOCOL_SEL) | BIT4);
init_cpri_pma_rst();
@ -2602,7 +2602,7 @@ void init_cpri(uint32_t cpri_speed_sel)
{
}
jecspma_recrx_eq();
#if 0
#if 1
delay_us(10000);
for(uint32_t i=0;i<3000;i++)
{

View File

@ -671,7 +671,7 @@ uint32_t start = GET_STC_CNT();
#endif
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+1), pMtimerInt->pp1sIntCnt); // 0x104
#ifdef PALLADIUM_TEST
#if 0 //def PALLADIUM_TEST
//debug_write((DBG_DDR_IDX_DRV_BASE+576+(gCpriTimerPara.pp1sIntCnt&0x3f)), get_tx_nr_slot(1)); // 0xB7E06900
uint32_t val = 0;

View File

@ -75,7 +75,7 @@ void jesd_init()
#endif
jesd_mtimer_init(MTIMER_JESD_RX0_ID, NR_SCS_30K, 10);
jesd_mtimer_init(MTIMER_JESD_RX1_ID, NR_SCS_30K, 10);
//jesd_mtimer_init(MTIMER_JESD_RX1_ID, NR_SCS_30K, 10);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0xB8
@ -862,7 +862,7 @@ uint32_t start = GET_STC_CNT();
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+1), pMtimerInt->pp1sIntCnt); // 0x104
#ifdef PALLADIUM_TEST
#if 0 //def PALLADIUM_TEST
uint32_t val = 0;
for (int32_t core = 0; core < 12; core++)
{

View File

@ -14,6 +14,9 @@ extern uint32_t gScsId;
extern uint32_t gMtimerId;
extern stSfnPara gCellSfnPara[2]; // cell para
extern stPhyScsPara* phyPara;
extern uint32_t reCfgFlag;
extern void check_phy_cell(void);
void phy_cell_para_init(int32_t nScsId)
{
@ -47,6 +50,9 @@ void mtimer_init4phy(phy_timer_config_ind_t *mtmr)
gMtimerId = MTIMER_JESD_RX0_ID;
#endif
do_write((&(pPhyCellPara->flag)), PHY_CELL_FLAG);
__ucps2_synch(f_SM);
check_phy_cell();
}
// 建小区先走ecs rfm1的建小区流程再通知APE
@ -118,6 +124,10 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
#ifdef DISTRIBUTED_BS
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
if (-1 == set_cpri_ape_slot_offset(my_mtmr->runCoreId))
{
flag++;
@ -127,6 +137,10 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
}
#endif
#ifdef INTEGRATED_BS
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX0_ID, my_mtmr->runCoreId))
{
flag++;
@ -156,6 +170,10 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
{
do_write_short((&(phyPara[nScsId].mtimerId)), SCS_2nd_MTIMER_ID);
#ifdef DISTRIBUTED_BS
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
ecpri_timer_reconfig(my_mtmr);
if (-1 == set_ecpri_ape_slot_offset(my_mtmr->runCoreId))
{
@ -163,6 +181,10 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
}
#endif
#ifdef INTEGRATED_BS
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
jesd_timer_reconfig(MTIMER_JESD_RX1_ID, my_mtmr);
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, my_mtmr->runCoreId))
{

View File

@ -83,7 +83,7 @@ int32_t main(int32_t argc, char* argv[])
check_test_outcome(0);
#endif
#if 1
#if 0
if (1 == do_read_volatile(0x0A4D726C))
{
#ifdef CPRI_TIMING_7D2U_TEST
@ -98,7 +98,6 @@ int32_t main(int32_t argc, char* argv[])
{
check_phy_cell();
}
#endif
if (3 == do_read_volatile(0x0A4D726C))
{
#ifdef CPRI_TIMING_7D2U_TEST
@ -121,6 +120,7 @@ int32_t main(int32_t argc, char* argv[])
#endif
do_write(0x0A4D726C, 0);
}
#endif
phy_queue_polling();