From 384d6573f6c1a6c74d95c98282109ea8d9ae114e Mon Sep 17 00:00:00 2001 From: "cheng.wan" Date: Thu, 29 Feb 2024 10:48:31 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BC=98=E5=8C=96CPRI=E9=93=BE=E8=B7=AF?= =?UTF-8?q?=E5=A4=B1=E6=AD=A5=E6=97=B6=E7=9A=84=E9=87=8D=E5=90=8C=E6=AD=A5?= =?UTF-8?q?=E6=9C=BA=E5=88=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- public/ecs_rfm_spu1/driver/inc/cpri_driver.h | 2 +- .../ecs_rfm_spu1/driver/src/cpri_driver.s.c | 93 ++++++++++++++++--- .../driver/src/cpri_test_mode.s.c | 16 +++- public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c | 7 +- 4 files changed, 95 insertions(+), 23 deletions(-) diff --git a/public/ecs_rfm_spu1/driver/inc/cpri_driver.h b/public/ecs_rfm_spu1/driver/inc/cpri_driver.h index 9046cee..63c5d04 100644 --- a/public/ecs_rfm_spu1/driver/inc/cpri_driver.h +++ b/public/ecs_rfm_spu1/driver/inc/cpri_driver.h @@ -35,7 +35,7 @@ void Init_jecspma(uint32_t cpri_speed_sel); void Init_pma_commonconfig(uint32_t cpri_speed_sel); void jecspma_recrx_eq(); -void jecspma_recrx_reset(); +void jecspma_recrx_reset(uint32_t pcs_flag); //void config_cpri_map_directed(uint32_t cpri_speed_sel); diff --git a/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c b/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c index 281f1d7..06d5a69 100644 --- a/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c +++ b/public/ecs_rfm_spu1/driver/src/cpri_driver.s.c @@ -15,6 +15,8 @@ #include "mem_sections.h" #include "ucp_sfr_c.h" #include "phy_para.h" +#include "mtimer_drv.h" +#include "cpri_csu_api.h" //#define CPRI_SPEED 8//option 8 @@ -2403,19 +2405,22 @@ void jecspma_recrx_eq() } -void jecspma_recrx_reset() + + +void jecspma_recrx_reset(uint32_t pcs_flag) { - uint32_t i=0; - uint32_t j=0; - init_jecspma_recrx(); - while(1) + // uint32_t i=0; + // uint32_t j=0; + //init_jecspma_recrx(); + //while(1) { - i++; + // i++; //rx adapt eq //UARTPrintStr("PMA RX ADAPT EQ START"); //De-assert rx_data_en - if((0 == (j % 100)) && (1< j)) + //if((0 == (j % 100)) && (1< j)) + if(pcs_flag == 1) { Clk_To_XTAL(); do_write(&CPRI_PCS_ADDR_CFG, 0); @@ -2439,7 +2444,6 @@ void jecspma_recrx_reset() do_write(&CPRI_PCS_CTRL_CFG, 0x2); __ucps2_synch(f_SM); Clk_To_Normal(); - } do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4); @@ -2467,7 +2471,7 @@ void jecspma_recrx_reset() //Wait for assertion of rx_adapt_ack from the PHY while((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)&BIT0) != BIT0); - debug_write((DBG_DDR_IDX_CPRI_BASE+4), do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)); + //debug_write((DBG_DDR_IDX_CPRI_BASE+4), do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK)); //UARTPrintStr_f("JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK",JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK); //De-assert rx_adapt_req to the PHY @@ -2483,9 +2487,9 @@ void jecspma_recrx_reset() // do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL)| BIT24); #endif - debug_write((DBG_DDR_IDX_CPRI_BASE+5), i); - //debug_write((DBG_DDR_IDX_CPRI_BASE+4), j); -#if 1 + //debug_write((DBG_DDR_IDX_CPRI_BASE + 5), i); + //debug_write((DBG_DDR_IDX_CPRI_BASE + 6), j); +#if 0 //ucp_nop(400); //if(0xA0 < (((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK))>>8) & 0xFF)) @@ -2501,8 +2505,6 @@ void jecspma_recrx_reset() break; } } - - #endif } @@ -2525,8 +2527,69 @@ void jecspma_recrx_reset() } } #endif - } + + +extern stCpriIntStat gCpriIntStatus; + uint32_t cpri_async_flag = 0; + uint32_t cpri_monitor_cnt = 0; + uint32_t cpri_resync_cnt = 0; + uint32_t cpri_pcs_thr_cnt = 0; +void cpri_link_monitor(void) +{ + uint32_t link_fom = 0; + uint32_t link_stat = 0; + + + cpri_monitor_cnt++; + + link_stat = do_read_volatile(&CPRI_FRAME_RX_STAT); + if(link_stat != 0x1E) + { + if(cpri_async_flag == 0) + { + cpri_async_flag = 1; + gCpriIntStatus.cpriSyncFlag = 0; + UCP_API_CPRI_CSU_STOP(); + init_jecspma_recrx(); + } + } + + if(cpri_async_flag == 1) + { + cpri_resync_cnt++; + jecspma_recrx_reset(0); //reset pma + + link_stat = do_read_volatile(&CPRI_FRAME_RX_STAT); + link_fom = (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK) >> 8)&0xFF; + if(link_fom > 0x80) + { + if(link_stat == 0x1E) + { + cpri_async_flag = 0; + cpri_pcs_thr_cnt = 0; + set_cpri_tmr_ctrl(); + }else + { + cpri_pcs_thr_cnt++; + if(cpri_pcs_thr_cnt%100 == 0) + { + jecspma_recrx_reset(1); //reset pcs&pma + } + } + } + + debug_write((DBG_DDR_IDX_CPRI_BASE + 4), link_fom); + debug_write((DBG_DDR_IDX_CPRI_BASE + 5), cpri_resync_cnt); + debug_write((DBG_DDR_IDX_CPRI_BASE + 6), cpri_pcs_thr_cnt); + } + + debug_write((DBG_DDR_IDX_CPRI_BASE + 7), cpri_monitor_cnt); +} + + + + void init_cpri(uint32_t cpri_speed_sel) { // uint32_t resynctimes = 0; diff --git a/public/ecs_rfm_spu1/driver/src/cpri_test_mode.s.c b/public/ecs_rfm_spu1/driver/src/cpri_test_mode.s.c index 40a9ef7..1839a56 100644 --- a/public/ecs_rfm_spu1/driver/src/cpri_test_mode.s.c +++ b/public/ecs_rfm_spu1/driver/src/cpri_test_mode.s.c @@ -25,7 +25,7 @@ DDR0 uint32_t test_srcImData[4*1024] = {0}; extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM]; extern volatile uint32_t CsuStopFlag ; extern uint32_t gCpriCsuCmdCnt; -extern stCpriIntStat gCpriIntStatus; + uint32_t NormalToTest = 0; uint32_t TestToNormal = 0; @@ -642,8 +642,10 @@ void check_cpri(void) do_write(ENTER_TEST_MODE_ADDR, 0);//初始化默认0，正式模式 } + #if 0 if(0 == do_read_volatile(ENTER_TEST_MODE_ADDR))//Normal mode - { + + { if((do_read_volatile(&CPRI_FRAME_RX_STAT))!= 0x1e)//失步 { gCpriIntStatus.cpriSyncFlag = 0; // cpri sync flag = 0 @@ -654,15 +656,17 @@ void check_cpri(void) debug_write((DBG_DDR_IDX_CPRI_BASE+1027), ResetSyncCnt0); set_cpri_tmr_ctrl(); - } - + } } - + #endif + if(1 == do_read_volatile(ENTER_TEST_MODE_ADDR)) //进入测试模式 { test_mode_cnt++; debug_write((DBG_DDR_IDX_CPRI_BASE+1026), test_mode_cnt); debug_write((DBG_DDR_IDX_CPRI_BASE+1028), 0); + + #if 0 if((do_read_volatile(&CPRI_FRAME_RX_STAT))!= 0x1e)//失步 { gCpriIntStatus.cpriSyncFlag = 0; // cpri sync flag = 0 @@ -674,6 +678,8 @@ void check_cpri(void) set_cpri_tmr_ctrl(); } + #endif + if( 1 == test_mode_cnt) { Axc_data_test_init(); diff --git a/public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c b/public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c index 627817a..e9e7c7d 100644 --- a/public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c +++ b/public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c @@ -29,6 +29,7 @@ #endif extern int32_t phy_fh_drv_init(); +extern void cpri_link_monitor(); void ecs_rfm1_drv_init(void) { @@ -166,10 +167,12 @@ int32_t check_phy_cell(void) return 0; } + void check_10ms_offset(void) { if (1 == get_sfnoffset_int_flag()) { + cpri_link_monitor(); update_cpri_link_status(); cpri_delay_measurement_ck(); clear_sfnoffset_int_flag(); @@ -200,8 +203,8 @@ int32_t fronthaul_drv_cfg(stFrontHaulDrvPara* pFhDrvPara) void spu_ddr_monitor_start(uint32_t monitorCnt) { - do_write(DDR_MONITOR_ENABLE, 1); - do_write(DDR_MONITOR_CNT, monitorCnt); + do_write(DDR_MONITOR_ENABLE, 1); + do_write(DDR_MONITOR_CNT, monitorCnt); } int32_t set_mtimer_scratch_tod()