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Merge branch 'dev_ck_v2.1_feature#1807#' into 'dev_ck_v2.1'

Browse Source 
UCP4008-SL feature enhancement #1807

See merge request ucp/driver/ucp4008_platform_spu!102
This commit is contained in:
Weihua Li 2024-04-07 09:39:39 +00:00
commit 5a8c48bf7a
7 changed files with 107 additions and 84 deletions
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10
public/common/driver/inc/mtimer_com.h
View File

@ -176,23 +176,25 @@ typedef struct _tagMtimerIntStat{
}stMtimerIntStat;
typedef struct _tagMtimerPhyPara{
// symbol相关
// about symbol
uint32_t symbolMaxNum;
uint32_t txSymbolNum;
// 物理层时隙相关
// about phy slot
uint32_t slotMaxNum;
uint32_t slotNumPP1s;
uint32_t txSlotNum;
uint32_t rxSlotNum;
uint32_t txSfnNum;
uint32_t rxSfnNum;
uint32_t cellSetup; // cell setup flag, have cell:1, no cell:0
uint32_t reserved;
uint64_t txSlotTiming;
uint64_t rxSlotTiming;
}stMtimerPhyPara;
typedef struct _tagMtimerSfnCal{
int32_t pp1sLockFlagPre; // 上一个pp1s时刻记录的pp1s锁定标志
int32_t pp1sLockFlag; // pp1s锁定标志，由arm发消息通知
int32_t pp1sLockFlagPre; // gps lock flag of last pp1s int
int32_t pp1sLockFlag; // gps lock flag, informed by arm
uint32_t sfnCalCnt; // sfn cnt from arm£¬for sfn calibration of ape
int32_t startCalFlag; // calibration flag
int32_t sfnCalFinished; // calibration flag

4
public/ecs_rfm_spu1/driver/src/cpri_delay.s.c
View File

@ -520,7 +520,7 @@ void get_cpri_delay(uint32_t* delay)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stCpriDelayMeasure* pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
*delay = pCpriDelay->cpriTxOffset;
*delay = pCpriDelay->cpriRxOffset;
}
void get_cpri_advance(uint32_t* advance)
@ -528,7 +528,7 @@ void get_cpri_advance(uint32_t* advance)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stCpriDelayMeasure* pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
*advance = pCpriDelay->cpriRxOffset;
*advance = pCpriDelay->cpriTxOffset;
}
void get_cpri_frame_data_offset(uint32_t* offset)

59
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -250,12 +250,16 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
}
reCfgFlag = 3;
pMtimerSfn->cellSetup = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+912), pMtimerSfn->txSfnNum); // 0xE40
debug_write((DBG_DDR_IDX_DRV_BASE+913), GET_STC_CNT()); // 0xE44
}
void cpri_timer_clear_cell(uint8_t scsId)
{
stMtimerSfnCal* pSfnCal = &gMtimerSfnCalPara[MTIMER_CPRI_ID];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
pSfnCal->sfnCalFinished = 0;
pMtimerInt->csuEnCnt = 0;
@ -268,6 +272,7 @@ void cpri_timer_clear_cell(uint8_t scsId)
{
clear_cpri_lte_fapi_offset();
}
pMtimerSfn->cellSetup = 0;
}
void cpri_timer_rcfg_act()
@ -289,6 +294,8 @@ void cpri_timer_rcfg_act()
if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
{
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
}
addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
@ -332,6 +339,8 @@ void cpri_timer_rcfg_act()
}
reCfgFlag = 5;
debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum); // 0xE50
debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT()); // 0xE54
}
void set_cpri_tmr_period(void)
@ -546,6 +555,7 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId)
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
pMtimerPara->runCoreId = apeCoreId;
txOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
rxOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
@ -587,6 +597,8 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId)
}
reCfgFlag = 4;
debug_write((DBG_DDR_IDX_DRV_BASE+914), pMtimerSfn->txSfnNum); // 0xE48
debug_write((DBG_DDR_IDX_DRV_BASE+915), GET_STC_CNT()); // 0xE4c
return 0;
}
@ -718,10 +730,11 @@ void isr_cpri_10ms(void)
uint32_t tEventFlag = 0;
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
//stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[MTIMER_CPRI_ID];
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
uint8_t apeId = get_core_id();
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG) ;
//__ucps2_synch(0);
@ -743,11 +756,13 @@ void isr_cpri_10ms(void)
{
start_cpri_timer();
gtimer2_start(0);
pMtimerSfn->txSfnNum = 0;
pMtimerInt->tmrPP1sCost = GET_STC_CNT();
debug_write((DBG_DDR_IDX_DRV_BASE+61), pMtimerInt->tmrPP1sCost); // 0xF4
}
#ifdef ENABLE_SFNCAL
debug_write((DBG_DDR_IDX_DRV_BASE+60), pMtimerSfn->txSfnNum);
mtimer_1pps_func(MTIMER_CPRI_ID);
#endif
pMtimerInt->pp1sIntCnt++;
@ -772,6 +787,30 @@ void isr_cpri_10ms(void)
}
#endif
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
}
if (tEventFlag & (1<<MTMR_10ms_OFFSET)) // 10ms offset int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_10ms_OFFSET));
do_write(tFlagAddr, (1<<MTMR_10ms_OFFSET)); // clear int flag
pMtimerInt->sfnOffsetIntFlag = 1;
pMtimerInt->sfnOffsetIntCnt++;
if (0 == pMtimerSfn->cellSetup)
{
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2), pMtimerSfn->txSfnNum);
}
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+3), pMtimerInt->sfnOffsetIntCnt); // 0x10C
//debug_write((DBG_DDR_IDX_DRV_BASE+672+(pMtimerInt->sfnOffsetIntCnt&0x1f)), pMtimerSfn->txSlotNum); //get_tx_nr_slot(1)); // 0xb7e06a00
#endif
//uint32_t start = GET_STC_CNT();
if (0 == (pMtimerInt->sfnOffsetIntCnt&0x3))
{
spu_log_server_isr();
}
//debug_write((DBG_DDR_IDX_DRV_BASE+259), (GET_STC_CNT()-start)); // 0x40c
}
if (cEventFlag & (1<<MTMR_CEVENT_CNT14H)) // 10ms int
{
@ -794,24 +833,6 @@ void isr_cpri_10ms(void)
}
set_trigger_state(GPIO_ON);
}
if (tEventFlag & (1<<MTMR_10ms_OFFSET)) // 10ms offset int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_10ms_OFFSET));
do_write(tFlagAddr, (1<<MTMR_10ms_OFFSET)); // clear int flag
pMtimerInt->sfnOffsetIntFlag = 1;
pMtimerInt->sfnOffsetIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+3), pMtimerInt->sfnOffsetIntCnt); // 0x10C
//debug_write((DBG_DDR_IDX_DRV_BASE+672+(pMtimerInt->sfnOffsetIntCnt&0x1f)), pMtimerSfn->txSlotNum); //get_tx_nr_slot(1)); // 0xb7e06a00
#endif
//uint32_t start = GET_STC_CNT();
if (0 == (pMtimerInt->sfnOffsetIntCnt&0x3))
{
spu_log_server_isr();
}
//debug_write((DBG_DDR_IDX_DRV_BASE+259), (GET_STC_CNT()-start)); // 0x40c
}
cEventFlag = do_read_volatile(cFlagAddr);
tEventFlag = do_read_volatile(tFlagAddr);
}

4
public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c
View File

@ -140,8 +140,7 @@ void ecpri_timer_rcfg_act()
if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
{
pMtimerSfn->txSfnNum = 0;
pMtimerSfn->rxSfnNum = 0; //1023;
pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
@ -589,6 +588,7 @@ void isr_ecpri_timer(void)
reCfgFlag = 0;
//disable_mtimer_cevent_int(MTIMER_ECPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
}
pMtimerSfn->txSlotTiming = GET_STC_CNT();
pMtimerSfn->txSlotNum++;
__ucps2_synch(0);
if (pMtimerSfn->txSlotNum == pMtimerSfn->slotMaxNum)

69
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -528,12 +528,17 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
}
reCfgFlag = 1;
pMtimerSfn->cellSetup = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+912), pMtimerSfn->txSfnNum); // 0xE40
debug_write((DBG_DDR_IDX_DRV_BASE+913), GET_STC_CNT()); // 0xE44
return 0;
}
int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
{
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
if (MTIMER_JESD_RX0_ID == nTmrId)
{
clear_jesd_tdd_offset(nTmrId);
@ -547,6 +552,9 @@ int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
}
clear_jesd_tx_slot_offset(nTmrId);
clear_jesd_rx_slot_offset(nTmrId);
pMtimerSfn->cellSetup = 0;
if (LTE_SCS_ID == scsId)
{
//clear_jesd_lte_fapi_offset();
@ -578,6 +586,8 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
{
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
@ -616,6 +626,8 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
}
reCfgFlag = 5;
debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum); // 0xE50
debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT()); // 0xE54
}
int32_t jesd_pin_ctrl(int32_t nTmrId)
@ -782,6 +794,7 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
pMtimerPara->runCoreId = apeCoreId;
txOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;
rxOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;
@ -820,6 +833,8 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
}
reCfgFlag = 4;
debug_write((DBG_DDR_IDX_DRV_BASE+914), pMtimerSfn->txSfnNum); // 0xE48
debug_write((DBG_DDR_IDX_DRV_BASE+915), GET_STC_CNT()); // 0xE4c
return 0;
}
@ -1216,6 +1231,8 @@ void jesd_10ms_callback(uint8_t nTmrId)
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[nTmrId];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
int32_t apeId = get_core_id();
tmrIntcFlag = do_read_volatile(tmrBaseAddr+MTMR_INTC_REG) ;
__ucps2_synch(0);
@ -1235,13 +1252,14 @@ void jesd_10ms_callback(uint8_t nTmrId)
//uint32_t start = GET_STC_CNT();
if (0 == pMtimerInt->pp1sIntCnt)
{
gtimer2_start(0);
start_jesd_timer(nTmrId);
gtimer2_start(0);
if (MTIMER_JESD_RX0_ID == nTmrId)
{
start_jesd_timer(MTIMER_JESD_TX0_ID);
debug_write((DBG_DDR_IDX_DRV_BASE+57), GET_STC_CNT());
}
pMtimerSfn->txSfnNum = 0;
pMtimerInt->tmrPP1sCost = GET_STC_CNT();
}
@ -1254,7 +1272,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
#ifdef ENABLE_SFNCAL
if (MTIMER_JESD_RX0_ID == nTmrId)
{
//debug_write((DBG_DDR_IDX_DRV_BASE+57), GET_STC_CNT());
debug_write((DBG_DDR_IDX_DRV_BASE+69), pMtimerSfn->txSfnNum);
mtimer_1pps_func(nTmrId);
}
#endif
@ -1281,6 +1299,26 @@ void jesd_10ms_callback(uint8_t nTmrId)
#endif
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
}
if (tEventFlag & (1<<MTMR_10ms_OFFSET)) // 10ms offset int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_10ms_OFFSET));
do_write(tFlagAddr, (1<<MTMR_10ms_OFFSET)); // clear int flag
pMtimerInt->sfnOffsetIntFlag = 1;
pMtimerInt->sfnOffsetIntCnt++;
if (0 == pMtimerSfn->cellSetup)
{
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2)+(nTmrId<<5), pMtimerSfn->txSfnNum);
}
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C
#endif
if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == (pMtimerInt->sfnOffsetIntCnt&0x3)))
{
spu_log_server_isr();
}
}
if (cEventFlag & (1<<MTMR_CEVENT_CNT14H)) // 10ms int
{
do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_CNT14H));
@ -1302,33 +1340,6 @@ void jesd_10ms_callback(uint8_t nTmrId)
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
}
}
if (tEventFlag & (1<<MTMR_10ms_OFFSET)) // 10ms offset int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_10ms_OFFSET));
do_write(tFlagAddr, (1<<MTMR_10ms_OFFSET)); // clear int flag
pMtimerInt->sfnOffsetIntFlag = 1;
pMtimerInt->sfnOffsetIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C
#endif
#if 0
if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == pMtimerInt->txSlotIntCnt))
{
if (0 == (pMtimerInt->sfnOffsetIntCnt&0x1))
{
set_trigger_state(GPIO_ON);
}
else
{
set_trigger_state(GPIO_OFF);
}
}
#endif
if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == (pMtimerInt->sfnOffsetIntCnt&0x3)))
{
spu_log_server_isr();
}
}
if ((tEventFlag & (1<<MTMR_TDD_OFFSET_10000)) && (MTIMER_JESD_RX1_ID == nTmrId)) // orx 25ms timer int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET_10000));

13
public/ecs_rfm_spu1/driver/src/mtimer_cal.s.c
View File

@ -154,17 +154,8 @@ void mtimer_1pps_sfn_cal(uint8_t nTmrId)
int32_t gPP1sLockCnt = 0;
int32_t mtimer_1pps_func(uint8_t nTmrId)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
JesdOrxPara_t* orx_para_ptr = pEcsDmLocalMgt->jesd_orx_para_ptr;
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[nTmrId];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
// orx adjust pp1s
if ((0 < orx_para_ptr->orx_calldrv_cnt) && (1 == orx_para_ptr->pp1s_adjust_flag))
{
mtimer_1pps_resync(nTmrId);
orx_para_ptr->pp1s_adjust_flag = 0;
}
//stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
// gps unlock -> lock, adjust pp1s
pMtimerCal->pp1sLockFlag = do_read_volatile(ARM_LOCK_FLAG_ADDR);
@ -187,7 +178,7 @@ int32_t mtimer_1pps_func(uint8_t nTmrId)
pMtimerCal->sfnValidFlag = do_read_volatile(ARM_SFN_VALID_ADDR);
pMtimerCal->sfnFlipFlag = do_read_volatile(ARM_SFN_FLIP_ADDR);
__ucps2_synch(f_SMR);
if ((0 < pMtimerInt->txSlotIntCnt) && (ARM_SFN_VALID_FLAG == pMtimerCal->sfnValidFlag) && (pMtimerCal->sfnFlipFlag != pMtimerCal->sfnFlipFlagPre))
if (/*(0 < pMtimerInt->txSlotIntCnt) && */(ARM_SFN_VALID_FLAG == pMtimerCal->sfnValidFlag) && (pMtimerCal->sfnFlipFlag != pMtimerCal->sfnFlipFlagPre))
{
do_write(ARM_SFN_VALID_ADDR, ARM_SFN_NOTVALID_FLAG);
__ucps2_synch(f_SMW);

30
public/ecs_rfm_spu1/driver/src/mtimer_cell.s.c
View File

@ -40,7 +40,7 @@ int32_t mtimer_init4phy(phy_timer_config_ind_t *mtmr)
return check_phy_cell();
}
// 建小区，先走ecs rfm1的建小区流程，再通知APE
// cell building, first build cell on ecs rfm1, and then inform ape cores
int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
{
int32_t nScsId = my_mtmr->scsId;
@ -57,7 +57,7 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
int32_t j = 0;
for (i = 0; i < PHY_SCS_MAX_NUM; i++)
{
if (SCS_1st_MTIMER_ID == do_read_volatile_short(&(phyPara[i].mtimerId))) // 已建了第一个子载波小区
if (SCS_1st_MTIMER_ID == do_read_volatile_short(&(phyPara[i].mtimerId))) // already building the first scs id cell
{
break;
}
@ -67,7 +67,7 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+33), i); // 0xb7e06084
// 没有任何scs建过小区
// no cell built on any scs id
if (PHY_SCS_MAX_NUM == i) // no cell on cpri timer, build cell on cpri timer
{
do_write_short((&(phyPara[nScsId].mtimerId)), SCS_1st_MTIMER_ID);
@ -94,14 +94,12 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+34), my_mtmr->runCoreId); // 0xb7e06088
debug_write((DBG_DDR_IDX_DRV_BASE+35), nScsId); // 0xb7e0608c
debug_write((DBG_DDR_IDX_DRV_BASE+35), my_mtmr->scsId); // 0xb7e06090
}
else // 已建过小区
else // have cell built
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
if (my_mtmr->scsId == do_read_volatile_short(&(phyPara[i].scsId))) // 继续在第一个子载波建小区
if (my_mtmr->scsId == do_read_volatile_short(&(phyPara[i].scsId))) // continue building cell on the first scs id
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
@ -109,7 +107,7 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
if (0 != (my_mtmr->runCoreId & runCore))
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), runCore); // 0xb7e06090
return -1; // 该小区已建过
return -1; // this cell has been built
}
else
{
@ -126,7 +124,7 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // 输入的coreId有误
return -2; // the input coreId is not correct
}
}
else
@ -136,18 +134,18 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // 输入的coreId有误
return -2; // the input coreId is not correct
}
}
}
}
else // 第二个子载波
else // the second scs id
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
for (j = 0; j < PHY_SCS_MAX_NUM; j++)
{
if (SCS_2nd_MTIMER_ID == do_read_volatile_short(&(phyPara[j].mtimerId))) // 已建过第二个子载波小区
if (SCS_2nd_MTIMER_ID == do_read_volatile_short(&(phyPara[j].mtimerId))) // already building the second scs id cell
{
break;
}
@ -189,11 +187,11 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
}
else
{
if (my_mtmr->scsId == do_read_volatile_short(&(phyPara[j].scsId))) // 继续在第二个子载波建小区
if (my_mtmr->scsId == do_read_volatile_short(&(phyPara[j].scsId))) // continue building cell on the first scs id
{
if (0 != (my_mtmr->runCoreId & runCore))
{
return -1; // 该小区已建过
return -1; // this cell has been built
}
else
{
@ -205,14 +203,14 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
{
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, my_mtmr->runCoreId))
{
return -2; // 输入的coreId有误
return -2; // the input coreId is not correct
}
}
else
{
if (-1 == set_ecpri_ape_slot_offset(my_mtmr->runCoreId))
{
return -2; // 输入的coreId有误
return -2; // the input coreId is not correct
}
}
}