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1. fix UCP4008-SL-EVB new feature #1173;

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2. modify shared SM5 address.
This commit is contained in:
xinxin.li 2023-10-30 16:45:47 +08:00
parent 0cc4a18455
commit 726d268715
1 changed files with 28 additions and 28 deletions
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56
public/common/driver/inc/phy_para.h
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@ -7,23 +7,23 @@
#define SFN_PERIOD 10000 // 10ms
#define SLOT_SYMBOL_NUM 14
#define SPU_DRV_SM_ADDR (0x0A4D7000) // (0x0A4F2000)
#define SPU_DRV_SM_ADDR (0x0A4F2000) // (0x0A4D7000)
#define PROTO_SEL_ADDR (SPU_DRV_SM_ADDR+0x0)
#define PROTO_OPT_ADDR (SPU_DRV_SM_ADDR+0x4)
#define PHY_PARA_ADDR (SPU_DRV_SM_ADDR+0x8)
#define PHY_CELL_ADDR (SPU_DRV_SM_ADDR+0x100)
#define ORX_ADJUST_FLAG_ADDR (SPU_DRV_SM_ADDR+0x140)
#define ORX_ADJUST_FLAG_ADDR (SPU_DRV_SM_ADDR+0x140)
#define ORX_ADJUST_VAL_ADDR (SPU_DRV_SM_ADDR+0x144)
#define STC_TOD_INT_ADDR (SPU_DRV_SM_ADDR+0x200)
#define STC_RT_ADDR (SPU_DRV_SM_ADDR+0x204)
#define STC_RT_ADDR (SPU_DRV_SM_ADDR+0x204)
#define STC_CTW_EN_ADDR (SPU_DRV_SM_ADDR+0x208)
#define CPRI_DELAY_ADDR (SPU_DRV_SM_ADDR+0x210)
#define CPRI_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x214)
#define CPRI_TDD_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x218)
#define CPRI_TDD_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x218)
#define CTC_INT_TYPE_ADDR (SPU_DRV_SM_ADDR+0x21C)
@ -33,7 +33,7 @@
#define ARM_LOCK_FLAG_ADDR (SPU_DRV_SM_ADDR+0x22C)
#define ARM_SFN_VALID_FLAG (0x55)
#define ARM_SFN_NOTVALID_FLAG (0xAA)
#define ARM_SFN_NOTVALID_FLAG (0xAA)
#define CSU_STOP_CMD_ADDR (SPU_DRV_SM_ADDR+0x230)
#define CSU_UL_HEADER_DATA_OFFSET (SPU_DRV_SM_ADDR+0x234) // ul, the interval of frame header and frame data, ns as unit
@ -43,14 +43,14 @@
#define SERDES_INIT_FLAG_ADDR (SPU_DRV_SM_ADDR+0x240) // cpri or jesd clk init finished
#define STC_ONEPPS_OUT_ADDR (SPU_DRV_SM_ADDR+0x244)
#define JESD_RX_CH_PARA (SPU_DRV_SM_ADDR+0x248)
#define JESD_RX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x24C)
#define JESD_RX_CH_PARA (SPU_DRV_SM_ADDR+0x248)
#define JESD_RX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x24C)
#define JESD_ORX_CH_PARA (SPU_DRV_SM_ADDR+0x250)
#define JESD_ORX_CH_PARA (SPU_DRV_SM_ADDR+0x250)
#define JESD_ORX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x254)
#define JESD_TX_CH_PARA (SPU_DRV_SM_ADDR+0x258)
#define JESD_TX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x25C)
#define JESD_TX_CH_PARA (SPU_DRV_SM_ADDR+0x258)
#define JESD_TX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x25C)
#define CPRI_TX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x260)
#define CPRI_RX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x264)
@ -59,35 +59,35 @@
#define DDR_MONITOR_ENABLE (SPU_DRV_SM_ADDR+0x270) // 开始监测ddr性能
#define DDR_MONITOR_CNT (SPU_DRV_SM_ADDR+0x274)
#define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // us as unit
#define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C)
#define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // us as unit
#define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C)
// GPIO JESD TX/RX/ORX bit
#define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280)
#define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0)
#define GPIO_JESD_RF_VALID (GPIO_FROM_CFG_FILE+0x10)
#define GPIO_JESD_TRIGGER_BIT (GPIO_FROM_CFG_FILE+0x60)
#define GPIO_JESD_TRIGGER_VALID (GPIO_FROM_CFG_FILE+0x70)
#define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280)
#define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0)
#define GPIO_JESD_RF_VALID (GPIO_FROM_CFG_FILE+0x10)
#define GPIO_JESD_TRIGGER_BIT (GPIO_FROM_CFG_FILE+0x60)
#define GPIO_JESD_TRIGGER_VALID (GPIO_FROM_CFG_FILE+0x70)
#define SLOT_NUM_DEBUG_ADDR (0x0A4D7300)
#define APE_INT_INFO_ADDR (0x0A4D7400)
#define SLOT_NUM_DEBUG_ADDR (0x0A4D7300)
#define APE_INT_INFO_ADDR (0x0A4D7400)
#define PHY_CELL_FLAG 0xAFAFAFAF
#define ARM_SFN_UPDATE_FLAG 0xA5A5A5A5
#define PHY_CELL_FLAG 0xAFAFAFAF
#define ARM_SFN_UPDATE_FLAG 0xA5A5A5A5
#define ENABLE_SFNCAL // 使能与arm的帧号校准功能
#define ENABLE_SFNCAL // 使能与arm的帧号校准功能
//#define DISTRIBUTED_BS
//#define INTEGRATION_BS
//#define GPS_PP1S_SYNC
#define GPS_LTE_OFFSET 0 // 700 // us
#define GPS_NR_OFFSET 0 // 2700 // us
#define LTE_NR_OFFSET 0 // 2000 // us
#define GPS_LTE_OFFSET 0 // 700 // us
#define GPS_NR_OFFSET 0 // 2700 // us
#define LTE_NR_OFFSET 0 // 2000 // us
#define SCS_MAX_NUM 2
#define SCS_MAX_NUM 2
#define MTIMER_INTEGRATED_MAX_NUM 4
#define MTIMER_DISTRIBUTED_MAX_NUM 2
#define MTIMER_INTEGRATED_MAX_NUM 4
#define MTIMER_DISTRIBUTED_MAX_NUM 2
typedef enum _tagScsId
{