From 79c795ee4df74344a668e7a961ff9e34d42babce Mon Sep 17 00:00:00 2001 From: "xinxin.li" Date: Wed, 24 Apr 2024 20:28:37 +0800 Subject: [PATCH] =?UTF-8?q?1.=20UCP4008-SL-EVB=20feature=20enhancement#174?= =?UTF-8?q?0/1741;=202.=20=E5=B0=86pp1s=E4=B8=AD=E6=96=AD=E4=BB=8EAPE0?= =?UTF-8?q?=E7=A7=BB=E5=88=B0PET=20RFM1=EF=BC=9B=203.=20=E5=8E=BB=E6=8E=89?= =?UTF-8?q?APE=E4=B8=8A=E7=9A=84=E6=8E=A5=E6=94=B6=E6=97=B6=E9=9A=99?= =?UTF-8?q?=E4=B8=AD=E6=96=AD=EF=BC=8C=E5=B9=B6=E4=BF=AE=E6=94=B9=E6=8E=A5?= =?UTF-8?q?=E6=94=B6=E5=B8=A7=E5=8F=B7/=E6=97=B6=E9=9A=99=E5=8F=B7/?= =?UTF-8?q?=E6=97=B6=E9=9A=99cycle=E7=9A=84=E8=AE=A1=E7=AE=97=E6=96=B9?= =?UTF-8?q?=E5=BC=8F=EF=BC=9B=204.=20=E6=B5=8B=E8=AF=95case=EF=BC=9Acase21?= =?UTF-8?q?=E3=80=81case24=E3=80=81case34.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- inc/drv_ape.h | 26 ++-- public/ape_spu/driver/inc/ape_mtimer.h | 16 +- public/ape_spu/driver/src/ape_drv.s.c | 2 +- public/ape_spu/driver/src/ape_mtimer.s.c | 144 ++++++++++++++---- public/ape_spu/driver/src/ape_stc_timer.s.c | 8 +- public/ape_spu/osp/src/osp_init.s.c | 2 +- public/common/driver/inc/phy_para.h | 1 + public/common/driver/src/phy_para.s.c | 20 +++ public/ecs_rfm_spu1/driver/src/cpri_timer.s.c | 10 +- .../ecs_rfm_spu1/driver/src/ecpri_timer.s.c | 10 +- public/ecs_rfm_spu1/driver/src/jesd_timer.s.c | 41 ++--- public/pet_rfm_spu1/top/src/main.s.c | 3 + .../pet_rfm_spu1/top/src/pet_rfm_spu1_top.s.c | 2 + public/pet_rfm_spu1/top/src/stc_tod.s.c | 50 ++++++ 14 files changed, 251 insertions(+), 84 deletions(-) create mode 100644 public/pet_rfm_spu1/top/src/stc_tod.s.c diff --git a/inc/drv_ape.h b/inc/drv_ape.h index befdd3c..55e7ac0 100644 --- a/inc/drv_ape.h +++ b/inc/drv_ape.h @@ -56,10 +56,10 @@ void stc_timer_todint_init(void); /**************************************************/ /* 函数名称：get_tx_nr_sfn - 函数入参：scs + 函数入参：无 函数功能：获取发送帧号 */ -int get_tx_nr_sfn(uint8_t scs); +int get_tx_nr_sfn(); /* 函数名称：get_tx_lte_sfn @@ -70,10 +70,10 @@ int get_tx_lte_sfn(); /* 函数名称：get_tx_nr_slot - 函数入参：scs + 函数入参：无 函数功能：获取发送时隙号 */ -int get_tx_nr_slot(uint8_t scs); +int get_tx_nr_slot(); /* 函数名称：get_tx_lte_subframe @@ -84,10 +84,10 @@ int get_tx_lte_subframe(); /* 函数名称：get_rx_nr_sfn - 函数入参：scs + 函数入参：无 函数功能：接收帧号 */ -int get_rx_nr_sfn(uint8_t scs); +int get_rx_nr_sfn(); /* 函数名称：get_rx_lte_sfn @@ -98,10 +98,10 @@ int get_rx_lte_sfn(); /* 函数名称：get_rx_nr_slot - 函数入参：scs + 函数入参：无 函数功能：接收时隙号 */ -int get_rx_nr_slot(uint8_t scs); +int get_rx_nr_slot(); /* 函数名称：get_rx_lte_subframe @@ -112,10 +112,10 @@ int get_rx_lte_subframe(); /* 函数名称：get_tx_nr_slot_cycle - 函数入参：scs + 函数入参：无 函数功能：获取发送时隙偏移，单位为ns */ -int get_tx_nr_slot_cycle(uint8_t scs); +int get_tx_nr_slot_cycle(); /* 函数名称：get_tx_lte_slot_cycle @@ -126,14 +126,14 @@ int get_tx_lte_subframe_cycle(); /* 函数名称：get_rx_nr_slot_cycle - 函数入参：scs + 函数入参：无 函数功能：获取接收时隙偏移，单位为ns */ -int get_rx_nr_slot_cycle(uint8_t scs); +int get_rx_nr_slot_cycle(); /* 函数名称：get_rx_lte_slot_cycle - 函数入参：scs + 函数入参：无 函数功能：获取接收时隙偏移，单位为ns */ int get_rx_lte_subframe_cycle(); diff --git a/public/ape_spu/driver/inc/ape_mtimer.h b/public/ape_spu/driver/inc/ape_mtimer.h index 3b16b6a..a958314 100644 --- a/public/ape_spu/driver/inc/ape_mtimer.h +++ b/public/ape_spu/driver/inc/ape_mtimer.h @@ -15,20 +15,20 @@ int32_t mtimer_sfn_para_init(int32_t nTmrId, int32_t nScsId); void ape_slot_ctw_set(uint8_t nTmrId); int32_t mtimer_ape_slot_callback(uint8_t nTmrId); -int32_t get_tx_nr_sfn(uint8_t scs); +int32_t get_tx_nr_sfn(); int32_t get_tx_lte_sfn(); -int32_t get_tx_nr_slot(uint8_t scs); +int32_t get_tx_nr_slot(); int32_t get_tx_lte_subframe(); -int32_t get_rx_nr_sfn(uint8_t scs); +int32_t get_rx_nr_sfn(); int32_t get_rx_lte_sfn(); -int32_t get_rx_nr_slot(uint8_t scs); +int32_t get_rx_nr_slot(); int32_t get_rx_lte_subframe(); -uint32_t get_tx_nr_slot_cycle(); -uint32_t get_tx_lte_subframe_cycle(); -uint32_t get_rx_nr_slot_cycle(); -uint32_t get_rx_lte_subframe_cycle(); +int32_t get_tx_nr_slot_cycle(); +int32_t get_tx_lte_subframe_cycle(); +int32_t get_rx_nr_slot_cycle(); +int32_t get_rx_lte_subframe_cycle(); #endif diff --git a/public/ape_spu/driver/src/ape_drv.s.c b/public/ape_spu/driver/src/ape_drv.s.c index c86ad6a..cd8651f 100644 --- a/public/ape_spu/driver/src/ape_drv.s.c +++ b/public/ape_spu/driver/src/ape_drv.s.c @@ -71,7 +71,7 @@ void tod_int_init(void) int apeId = get_core_id(); if (0 == apeId) { - stc_timer_todint_init(); + //stc_timer_todint_init(); UCP_PRINT_EMPTY("stc tod int init. \r\n"); } diff --git a/public/ape_spu/driver/src/ape_mtimer.s.c b/public/ape_spu/driver/src/ape_mtimer.s.c index cfda4b9..79bfbc7 100644 --- a/public/ape_spu/driver/src/ape_mtimer.s.c +++ b/public/ape_spu/driver/src/ape_mtimer.s.c @@ -387,7 +387,7 @@ int32_t mtimer_ape_slot_callback(uint8_t nTmrId) return 0; } -int32_t get_tx_nr_sfn(uint8_t scs) +int32_t get_tx_nr_sfn() { return gCellSfnPara[gMtimerId].txSfnNum; } @@ -397,7 +397,7 @@ int32_t get_tx_lte_sfn() return gCellSfnPara[gMtimerId].txSfnNum; } -int32_t get_tx_nr_slot(uint8_t scs) +int32_t get_tx_nr_slot() { return gCellSfnPara[gMtimerId].txSlotNum; } @@ -407,27 +407,97 @@ int32_t get_tx_lte_subframe() return gCellSfnPara[gMtimerId].txSlotNum; } -int32_t get_rx_nr_sfn(uint8_t scs) +int32_t get_rx_nr_sfn() { - return gCellSfnPara[gMtimerId].rxSfnNum; + int32_t txSlotNum = get_tx_nr_slot(); + int32_t rxSlotNum = get_rx_nr_slot(); + if (-1 == rxSlotNum) + { + return -1; + } + if (txSlotNum >= rxSlotNum) + { + return get_tx_nr_sfn(); + } + else + { + return (get_tx_nr_sfn()-1); + } } int32_t get_rx_lte_sfn() { - return gCellSfnPara[gMtimerId].rxSfnNum; + int32_t txSlotNum = get_tx_lte_subframe(); + int32_t rxSlotNum = get_rx_lte_subframe(); + if (-1 == rxSlotNum) + { + return -1; + } + if (txSlotNum >= rxSlotNum) + { + return get_tx_lte_sfn(); + } + else + { + return (get_tx_lte_sfn()-1); + } } -int32_t get_rx_nr_slot(uint8_t scs) +int32_t get_rx_nr_slot() { - return gCellSfnPara[gMtimerId].rxSlotNum; + int32_t rxSlotNum = 0; + int32_t offsetCycle = get_rx_nr_slot_cycle(); + if (-1 != offsetCycle) + { + if (0 <= offsetCycle) + { + rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - (offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000); + } + else + { + rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - 1 - __ucps2_abs(offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000); + } + if (0 > rxSlotNum) + { + rxSlotNum = (rxSlotNum + gCellSfnPara[gMtimerId].slotMaxNum) % gCellSfnPara[gMtimerId].slotMaxNum; + } + + return rxSlotNum; + } + else + { + return -1; + } } int32_t get_rx_lte_subframe() { - return gCellSfnPara[gMtimerId].rxSlotNum; + int32_t rxSlotNum = 0; + int32_t offsetCycle = get_rx_lte_subframe_cycle(); + if (-1 != offsetCycle) + { + if (0 <= offsetCycle) + { + rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - (offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000); + } + else + { + rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - 1 - __ucps2_abs(offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000); + } + if (0 > rxSlotNum) + { + rxSlotNum = (rxSlotNum + gCellSfnPara[gMtimerId].slotMaxNum) % gCellSfnPara[gMtimerId].slotMaxNum; + } + + return rxSlotNum; + } + else + { + return -1; + } } -uint32_t get_tx_nr_slot_cycle() +int32_t get_tx_nr_slot_cycle() { uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming; __ucps2_synch(0); @@ -441,7 +511,7 @@ uint32_t get_tx_nr_slot_cycle() return offsetCycle; } -uint32_t get_tx_lte_subframe_cycle() +int32_t get_tx_lte_subframe_cycle() { uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming; __ucps2_synch(0); @@ -455,31 +525,49 @@ uint32_t get_tx_lte_subframe_cycle() return offsetCycle; } -uint32_t get_rx_nr_slot_cycle() +int32_t get_rx_nr_slot_cycle() { - uint32_t rxSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].rxSlotTiming; - __ucps2_synch(0); - int32_t offsetCycle = GET_STC_CNT() - rxSlotTiming; - if (0 > offsetCycle) + int32_t interval = get_tx_rx_interval(); + if (0 <= interval) { - uint32_t limitVal = 1000000000; - offsetCycle = (offsetCycle+limitVal)%limitVal; + uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming; + __ucps2_synch(0); + int32_t offsetCycle = GET_STC_CNT() - txSlotTiming; + if (0 > offsetCycle) + { + uint32_t limitVal = 1000000000; + offsetCycle = (offsetCycle+limitVal)%limitVal; + } + offsetCycle -= interval; + + return offsetCycle; + } + else + { + return -1; } - - return offsetCycle; } -uint32_t get_rx_lte_subframe_cycle() +int32_t get_rx_lte_subframe_cycle() { - uint32_t rxSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].rxSlotTiming; - __ucps2_synch(0); - int32_t offsetCycle = GET_STC_CNT() - rxSlotTiming; - if (0 > offsetCycle) + int32_t interval = get_tx_rx_interval(); + if (0 <= interval) { - uint32_t limitVal = 1000000000; - offsetCycle = (offsetCycle+limitVal)%limitVal; + uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming; + __ucps2_synch(0); + int32_t offsetCycle = GET_STC_CNT() - txSlotTiming; + if (0 > offsetCycle) + { + uint32_t limitVal = 1000000000; + offsetCycle = (offsetCycle+limitVal)%limitVal; + } + offsetCycle -= interval; + + return offsetCycle; + } + else + { + return -1; } - - return offsetCycle; } diff --git a/public/ape_spu/driver/src/ape_stc_timer.s.c b/public/ape_spu/driver/src/ape_stc_timer.s.c index 8da60bd..52032e7 100644 --- a/public/ape_spu/driver/src/ape_stc_timer.s.c +++ b/public/ape_spu/driver/src/ape_stc_timer.s.c @@ -106,7 +106,7 @@ void stc_timer_set_next_ctw(int32_t setFlag) // debug_write((DBG_DDR_IDX_DRV_BASE+6144 + (setCnt&0x1FF) + (apeId << 9)), gStcTimerPara.ctwVal); // 0x6000 #endif } - +#if 0 void stc_timer_todint_init(void) { int32_t apeId = get_core_id(); @@ -124,7 +124,7 @@ void stc_timer_todint_init(void) debug_write(DBG_DDR_ERR_IDX(apeId, 8), ret); } } - +#endif ddr_spinlock_t gSpinLockCtwInit; void stc_timer_ctwint_init() { @@ -240,7 +240,7 @@ void isr_stc_timer_int() status = do_read_volatile(&CTW_REG_STATUS); } } - +#if 0 //extern UINT8 waitTodInt; //uint32_t gApe0TodIntCnt = 0; void isr_stc_tod_int() @@ -296,6 +296,6 @@ void isr_stc_tod_int() status = do_read_volatile(&TOD_REG_INT_STATUS); } } - +#endif diff --git a/public/ape_spu/osp/src/osp_init.s.c b/public/ape_spu/osp/src/osp_init.s.c index 0073dfd..3601cca 100644 --- a/public/ape_spu/osp/src/osp_init.s.c +++ b/public/ape_spu/osp/src/osp_init.s.c @@ -276,7 +276,7 @@ void osp_init() /*******************************************************************/ start_hook_func osp_init_start_hook[] = { - tod_int_init, + //tod_int_init, ape_drv_int_init, osp_init, phy_init, diff --git a/public/common/driver/inc/phy_para.h b/public/common/driver/inc/phy_para.h index eb2e7d8..31b75ba 100644 --- a/public/common/driver/inc/phy_para.h +++ b/public/common/driver/inc/phy_para.h @@ -307,5 +307,6 @@ int32_t send_cpri_csu_stop_cmd(); int32_t send_cpri_csu_start_cmd(); +int32_t get_tx_rx_interval(); #endif /* COMMON_INC_PHY_PARA_H_ */ diff --git a/public/common/driver/src/phy_para.s.c b/public/common/driver/src/phy_para.s.c index 9a3dd7c..d0a97a4 100644 --- a/public/common/driver/src/phy_para.s.c +++ b/public/common/driver/src/phy_para.s.c @@ -179,3 +179,23 @@ int32_t send_cpri_csu_start_cmd() return 0; } +int32_t get_tx_rx_interval() +{ + uint8_t nBsType = get_protocol_sel(); + if (PROTOCOL_JESD == nBsType) + { + return 0; + } + else if (PROTOCOL_CPRI == nBsType) + { + uint32_t advance = do_read_volatile(CPRI_ADVANCE_ADDR); + uint32_t delay = do_read_volatile(CPRI_DELAY_ADDR); + + return (advance+delay); + } + else + { + return -1; + } +} + diff --git a/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c b/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c index b40fee2..2939867 100644 --- a/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c @@ -587,9 +587,9 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId) set_mtimer_tmrpoint_ns(MTIMER_CPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT); enable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); // rx slot int - tmrId = MTMR_APE0_RXSLOT + (apeId<<1); - set_mtimer_tmrpoint_ns(MTIMER_CPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT); - enable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); + //tmrId = MTMR_APE0_RXSLOT + (apeId<<1); + //set_mtimer_tmrpoint_ns(MTIMER_CPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT); + //enable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); @@ -622,8 +622,8 @@ int32_t clear_cpri_ape_slot_offset(uint32_t apeCoreId) tmrId = MTMR_APE0_TXSLOT + (apeId<<1); disable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); // rx slot int - tmrId = MTMR_APE0_RXSLOT + (apeId<<1); - disable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); + //tmrId = MTMR_APE0_RXSLOT + (apeId<<1); + //disable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); diff --git a/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c b/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c index 397fa2d..d03a49c 100644 --- a/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c @@ -335,9 +335,9 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId) set_mtimer_tmrpoint_ns(MTIMER_ECPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT); enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); // rx slot int - tmrId = MTMR_APE0_RXSLOT + (apeId<<1); - set_mtimer_tmrpoint_ns(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT); - enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); + //tmrId = MTMR_APE0_RXSLOT + (apeId<<1); + //set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT); + //enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); @@ -368,8 +368,8 @@ int32_t clear_ecpri_ape_slot_offset(uint32_t apeCoreId) tmrId = MTMR_APE0_TXSLOT + (apeId<<1); disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); // rx slot int - tmrId = MTMR_APE0_RXSLOT + (apeId<<1); - disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); + //tmrId = MTMR_APE0_RXSLOT + (apeId<<1); + //disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); diff --git a/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c b/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c index f4e7958..0a25f82 100644 --- a/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c @@ -255,8 +255,8 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd get_jesd_timer_pointns_para(nTmrId, pMtimerPara->rxCsuOn[0].timerPoint, &pMtimerPara->rxCsuOn[0].pointL, &pMtimerPara->rxCsuOn[0].pointM, &pMtimerPara->rxCsuOn[0].pointH); - debug_write((DBG_DDR_IDX_DRV_BASE+48+(0<<2)), pMtimerTxPara->txCsuOn[0].timerPoint); // 0xC0 - debug_write((DBG_DDR_IDX_DRV_BASE+50+(0<<2)), pMtimerPara->rxCsuOn[0].timerPoint); // 0xC8 + debug_write((DBG_DDR_IDX_DRV_BASE+992+(0<<2)), pMtimerTxPara->txCsuOn[0].timerPoint); // 0xF80 + debug_write((DBG_DDR_IDX_DRV_BASE+993+(0<<2)), pMtimerPara->rxCsuOn[0].timerPoint); // 0xF84 } else { @@ -586,11 +586,11 @@ void jesd_timer_rcfg_act(int32_t nTmrId) pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1; //if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell - if (0 == pMtimerSfn->slotNumPP1s) // no frame header offset, and the first cell + if (0 != reCfgFlag) // no frame header offset, and the first cell { - //pMtimerSfn->txSfnNum++; - //pMtimerSfn->txSfnNum &= 0x3FF; - pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum; + pMtimerSfn->txSfnNum++; + pMtimerSfn->txSfnNum &= 0x3FF; + //pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum; //pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1; } addr = (uint32_t)&(phyPara[nScsId].txSfnNum); @@ -829,9 +829,9 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId) set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr3Point, MTIMER_MASK_32BIT); enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId)); // rx slot int - tmrId = MTMR_APE0_RXSLOT + (apeId<<1); - set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr4Point, MTIMER_MASK_32BIT); - enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId)); + //tmrId = MTMR_APE0_RXSLOT + (apeId<<1); + //set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr4Point, MTIMER_MASK_32BIT); + //enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId)); runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); @@ -864,8 +864,8 @@ int32_t clear_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId) tmrId = MTMR_APE0_TXSLOT + (apeId<<1); disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId)); // rx slot int - tmrId = MTMR_APE0_RXSLOT + (apeId<<1); - disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId)); + //tmrId = MTMR_APE0_RXSLOT + (apeId<<1); + //disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId)); runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); @@ -1294,13 +1294,13 @@ void jesd_10ms_callback(uint8_t nTmrId) debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2))), val); // 0xd00 val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((1+(core<<2))<<2)); - debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 1), val); // 0xd00 + debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 1), val); // 0xd04 - val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((2+(core<<2))<<2)); - debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 2), val); // 0xd00 + //val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((2+(core<<2))<<2)); + //debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 2), val); // 0xd00 - val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((3+(core<<2))<<2)); - debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 3), val); // 0xd00 + //val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((3+(core<<2))<<2)); + //debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 3), val); // 0xd00 } #endif //debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480 @@ -1309,9 +1309,10 @@ void jesd_10ms_callback(uint8_t nTmrId) { do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<sfnOffsetIntFlag = 1; pMtimerInt->sfnOffsetIntCnt++; - if (0 == pMtimerSfn->cellSetup) + if (0 == reCfgFlag) { pMtimerSfn->txSfnNum++; pMtimerSfn->txSfnNum &= 0x3FF; @@ -1329,11 +1330,13 @@ void jesd_10ms_callback(uint8_t nTmrId) { spu_log_server_isr(); } +debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480 } if (cEventFlag & (1<sfnIntCnt++; #ifdef PALLADIUM_TEST debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(nTmrId<<2)), pMtimerInt->sfnIntCnt); // 0x108 @@ -1342,14 +1345,14 @@ void jesd_10ms_callback(uint8_t nTmrId) if (((runCore & pMtimerPara->runCoreId) == pMtimerPara->runCoreId) && (4 == reCfgFlag)) { debug_write((DBG_DDR_IDX_DRV_BASE+907), GET_STC_CNT()); // 0xe2c // timer restart finished -//uint32_t start = GET_STC_CNT(); jesd_timer_rcfg_act(nTmrId); -//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480 + pMtimerCal->sfnCalFinished = 1; pMtimerInt->tddOffsetIntCnt = 0; debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38 debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C } +debug_write((DBG_DDR_IDX_DRV_BASE+289), (GET_STC_CNT()-start)); // 0x484 } if ((tEventFlag & (1<