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1. UCP4008-SL-EVB feature enhancement#1740/1741;

Browse Source 
2. 将pp1s中断从APE0移到PET RFM1；
3. 去掉APE上的接收时隙中断，并修改接收帧号/时隙号/时隙cycle的计算方式；
4. 测试case：case21、case24、case34.
This commit is contained in:
xinxin.li 2024-04-24 20:28:37 +08:00
parent 57f144a163
commit 79c795ee4d
14 changed files with 251 additions and 84 deletions
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26
inc/drv_ape.h
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@ -56,10 +56,10 @@ void stc_timer_todint_init(void);
/**************************************************/
/*
函数名称：get_tx_nr_sfn
函数入参：scs
函数入参：无
函数功能：获取发送帧号
*/
int get_tx_nr_sfn(uint8_t scs);
int get_tx_nr_sfn();
/*
函数名称：get_tx_lte_sfn
@ -70,10 +70,10 @@ int get_tx_lte_sfn();
/*
函数名称：get_tx_nr_slot
函数入参：scs
函数入参：无
函数功能：获取发送时隙号
*/
int get_tx_nr_slot(uint8_t scs);
int get_tx_nr_slot();
/*
函数名称：get_tx_lte_subframe
@ -84,10 +84,10 @@ int get_tx_lte_subframe();
/*
函数名称：get_rx_nr_sfn
函数入参：scs
函数入参：无
函数功能：接收帧号
*/
int get_rx_nr_sfn(uint8_t scs);
int get_rx_nr_sfn();
/*
函数名称：get_rx_lte_sfn
@ -98,10 +98,10 @@ int get_rx_lte_sfn();
/*
函数名称：get_rx_nr_slot
函数入参：scs
函数入参：无
函数功能：接收时隙号
*/
int get_rx_nr_slot(uint8_t scs);
int get_rx_nr_slot();
/*
函数名称：get_rx_lte_subframe
@ -112,10 +112,10 @@ int get_rx_lte_subframe();
/*
函数名称：get_tx_nr_slot_cycle
函数入参：scs
函数入参：无
函数功能：获取发送时隙偏移，单位为ns
*/
int get_tx_nr_slot_cycle(uint8_t scs);
int get_tx_nr_slot_cycle();
/*
函数名称：get_tx_lte_slot_cycle
@ -126,14 +126,14 @@ int get_tx_lte_subframe_cycle();
/*
函数名称：get_rx_nr_slot_cycle
函数入参：scs
函数入参：无
函数功能：获取接收时隙偏移，单位为ns
*/
int get_rx_nr_slot_cycle(uint8_t scs);
int get_rx_nr_slot_cycle();
/*
函数名称：get_rx_lte_slot_cycle
函数入参：scs
函数入参：无
函数功能：获取接收时隙偏移，单位为ns
*/
int get_rx_lte_subframe_cycle();

16
public/ape_spu/driver/inc/ape_mtimer.h
View File

@ -15,20 +15,20 @@ int32_t mtimer_sfn_para_init(int32_t nTmrId, int32_t nScsId);
void ape_slot_ctw_set(uint8_t nTmrId);
int32_t mtimer_ape_slot_callback(uint8_t nTmrId);
int32_t get_tx_nr_sfn(uint8_t scs);
int32_t get_tx_nr_sfn();
int32_t get_tx_lte_sfn();
int32_t get_tx_nr_slot(uint8_t scs);
int32_t get_tx_nr_slot();
int32_t get_tx_lte_subframe();
int32_t get_rx_nr_sfn(uint8_t scs);
int32_t get_rx_nr_sfn();
int32_t get_rx_lte_sfn();
int32_t get_rx_nr_slot(uint8_t scs);
int32_t get_rx_nr_slot();
int32_t get_rx_lte_subframe();
uint32_t get_tx_nr_slot_cycle();
uint32_t get_tx_lte_subframe_cycle();
uint32_t get_rx_nr_slot_cycle();
uint32_t get_rx_lte_subframe_cycle();
int32_t get_tx_nr_slot_cycle();
int32_t get_tx_lte_subframe_cycle();
int32_t get_rx_nr_slot_cycle();
int32_t get_rx_lte_subframe_cycle();
#endif

2
public/ape_spu/driver/src/ape_drv.s.c
View File

@ -71,7 +71,7 @@ void tod_int_init(void)
int apeId = get_core_id();
if (0 == apeId)
{
stc_timer_todint_init();
//stc_timer_todint_init();
UCP_PRINT_EMPTY("stc tod int init. \r\n");
}

122
public/ape_spu/driver/src/ape_mtimer.s.c
View File

@ -387,7 +387,7 @@ int32_t mtimer_ape_slot_callback(uint8_t nTmrId)
return 0;
}
int32_t get_tx_nr_sfn(uint8_t scs)
int32_t get_tx_nr_sfn()
{
return gCellSfnPara[gMtimerId].txSfnNum;
}
@ -397,7 +397,7 @@ int32_t get_tx_lte_sfn()
return gCellSfnPara[gMtimerId].txSfnNum;
}
int32_t get_tx_nr_slot(uint8_t scs)
int32_t get_tx_nr_slot()
{
return gCellSfnPara[gMtimerId].txSlotNum;
}
@ -407,27 +407,97 @@ int32_t get_tx_lte_subframe()
return gCellSfnPara[gMtimerId].txSlotNum;
}
int32_t get_rx_nr_sfn(uint8_t scs)
int32_t get_rx_nr_sfn()
{
return gCellSfnPara[gMtimerId].rxSfnNum;
int32_t txSlotNum = get_tx_nr_slot();
int32_t rxSlotNum = get_rx_nr_slot();
if (-1 == rxSlotNum)
{
return -1;
}
if (txSlotNum >= rxSlotNum)
{
return get_tx_nr_sfn();
}
else
{
return (get_tx_nr_sfn()-1);
}
}
int32_t get_rx_lte_sfn()
{
return gCellSfnPara[gMtimerId].rxSfnNum;
int32_t txSlotNum = get_tx_lte_subframe();
int32_t rxSlotNum = get_rx_lte_subframe();
if (-1 == rxSlotNum)
{
return -1;
}
if (txSlotNum >= rxSlotNum)
{
return get_tx_lte_sfn();
}
else
{
return (get_tx_lte_sfn()-1);
}
}
int32_t get_rx_nr_slot(uint8_t scs)
int32_t get_rx_nr_slot()
{
return gCellSfnPara[gMtimerId].rxSlotNum;
int32_t rxSlotNum = 0;
int32_t offsetCycle = get_rx_nr_slot_cycle();
if (-1 != offsetCycle)
{
if (0 <= offsetCycle)
{
rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - (offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000);
}
else
{
rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - 1 - __ucps2_abs(offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000);
}
if (0 > rxSlotNum)
{
rxSlotNum = (rxSlotNum + gCellSfnPara[gMtimerId].slotMaxNum) % gCellSfnPara[gMtimerId].slotMaxNum;
}
return rxSlotNum;
}
else
{
return -1;
}
}
int32_t get_rx_lte_subframe()
{
return gCellSfnPara[gMtimerId].rxSlotNum;
int32_t rxSlotNum = 0;
int32_t offsetCycle = get_rx_lte_subframe_cycle();
if (-1 != offsetCycle)
{
if (0 <= offsetCycle)
{
rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - (offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000);
}
else
{
rxSlotNum = gCellSfnPara[gMtimerId].txSlotNum - 1 - __ucps2_abs(offsetCycle)/(gCellSfnPara[gMtimerId].slotPeriod*1000);
}
if (0 > rxSlotNum)
{
rxSlotNum = (rxSlotNum + gCellSfnPara[gMtimerId].slotMaxNum) % gCellSfnPara[gMtimerId].slotMaxNum;
}
uint32_t get_tx_nr_slot_cycle()
return rxSlotNum;
}
else
{
return -1;
}
}
int32_t get_tx_nr_slot_cycle()
{
uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
__ucps2_synch(0);
@ -441,7 +511,7 @@ uint32_t get_tx_nr_slot_cycle()
return offsetCycle;
}
uint32_t get_tx_lte_subframe_cycle()
int32_t get_tx_lte_subframe_cycle()
{
uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
__ucps2_synch(0);
@ -455,31 +525,49 @@ uint32_t get_tx_lte_subframe_cycle()
return offsetCycle;
}
uint32_t get_rx_nr_slot_cycle()
int32_t get_rx_nr_slot_cycle()
{
uint32_t rxSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].rxSlotTiming;
int32_t interval = get_tx_rx_interval();
if (0 <= interval)
{
uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
__ucps2_synch(0);
int32_t offsetCycle = GET_STC_CNT() - rxSlotTiming;
int32_t offsetCycle = GET_STC_CNT() - txSlotTiming;
if (0 > offsetCycle)
{
uint32_t limitVal = 1000000000;
offsetCycle = (offsetCycle+limitVal)%limitVal;
}
offsetCycle -= interval;
return offsetCycle;
}
uint32_t get_rx_lte_subframe_cycle()
else
{
uint32_t rxSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].rxSlotTiming;
return -1;
}
}
int32_t get_rx_lte_subframe_cycle()
{
int32_t interval = get_tx_rx_interval();
if (0 <= interval)
{
uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
__ucps2_synch(0);
int32_t offsetCycle = GET_STC_CNT() - rxSlotTiming;
int32_t offsetCycle = GET_STC_CNT() - txSlotTiming;
if (0 > offsetCycle)
{
uint32_t limitVal = 1000000000;
offsetCycle = (offsetCycle+limitVal)%limitVal;
}
offsetCycle -= interval;
return offsetCycle;
}
else
{
return -1;
}
}

8
public/ape_spu/driver/src/ape_stc_timer.s.c
View File

@ -106,7 +106,7 @@ void stc_timer_set_next_ctw(int32_t setFlag)
// debug_write((DBG_DDR_IDX_DRV_BASE+6144 + (setCnt&0x1FF) + (apeId << 9)), gStcTimerPara.ctwVal); // 0x6000
#endif
}
#if 0
void stc_timer_todint_init(void)
{
int32_t apeId = get_core_id();
@ -124,7 +124,7 @@ void stc_timer_todint_init(void)
debug_write(DBG_DDR_ERR_IDX(apeId, 8), ret);
}
}
#endif
ddr_spinlock_t gSpinLockCtwInit;
void stc_timer_ctwint_init()
{
@ -240,7 +240,7 @@ void isr_stc_timer_int()
status = do_read_volatile(&CTW_REG_STATUS);
}
}
#if 0
//extern UINT8 waitTodInt;
//uint32_t gApe0TodIntCnt = 0;
void isr_stc_tod_int()
@ -296,6 +296,6 @@ void isr_stc_tod_int()
status = do_read_volatile(&TOD_REG_INT_STATUS);
}
}
#endif

2
public/ape_spu/osp/src/osp_init.s.c
View File

@ -276,7 +276,7 @@ void osp_init()
/*******************************************************************/
start_hook_func osp_init_start_hook[] =
{
tod_int_init,
//tod_int_init,
ape_drv_int_init,
osp_init,
phy_init,

1
public/common/driver/inc/phy_para.h
View File

@ -307,5 +307,6 @@ int32_t send_cpri_csu_stop_cmd();
int32_t send_cpri_csu_start_cmd();
int32_t get_tx_rx_interval();
#endif /* COMMON_INC_PHY_PARA_H_ */

20
public/common/driver/src/phy_para.s.c
View File

@ -179,3 +179,23 @@ int32_t send_cpri_csu_start_cmd()
return 0;
}
int32_t get_tx_rx_interval()
{
uint8_t nBsType = get_protocol_sel();
if (PROTOCOL_JESD == nBsType)
{
return 0;
}
else if (PROTOCOL_CPRI == nBsType)
{
uint32_t advance = do_read_volatile(CPRI_ADVANCE_ADDR);
uint32_t delay = do_read_volatile(CPRI_DELAY_ADDR);
return (advance+delay);
}
else
{
return -1;
}
}

10
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -587,9 +587,9 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId)
set_mtimer_tmrpoint_ns(MTIMER_CPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
// rx slot int
tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
set_mtimer_tmrpoint_ns(MTIMER_CPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
//tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
//set_mtimer_tmrpoint_ns(MTIMER_CPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT);
//enable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
@ -622,8 +622,8 @@ int32_t clear_cpri_ape_slot_offset(uint32_t apeCoreId)
tmrId = MTMR_APE0_TXSLOT + (apeId<<1);
disable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
// rx slot int
tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
disable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
//tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
//disable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);

10
public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c
View File

@ -335,9 +335,9 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId)
set_mtimer_tmrpoint_ns(MTIMER_ECPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
// rx slot int
tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
set_mtimer_tmrpoint_ns(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
//tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
//set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT);
//enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
@ -368,8 +368,8 @@ int32_t clear_ecpri_ape_slot_offset(uint32_t apeCoreId)
tmrId = MTMR_APE0_TXSLOT + (apeId<<1);
disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
// rx slot int
tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
//tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
//disable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId));
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);

41
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -255,8 +255,8 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
get_jesd_timer_pointns_para(nTmrId, pMtimerPara->rxCsuOn[0].timerPoint, &pMtimerPara->rxCsuOn[0].pointL,
&pMtimerPara->rxCsuOn[0].pointM, &pMtimerPara->rxCsuOn[0].pointH);
debug_write((DBG_DDR_IDX_DRV_BASE+48+(0<<2)), pMtimerTxPara->txCsuOn[0].timerPoint); // 0xC0
debug_write((DBG_DDR_IDX_DRV_BASE+50+(0<<2)), pMtimerPara->rxCsuOn[0].timerPoint); // 0xC8
debug_write((DBG_DDR_IDX_DRV_BASE+992+(0<<2)), pMtimerTxPara->txCsuOn[0].timerPoint); // 0xF80
debug_write((DBG_DDR_IDX_DRV_BASE+993+(0<<2)), pMtimerPara->rxCsuOn[0].timerPoint); // 0xF84
}
else
{
@ -586,11 +586,11 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;
//if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
if (0 == pMtimerSfn->slotNumPP1s) // no frame header offset, and the first cell
if (0 != reCfgFlag) // no frame header offset, and the first cell
{
//pMtimerSfn->txSfnNum++;
//pMtimerSfn->txSfnNum &= 0x3FF;
pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
//pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
@ -829,9 +829,9 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
// rx slot int
tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
//tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
//set_mtimer_tmrpoint_ns(nTmrId, tmrId, tmr4Point, MTIMER_MASK_32BIT);
//enable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
@ -864,8 +864,8 @@ int32_t clear_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
tmrId = MTMR_APE0_TXSLOT + (apeId<<1);
disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
// rx slot int
tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
//tmrId = MTMR_APE0_RXSLOT + (apeId<<1);
//disable_mtimer_tmrpoint_int(nTmrId, tmrId, (MTMR_INT_APE0_SLOT+apeId));
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
@ -1294,13 +1294,13 @@ void jesd_10ms_callback(uint8_t nTmrId)
debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2))), val); // 0xd00
val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((1+(core<<2))<<2));
debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 1), val); // 0xd00
debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 1), val); // 0xd04
val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((2+(core<<2))<<2));
debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 2), val); // 0xd00
//val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((2+(core<<2))<<2));
//debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 2), val); // 0xd00
val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((3+(core<<2))<<2));
debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 3), val); // 0xd00
//val = do_read_volatile(SLOT_NUM_DEBUG_ADDR+((3+(core<<2))<<2));
//debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 3), val); // 0xd00
}
#endif
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
@ -1309,9 +1309,10 @@ void jesd_10ms_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_10ms_OFFSET));
do_write(tFlagAddr, (1<<MTMR_10ms_OFFSET)); // clear int flag
uint32_t start = GET_STC_CNT();
pMtimerInt->sfnOffsetIntFlag = 1;
pMtimerInt->sfnOffsetIntCnt++;
if (0 == pMtimerSfn->cellSetup)
if (0 == reCfgFlag)
{
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
@ -1329,11 +1330,13 @@ void jesd_10ms_callback(uint8_t nTmrId)
{
spu_log_server_isr();
}
debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
}
if (cEventFlag & (1<<MTMR_CEVENT_CNT14H)) // 10ms int
{
do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_CNT14H));
do_write(cFlagAddr, (1<<MTMR_CEVENT_CNT14H)); // clear int flag
uint32_t start = GET_STC_CNT();
pMtimerInt->sfnIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(nTmrId<<2)), pMtimerInt->sfnIntCnt); // 0x108
@ -1342,14 +1345,14 @@ void jesd_10ms_callback(uint8_t nTmrId)
if (((runCore & pMtimerPara->runCoreId) == pMtimerPara->runCoreId) && (4 == reCfgFlag))
{
debug_write((DBG_DDR_IDX_DRV_BASE+907), GET_STC_CNT()); // 0xe2c // timer restart finished
//uint32_t start = GET_STC_CNT();
jesd_timer_rcfg_act(nTmrId);
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
pMtimerCal->sfnCalFinished = 1;
pMtimerInt->tddOffsetIntCnt = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
}
debug_write((DBG_DDR_IDX_DRV_BASE+289), (GET_STC_CNT()-start)); // 0x484
}
if ((tEventFlag & (1<<MTMR_TDD_OFFSET_10000)) && (MTIMER_JESD_RX1_ID == nTmrId)) // orx 25ms timer int
{

3
public/pet_rfm_spu1/top/src/main.s.c
View File

@ -22,6 +22,7 @@
#include "pet_rfm_spu1_oam.h"
#include "hwque.h"
#include "lib_debug_init.h"
#include "stc_timer.h"
int32_t main(int32_t argc, char* argv[])
{
@ -42,6 +43,8 @@ int32_t main(int32_t argc, char* argv[])
pet_rfm_spu1_msg_transfer_init();
stc_timer_todint_init();
spu_oam_init();
while(1) {

2
public/pet_rfm_spu1/top/src/pet_rfm_spu1_top.s.c
View File

@ -19,6 +19,7 @@
#include "spu_hw_queue.h"
#include "app_interface.h"
#include "ape_csu.h"
#include "inter_vector.h"
void phy_init(void);//phy application function:msg_transfer_cfg
@ -33,6 +34,7 @@ void pet_rfm_spu1_drv_init(void)
//pet_rfm_dm_alloc();
pet_sm_alloc();
smart_irq_init(core_id);
ape_csu_init();
ecs_hw_que_init(core_id);
ecs_hw_que_init_withirq(core_id, core_id);

50
public/pet_rfm_spu1/top/src/stc_tod.s.c Normal file
View File

@ -0,0 +1,50 @@
#include "stc_timer.h"
#include "ucp_drv_common.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "inter_vector.h"
void stc_timer_todint_init(void)
{
int32_t apeId = get_core_id();
TOD_REG_IRQ_EN |= 0x1; // set tod int enable
uint32_t intNum = APC_STC_INTR8;
// attach interrupt func
int32_t ret = smart_irq_request(intNum, isr_stc_tod_int);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
debug_write(DBG_DDR_ERR_IDX(apeId, 8), ret);
}
}
uint32_t gTodLastStcCnt = 0;
uint32_t gTodIntCnt = 0;
void isr_stc_tod_int()
{
int32_t status = do_read_volatile(&TOD_REG_INT_STATUS);
__ucps2_synch(0);
if (status & 0x1)
{
do_write((&TOD_REG_INT_STATUS), 0x1);
if (0 < gTodIntCnt)
{
uint64_t temp = do_read_volatile(0x04a80008) + 0xFFFFFFFF;
uint32_t period = temp - gTodLastStcCnt;
debug_write(((DBG_DDR_IDX_DRV_BASE+1088)+((gTodIntCnt-1)&0x3F)), period); // 0x1000
}
gTodLastStcCnt = do_read_volatile(0x04a80008);
gTodIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64), gTodIntCnt); // 0x100
status = do_read_volatile(&TOD_REG_INT_STATUS);
}
}