jinhong/YB_Platform
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

1. fix UCP4008-SL bug#2002;

Browse Source 
2. 解决扩皮项目，打开tfu帧号校准功能后，重建小区，上行数据对不齐的问题；
3. 调整ape csu访问总线的效率。
This commit is contained in:
xinxin.li 2024-06-13 11:17:11 +08:00
parent 8e4bbcf0bd
commit 7f00eaf5a8
2 changed files with 36 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
public/common/driver/src/ape_csu.s.c
View File

@ -27,10 +27,10 @@ void ape_csu_init()
}
if (8 > coreId)
{
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x5<<5) + 0x9;
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x1<<14) + (0x5<<5) + 0x9; //smsel=0x2A, burst sel = 0
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x2<<14) + (0x5<<5) + 0x9;
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x3<<14) + (0x5<<5) + 0x9;
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x1<<5) + 0x5; // (0x5<<5) + 0x9;
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x1<<14) + (0x1<<5) + 0x5; //(0x5<<5) + 0x9; //smsel=0x2A, burst sel = 0
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x2<<14) + (0x1<<5) + 0x5; //(0x5<<5) + 0x9;
APC_CSU_EM_BS_SMSEL_PREDATANUM = (0x2A<<16) + (0x3<<14) + (0x1<<5) + 0x5; //(0x5<<5) + 0x9;
}
else
{

44
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -248,9 +248,8 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
}
reCfgFlag = 3;
pMtimerSfn->cellSetup = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+912), pMtimerSfn->txSfnNum); // 0xE40
debug_write((DBG_DDR_IDX_DRV_BASE+913), GET_STC_CNT()); // 0xE44
debug_write((DBG_DDR_IDX_DRV_BASE+920), pMtimerSfn->txSfnNum); // 0xE60
debug_write((DBG_DDR_IDX_DRV_BASE+921), GET_STC_CNT()); // 0xE64
}
void cpri_timer_clear_cell(uint8_t scsId)
@ -260,6 +259,7 @@ void cpri_timer_clear_cell(uint8_t scsId)
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
pSfnCal->sfnCalFinished = 0;
pMtimerInt->csuEnCnt = 0;
gCpriIntStatus.cpriSyncFlag = 0;
UCP_API_CPRI_CSU_STOP(); // 是否需要等几个ms
@ -290,7 +290,8 @@ void cpri_timer_rcfg_act()
//pMtimerSfn->rxSfnNum = 0; // 1023;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;
if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
//if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
if (0 != reCfgFlag) // no frame header offset, and the first cell
{
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
@ -338,8 +339,9 @@ void cpri_timer_rcfg_act()
reCfgFlag = 5;
disable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // disable 10ms int
debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum); // 0xE50
debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT()); // 0xE54
pMtimerSfn->cellSetup = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+924), pMtimerSfn->txSfnNum); // 0xE70
debug_write((DBG_DDR_IDX_DRV_BASE+925), GET_STC_CNT()); // 0xE74
}
void set_cpri_tmr_period(void)
@ -594,8 +596,8 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId)
}
reCfgFlag = 4;
debug_write((DBG_DDR_IDX_DRV_BASE+914), pMtimerSfn->txSfnNum); // 0xE48
debug_write((DBG_DDR_IDX_DRV_BASE+915), GET_STC_CNT()); // 0xE4c
debug_write((DBG_DDR_IDX_DRV_BASE+922), pMtimerSfn->txSfnNum); // 0xE68
debug_write((DBG_DDR_IDX_DRV_BASE+923), GET_STC_CNT()); // 0xE6c
return 0;
}
@ -790,7 +792,7 @@ void isr_cpri_10ms(void)
pMtimerInt->sfnOffsetIntFlag = 1;
pMtimerInt->sfnOffsetIntCnt++;
if (0 == pMtimerSfn->cellSetup)
if (0 == reCfgFlag)
{
pMtimerSfn->txSfnNum++;
pMtimerSfn->txSfnNum &= 0x3FF;
@ -823,8 +825,8 @@ void isr_cpri_10ms(void)
cpri_timer_rcfg_act();
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
pMtimerCal->sfnCalFinished = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
debug_write((DBG_DDR_IDX_DRV_BASE+908), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe30
debug_write((DBG_DDR_IDX_DRV_BASE+909), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe34
}
set_trigger_state(GPIO_ON);
}
@ -850,6 +852,7 @@ void isr_cpri_tdd_offset(void)
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
uint32_t cellFlag = gMtimerSfnNum[SCS_1st_MTIMER_ID].cellSetup | gMtimerSfnNum[SCS_2nd_MTIMER_ID].cellSetup;
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG); // &CPRI_TMR_INTC_REG);
//__ucps2_synch(0);
if ((tmrIntcFlag & (1 << MTMR_INT_TDD_OFFSET))) /* tmr int */
@ -865,6 +868,11 @@ void isr_cpri_tdd_offset(void)
uint32_t setFlag = tEventFlag & tddVal;
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), setFlag);
do_write(tFlagAddr, setFlag); // clear int flag
if (0 == cellFlag)
{
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); // clear int
return;
}
//uint32_t start = GET_STC_CNT();
pMtimerInt->tddOffsetIntCnt++;
// start_csu_timing
@ -903,8 +911,9 @@ void isr_cpri_tdd_offset(void)
UCP_API_CPRI_CSU_CH_Disable(UCP_API_CPRI_CSU_Get_AxcIdNum(), UCP_API_CPRI_CSU_Get_LatchNum());
do_write(CSU_STOP_CMD_ADDR, 0);
pMtimerInt->csuEnCnt = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+908), GET_STC_CNT()); // 0xe30
debug_write((DBG_DDR_IDX_DRV_BASE+909), tEventFlag); // 0xe34
debug_write((DBG_DDR_IDX_DRV_BASE+912), GET_STC_CNT()); // 0xe40
debug_write((DBG_DDR_IDX_DRV_BASE+913), tEventFlag); // 0xe44
debug_write((DBG_DDR_IDX_DRV_BASE+914), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // 0xe48
}
}
if (((0 == do_read_volatile(CSU_STOP_CMD_ADDR)) && (0 == pMtimerInt->csuEnCnt) && (tEventFlag & (1<<MTMR_TDD_OFFSET_10000))) || (0 != pMtimerInt->csuEnCnt))
@ -916,7 +925,9 @@ void isr_cpri_tdd_offset(void)
if ((1 == pMtimerInt->csuEnCnt) && (tEventFlag & (BIT25)))
{
UCP_API_CPRI_CSU_CH_Enable(UCP_API_CPRI_CSU_Get_AxcIdNum(), UCP_API_CPRI_CSU_Get_LatchNum());
debug_write((DBG_DDR_IDX_DRV_BASE+974), GET_STC_CNT()); // 0xf38
debug_write((DBG_DDR_IDX_DRV_BASE+916), GET_STC_CNT()); // 0xe50
debug_write((DBG_DDR_IDX_DRV_BASE+917), tEventFlag); // 0xe54
debug_write((DBG_DDR_IDX_DRV_BASE+918), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // 0xe58
debug_write((DBG_DDR_IDX_DRV_BASE+896), cpri_aux_get_tx_hfn()); // 0xe00
debug_write((DBG_DDR_IDX_DRV_BASE+897), cpri_aux_get_rx_hfn()); // 0xe04
debug_write((DBG_DDR_IDX_DRV_BASE+898), pMtimerInt->tddOffsetIntCnt); // 0xe08
@ -967,6 +978,11 @@ void isr_cpri_tdd_offset(void)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_CSU_INSERT));
do_write(tFlagAddr, (1<<MTMR_CSU_INSERT)); // clear int flag
if (0 == cellFlag)
{
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); // clear int
return;
}
pMtimerInt->insOffsetIntCnt++;
// start_csu_timing
#ifdef PALLADIUM_TEST