diff --git a/public/ecs_rfm_spu1/driver/src/cpri_link.s.c b/public/ecs_rfm_spu1/driver/src/cpri_link.s.c
index cb3f803..e4a3abf 100644
--- a/public/ecs_rfm_spu1/driver/src/cpri_link.s.c
+++ b/public/ecs_rfm_spu1/driver/src/cpri_link.s.c
@@ -1239,7 +1239,8 @@ void cpri_link_monitor(void)
         {
             cpri_async_flag = 1;          
             gCpriIntStatus.cpriSyncFlag = 0;
-            UCP_API_CPRI_CSU_STOP();
+            //UCP_API_CPRI_CSU_STOP();
+			do_write(CSU_STOP_CMD_ADDR, 1); // csu stop
             cpri_pma_rx();
         }
     }
diff --git a/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c b/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
index 529e53c..da1104a 100644
--- a/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
+++ b/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
@@ -157,7 +157,16 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
 
 	if (PROTOCOL_CPRI == nBsType)
 	{
+		debug_write((DBG_DDR_IDX_DRV_BASE+116), do_read_volatile(CPRI_TX_ADVANCE_PP1S_ADDR));
+		debug_write((DBG_DDR_IDX_DRV_BASE+117), pCpriDelay->cpri10ms2PP1sTxOffset);
+		uint32_t cpriHdrOffset = __ucps2_abs(do_read_volatile(CPRI_TX_ADVANCE_PP1S_ADDR) - pCpriDelay->cpri10ms2PP1sTxOffset);
+		debug_write((DBG_DDR_IDX_DRV_BASE+118), cpriHdrOffset);
+		if (0 == (cpriHdrOffset % 200000))
+		{
+		    pCpriDelay->cpri10ms2PP1sTxOffset += 10;
+		}
 		set_cpri_tx_rfp();
+		
 	    if (do_read_volatile(CPRI_TX_ADVANCE_PP1S_ADDR) != pCpriDelay->cpri10ms2PP1sTxOffset)
 		{
 			while (1 == reCfgFlag);
@@ -290,8 +299,8 @@ void cpri_timer_rcfg_act()
 	//pMtimerSfn->rxSfnNum = 0; // 1023;
 	pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;
 
-	//if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
-	if (0 != reCfgFlag) // no frame header offset, and the first cell
+	if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
+	//if (0 != reCfgFlag) // no frame header offset, and the first cell
 	{
 		pMtimerSfn->txSfnNum++;
 		pMtimerSfn->txSfnNum &= 0x3FF;
@@ -790,9 +799,10 @@ void isr_cpri_10ms(void)
 				do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_10ms_OFFSET));
 				do_write(tFlagAddr, (1<<MTMR_10ms_OFFSET));	// clear int flag
 
+				set_trigger_state(GPIO_ON);
 				pMtimerInt->sfnOffsetIntFlag = 1;
 				pMtimerInt->sfnOffsetIntCnt++;
-				if (0 == reCfgFlag)
+				if (0 == pMtimerSfn->cellSetup)
 				{
 					pMtimerSfn->txSfnNum++;
 					pMtimerSfn->txSfnNum &= 0x3FF;
@@ -828,7 +838,6 @@ void isr_cpri_10ms(void)
 					debug_write((DBG_DDR_IDX_DRV_BASE+908), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe30
 					debug_write((DBG_DDR_IDX_DRV_BASE+909), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe34
 				}
-				set_trigger_state(GPIO_ON);
 			}
 			cEventFlag = do_read_volatile(cFlagAddr);
 			tEventFlag = do_read_volatile(tFlagAddr);