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1. fix UCP4008_SL new feature#1412;

Browse Source 
2. add fdd function of 122.88M and 61.44M;
3. test case : case41,case42,case44,case48
This commit is contained in:
xinxin.li 2023-12-28 15:05:58 +08:00
parent 4655f82bf0
commit 8da2b23130
24 changed files with 369077 additions and 43 deletions
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19
public/ape_spu/driver/src/ape_mtimer.s.c
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@ -70,6 +70,8 @@ void ape_mtimer_int_clear(uint16_t nTimerId)
void ape_mtimer_sync(int32_t nScsId)
{
uint16_t apeId = get_core_id();
//uint32_t errAddr = 0;
//int32_t ret = 0;
gScsId = nScsId; // LTE_SCS_ID; //
uint16_t nTimerId = do_read_volatile_short(&(phyPara[nScsId].mtimerId));
__ucps2_synch(f_SM);
@ -78,10 +80,21 @@ void ape_mtimer_sync(int32_t nScsId)
{
return;
}
gSpinLockBuildCell.lock_addr = 0xB7FD1440;
gSpinLockBuildCell.flag_addr = 0xB7FD1444;
#if 1
gSpinLockBuildCell.lock_addr = 0xB7FD1500;
gSpinLockBuildCell.flag_addr = 0xB7FD1504;
smart_ddr_spinlock_init(&gSpinLockBuildCell);
#else
gSpinLockBuildCell.lock_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_BUILD_CELL*DBG_DDR_SPIN_LEN; // 0xB7FD1420;
gSpinLockBuildCell.flag_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_BUILD_CELL*DBG_DDR_SPIN_LEN + 0x4; // 0xB7FD1424;
errAddr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_BUILD_CELL*DBG_DDR_SPIN_LEN + 0x40 + (apeId<<2);
ret = smart_ddr_spinlock_init(&gSpinLockBuildCell);
if (0 != ret)
{
debug_write(errAddr, ret);
return;
}
#endif
smart_ddr_spinlock(&gSpinLockBuildCell);
ape_mtimer_int_init(nTimerId); // mtimer int attach

23
public/ape_spu/driver/src/ape_stc_timer.s.c
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@ -129,20 +129,29 @@ ddr_spinlock_t gSpinLockCtwInit;
void stc_timer_ctwint_init()
{
int32_t apeId = get_core_id();
int32_t ret = 0;
//uint32_t errAddr = 0;
#if 1
gSpinLockCtwInit.lock_addr = 0xB7FD1400;
gSpinLockCtwInit.flag_addr = 0xB7FD1404;
//gSpinLockCtwInit.spin_lock_addr = 0xB7FD1408;
//gSpinLockCtwInit.lock_w_addr = 0xB7FD140C;
//gSpinLockCtwInit.lock_loop_addr = 0xB7FD1410;
//gSpinLockCtwInit.unlock_loop_addr = 0xB7FD1410;
//gSpinLockCtwInit.unlock_addr = 0xB7FD1418;
smart_ddr_spinlock_init(&gSpinLockCtwInit);
#else
gSpinLockCtwInit.lock_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_STC_CTW*DBG_DDR_SPIN_LEN; // 0xB7FD1400;
gSpinLockCtwInit.flag_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_STC_CTW*DBG_DDR_SPIN_LEN + 0x4; // 0xB7FD1404;
errAddr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_STC_CTW*DBG_DDR_SPIN_LEN + 0x40 + (apeId<<2);
ret = smart_ddr_spinlock_init(&gSpinLockCtwInit);
if (0 != ret)
{
debug_write(errAddr, ret);
return;
}
#endif
uint32_t intNum = APC_STC_INTR0 + apeId;
// attach interrupt func
smart_ddr_spinlock(&gSpinLockCtwInit);
int32_t ret = smart_irq_request(intNum, isr_stc_timer_int);
ret = smart_irq_request(intNum, isr_stc_timer_int);
smart_ddr_spinunlock(&gSpinLockCtwInit);
if (0 != ret)
{

4
public/common/driver/inc/mtimer_com.h
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@ -4,8 +4,8 @@
#define APE_NUM (8) //4
#define FIBER_MIN_DELAY 2 // 10 //
#define INT_DELAY 3.5 // 4 // 6 // // us
#define EDMA_OFFSET 10 // 6 // 8 // 2 // us
#define INT_DELAY 4 // 6 // // us
#define EDMA_OFFSET 50 // 6 // 8 // 2 // us
#define CPRI_RE_TOFFSET 0 // 100 // 200 // ns // Toffset, to be change
#define CPRI_T2A 100 // 1 // 10 // ns

4
public/common/driver/inc/phy_para.h
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@ -62,15 +62,19 @@
#define JESD_RX_CH_PARA (JESD_CFG_ADDR+0x10)
#define JESD_RX_SAMPLE_RATE (JESD_CFG_ADDR+0x20)
#define JESD_RX_CLK_RATIO (JESD_CFG_ADDR+0x24) // byte0: SAM_CLK/sample_clk, byte1: CHA_CLK_sample_clk
#define JESD_ORX_CH_PARA (JESD_CFG_ADDR+0x30)
#define JESD_ORX_SAMPLE_RATE (JESD_CFG_ADDR+0x40)
#define JESD_ORX_CLK_RATIO (JESD_CFG_ADDR+0x44)
#define JESD_TX_CH_PARA (JESD_CFG_ADDR+0x50)
#define JESD_TX_SAMPLE_RATE (JESD_CFG_ADDR+0x60)
#define JESD_TX_CLK_RATIO (JESD_CFG_ADDR+0x64)
#define JESD_TX1_CH_PARA (JESD_CFG_ADDR+0x70)
#define JESD_TX1_SAMPLE_RATE (JESD_CFG_ADDR+0x80)
#define JESD_TX1_CLK_RATIO (JESD_CFG_ADDR+0x84)
#define GPIO_JESD_TRIGGER_BIT (JESD_CFG_ADDR+0x100)
#define GPIO_JESD_TRIGGER_VALID (JESD_CFG_ADDR+0x110)

2
public/common/driver/inc/stc_timer.h
View File

@ -66,6 +66,8 @@ int32_t gcd_stein(uint32_t x, uint32_t y);
void stc_timer_init(uint32_t pClk, uint32_t valR);
void stc_timer_tod_init(uint32_t pClk);
void stc_pp1s_src_init(uint8_t srcId);
void stc_pp1s_out_set();
void stc_timer_para_init(uint32_t pClk, uint32_t valR);
void stc_timer_local_init();
void stc_timer0_para_init();

26
public/common/driver/src/ctc_intr.s.c
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@ -22,6 +22,8 @@ ddr_spinlock_t gSpinLockCtcInit;
int32_t ctc_cal_intr_init(void)
{
int32_t apeId = get_core_id();
//uint32_t errAddr = 0;
int32_t ret = 0;
if (11 == apeId)
{
@ -29,18 +31,24 @@ int32_t ctc_cal_intr_init(void)
}
else if (((0 <= apeId) && (7 >= apeId)) || (10 == apeId))
{
gSpinLockCtcInit.lock_addr = 0xB7FD1420;
gSpinLockCtcInit.flag_addr = 0xB7FD1424;
//gSpinLockCtcInit.spin_lock_addr = 0xB7FD1428;
//gSpinLockCtcInit.lock_w_addr = 0xB7FD142C;
//gSpinLockCtcInit.lock_loop_addr = 0xB7FD1430;
//gSpinLockCtcInit.unlock_loop_addr = 0xB7FD1434;
//gSpinLockCtcInit.unlock_addr = 0xB7FD1438;
#if 1
gSpinLockCtcInit.lock_addr = 0xB7FD1480;
gSpinLockCtcInit.flag_addr = 0xB7FD1484;
smart_ddr_spinlock_init(&gSpinLockCtcInit);
#else
gSpinLockCtcInit.lock_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_CTC*DBG_DDR_SPIN_LEN; // 0xB7FD1420;
gSpinLockCtcInit.flag_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_CTC*DBG_DDR_SPIN_LEN + 0x4; // 0xB7FD1424;
errAddr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_CTC*DBG_DDR_SPIN_LEN + 0x40 + (apeId<<2);
ret = smart_ddr_spinlock_init(&gSpinLockCtcInit);
if (0 != ret)
{
debug_write(errAddr, ret);
return -1;
}
#endif
int32_t ctcIntNum = CTC_CAL_INT_APE0 + apeId;
smart_ddr_spinlock(&gSpinLockCtcInit);
int32_t ret = smart_irq_request(ctcIntNum, isr_ctc_cal);
ret = smart_irq_request(ctcIntNum, isr_ctc_cal);
smart_ddr_spinunlock(&gSpinLockCtcInit);
if (0 != ret)
{

9
public/common/utility/inc/ucp_utility.h
View File

@ -56,6 +56,13 @@ typedef enum eUcpSpinlockType {
LOCK_BUILD_CELL,
} UcpSpinlockType_e;
typedef enum eDdrSpinlockType {
LOCK_DDR_STC_CTW = 0,
LOCK_DDR_CTC,
LOCK_DDR_BUILD_CELL,
} DdrSpinlockType_e;
ALWAYS_INLINE int32_t get_core_id();
int32_t isPowerOf2(uint32_t n);
void ucp_spinlock_init();
@ -81,7 +88,7 @@ void ucp_nop(uint32_t cycleCnt);
#define DBG_DDR_HW_ADDR_BASE (0xB7FD0400)
#define DBG_DDR_HW_LEN (0x200)
#define DBG_DDR_SPIN_ADDR_BASE (0xB7FD1400)
#define DBG_DDR_SPIN_LEN (0x40)
#define DBG_DDR_SPIN_LEN (0x80)
#define DBG_DDR_OSP_HW_BASE (476544) // 0xB7FD1600
#define DBG_DDR_OSP_HW_LEN (0x30) // 48

2
public/ecs_rfm_spu1/driver/inc/jesd_csu.h
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@ -89,5 +89,7 @@ int32_t jesd_csu_orx_start(uint8_t nListId);
int32_t jesd_csu_stat_lookup(uint8_t tag);
int32_t jesd_csu_clear_list();
#endif

3
public/ecs_rfm_spu1/driver/inc/jesd_csu_lte_fdd.h
View File

@ -31,6 +31,9 @@
#define JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR 0x6BCF0000 // 0xF0000
int32_t jesd_csu_init_lte_fdd();
int32_t jesd_csu_init_lte_fdd_slot0();
#if 0
int32_t jesd_csu_init_nr_7ds2u_iomode();
int32_t jesd_csu_init_nr_7ds2u_8t8r();

43
public/ecs_rfm_spu1/driver/src/jesd_csu.s.c
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@ -13,6 +13,7 @@ stJesdListPara gJesdTxListPara[JESD_CH_NUM][JESD_LIST_NUM];
stJesdListPara gJesdRxListPara[JESD_CH_NUM][JESD_LIST_NUM];
uint32_t gJesdOrxCsuIntCnt = 0;
uint32_t gJesdListInitFinished = 0;
extern uint32_t gJesdTFMode;
extern void phy_sniffer_data_proc();
@ -57,6 +58,8 @@ int32_t jesd_csu_init(uint8_t antNum, uint8_t margin)
do_write((reg_addr+index), 0);
}
memset(&gJesdTxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM);
memset(&gJesdRxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM);
memset(&gJesdCsuPara, 0, sizeof(stJesdCsuPara));
gJesdCsuPara.antNum = antNum;
gJesdCsuPara.m = antNum*2;
@ -99,8 +102,8 @@ int32_t jesd_csu_init(uint8_t antNum, uint8_t margin)
}
do_write((&JS_CSU_JESDRX0SET), val);
do_write((&JS_CSU_FINDDMATAG), 0x60); // st wait wr resp
//do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00040010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit
do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00000010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit
do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00040010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit
//do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00000010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit
do_write((&JS_CSU_EM_BS_SMSEL_PREDATANUM), ((0x1<<14) | (0x5<<5) | 0x8));
if (4 < antNum)
{
@ -132,7 +135,9 @@ int32_t jesd_orx_csu_init(void)
debug_write((DBG_DDR_IDX_DRV_BASE+121), ret);
}
JS_CSU_INTMASK |= BIT14;
JS_CSU_TAGMASK2 &= (~BIT2);
JS_CSU_EVENTINTCLEAR = 46;
return 0;
}
@ -250,7 +255,7 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
int32_t i = 0;
for(i = 0; i < nodeNum; i++)
{
if (FDD_MODE != gJesdTFMode)
if ((FDD_MODE != gJesdTFMode) && (1 != orxFlag))
{
if (0 == i)
{
@ -274,13 +279,13 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
stLinkDesc.dmaZStep = 0x20;
stLinkDesc.dmaAllNum = pListNode[i].allNum;
if (FDD_MODE == gJesdTFMode)
if ((FDD_MODE != gJesdTFMode) && (1 != orxFlag))
{
stLinkDesc.dmaCGran = 0;
stLinkDesc.dmaCGran = 1;
}
else
{
stLinkDesc.dmaCGran = 1;
stLinkDesc.dmaCGran = 0;
}
stLinkDesc.dmaGran = 0;
@ -363,7 +368,7 @@ int32_t jesd_csu_tx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
stLinkDesc.dmaSize = 0; // 0x8;//
if (FDD_MODE == gJesdTFMode)
{
stLinkDesc.dmaCGran = 0; //1;
stLinkDesc.dmaCGran = 0;
}
else
{
@ -412,6 +417,12 @@ int32_t jesd_csu_tx_dmaReg_Cfg(uint8_t nChId, uint8_t nListId) // uint32_t listA
int32_t jesd_csu_rx_start_ch(uint8_t nChId, uint8_t nListId)
{
if ((0 == gJesdRxListPara[nChId][nListId].listAddr) && (0 == gJesdRxListPara[nChId][nListId].listNodeNum))
{
return -1; // list not init
}
gJesdListInitFinished++;
stCsuDmaCmdL cpriCmdL;
*(uint32_t*)(&cpriCmdL) = 0;
@ -437,6 +448,11 @@ int32_t jesd_csu_rx_start_ch(uint8_t nChId, uint8_t nListId)
int32_t jesd_csu_tx_start_ch(uint8_t nChId, uint8_t nListId)
{
if ((0 == gJesdTxListPara[nChId][nListId].listAddr) && (0 == gJesdTxListPara[nChId][nListId].listNodeNum))
{
return -1; // list not init
}
stCsuDmaCmdL cpriCmdL;
*(uint32_t*)(&cpriCmdL) = 0;
@ -486,7 +502,7 @@ int32_t jesd_csu_orx_start(uint8_t nListId)
jesd_csu_rx_start_ch(1, nListId);
do_write(&(JS_CSU_TAGMASK2), BIT2);
return 0;
}
@ -499,3 +515,12 @@ int32_t jesd_csu_stat_lookup(uint8_t tag)
return ((do_read_volatile(&JS_CSU_DMASTATUS)>>tag)&0x1);
}
int32_t jesd_csu_clear_list()
{
memset(&gJesdTxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM);
memset(&gJesdRxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM);
gJesdListInitFinished = 0;
return 0;
}

48
public/ecs_rfm_spu1/driver/src/jesd_csu_lte_fdd.s.c
View File

@ -49,6 +49,54 @@ int32_t jesd_csu_init_lte_fdd()
return 0;
}
int32_t jesd_csu_init_lte_fdd_slot0()
{
jesd_csu_init(JESD_LTEFDD_ANT_NUM, JESD_LTEFDD_MARGIN);
stJesdCsuNodePara txCsuNode[JESD_LTEFDD_TX_NODENUM];
stJesdCsuNodePara rxCsuNode[JESD_LTEFDD_RX_NODENUM];
//tx的链表地址
uint32_t txListAddr = JESD_LTEFDD_TX_LIST_ADDR; // 0x8A000000
//rx的链表地址
uint32_t rxListAddr = JESD_LTEFDD_RX_LIST_ADDR; // 0x8A008000
int32_t i = 0;
// tx/rx, subframe 0~9
for (i = 0; i < JESD_LTEFDD_TX_NODENUM; i++)
{
if (0 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR;
txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
}
else if (1 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR;
txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM;
}
}
jesd_csu_tx_cfg(txListAddr, 1, txCsuNode, JESD_CSU_CH0, 0);
jesd_csu_rx_cfg(rxListAddr, 1, rxCsuNode, JESD_CSU_CH0, 0);
#if 0
jesd_csu_tx_list_init(txListAddr, JESD_LTEFDD_TX_NODENUM, txCsuNode);
jesd_csu_tx_dmaReg_Cfg(JESD_CSU_CH0, txListAddr, JESD_LTEFDD_TX_NODENUM);
jesd_csu_rx_list_init(rxListAddr, JESD_LTEFDD_RX_NODENUM, rxCsuNode);
jesd_csu_rx_dmaReg_Cfg(JESD_CSU_CH0, rxListAddr, JESD_LTEFDD_RX_NODENUM);
#endif
return 0;
}
#if 0
int32_t jesd_csu_start_lte()
{

1
public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c
View File

@ -595,6 +595,7 @@ int32_t jesd_csu_init_nr_2500us_double_slot0()
rxCsuNode1[1].allNum = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4)*2;
jesd_csu_tx_cfg(tx1ListAddr, 2, txCsuNode1, JESD_CSU_CH0, 0);
//jesd_csu_rx_cfg(rx1ListAddr, 0, rxCsuNode1, JESD_CSU_CH0, 0);
jesd_csu_rx_cfg(rx1ListAddr, JESD_2500US_DOUBLE_RX_NODENUM1, rxCsuNode1, JESD_CSU_CH0, 0);
// tx, slot5~6

25
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -48,6 +48,7 @@ extern void rfm1_fapi_callback();
extern void phy_sniffer_data_proc();
extern uint32_t reCfgFlag;
extern uint32_t gJesdListInitFinished;
void jesd_init(uint8_t option)
{
@ -213,11 +214,13 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
if (FDD_MODE == gJesdTFMode)
{
//pMtimerTxPara->txCsuOn[0].timerPoint = (tdd*1000.0 - gCsuTxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset;
pMtimerTxPara->txCsuOn[0].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOn[0].timerPoint, &pMtimerTxPara->txCsuOn[0].pointL,
&pMtimerTxPara->txCsuOn[0].pointM, &pMtimerTxPara->txCsuOn[0].pointH);
pMtimerPara->rxCsuOn[0].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY;
//pMtimerPara->rxCsuOn[0].timerPoint = (tdd*1000.0 - gCsuRxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000;
pMtimerPara->rxCsuOn[0].timerPoint = tdd - gCsuRxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY;
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOn[0].timerPoint, &pMtimerPara->rxCsuOn[0].pointL,
&pMtimerPara->rxCsuOn[0].pointM, &pMtimerPara->rxCsuOn[0].pointH);
@ -238,10 +241,12 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
dlSlotCnt = my_jesdtmr->num_t_dl[0];
dlSymbolCnt = my_jesdtmr->num_t_dl_symb[0];
}
//pMtimerTxPara->txCsuOn[i].timerPoint = (tdd*1000.0 - gCsuTxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset;
pMtimerTxPara->txCsuOn[i].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOn[i].timerPoint, &pMtimerTxPara->txCsuOn[i].pointL,
&pMtimerTxPara->txCsuOn[i].pointM, &pMtimerTxPara->txCsuOn[i].pointH);
//pMtimerTxPara->txCsuOff[i].timerPoint = (dlSlotCnt*slotUs*1000.0 + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost) - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset;
pMtimerTxPara->txCsuOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOff[i].timerPoint, &pMtimerTxPara->txCsuOff[i].pointL,
&pMtimerTxPara->txCsuOff[i].pointM, &pMtimerTxPara->txCsuOff[i].pointH);
@ -250,6 +255,7 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOn[i].timerPoint, &pMtimerPara->rxCsuOn[i].pointL,
&pMtimerPara->rxCsuOn[i].pointM, &pMtimerPara->rxCsuOn[i].pointH);
//pMtimerPara->rxCsuOff[i].timerPoint = (tdd*1000.0 - gCsuRxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset;
pMtimerPara->rxCsuOff[i].timerPoint = tdd - gCsuRxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOff[i].timerPoint, &pMtimerPara->rxCsuOff[i].pointL,
&pMtimerPara->rxCsuOff[i].pointM, &pMtimerPara->rxCsuOff[i].pointH);
@ -302,6 +308,7 @@ int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdt
get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOn[i].timerPoint, &pMtimerPara->txRfOn[i].pointL,
&pMtimerPara->txRfOn[i].pointM, &pMtimerPara->txRfOn[i].pointH);
//pMtimerPara->txRfOff[i].timerPoint = (dlSlotCnt*slotUs*1000.0 + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost) - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset;
pMtimerPara->txRfOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOff[i].timerPoint, &pMtimerPara->txRfOff[i].pointL,
&pMtimerPara->txRfOff[i].pointM, &pMtimerPara->txRfOff[i].pointH);
@ -452,8 +459,8 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
if (FDD_MODE == gJesdTFMode)
{
jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
//set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
//set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
}
else
{
@ -492,6 +499,8 @@ int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
clear_jesd_txoff_point(nTmrId);
clear_jesd_rxon_point(nTmrId);
clear_jesd_rxoff_point(nTmrId);
jesd_csu_clear_list();
}
clear_jesd_tx_slot_offset(nTmrId);
clear_jesd_rx_slot_offset(nTmrId);
@ -580,6 +589,7 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_PIN_CTRL_REG), 0x3); //CTRL_SEL
do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), 0); //IO ctrl
#if 0
if (FDD_MODE == gJesdTFMode)
{
set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
@ -592,6 +602,7 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
set_jesd_rf_state(JESD_RF_RX, GPIO_ON); // RxOn();
set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn();
}
#endif
}
else
{
@ -1260,7 +1271,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C
#endif
#if 1
#if 0
if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == pMtimerInt->txSlotIntCnt))
{
if (0 == (pMtimerInt->sfnOffsetIntCnt&0x1))
@ -1367,6 +1378,12 @@ void jesd_tdd_callback(uint8_t nTmrId)
jesd_csu_rx_start(nListId);
}
if ((1 == gJesdListInitFinished) && (FDD_MODE == gJesdTFMode))
{
set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
}
}
if (tEventFlag & (1<<MTMR_JESD_RXON)) // rx on int
{

4
public/ecs_rfm_spu1/driver/src/mtimer_drv.s.c
View File

@ -35,7 +35,9 @@ int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
}
else if (PROTOCOL_JESD == nBsType)
{
coreClk = do_read_volatile(JESD_RX_SAMPLE_RATE+(nTmrId<<5)); // 122880000;
uint32_t sample_clk = do_read_volatile(JESD_RX_SAMPLE_RATE+(nTmrId<<5));
uint32_t sam_clk_ratio = do_read_volatile(JESD_RX_CLK_RATIO+(nTmrId<<5)) & 0xFF;
coreClk = sample_clk * sam_clk_ratio;
}
else if (PROTOCOL_ECPRI == nBsType)
{

16
public/ecs_rfm_spu1/driver/src/stc_timer.s.c
View File

@ -50,6 +50,7 @@ uint32_t stc_pclk_init()
uint32_t pClk = 0;
int32_t protoSel = get_protocol_sel();
int32_t protoOpt = get_protocol_opt();
if (PROTOCOL_CPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait cpri serdes clk init finished
@ -154,6 +155,8 @@ uint32_t stc_pclk_init()
UCP_PRINT_EMPTY("stc_pclk_init: use soc_crg to generate pclk, 250M. \r\n");
}
JECS_CRG_STC_RST_CTRL |= BIT24; // enable stc
return pClk;
}
@ -280,12 +283,11 @@ void stc_timer_para_init(uint32_t pClk, uint32_t valR)
void stc_timer_tod_init(uint32_t pClk)
{
JECS_CRG_STC_RST_CTRL |= BIT24;
stc_tod_para_init(pClk);
//stc_timer_todint_init();
//do_write(STC_TOD_INT_ADDR, 0); // clear tod int flag
stc_pp1s_out_set();
}
void stc_pp1s_src_init(uint8_t srcId)
@ -296,6 +298,16 @@ void stc_pp1s_src_init(uint8_t srcId)
JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 7); // select gps pp1s as stc ppls input
}
void stc_pp1s_out_set()
{
PC_PMUX_REG &= ~(0x3<<28);
PC_PMUX_REG |= (0x2<<28); // PC14: GNSS_PPS
JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 4);
JECS_CTRL_CPRI_GMAC_PHY_INT |= (0x6 << 4); // select tod_one_pps_out as gnss ppls output
}
void stc_timer_local_init()
{
LTBG_REG_R = gStcTimerPara.R;

6
public/ecs_rfm_spu1/top/src/phy_init.s.c
View File

@ -139,9 +139,9 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId, uint3
my_cpritmr.runCoreId = 0;
}
my_cpritmr.frameType = frame_type;
if (TDD_2500US_DOUBLE == frame_type)
{
my_cpritmr.frameType = TDD_2500US_DOUBLE;
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
@ -162,7 +162,7 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId, uint3
if (NR_SCS_30K == scsId)
{
//my_cpritmr.frameType = TDD_MODE;
my_cpritmr.frameType = FDD_MODE;
//my_cpritmr.frameType = FDD_MODE;
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
@ -175,6 +175,8 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId, uint3
}
else if (LTE_SCS_ID == scsId)
{
//my_cpritmr.frameType = TDD_MODE;
//my_cpritmr.frameType = FDD_MODE;
my_cpritmr.t_period = 10000;
my_cpritmr.t_us = 1000;
my_cpritmr.num_tti = 10;

245761
public/test/testcases/case41/fronthaul/DATA/DL_CASE0_jesd_122880000_2140000000/dl_ant_upsample_all.dat Normal file
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File diff suppressed because it is too large Load Diff

5
public/test/testcases/case41/fronthaul/src/jesd_test_case41.s.c
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@ -23,7 +23,7 @@
#include "jesd_test_case41.h"
#include "rfm1_drv.h"
extern uint32_t antDataNr[122880];
extern uint32_t antDataNr[245760];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
@ -58,7 +58,8 @@ int32_t fh_drv_init(void)
int32_t fh_csu_test_init(void)
{
jesd_csu_init_nr_fdd_slot0();
jesd_csu_init_nr_fdd();
//jesd_csu_init_nr_fdd_slot0();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);

45
public/test/testcases/case42/fronthaul/inc/jesd_test_case42.h Normal file
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@ -0,0 +1,45 @@
#ifndef _JESD_TEST_CASE41_H_
#define _JESD_TEST_CASE41_H_
#if 0
#define JESD_CASE44_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE44_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE44_RX_SLOTD_DATA_LEN 0xF0000
#define JESD_CASE44_TDD_DATA_LEN 0x960000
#define JESD_CASE44_RX1_DUMMY_DATA_ADDR 0xB4BA4800
#define JESD_CASE44_RX1_SLOTS_DATA_ADDR ((JESD_CASE44_RX1_DUMMY_DATA_ADDR)+(JESD_CASE44_RX_DUMMY_DATA_LEN))
#define JESD_CASE44_RX1_SLOT8_DATA_ADDR ((JESD_CASE44_RX1_SLOTS_DATA_ADDR)+(JESD_CASE44_RX_SLOTS_DATA_LEN))
#define JESD_CASE44_RX1_SLOT9_DATA_ADDR ((JESD_CASE44_RX1_SLOT8_DATA_ADDR)+(JESD_CASE44_RX_SLOTD_DATA_LEN))
#define JESD_CASE44_RX2_DUMMY_DATA_ADDR 0xB5504800
#define JESD_CASE44_RX2_SLOTS_DATA_ADDR ((JESD_CASE44_RX2_DUMMY_DATA_ADDR)+(JESD_CASE44_RX_DUMMY_DATA_LEN))
#define JESD_CASE44_RX2_SLOT8_DATA_ADDR ((JESD_CASE44_RX2_SLOTS_DATA_ADDR)+(JESD_CASE44_RX_SLOTS_DATA_LEN))
#define JESD_CASE44_RX2_SLOT9_DATA_ADDR ((JESD_CASE44_RX2_SLOT8_DATA_ADDR)+(JESD_CASE44_RX_SLOTD_DATA_LEN))
#define JESD_CASE44_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define JESD_CASE44_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define JESD_CASE44_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define JESD_CASE44_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define JESD_CASE44_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define JESD_CASE44_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE44_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE44_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case42/fronthaul/note.txt Normal file
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@ -0,0 +1 @@
NR15K，122.88M采样率，40M带宽，发256QAM宽带信号

125
public/test/testcases/case42/fronthaul/src/jesd_test_case42.s.c Normal file
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@ -0,0 +1,125 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case44.c
// Author : xinxin.li
// Created On : 2023-03-22s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_lte_fdd.h"
#include "jesd_test.h"
#include "jesd_test_case42.h"
#include "rfm1_drv.h"
extern uint32_t antDataLte[122880]; // 256QAM, NR15K, 61.44, 40M
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
extern uint32_t gJesdTFMode;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
gJesdTFMode = FDD_MODE;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stFrontHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fhDrvPara.rateOption = JESD_OPTION_204B;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
jesd_csu_init_lte_fdd_slot0();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = JESD_LTEFDD_ANT_NUM;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
uint32_t slotSamCnt = JESD_LTEFDD_SUBFRAME_SAM_CNT;
uint32_t cpyCnt = 0;
memset_ucp((void*)JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset_ucp((void*)JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
if (0 == idSlot) // even slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataLte[0]); // + idAnt*slotSamCnt;
dstAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
}
else if (1 == idSlot) // odd slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataLte[0]); // + idAnt*slotSamCnt;
dstAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
memset((void*)JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset((void*)JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
}

122886
public/test/testcases/case42/fronthaul/src/jesd_test_case42_antdata.s.c Normal file
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File diff suppressed because it is too large Load Diff

60
public/test/testcases/case42/osp/src/ape_test_case41.s.c Normal file
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@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

2
public/test/testcases/case46/fronthaul/src/jesd_test_case46.s.c
View File

@ -24,7 +24,7 @@
#include "jesd_test_case46.h"
#include "rfm1_drv.h"
extern uint32_t antDataNr[122880];
extern uint32_t antDataNr[245760];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;