From 8da2b23130db5f9a10abbe4b78d141fd73edb821 Mon Sep 17 00:00:00 2001 From: "xinxin.li" Date: Thu, 28 Dec 2023 15:05:58 +0800 Subject: [PATCH] 1. fix UCP4008_SL new feature#1412; 2. add fdd function of 122.88M and 61.44M; 3. test case : case41,case42,case44,case48 --- public/ape_spu/driver/src/ape_mtimer.s.c | 19 +- public/ape_spu/driver/src/ape_stc_timer.s.c | 23 +- public/common/driver/inc/mtimer_com.h | 4 +- public/common/driver/inc/phy_para.h | 4 + public/common/driver/inc/stc_timer.h | 2 + public/common/driver/src/ctc_intr.s.c | 26 +- public/common/utility/inc/ucp_utility.h | 9 +- public/ecs_rfm_spu1/driver/inc/jesd_csu.h | 2 + .../driver/inc/jesd_csu_lte_fdd.h | 3 + public/ecs_rfm_spu1/driver/src/jesd_csu.s.c | 43 +- .../driver/src/jesd_csu_lte_fdd.s.c | 48 + .../driver/src/jesd_csu_nr_7ds2u.s.c | 1 + public/ecs_rfm_spu1/driver/src/jesd_timer.s.c | 25 +- public/ecs_rfm_spu1/driver/src/mtimer_drv.s.c | 4 +- public/ecs_rfm_spu1/driver/src/stc_timer.s.c | 16 +- public/ecs_rfm_spu1/top/src/phy_init.s.c | 6 +- .../dl_ant_upsample_all.dat | 245761 +++++++++++++++ .../case41/fronthaul/src/jesd_test_case41.s.c | 5 +- .../case42/fronthaul/inc/jesd_test_case42.h | 45 + .../test/testcases/case42/fronthaul/note.txt | 1 + .../case42/fronthaul/src/jesd_test_case42.s.c | 125 + .../src/jesd_test_case42_antdata.s.c | 122886 ++++++++ .../case42/osp/src/ape_test_case41.s.c | 60 + .../case46/fronthaul/src/jesd_test_case46.s.c | 2 +- 24 files changed, 369077 insertions(+), 43 deletions(-) create mode 100644 public/test/testcases/case41/fronthaul/DATA/DL_CASE0_jesd_122880000_2140000000/dl_ant_upsample_all.dat create mode 100644 public/test/testcases/case42/fronthaul/inc/jesd_test_case42.h create mode 100644 public/test/testcases/case42/fronthaul/note.txt create mode 100644 public/test/testcases/case42/fronthaul/src/jesd_test_case42.s.c create mode 100644 public/test/testcases/case42/fronthaul/src/jesd_test_case42_antdata.s.c create mode 100644 public/test/testcases/case42/osp/src/ape_test_case41.s.c diff --git a/public/ape_spu/driver/src/ape_mtimer.s.c b/public/ape_spu/driver/src/ape_mtimer.s.c index 7f13751..cfda4b9 100644 --- a/public/ape_spu/driver/src/ape_mtimer.s.c +++ b/public/ape_spu/driver/src/ape_mtimer.s.c @@ -70,6 +70,8 @@ void ape_mtimer_int_clear(uint16_t nTimerId) void ape_mtimer_sync(int32_t nScsId) { uint16_t apeId = get_core_id(); + //uint32_t errAddr = 0; + //int32_t ret = 0; gScsId = nScsId; // LTE_SCS_ID; // uint16_t nTimerId = do_read_volatile_short(&(phyPara[nScsId].mtimerId)); __ucps2_synch(f_SM); @@ -78,10 +80,21 @@ void ape_mtimer_sync(int32_t nScsId) { return; } - gSpinLockBuildCell.lock_addr = 0xB7FD1440; - gSpinLockBuildCell.flag_addr = 0xB7FD1444; +#if 1 + gSpinLockBuildCell.lock_addr = 0xB7FD1500; + gSpinLockBuildCell.flag_addr = 0xB7FD1504; smart_ddr_spinlock_init(&gSpinLockBuildCell); - +#else + gSpinLockBuildCell.lock_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_BUILD_CELL*DBG_DDR_SPIN_LEN; // 0xB7FD1420; + gSpinLockBuildCell.flag_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_BUILD_CELL*DBG_DDR_SPIN_LEN + 0x4; // 0xB7FD1424; + errAddr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_BUILD_CELL*DBG_DDR_SPIN_LEN + 0x40 + (apeId<<2); + ret = smart_ddr_spinlock_init(&gSpinLockBuildCell); + if (0 != ret) + { + debug_write(errAddr, ret); + return; + } +#endif smart_ddr_spinlock(&gSpinLockBuildCell); ape_mtimer_int_init(nTimerId); // mtimer int attach diff --git a/public/ape_spu/driver/src/ape_stc_timer.s.c b/public/ape_spu/driver/src/ape_stc_timer.s.c index a07119a..8da60bd 100644 --- a/public/ape_spu/driver/src/ape_stc_timer.s.c +++ b/public/ape_spu/driver/src/ape_stc_timer.s.c @@ -129,20 +129,29 @@ ddr_spinlock_t gSpinLockCtwInit; void stc_timer_ctwint_init() { int32_t apeId = get_core_id(); - + int32_t ret = 0; + //uint32_t errAddr = 0; + +#if 1 gSpinLockCtwInit.lock_addr = 0xB7FD1400; gSpinLockCtwInit.flag_addr = 0xB7FD1404; - //gSpinLockCtwInit.spin_lock_addr = 0xB7FD1408; - //gSpinLockCtwInit.lock_w_addr = 0xB7FD140C; - //gSpinLockCtwInit.lock_loop_addr = 0xB7FD1410; - //gSpinLockCtwInit.unlock_loop_addr = 0xB7FD1410; - //gSpinLockCtwInit.unlock_addr = 0xB7FD1418; smart_ddr_spinlock_init(&gSpinLockCtwInit); +#else + gSpinLockCtwInit.lock_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_STC_CTW*DBG_DDR_SPIN_LEN; // 0xB7FD1400; + gSpinLockCtwInit.flag_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_STC_CTW*DBG_DDR_SPIN_LEN + 0x4; // 0xB7FD1404; + errAddr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_STC_CTW*DBG_DDR_SPIN_LEN + 0x40 + (apeId<<2); + ret = smart_ddr_spinlock_init(&gSpinLockCtwInit); + if (0 != ret) + { + debug_write(errAddr, ret); + return; + } +#endif uint32_t intNum = APC_STC_INTR0 + apeId; // attach interrupt func smart_ddr_spinlock(&gSpinLockCtwInit); - int32_t ret = smart_irq_request(intNum, isr_stc_timer_int); + ret = smart_irq_request(intNum, isr_stc_timer_int); smart_ddr_spinunlock(&gSpinLockCtwInit); if (0 != ret) { diff --git a/public/common/driver/inc/mtimer_com.h b/public/common/driver/inc/mtimer_com.h index 71a871e..fb7be65 100644 --- a/public/common/driver/inc/mtimer_com.h +++ b/public/common/driver/inc/mtimer_com.h @@ -4,8 +4,8 @@ #define APE_NUM (8) //4 #define FIBER_MIN_DELAY 2 // 10 // -#define INT_DELAY 3.5 // 4 // 6 // // us -#define EDMA_OFFSET 10 // 6 // 8 // 2 // us +#define INT_DELAY 4 // 6 // // us +#define EDMA_OFFSET 50 // 6 // 8 // 2 // us #define CPRI_RE_TOFFSET 0 // 100 // 200 // ns // Toffset, to be change #define CPRI_T2A 100 // 1 // 10 // ns diff --git a/public/common/driver/inc/phy_para.h b/public/common/driver/inc/phy_para.h index 016276a..466c81c 100644 --- a/public/common/driver/inc/phy_para.h +++ b/public/common/driver/inc/phy_para.h @@ -62,15 +62,19 @@ #define JESD_RX_CH_PARA (JESD_CFG_ADDR+0x10) #define JESD_RX_SAMPLE_RATE (JESD_CFG_ADDR+0x20) +#define JESD_RX_CLK_RATIO (JESD_CFG_ADDR+0x24) // byte0: SAM_CLK/sample_clk, byte1: CHA_CLK_sample_clk #define JESD_ORX_CH_PARA (JESD_CFG_ADDR+0x30) #define JESD_ORX_SAMPLE_RATE (JESD_CFG_ADDR+0x40) +#define JESD_ORX_CLK_RATIO (JESD_CFG_ADDR+0x44) #define JESD_TX_CH_PARA (JESD_CFG_ADDR+0x50) #define JESD_TX_SAMPLE_RATE (JESD_CFG_ADDR+0x60) +#define JESD_TX_CLK_RATIO (JESD_CFG_ADDR+0x64) #define JESD_TX1_CH_PARA (JESD_CFG_ADDR+0x70) #define JESD_TX1_SAMPLE_RATE (JESD_CFG_ADDR+0x80) +#define JESD_TX1_CLK_RATIO (JESD_CFG_ADDR+0x84) #define GPIO_JESD_TRIGGER_BIT (JESD_CFG_ADDR+0x100) #define GPIO_JESD_TRIGGER_VALID (JESD_CFG_ADDR+0x110) diff --git a/public/common/driver/inc/stc_timer.h b/public/common/driver/inc/stc_timer.h index 5df397b..3f85137 100644 --- a/public/common/driver/inc/stc_timer.h +++ b/public/common/driver/inc/stc_timer.h @@ -66,6 +66,8 @@ int32_t gcd_stein(uint32_t x, uint32_t y); void stc_timer_init(uint32_t pClk, uint32_t valR); void stc_timer_tod_init(uint32_t pClk); void stc_pp1s_src_init(uint8_t srcId); +void stc_pp1s_out_set(); + void stc_timer_para_init(uint32_t pClk, uint32_t valR); void stc_timer_local_init(); void stc_timer0_para_init(); diff --git a/public/common/driver/src/ctc_intr.s.c b/public/common/driver/src/ctc_intr.s.c index 577d3bd..b42ce63 100644 --- a/public/common/driver/src/ctc_intr.s.c +++ b/public/common/driver/src/ctc_intr.s.c @@ -22,6 +22,8 @@ ddr_spinlock_t gSpinLockCtcInit; int32_t ctc_cal_intr_init(void) { int32_t apeId = get_core_id(); + //uint32_t errAddr = 0; + int32_t ret = 0; if (11 == apeId) { @@ -29,18 +31,24 @@ int32_t ctc_cal_intr_init(void) } else if (((0 <= apeId) && (7 >= apeId)) || (10 == apeId)) { - gSpinLockCtcInit.lock_addr = 0xB7FD1420; - gSpinLockCtcInit.flag_addr = 0xB7FD1424; - //gSpinLockCtcInit.spin_lock_addr = 0xB7FD1428; - //gSpinLockCtcInit.lock_w_addr = 0xB7FD142C; - //gSpinLockCtcInit.lock_loop_addr = 0xB7FD1430; - //gSpinLockCtcInit.unlock_loop_addr = 0xB7FD1434; - //gSpinLockCtcInit.unlock_addr = 0xB7FD1438; +#if 1 + gSpinLockCtcInit.lock_addr = 0xB7FD1480; + gSpinLockCtcInit.flag_addr = 0xB7FD1484; smart_ddr_spinlock_init(&gSpinLockCtcInit); - +#else + gSpinLockCtcInit.lock_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_CTC*DBG_DDR_SPIN_LEN; // 0xB7FD1420; + gSpinLockCtcInit.flag_addr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_CTC*DBG_DDR_SPIN_LEN + 0x4; // 0xB7FD1424; + errAddr = DBG_DDR_SPIN_ADDR_BASE + LOCK_DDR_CTC*DBG_DDR_SPIN_LEN + 0x40 + (apeId<<2); + ret = smart_ddr_spinlock_init(&gSpinLockCtcInit); + if (0 != ret) + { + debug_write(errAddr, ret); + return -1; + } +#endif int32_t ctcIntNum = CTC_CAL_INT_APE0 + apeId; smart_ddr_spinlock(&gSpinLockCtcInit); - int32_t ret = smart_irq_request(ctcIntNum, isr_ctc_cal); + ret = smart_irq_request(ctcIntNum, isr_ctc_cal); smart_ddr_spinunlock(&gSpinLockCtcInit); if (0 != ret) { diff --git a/public/common/utility/inc/ucp_utility.h b/public/common/utility/inc/ucp_utility.h index cc077a9..eab25df 100644 --- a/public/common/utility/inc/ucp_utility.h +++ b/public/common/utility/inc/ucp_utility.h @@ -56,6 +56,13 @@ typedef enum eUcpSpinlockType { LOCK_BUILD_CELL, } UcpSpinlockType_e; +typedef enum eDdrSpinlockType { + LOCK_DDR_STC_CTW = 0, + LOCK_DDR_CTC, + LOCK_DDR_BUILD_CELL, +} DdrSpinlockType_e; + + ALWAYS_INLINE int32_t get_core_id(); int32_t isPowerOf2(uint32_t n); void ucp_spinlock_init(); @@ -81,7 +88,7 @@ void ucp_nop(uint32_t cycleCnt); #define DBG_DDR_HW_ADDR_BASE (0xB7FD0400) #define DBG_DDR_HW_LEN (0x200) #define DBG_DDR_SPIN_ADDR_BASE (0xB7FD1400) -#define DBG_DDR_SPIN_LEN (0x40) +#define DBG_DDR_SPIN_LEN (0x80) #define DBG_DDR_OSP_HW_BASE (476544) // 0xB7FD1600 #define DBG_DDR_OSP_HW_LEN (0x30) // 48 diff --git a/public/ecs_rfm_spu1/driver/inc/jesd_csu.h b/public/ecs_rfm_spu1/driver/inc/jesd_csu.h index 47a727e..f8508d0 100644 --- a/public/ecs_rfm_spu1/driver/inc/jesd_csu.h +++ b/public/ecs_rfm_spu1/driver/inc/jesd_csu.h @@ -89,5 +89,7 @@ int32_t jesd_csu_orx_start(uint8_t nListId); int32_t jesd_csu_stat_lookup(uint8_t tag); +int32_t jesd_csu_clear_list(); + #endif diff --git a/public/ecs_rfm_spu1/driver/inc/jesd_csu_lte_fdd.h b/public/ecs_rfm_spu1/driver/inc/jesd_csu_lte_fdd.h index 0625d39..818f3df 100644 --- a/public/ecs_rfm_spu1/driver/inc/jesd_csu_lte_fdd.h +++ b/public/ecs_rfm_spu1/driver/inc/jesd_csu_lte_fdd.h @@ -31,6 +31,9 @@ #define JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR 0x6BCF0000 // 0xF0000 int32_t jesd_csu_init_lte_fdd(); + +int32_t jesd_csu_init_lte_fdd_slot0(); + #if 0 int32_t jesd_csu_init_nr_7ds2u_iomode(); int32_t jesd_csu_init_nr_7ds2u_8t8r(); diff --git a/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c b/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c index b83756d..8614cfc 100644 --- a/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c +++ b/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c @@ -13,6 +13,7 @@ stJesdListPara gJesdTxListPara[JESD_CH_NUM][JESD_LIST_NUM]; stJesdListPara gJesdRxListPara[JESD_CH_NUM][JESD_LIST_NUM]; uint32_t gJesdOrxCsuIntCnt = 0; +uint32_t gJesdListInitFinished = 0; extern uint32_t gJesdTFMode; extern void phy_sniffer_data_proc(); @@ -57,6 +58,8 @@ int32_t jesd_csu_init(uint8_t antNum, uint8_t margin) do_write((reg_addr+index), 0); } + memset(&gJesdTxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM); + memset(&gJesdRxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM); memset(&gJesdCsuPara, 0, sizeof(stJesdCsuPara)); gJesdCsuPara.antNum = antNum; gJesdCsuPara.m = antNum*2; @@ -99,8 +102,8 @@ int32_t jesd_csu_init(uint8_t antNum, uint8_t margin) } do_write((&JS_CSU_JESDRX0SET), val); do_write((&JS_CSU_FINDDMATAG), 0x60); // st wait wr resp - //do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00040010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit - do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00000010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit + do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00040010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit + //do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00000010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit do_write((&JS_CSU_EM_BS_SMSEL_PREDATANUM), ((0x1<<14) | (0x5<<5) | 0x8)); if (4 < antNum) { @@ -132,7 +135,9 @@ int32_t jesd_orx_csu_init(void) debug_write((DBG_DDR_IDX_DRV_BASE+121), ret); } JS_CSU_INTMASK |= BIT14; - + JS_CSU_TAGMASK2 &= (~BIT2); + JS_CSU_EVENTINTCLEAR = 46; + return 0; } @@ -250,7 +255,7 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode int32_t i = 0; for(i = 0; i < nodeNum; i++) { - if (FDD_MODE != gJesdTFMode) + if ((FDD_MODE != gJesdTFMode) && (1 != orxFlag)) { if (0 == i) { @@ -274,13 +279,13 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode stLinkDesc.dmaZStep = 0x20; stLinkDesc.dmaAllNum = pListNode[i].allNum; - if (FDD_MODE == gJesdTFMode) + if ((FDD_MODE != gJesdTFMode) && (1 != orxFlag)) { - stLinkDesc.dmaCGran = 0; + stLinkDesc.dmaCGran = 1; } else { - stLinkDesc.dmaCGran = 1; + stLinkDesc.dmaCGran = 0; } stLinkDesc.dmaGran = 0; @@ -363,7 +368,7 @@ int32_t jesd_csu_tx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode stLinkDesc.dmaSize = 0; // 0x8;// if (FDD_MODE == gJesdTFMode) { - stLinkDesc.dmaCGran = 0; //1; + stLinkDesc.dmaCGran = 0; } else { @@ -412,6 +417,12 @@ int32_t jesd_csu_tx_dmaReg_Cfg(uint8_t nChId, uint8_t nListId) // uint32_t listA int32_t jesd_csu_rx_start_ch(uint8_t nChId, uint8_t nListId) { + if ((0 == gJesdRxListPara[nChId][nListId].listAddr) && (0 == gJesdRxListPara[nChId][nListId].listNodeNum)) + { + return -1; // list not init + } + gJesdListInitFinished++; + stCsuDmaCmdL cpriCmdL; *(uint32_t*)(&cpriCmdL) = 0; @@ -437,6 +448,11 @@ int32_t jesd_csu_rx_start_ch(uint8_t nChId, uint8_t nListId) int32_t jesd_csu_tx_start_ch(uint8_t nChId, uint8_t nListId) { + if ((0 == gJesdTxListPara[nChId][nListId].listAddr) && (0 == gJesdTxListPara[nChId][nListId].listNodeNum)) + { + return -1; // list not init + } + stCsuDmaCmdL cpriCmdL; *(uint32_t*)(&cpriCmdL) = 0; @@ -486,7 +502,7 @@ int32_t jesd_csu_orx_start(uint8_t nListId) jesd_csu_rx_start_ch(1, nListId); do_write(&(JS_CSU_TAGMASK2), BIT2); - + return 0; } @@ -499,3 +515,12 @@ int32_t jesd_csu_stat_lookup(uint8_t tag) return ((do_read_volatile(&JS_CSU_DMASTATUS)>>tag)&0x1); } +int32_t jesd_csu_clear_list() +{ + memset(&gJesdTxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM); + memset(&gJesdRxListPara[0][0], 0, sizeof(stJesdListPara)*JESD_CH_NUM*JESD_LIST_NUM); + gJesdListInitFinished = 0; + + return 0; +} + diff --git a/public/ecs_rfm_spu1/driver/src/jesd_csu_lte_fdd.s.c b/public/ecs_rfm_spu1/driver/src/jesd_csu_lte_fdd.s.c index 43ea535..a5614e1 100644 --- a/public/ecs_rfm_spu1/driver/src/jesd_csu_lte_fdd.s.c +++ b/public/ecs_rfm_spu1/driver/src/jesd_csu_lte_fdd.s.c @@ -49,6 +49,54 @@ int32_t jesd_csu_init_lte_fdd() return 0; } +int32_t jesd_csu_init_lte_fdd_slot0() +{ + jesd_csu_init(JESD_LTEFDD_ANT_NUM, JESD_LTEFDD_MARGIN); + stJesdCsuNodePara txCsuNode[JESD_LTEFDD_TX_NODENUM]; + stJesdCsuNodePara rxCsuNode[JESD_LTEFDD_RX_NODENUM]; + //tx的链表地址 + uint32_t txListAddr = JESD_LTEFDD_TX_LIST_ADDR; // 0x8A000000 + //rx的链表地址 + uint32_t rxListAddr = JESD_LTEFDD_RX_LIST_ADDR; // 0x8A008000 + int32_t i = 0; + + // tx/rx, subframe 0~9 + for (i = 0; i < JESD_LTEFDD_TX_NODENUM; i++) + { + if (0 == (i&0x1)) + { + txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR; + txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2); + txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM; + + rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR; + rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2); + rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM; + } + else if (1 == (i&0x1)) + { + txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR; + txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2); + txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM; + + rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR; + rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2); + rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2)*JESD_LTEFDD_ANT_NUM; + } + } + + jesd_csu_tx_cfg(txListAddr, 1, txCsuNode, JESD_CSU_CH0, 0); + jesd_csu_rx_cfg(rxListAddr, 1, rxCsuNode, JESD_CSU_CH0, 0); +#if 0 + jesd_csu_tx_list_init(txListAddr, JESD_LTEFDD_TX_NODENUM, txCsuNode); + jesd_csu_tx_dmaReg_Cfg(JESD_CSU_CH0, txListAddr, JESD_LTEFDD_TX_NODENUM); + jesd_csu_rx_list_init(rxListAddr, JESD_LTEFDD_RX_NODENUM, rxCsuNode); + jesd_csu_rx_dmaReg_Cfg(JESD_CSU_CH0, rxListAddr, JESD_LTEFDD_RX_NODENUM); +#endif + return 0; +} + + #if 0 int32_t jesd_csu_start_lte() { diff --git a/public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c b/public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c index 2bf6ecc..6c55e9b 100644 --- a/public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c +++ b/public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c @@ -595,6 +595,7 @@ int32_t jesd_csu_init_nr_2500us_double_slot0() rxCsuNode1[1].allNum = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4)*2; jesd_csu_tx_cfg(tx1ListAddr, 2, txCsuNode1, JESD_CSU_CH0, 0); + //jesd_csu_rx_cfg(rx1ListAddr, 0, rxCsuNode1, JESD_CSU_CH0, 0); jesd_csu_rx_cfg(rx1ListAddr, JESD_2500US_DOUBLE_RX_NODENUM1, rxCsuNode1, JESD_CSU_CH0, 0); // tx, slot5~6 diff --git a/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c b/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c index 04f9896..18c07e8 100644 --- a/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c @@ -48,6 +48,7 @@ extern void rfm1_fapi_callback(); extern void phy_sniffer_data_proc(); extern uint32_t reCfgFlag; +extern uint32_t gJesdListInitFinished; void jesd_init(uint8_t option) { @@ -213,11 +214,13 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd if (FDD_MODE == gJesdTFMode) { + //pMtimerTxPara->txCsuOn[0].timerPoint = (tdd*1000.0 - gCsuTxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset; pMtimerTxPara->txCsuOn[0].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset; get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOn[0].timerPoint, &pMtimerTxPara->txCsuOn[0].pointL, &pMtimerTxPara->txCsuOn[0].pointM, &pMtimerTxPara->txCsuOn[0].pointH); - pMtimerPara->rxCsuOn[0].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; + //pMtimerPara->rxCsuOn[0].timerPoint = (tdd*1000.0 - gCsuRxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; + pMtimerPara->rxCsuOn[0].timerPoint = tdd - gCsuRxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOn[0].timerPoint, &pMtimerPara->rxCsuOn[0].pointL, &pMtimerPara->rxCsuOn[0].pointM, &pMtimerPara->rxCsuOn[0].pointH); @@ -238,10 +241,12 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd dlSlotCnt = my_jesdtmr->num_t_dl[0]; dlSymbolCnt = my_jesdtmr->num_t_dl_symb[0]; } + //pMtimerTxPara->txCsuOn[i].timerPoint = (tdd*1000.0 - gCsuTxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset; pMtimerTxPara->txCsuOn[i].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset; get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOn[i].timerPoint, &pMtimerTxPara->txCsuOn[i].pointL, &pMtimerTxPara->txCsuOn[i].pointM, &pMtimerTxPara->txCsuOn[i].pointH); + //pMtimerTxPara->txCsuOff[i].timerPoint = (dlSlotCnt*slotUs*1000.0 + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost) - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset; pMtimerTxPara->txCsuOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset; get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOff[i].timerPoint, &pMtimerTxPara->txCsuOff[i].pointL, &pMtimerTxPara->txCsuOff[i].pointM, &pMtimerTxPara->txCsuOff[i].pointH); @@ -250,6 +255,7 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOn[i].timerPoint, &pMtimerPara->rxCsuOn[i].pointL, &pMtimerPara->rxCsuOn[i].pointM, &pMtimerPara->rxCsuOn[i].pointH); + //pMtimerPara->rxCsuOff[i].timerPoint = (tdd*1000.0 - gCsuRxAdvanceNs - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset; pMtimerPara->rxCsuOff[i].timerPoint = tdd - gCsuRxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset; get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOff[i].timerPoint, &pMtimerPara->rxCsuOff[i].pointL, &pMtimerPara->rxCsuOff[i].pointM, &pMtimerPara->rxCsuOff[i].pointH); @@ -302,6 +308,7 @@ int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdt get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOn[i].timerPoint, &pMtimerPara->txRfOn[i].pointL, &pMtimerPara->txRfOn[i].pointM, &pMtimerPara->txRfOn[i].pointH); + //pMtimerPara->txRfOff[i].timerPoint = (dlSlotCnt*slotUs*1000.0 + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost) - pJesdDelay->gps_offset*1000.0 - INT_DELAY*1000.0)/1000; // pJesdDelay->jesd_10ms2pp1s_txoffset; pMtimerPara->txRfOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset; get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOff[i].timerPoint, &pMtimerPara->txRfOff[i].pointL, &pMtimerPara->txRfOff[i].pointM, &pMtimerPara->txRfOff[i].pointH); @@ -452,8 +459,8 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr) if (FDD_MODE == gJesdTFMode) { jesd_timer_get_csu_point(nTmrId, my_jesdtmr); - set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0); - set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0); + //set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0); + //set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0); } else { @@ -492,6 +499,8 @@ int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId) clear_jesd_txoff_point(nTmrId); clear_jesd_rxon_point(nTmrId); clear_jesd_rxoff_point(nTmrId); + + jesd_csu_clear_list(); } clear_jesd_tx_slot_offset(nTmrId); clear_jesd_rx_slot_offset(nTmrId); @@ -580,6 +589,7 @@ int32_t jesd_pin_ctrl(int32_t nTmrId) { do_write((tmrBaseAddr+MTMR_PIN_CTRL_REG), 0x3); //CTRL_SEL do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), 0); //IO ctrl +#if 0 if (FDD_MODE == gJesdTFMode) { set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn(); @@ -592,6 +602,7 @@ int32_t jesd_pin_ctrl(int32_t nTmrId) set_jesd_rf_state(JESD_RF_RX, GPIO_ON); // RxOn(); set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn(); } +#endif } else { @@ -1260,7 +1271,7 @@ void jesd_10ms_callback(uint8_t nTmrId) #ifdef PALLADIUM_TEST debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C #endif -#if 1 +#if 0 if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == pMtimerInt->txSlotIntCnt)) { if (0 == (pMtimerInt->sfnOffsetIntCnt&0x1)) @@ -1367,6 +1378,12 @@ void jesd_tdd_callback(uint8_t nTmrId) jesd_csu_rx_start(nListId); } + if ((1 == gJesdListInitFinished) && (FDD_MODE == gJesdTFMode)) + { + set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0); + set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0); + } + } if (tEventFlag & (1<