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Merge branch 'dev_ck_v2.1_bug#1967' into 'dev_ck_v2.1'

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UCP4008-SL bug#1967

See merge request ucp/driver/ucp4008_platform_spu!118
This commit is contained in:
Weihua Li 2024-06-13 01:43:59 +00:00
commit 8e4bbcf0bd
3 changed files with 94 additions and 14 deletions
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2
public/common/ecs_dm/inc/jesd_drv_para.h
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@ -15,6 +15,8 @@ typedef struct JesdDelay
int32_t jesd_10ms2pp1s_txoffset;
int32_t jesd_10ms2pp1s_rxoffset;
int32_t jesd_tdd2pp1s_offset;
int32_t jesd_sfn10ms2pp1s_offset;
}JesdDelay_t;
typedef struct JesdOrxPara

85
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -117,6 +117,7 @@ void jesd_delay_init()
jesd_delay_ptr->jesd_10ms2pp1s_txoffset = jesd_delay_ptr->tx_offset; // advance ns
jesd_delay_ptr->jesd_10ms2pp1s_rxoffset = jesd_delay_ptr->rx_offset; // gpsOffset - pJesdDelay->rxOffset; // delay ns
jesd_delay_ptr->jesd_tdd2pp1s_offset = jesd_delay_ptr->tdd_offset; // advance ns as positive number
jesd_delay_ptr->jesd_sfn10ms2pp1s_offset = 30000;
}
int32_t jesd_mtimer_init(int32_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
@ -529,7 +530,6 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
}
reCfgFlag = 1;
pMtimerSfn->cellSetup = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+912), pMtimerSfn->txSfnNum); // 0xE40
debug_write((DBG_DDR_IDX_DRV_BASE+913), GET_STC_CNT()); // 0xE44
@ -552,7 +552,7 @@ int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
jesd_csu_clear_list();
}
clear_jesd_tx_slot_offset(nTmrId);
clear_jesd_rx_slot_offset(nTmrId);
//clear_jesd_rx_slot_offset(nTmrId);
pMtimerSfn->cellSetup = 0;
@ -629,6 +629,7 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
reCfgFlag = 0; // 5;
disable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // disable 10ms int
pMtimerSfn->cellSetup = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum); // 0xE50
debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT()); // 0xE54
}
@ -733,7 +734,7 @@ void set_jesd_1pps_scratch(int32_t nTmrId)
void set_jesd_sfn_offset(int32_t nTmrId)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
uint32_t tmr0Point = SFN_PERIOD*1000 - pEcsDmLocalMgt->jesd_delay_ptr->jesd_10ms2pp1s_txoffset; // ns
uint32_t tmr0Point = SFN_PERIOD*1000 - pEcsDmLocalMgt->jesd_delay_ptr->jesd_sfn10ms2pp1s_offset; // pEcsDmLocalMgt->jesd_delay_ptr->jesd_10ms2pp1s_txoffset; // ns
set_mtimer_tmrpoint_ns(nTmrId, MTMR_10ms_OFFSET, tmr0Point, MTIMER_MASK_62BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_10ms_OFFSET, MTMR_INT_10ms);
@ -838,8 +839,8 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
}
reCfgFlag = 4;
debug_write((DBG_DDR_IDX_DRV_BASE+914), pMtimerSfn->txSfnNum); // 0xE48
debug_write((DBG_DDR_IDX_DRV_BASE+915), GET_STC_CNT()); // 0xE4c
debug_write((DBG_DDR_IDX_DRV_BASE+922), pMtimerSfn->txSfnNum); // 0xE68
debug_write((DBG_DDR_IDX_DRV_BASE+923), GET_STC_CNT()); // 0xE6c
return 0;
}
@ -1349,6 +1350,10 @@ uint32_t start = GET_STC_CNT();
pMtimerCal->sfnCalFinished = 1;
pMtimerInt->tddOffsetIntCnt = 0;
gRxOnCnt = 0;
gRxOffCnt = 0;
gTxOnCnt = 0;
gTxOffCnt = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
}
@ -1394,6 +1399,10 @@ void isr_jesd_10ms_rx1(void)
jesd_10ms_callback(tmrId);
}
uint32_t gRxCsuOnStc = 0;
uint32_t gRxCsuOffStc = 0;
uint32_t gRxCsuOnTime = 0;
uint32_t gRxCsuOnTimeErr = 0;
void jesd_tdd_callback(uint8_t nTmrId)
{
uint32_t tmrIntcFlag = 0;
@ -1408,6 +1417,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
uint32_t rfCtlVal = (1<<MTMR_JESD_TXOFF)|(1<<MTMR_JESD_TXON)|(1<<MTMR_JESD_RXON)|(1<<MTMR_CSU_INSERT);
uint32_t csuCtlVal = (1<<MTMR_CEVENT_RXEN2CSU0) | (1<<MTMR_CEVENT_RXEN2CSU1) | (1<<MTMR_CEVENT_TXEN2CSU0) | (1<<MTMR_CEVENT_TXEN2CSU1);
uint32_t cellFlag = gMtimerSfnNum[SCS_1st_MTIMER_ID].cellSetup | gMtimerSfnNum[SCS_2nd_MTIMER_ID].cellSetup;
tmrIntcFlag = do_read_volatile(tmrBaseAddr+MTMR_INTC_REG);
__ucps2_synch(0);
if ((tmrIntcFlag & (1 << MTMR_INT_TDD_OFFSET))) /* tmr int */
@ -1424,6 +1434,11 @@ void jesd_tdd_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (tEventFlag & tddVal));
do_write(tFlagAddr, (tEventFlag & tddVal)); // clear int flag
if (0 == cellFlag)
{
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); // clear int
return;
}
pMtimerInt->tddOffsetIntCnt++;
// start_csu_timing
#ifdef PALLADIUM_TEST
@ -1457,6 +1472,11 @@ void jesd_tdd_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_RXON));
do_write(tFlagAddr, (1<<MTMR_JESD_RXON)); // clear int flag
if (0 == cellFlag)
{
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); // clear int
return;
}
gRxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+78), gRxOnCnt); // 0x138
@ -1476,6 +1496,11 @@ void jesd_tdd_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_CSU_INSERT));
do_write(tFlagAddr, (1<<MTMR_CSU_INSERT)); // clear int flag
if (0 == cellFlag)
{
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); // clear int
return;
}
gRxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+79), gRxOffCnt); // 0x13C
if (6 > gPP1sFlag)
@ -1493,6 +1518,11 @@ void jesd_tdd_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_TXON));
do_write(tFlagAddr, (1<<MTMR_JESD_TXON)); // clear int flag
if (0 == cellFlag)
{
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); // clear int
return;
}
gTxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+76), gTxOnCnt); // 0x130
if (6 > gPP1sFlag)
@ -1555,6 +1585,11 @@ void jesd_tdd_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_TXOFF));
do_write(tFlagAddr, (1<<MTMR_JESD_TXOFF)); // clear int flag
if (0 == cellFlag)
{
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_TDD_OFFSET)); // clear int
return;
}
gTxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+77), gTxOffCnt); // 0x134
set_jesd_all_rf_state(0, GPIO_OFF);
@ -1570,6 +1605,22 @@ void jesd_tdd_callback(uint8_t nTmrId)
gRxCsuOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+392), gRxCsuOnCnt); // 0x620
debug_write((DBG_DDR_IDX_DRV_BASE+393), GET_STC_CNT()); // 0x624
gRxCsuOnStc = GET_STC_CNT();
if (0 == (pMtimerInt->tddOffsetIntCnt & 0x1))
{
debug_write((DBG_DDR_IDX_DRV_BASE+400), do_read_volatile(0x05f60070)); // 0x640
debug_write((DBG_DDR_IDX_DRV_BASE+401), do_read_volatile(0x05f60060)); // 0x644
debug_write((DBG_DDR_IDX_DRV_BASE+402), do_read_volatile(0x05f600e0)); // 0x658
debug_write((DBG_DDR_IDX_DRV_BASE+403), pMtimerInt->tddOffsetIntCnt); // 0x65c
}
else
{
debug_write((DBG_DDR_IDX_DRV_BASE+408), do_read_volatile(0x05f60070)); // 0x660
debug_write((DBG_DDR_IDX_DRV_BASE+409), do_read_volatile(0x05f60060)); // 0x664
debug_write((DBG_DDR_IDX_DRV_BASE+410), do_read_volatile(0x05f600e0)); // 0x668
debug_write((DBG_DDR_IDX_DRV_BASE+411), pMtimerInt->tddOffsetIntCnt); // 0x66c
}
}
if (cEventFlag & (1<<MTMR_CEVENT_RXEN2CSU1))
{
@ -1579,6 +1630,30 @@ void jesd_tdd_callback(uint8_t nTmrId)
gRxCsuOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+394), gRxCsuOffCnt); // 0x628
debug_write((DBG_DDR_IDX_DRV_BASE+395), GET_STC_CNT()); // 0x62C
gRxCsuOffStc = GET_STC_CNT();
gRxCsuOnTime = gRxCsuOffStc - gRxCsuOnStc;
debug_write((DBG_DDR_IDX_DRV_BASE+396), gRxCsuOnTime); // 0x630
if ((640000 > gRxCsuOnTime) || (1150000 < gRxCsuOnTime))
{
gRxCsuOnTimeErr++;
debug_write((DBG_DDR_IDX_DRV_BASE+397), gRxCsuOnTimeErr); // 0x634
debug_write((DBG_DDR_IDX_DRV_BASE+398), gRxCsuOnTime); // 0x638
}
if (0 == (pMtimerInt->tddOffsetIntCnt & 0x1))
{
debug_write((DBG_DDR_IDX_DRV_BASE+404), do_read_volatile(0x05f60070)); // 0x650
debug_write((DBG_DDR_IDX_DRV_BASE+405), do_read_volatile(0x05f60060)); // 0x654
debug_write((DBG_DDR_IDX_DRV_BASE+406), do_read_volatile(0x05f600e0)); // 0x658
debug_write((DBG_DDR_IDX_DRV_BASE+407), pMtimerInt->tddOffsetIntCnt); // 0x65c
}
else
{
debug_write((DBG_DDR_IDX_DRV_BASE+412), do_read_volatile(0x05f60070)); // 0x670
debug_write((DBG_DDR_IDX_DRV_BASE+413), do_read_volatile(0x05f60060)); // 0x674
debug_write((DBG_DDR_IDX_DRV_BASE+414), do_read_volatile(0x05f600e0)); // 0x678
debug_write((DBG_DDR_IDX_DRV_BASE+415), pMtimerInt->tddOffsetIntCnt); // 0x67c
}
}
cEventFlag = do_read_volatile(cFlagAddr);
tEventFlag = do_read_volatile(tFlagAddr);

21
public/ecs_rfm_spu1/driver/src/mtimer_cal.s.c
View File

@ -26,6 +26,7 @@ extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];
extern stPhyScsPara* phyPara;
extern volatile uint32_t reCfgFlag;
void mtimer_1pps_resync(uint8_t nTmrId)
{
@ -71,7 +72,7 @@ void mtimer_1pps_resync(uint8_t nTmrId)
uint32_t addr = (uint32_t)&(phyPara[pMtimerPara->scsId].gpsOffset);
uint16_t gpsOffset = do_read_volatile_short(addr);
pSfnCal->sfnCalBeta = 0;
pSfnCal->sfnCalAlpha = (float)(n10msOffset+gpsOffset) * 1228.8; // advance * 1.2288*(10^3)
pSfnCal->sfnCalAlpha = (float)(n10msOffset+gpsOffset) * 1.2288; // advance * 1.2288*(10^3)
}
void mtimer_1pps_sfn_cal(uint8_t nTmrId)
@ -99,13 +100,13 @@ void mtimer_1pps_sfn_cal(uint8_t nTmrId)
debug_write((DBG_DDR_IDX_DRV_BASE+965), pMtimerSfn->rxSfnNum); // 0xf14
debug_write((DBG_DDR_IDX_DRV_BASE+966), pMtimerSfn->txSlotNum); // 0xf18
debug_write((DBG_DDR_IDX_DRV_BASE+967), pMtimerSfn->rxSlotNum); // 0xf1c
debug_write((DBG_DDR_IDX_DRV_BASE+524+11), GET_STC_CNT()); // 0x830+11*4, 11:apeId
debug_write((DBG_DDR_IDX_DRV_BASE+524+11), GET_STC_CNT()); // 0x830+11*4, 11:apeId
#endif
pMtimerSfn->txSfnNum = sfnCalNum;
//gCpriTimerPara.txSfnNum = gCpriTimerPara.sfnCalCnt; // + 1; //gSfnCalCnt;
pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum; //gSfnCalCnt-1;
pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum; //sfnCalNum-1; //
pMtimerSfn->txSlotNum = pMtimerSfn->slotNumPP1s; // 0;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0; //gCpriTimerPara.slotMaxNum - 1;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // + pMtimerPara->slotMaxNum - 1;
//pMtimerInt->txSlotIntCnt = 0;
//pMtimerInt->rxSlotIntCnt = 0;
@ -122,7 +123,7 @@ void mtimer_1pps_sfn_cal(uint8_t nTmrId)
__ucps2_synch(f_SMW);
pMtimerSfn->rxSfnNum = pSfnCal->sfnCalCnt-1;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s + pMtimerSfn->slotMaxNum - 1;
do_write(CTC_INT_TYPE_ADDR, (nTmrId+1));
if (PROTOCOL_ECPRI == nBsType)
@ -154,12 +155,13 @@ int32_t gPP1sLockCnt = 0;
int32_t mtimer_1pps_func(uint8_t nTmrId)
{
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[nTmrId];
//stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
JesdOrxPara_t* orx_para_ptr = pEcsDmLocalMgt->jesd_orx_para_ptr;
// gps unlock -> lock, adjust pp1s
pMtimerCal->pp1sLockFlag = do_read_volatile(ARM_LOCK_FLAG_ADDR);
__ucps2_synch(f_SMR);
if ((0 == pMtimerCal->pp1sLockFlagPre) && (1 == pMtimerCal->pp1sLockFlag)) // pp1s刚锁定
if (((0 == pMtimerCal->pp1sLockFlagPre) && (1 == pMtimerCal->pp1sLockFlag)) || (0 < orx_para_ptr->orx_calldrv_cnt)) // pp1s刚锁定
{
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+968), GET_STC_CNT()); // 0xf20
@ -177,7 +179,8 @@ int32_t mtimer_1pps_func(uint8_t nTmrId)
pMtimerCal->sfnValidFlag = do_read_volatile(ARM_SFN_VALID_ADDR);
pMtimerCal->sfnFlipFlag = do_read_volatile(ARM_SFN_FLIP_ADDR);
__ucps2_synch(f_SMR);
if (/*(0 < pMtimerInt->txSlotIntCnt) && */(ARM_SFN_VALID_FLAG == pMtimerCal->sfnValidFlag) && (pMtimerCal->sfnFlipFlag != pMtimerCal->sfnFlipFlagPre))
//if ((0 < pMtimerInt->txSlotIntCnt) && (ARM_SFN_VALID_FLAG == pMtimerCal->sfnValidFlag) && (pMtimerCal->sfnFlipFlag != pMtimerCal->sfnFlipFlagPre))
if ((0 == reCfgFlag) && (ARM_SFN_VALID_FLAG == pMtimerCal->sfnValidFlag) && (pMtimerCal->sfnFlipFlag != pMtimerCal->sfnFlipFlagPre))
{
do_write(ARM_SFN_VALID_ADDR, ARM_SFN_NOTVALID_FLAG);
__ucps2_synch(f_SMW);