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ecpri function

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This commit is contained in:
huihui.shang 2023-12-14 10:55:49 +08:00
parent 59d85f14df
commit 96ec809d27
42 changed files with 276241 additions and 2886 deletions
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117
public/common/driver/inc/ecpri_comm.h Normal file
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/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_comm.h
* Create Date: 23/12/11
* Description: eCPRI Common Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/12/11 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_COMM_H_
#define _ECPRI_COMM_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
#ifndef NULL
#define NULL ((void *)0)
#endif
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* byte order convert */
#ifndef HTON_S
#define HTON_S(X) X = (((X & 0x00FF) << 8) | ((X & 0xFF00) >> 8))
#endif
#ifndef HTON_L
#define HTON_L(X) X = (((X & 0x000000FF) << 24) | \
((X & 0x0000FF00) << 8) | \
((X & 0x00FF0000) >> 8) | \
((X & 0xFF000000) >> 24))
#endif
/* MAC address length */
#ifndef MAC_ADDR_LEN
#define MAC_ADDR_LEN 6
#endif
/* eCPRI buffer address & size(64MB) */
#define ECPRI_BUF_ADDR 0xAEE00000ul
#define ECPRI_BUF_SIZE 0x04000000ul
/* eCPRI RX buffer address & size(63MB) */
#define ECPRI_RX_BUF_ADDR ECPRI_BUF_ADDR
#define ECPRI_RX_BUF_SIZE 0x03F00000ul
/* eCPRI TX buffer address & size(512KB) */
#define ECPRI_TX_BUF_ADDR (ECPRI_RX_BUF_ADDR + ECPRI_RX_BUF_SIZE)
#define ECPRI_TX_BUF_SIZE 0x00080000ul
/* eCPRI antenna config data address & size(512KB) */
#define ECPRI_ANT_BUF_ADDR (ECPRI_TX_BUF_ADDR + ECPRI_TX_BUF_SIZE)
#define ECPRI_ANT_BUF_SIZE 0x00080000ul
/* eCPRI packet size(16KB) */
#define ECPRI_PKT_SIZE 0x00004000ul
/* eCPRI packet max number */
#define ECPRI_PKT_MAX (ECPRI_RX_BUF_SIZE / ECPRI_PKT_SIZE)
/* eCPRI descriptor address unit（1:32B） */
#define ECPRI_DESC_ADDR_UNIT 32
/* eCPRI antenna number */
#define ECPRI_ANT_NUM 4
/* eCPRI slot number */
#define ECPRI_SLOT_NUM 20 // LTE 10
/* eCPRI slot type - odd/even */
#define ECPRI_SLOT_TYPE 2
#define ECPRI_SLOT_ODD 0
#define ECPRI_SLOT_EVEN 1
/* eCPRI symbol number */
#define ECPRI_SYM_NUM 14
/* eCPRI symbol info length(packet address + packet length) */
#define ECPRI_SYM_INFO_LEN 8
/* eCPRI debug ECS_RFM0 index & address - 0xB7E30000 ~ 0xB7E30FFC(x = 0 ~ 0x3FF) */
#define ECPRI_DBG_IDX0(X) DBG_DDR_ECPRI_IDX(0, X)
#define ECPRI_DBG_ADDR0(X) (DBG_DDR_ADDR_BASE + ECPRI_DBG_IDX0(X) * 4)
/* eCPRI debug ECS_RFM1 index & address - 0xB7E31000 ~ 0xB7E31FFC(x = 0 ~ 0x3FF) */
#define ECPRI_DBG_IDX1(X) DBG_DDR_ECPRI_IDX(1, X)
#define ECPRI_DBG_ADDR1(X) (DBG_DDR_ADDR_BASE + ECPRI_DBG_IDX1(X) * 4)
/* eCPRI test index & address - 0xB7E32000(X = 0 ~ 0x7FFF) */
#define ECPRI_TEST_IDX(X) DBG_DDR_ECPRI_IDX(2, X)
#define ECPRI_TEST_ADDR(X) (DBG_DDR_ADDR_BASE + ECPRI_TEST_IDX(X) * 4)
/* eCPRI test ECS_RFM0 index & address - 0xB7E32000 ~ 0xB7E41FFC(X = 0 ~ 0x3FFF) */
#define ECPRI_TEST_IDX0(X) ECPRI_TEST_IDX(X)
#define ECPRI_TEST_ADDR0(X) ECPRI_TEST_ADDR(X)
/* eCPRI test ECS_RFM1 index & address - 0xB7E42000 ~ 0xB7E51FFC(X = 0 ~ 0x3FFF) */
#define ECPRI_TEST_IDX1(X) ECPRI_TEST_IDX(X + 0x4000)
#define ECPRI_TEST_ADDR1(X) ECPRI_TEST_ADDR(X + 0x4000)
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
#endif /* _ECPRI_COMM_H_ */

230
public/common/utility/inc/ucp_utility.h
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@ -1,115 +1,115 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ucp_utility.h
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#ifndef __UCP_UTILITY_H__
#define __UCP_UTILITY_H__
#include <string.h>
#include "typedef.h"
#include "ucps2-intrin.h"
#include "mem_sections.h"
#include "spinlock.h"
#define do_write(a,v) __ucps2_store_ext_mem((void *)(a), (uint32_t)(v), f_W)
#define do_write_byte(a,v) __ucps2_store_ext_mem((void *)(a), (uint8_t)(v), f_B)
#define do_write_short(a,v) __ucps2_store_ext_mem((void *)(a), (uint16_t)(v), f_S)
#define do_read(a) __ucps2_load_ext_mem((void *)(a), f_W)
#define do_read_byte(a) __ucps2_load_ext_mem((void *)(a), f_B)
#define do_read_short(a) __ucps2_load_ext_mem((void *)(a), f_S)
#define do_read_volatile(a) __ucps2_load_ext_mem_v((void *)(a), f_W)
#define do_read_volatile_byte(a) __ucps2_load_ext_mem_v((void *)(a), f_B)
#define do_read_volatile_short(a) __ucps2_load_ext_mem_v((void *)(a), f_S)
#define memcpy_ucp(d,s,l) memcpy_ext((void *__restrict)(d), (const void *__restrict)(s), (l))
#define memset_ucp(d,v,l) memset_ext((void *)(d), (uint32_t)(v), (l))
//vector copy,sm address must align 64 bytes
#define memcpy_ucp_dm2sm(d,s,l) vmemcpy_dm2sm((void *__restrict)(d), (const void *__restrict)(s), (l))
#define memcpy_ucp_sm2dm(d,s,l) vmemcpy_sm2dm((void *__restrict)(d), (const void *__restrict)(s), (l))
#define sizeof_aligned_4bytes(a) (((sizeof(a) + 3) >> 2) << 2)//aligned 4 bytes
#define sizeof_aligned_64bytes(a) (((sizeof(a) + 63) >> 6) << 6)
#define spin_lock_init(x) smart_spinlock_init(x)
#define spin_lock(x) smart_spinlock_irq(x)//smart_spinlock(x)
#define spin_unlock(x) smart_spinunlock_irqrestore(x)//smart_spinunlock(x)
typedef enum eUcpSpinlockType {
LOCK_UL_TX_ALLOC = 1,
LOCK_UL_TX_PUT,
LOCK_DL_RX_GET,
LOCK_DL_RX_FREE,
LOCK_BUILD_CELL,
} UcpSpinlockType_e;
ALWAYS_INLINE int32_t get_core_id();
int32_t isPowerOf2(uint32_t n);
void ucp_spinlock_init();
void ucp_nop(uint32_t cycleCnt);
#define DBG_DDR_PALLADIUM
#define DBG_DDR_ADDR_BASE (0xB7E00000) //0xA8000000
#define DBG_DDR_IDX_COMMON_BASE (0)
#define DBG_DDR_IDX_OSP_BASE (2048*1)
#define DBG_DDR_IDX_MSG_BASE (2048*2)
#define DBG_DDR_IDX_DRV_BASE (2048*3)
#define DBG_DDR_IDX_OSP2_BASE (2048*11) // 0xB7E16000
#define DBG_DDR_IDX_ERR_BASE (2048*18)
#define DBG_DDR_IDX_CPRI_BASE (2048*20)
#define DBG_DDR_IDX_ECPRI_BASE (2048*24)
#define DBG_DDR_IRQ_ADDR_BASE (0xB7FC0000)
#define DBG_DDR_IRQ_LEN (0x1000)
#define DBG_DDR_OS_ADDR_BASE (0xB7FCD000)
#define DBG_DDR_OS_LEN (0x100) //(0x400)
#define DBG_DDR_OS_NO_IDLE_BASE (0xB7FCD800)
#define DBG_DDR_OS_NO_IDLE_LEN (0x100)
#define DBG_DDR_HW_ADDR_BASE (0xB7FD0400)
#define DBG_DDR_HW_LEN (0x200)
#define DBG_DDR_SPIN_ADDR_BASE (0xB7FD1400)
#define DBG_DDR_SPIN_LEN (0x40)
#define DBG_DDR_OSP_HW_BASE (476544) // 0xB7FD1600
#define DBG_DDR_OSP_HW_LEN (0x30) // 48
#define DBG_DDR_COMMON_IDX(core_id,x) (DBG_DDR_IDX_COMMON_BASE + (core_id) * 128 + (x))
#define DBG_DDR_MSG_IDX(queue_no,x) (DBG_DDR_IDX_MSG_BASE + (queue_no) * 192 + (x))
#define DBG_DDR_ERR_IDX(core_id,x) (DBG_DDR_IDX_ERR_BASE + (core_id)*128 + (x))
#define DBG_DDR_ECPRI_IDX(ape_id,x) (DBG_DDR_IDX_ECPRI_BASE + (ape_id)*1024 + (x))
#define OSP_DEBUG_HW_POT(core_id, idx) (DBG_DDR_OSP_HW_BASE + ((core_id)*DBG_DDR_OSP_HW_LEN) + idx)
#define UCP_OSP_DBG_HW_CNT_ENABLE
#ifdef DBG_DDR_PALLADIUM
void pld_debug_write(uint32_t idx, uint32_t value);
void pld_debug_write_splice_short(uint32_t idx, uint16_t hi, uint16_t lo);
void pld_debug_write_splice_byte(uint32_t idx, uint8_t hi0, uint8_t hi1, uint8_t lo0, uint8_t lo1);
#define debug_write(a, b) pld_debug_write((uint32_t)(a), (uint32_t)(b))
#define debug_write_splice_short(a, b, c) pld_debug_write_splice_short((a), (b), (c))
#define debug_write_splice_byte(a, b, c, d, e) pld_debug_write_splice_byte((a), (b), (c), (d), (e))
#else
#define debug_write(a, b)
#define debug_write_splice_short(a, b, c)
#define debug_write_splice_byte(a, b, c, d, e)
#endif
//#define ATOMIC_IMPLEMENTATION
#define atomic_load(object) __ucps2_atomicld((void *)object, f_W)
#define atomic_store(object, operand) __ucps2_atomicst((void *)object, operand, f_W)
ALWAYS_INLINE int32_t atomic_fetch_add(void* object, int32_t operand);
#endif
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ucp_utility.h
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#ifndef __UCP_UTILITY_H__
#define __UCP_UTILITY_H__
#include <string.h>
#include "typedef.h"
#include "ucps2-intrin.h"
#include "mem_sections.h"
#include "spinlock.h"
#define do_write(a,v) __ucps2_store_ext_mem((void *)(a), (uint32_t)(v), f_W)
#define do_write_byte(a,v) __ucps2_store_ext_mem((void *)(a), (uint8_t)(v), f_B)
#define do_write_short(a,v) __ucps2_store_ext_mem((void *)(a), (uint16_t)(v), f_S)
#define do_read(a) __ucps2_load_ext_mem((void *)(a), f_W)
#define do_read_byte(a) __ucps2_load_ext_mem((void *)(a), f_B)
#define do_read_short(a) __ucps2_load_ext_mem((void *)(a), f_S)
#define do_read_volatile(a) __ucps2_load_ext_mem_v((void *)(a), f_W)
#define do_read_volatile_byte(a) __ucps2_load_ext_mem_v((void *)(a), f_B)
#define do_read_volatile_short(a) __ucps2_load_ext_mem_v((void *)(a), f_S)
#define memcpy_ucp(d,s,l) memcpy_ext((void *__restrict)(d), (const void *__restrict)(s), (l))
#define memset_ucp(d,v,l) memset_ext((void *)(d), (uint32_t)(v), (l))
//vector copy,sm address must align 64 bytes
#define memcpy_ucp_dm2sm(d,s,l) vmemcpy_dm2sm((void *__restrict)(d), (const void *__restrict)(s), (l))
#define memcpy_ucp_sm2dm(d,s,l) vmemcpy_sm2dm((void *__restrict)(d), (const void *__restrict)(s), (l))
#define sizeof_aligned_4bytes(a) (((sizeof(a) + 3) >> 2) << 2)//aligned 4 bytes
#define sizeof_aligned_64bytes(a) (((sizeof(a) + 63) >> 6) << 6)
#define spin_lock_init(x) smart_spinlock_init(x)
#define spin_lock(x) smart_spinlock_irq(x)//smart_spinlock(x)
#define spin_unlock(x) smart_spinunlock_irqrestore(x)//smart_spinunlock(x)
typedef enum eUcpSpinlockType {
LOCK_UL_TX_ALLOC = 1,
LOCK_UL_TX_PUT,
LOCK_DL_RX_GET,
LOCK_DL_RX_FREE,
LOCK_BUILD_CELL,
} UcpSpinlockType_e;
ALWAYS_INLINE int32_t get_core_id();
int32_t isPowerOf2(uint32_t n);
void ucp_spinlock_init();
void ucp_nop(uint32_t cycleCnt);
#define DBG_DDR_PALLADIUM
#define DBG_DDR_ADDR_BASE (0xB7E00000) //0xA8000000
#define DBG_DDR_IDX_COMMON_BASE (0)
#define DBG_DDR_IDX_OSP_BASE (2048*1)
#define DBG_DDR_IDX_MSG_BASE (2048*2)
#define DBG_DDR_IDX_DRV_BASE (2048*3)
#define DBG_DDR_IDX_OSP2_BASE (2048*11) // 0xB7E16000
#define DBG_DDR_IDX_ERR_BASE (2048*18)
#define DBG_DDR_IDX_CPRI_BASE (2048*20)
#define DBG_DDR_IDX_ECPRI_BASE (2048*24) // 0xB7E30000
#define DBG_DDR_IRQ_ADDR_BASE (0xB7FC0000)
#define DBG_DDR_IRQ_LEN (0x1000)
#define DBG_DDR_OS_ADDR_BASE (0xB7FCD000)
#define DBG_DDR_OS_LEN (0x100) //(0x400)
#define DBG_DDR_OS_NO_IDLE_BASE (0xB7FCD800)
#define DBG_DDR_OS_NO_IDLE_LEN (0x100)
#define DBG_DDR_HW_ADDR_BASE (0xB7FD0400)
#define DBG_DDR_HW_LEN (0x200)
#define DBG_DDR_SPIN_ADDR_BASE (0xB7FD1400)
#define DBG_DDR_SPIN_LEN (0x40)
#define DBG_DDR_OSP_HW_BASE (476544) // 0xB7FD1600
#define DBG_DDR_OSP_HW_LEN (0x30) // 48
#define DBG_DDR_COMMON_IDX(core_id,x) (DBG_DDR_IDX_COMMON_BASE + (core_id) * 128 + (x))
#define DBG_DDR_MSG_IDX(queue_no,x) (DBG_DDR_IDX_MSG_BASE + (queue_no) * 192 + (x))
#define DBG_DDR_ERR_IDX(core_id,x) (DBG_DDR_IDX_ERR_BASE + (core_id)*128 + (x))
#define DBG_DDR_ECPRI_IDX(ecs_id, x) (DBG_DDR_IDX_ECPRI_BASE + (ecs_id) * 1024 + (x))
#define OSP_DEBUG_HW_POT(core_id, idx) (DBG_DDR_OSP_HW_BASE + ((core_id)*DBG_DDR_OSP_HW_LEN) + idx)
#define UCP_OSP_DBG_HW_CNT_ENABLE
#ifdef DBG_DDR_PALLADIUM
void pld_debug_write(uint32_t idx, uint32_t value);
void pld_debug_write_splice_short(uint32_t idx, uint16_t hi, uint16_t lo);
void pld_debug_write_splice_byte(uint32_t idx, uint8_t hi0, uint8_t hi1, uint8_t lo0, uint8_t lo1);
#define debug_write(a, b) pld_debug_write((uint32_t)(a), (uint32_t)(b))
#define debug_write_splice_short(a, b, c) pld_debug_write_splice_short((a), (b), (c))
#define debug_write_splice_byte(a, b, c, d, e) pld_debug_write_splice_byte((a), (b), (c), (d), (e))
#else
#define debug_write(a, b)
#define debug_write_splice_short(a, b, c)
#define debug_write_splice_byte(a, b, c, d, e)
#endif
//#define ATOMIC_IMPLEMENTATION
#define atomic_load(object) __ucps2_atomicld((void *)object, f_W)
#define atomic_store(object, operand) __ucps2_atomicst((void *)object, operand, f_W)
ALWAYS_INLINE int32_t atomic_fetch_add(void* object, int32_t operand);
#endif

17
public/ecs_rfm_spu0/driver/inc/ecpri_csu.h
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@ -15,22 +15,17 @@
#include "ucp_csu.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "ecpri_queue_proc.h"
#include "ecpri_que.h"
#ifndef NULL
#define NULL ((void *)0)
#define NULL ((void *)0)
#endif
#define ECPRI_CSU_REG_NUM 32
#define ECPRI_CSU_RFM_REG_START 0
#define ECPRI_CSU_RFM_REG_END 11
#define ECPRI_CSU_REG_NUM 32
#define ECPRI_CSU_RFM_REG_START 0
#define ECPRI_CSU_RFM_REG_END 11
#define ECPRI_CSU_DATA_BUF_ADDR (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE) // (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)
#define ECPRI_CSU_DBG_BUF_ADDR (ECPRI_DBG_BUF_ADDR + 0x00080000ul) // (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)
//#define SERDES_INIT_FLAG_ADDR (0x0A4D7240) // cpri or jesd clk init finished
typedef enum _tagEcpriChId
{
@ -46,8 +41,6 @@ uint32_t ecpri_csu_get_free_channel(void);
uint32_t ecpri_csu_send(uint64_t dataAddr, uint32_t dataLen, uint8_t isWait);
int32_t ecpri_csu_task_lookup(uint8_t task_tag, uint8_t isWait);
void ecpri_csu_send_test(void);
#endif

56
public/ecs_rfm_spu0/driver/inc/ecpri_irq.h Normal file
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@ -0,0 +1,56 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_irq.h
* Create Date: 23/09/04
* Description: eCPRI Interrupt Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/04 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_IRQ_H_
#define _ECPRI_IRQ_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "typedef.h"
#include "ucp_tick.h"
#include "ucp_utility.h"
#include "ecpri_comm.h"
#include "ecpri_csu.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* STC statistic max cycle */
#define STC_CYCLE_MAX 1000000000ul
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* eCPRI antenna config info structure */
typedef struct EcpriAntCfgInfo
{
uint32_t pkt_addr; /* packet address */
uint32_t pkt_len; /* packet length */
} EcpriAntCfgInfo_t;
/* eCPRI symbol interrupt statistic structure */
typedef struct EcpriSymIrqStats
{
uint32_t handle_times; /* handle times */
uint32_t handle_succ_times; /* handle success times */
uint32_t handle_fail_times; /* handle fail times */
uint32_t send_times; /* send times */
uint32_t send_succ_times; /* send success times */
uint32_t send_fail_times; /* send fail times */
} EcpriSymIrqStats_t;
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI symbol interrupt handle */
int32_t ecpri_sym_irq_handle(uint8_t slot_id, uint8_t sym_id);
/* eCPRI symbol interrupt send */
int32_t ecpri_sym_irq_send(uint8_t ant_id, uint8_t slot_type, uint8_t sym_id);
#endif /* _ECPRI_IRQ_H_ */

125
public/ecs_rfm_spu0/driver/inc/ecpri_que.h Normal file
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@ -0,0 +1,125 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_que.h
* Create Date: 23/05/15
* Description: eCPRI Queue Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/05/15 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_QUE_H_
#define _ECPRI_QUE_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include <stdbool.h>
#include "ucp_ecpri.h"
#include "ucp_param.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "app_interface.h"
#include "hwque.h"
#include "ecpri_comm.h"
#ifdef TEST_ENABLE
#include "ecpri_test.h"
#endif
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* eCPRI packet type field offset */
#define ECPRI_PKT_TYPE_OFFSET 16
/* eCPRI packet payload length field offset */
#define ECPRI_PKT_LEN_OFFSET 20
/* eCPRI packet head(eth_head+com_head) length */
#define ECPRI_PKT_HEAD_LEN 22 // 18
/* eCPRI descriptor packet length field offset */
#define ECPRI_DESC_PKT_LEN_OFFSET (ECPRI_PKT_SIZE - 0x1C)
/* eCPRI strip ethernet head enable */
//#define ECPRI_STRIP_ETH_HEAD_ENABLE
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* eCPRI ethernet type enumeration */
typedef enum EcpriEtherType
{
E_Ether_Type_PTP = 0x88F7, /* PTP(1588) */
E_Ether_Type_ECPRI = 0xAEFE /* eCPRI */
} EcpriEtherType_e;
/* eCPRI message type enumeration */
typedef enum EcpriMsgType
{
E_MSG_TYPE_APE = 0x55, /* APE message */
E_MSG_TYPE_ARM = 0xaa /* ARM message */
} EcpriMsgType_e;
/* eCPRI core ID enumeration */
typedef enum EcpriCoreId
{
E_CORE_ID_APE0 = 0, /* APE0 */
E_CORE_ID_APE1, /* APE1 */
E_CORE_ID_APE2, /* APE2 */
E_CORE_ID_APE3, /* APE3 */
E_CORE_ID_APE4, /* APE4 */
E_CORE_ID_APE5, /* APE5 */
E_CORE_ID_APE6, /* APE6 */
E_CORE_ID_APE7, /* APE7 */
E_CORE_ID_PET0, /* PET RFM SPU0 */
E_CORE_ID_PET1, /* PET RFM SPU1 */
E_CORE_ID_ECS0, /* ECS RFM SPU0 */
E_CORE_ID_ECS1, /* PET RFM SPU1 */
E_CORE_ID_ARM0 /* ARM0 */
} EcpriCoreId_t;
/* eCPRI packet statistic structure */
typedef struct EcpriPktStats
{
uint64_t total_pkts; /* total packets */
uint64_t ecpri_pkts; /* eCPRI packets */
uint64_t other_pkts; /* other packets */
} EcpriPktStats_t;
/* eCPRI ring buffer structure */
typedef struct EcpriRingBuf
{
uint32_t wr_idx; /* write index */
uint32_t rd_idx; /* read index */
EcpriPktStats_t ecpri_pkt_stats; /* eCPRI packet statistic */
} EcpriRingBuf_t;
/* eCPRI inform message structure */
typedef struct EcpriInformMsg
{
uint32_t pkt_addr; /* packet address */
uint32_t pkt_len; /* packet length */
} EcpriInformMsg_t;
/* eCPRI callback function type */
typedef void (* EcpriCallback)(uint32_t, uint16_t);
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI queue init */
int32_t ecpri_que_init(void);
/* eCPRI queue polling */
int32_t ecpri_que_polling(void);
/* eCPRI packet process */
void ecpri_pkt_proc(uint32_t pkt_addr);
/* eCPRI inform PL */
int32_t ecpri_inform_pl(uint32_t pkt_addr, uint16_t pkt_len);
/* eCPRI inform ARM */
int32_t ecpri_inform_arm(uint32_t pkt_addr);
/* eCPRI callback function register */
void ecpri_callback_register(EcpriCallback ecpri_callback);
/* eCPRI packet statistic get */
int32_t ecpri_pkt_stats_get(EcpriPktStats_t *ecpri_pkt_stats);
#endif /* _ECPRI_QUE_H_ */

127
public/ecs_rfm_spu0/driver/inc/ecpri_queue_proc.h
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@ -1,127 +0,0 @@
//******************** (C) COPYRIGHT 2020 SmartLogic*******************************
// FileName : ecpri_queue_proc.h
// Author : shanghuihui, huihui.shang@smartlogictech.com
// Date First Issued : 2023-05-15 11:16:39 AM
// Last Modified : 2023-05-15 11:16:39 AM
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef _ECPRI_QUEUE_PROC_H_
#define _ECPRI_QUEUE_PROC_H_
//#include <netinet/in.h>
//#include "typedef.h"
#include "ucp_ecpri.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "app_interface.h"
#include "ucp_handshake.h"
#include "ucp_tick.h"
#include "ape_csu.h"
#include "hwque.h"
#ifndef NULL
#define NULL ((void *)0)
#endif
/* eCPRI数据缓冲区地址 */
#define ECPRI_DATA_BUF_ADDR 0xAEE00000ul
/* eCPRI数据缓冲区大小（63MB） */
#define ECPRI_DATA_BUF_SIZE 0x01E00000ul // 0x03F00000ul
/* eCPRI调试缓冲区地址 */
#define ECPRI_DBG_BUF_ADDR (ECPRI_DATA_BUF_ADDR + 0x03F00000ul) // (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)
/* eCPRI调试缓冲区大小（1MB） */
#define ECPRI_DBG_BUF_SIZE 0x00100000ul
/* eCPRI数据包大小（16KB） */
#define ECPRI_DATA_PKT_SIZE 0x00004000ul
/* eCPRI数据包最大数量 */
#define ECPRI_DATA_PKT_MAX (ECPRI_DATA_BUF_SIZE / ECPRI_DATA_PKT_SIZE)
/* eCPRI ROEC DESC地址单位（1:32B） */
#define ECPRI_DESC_ADDR_UNIT 32
/* 数据包类型-eCPRI */
#define ECPRI_PKT_TYPE_ECPRI 0xAEFE
/* 数据包类型-1588 */
#define ECPRI_PKT_TYPE_1588 0x88F7
/* APE测试任务ID */
#define ECPRI_APE_TEST_TASK_ID 40 // 63
/* STC统计最大cycle值 */
#define STC_CYCLE_MAX 1000000000ul
/* 循环队列结构体 */
typedef struct Stru_Ring_Buf
{
uint32_t u32WrIdx; /* 写索引 */
uint32_t u32RdIdx; /* 读索引 */
uint32_t u32BufSize; /* 缓冲区大小 */
uint8_t *pu8Buf; /* 缓冲区指针 */
} STRU_RING_BUF;
/* 通知消息结构体 */
typedef struct Stru_Inform_Msg
{
uint32_t u32PktAddr; /* 数据包地址 */
uint32_t u32PktLen; /* 数据包长度 */
} STRU_INFORM_MSG;
/* 消息类型枚举 */
typedef enum Enum_Msg_Type
{
E_MSG_TYPE_APE = 0x55, /* APE消息类型 */
E_MSG_TYPE_ARM = 0xaa /* ARM消息类型 */
} ENUM_MSG_TYPE;
/* 核ID */
typedef enum Enum_Core_Id
{
E_CORE_ID_APE0 = 0, /* APE0核ID */
E_CORE_ID_APE1, /* APE1核ID */
E_CORE_ID_APE2, /* APE2核ID */
E_CORE_ID_APE3, /* APE3核ID */
E_CORE_ID_APE4, /* APE4核ID */
E_CORE_ID_APE5, /* APE5核ID */
E_CORE_ID_APE6, /* APE6核ID */
E_CORE_ID_APE7, /* APE7核ID */
E_CORE_ID_PET0, /* PET RFM SPU0核ID */
E_CORE_ID_PET1, /* PET RFM SPU1核ID */
E_CORE_ID_ECS0, /* ECS RFM SPU0核ID */
E_CORE_ID_ECS1, /* PET RFM SPU1核ID */
E_CORE_ID_ARM0 /* ARM0核ID */
} ENUM_APE_CORE_ID;
/* ecpri循环队列初始化 */
void ecpri_queue_init(void);
/* ecpri循环队列轮询 */
void ecpri_queue_proc(void);
/* ecpri数据包处理 */
void ecpri_packet_proc(uint32_t u32PktAddr);
/* ecpri通知ape */
int32_t ecpri_inform_ape(uint32_t u32PktAddr, uint32_t u32PktLen);
/* ecpri通知arm */
int32_t ecpri_inform_arm(uint32_t u32PktAddr, uint32_t u32PktLen);
/* ecpri通知arm扩展接口 */
int32_t ecpri_inform_arm_ex(uint32_t u32PktAddr);
/* ecpri内存拷贝测试 */
void ecpri_memcpy_test(void);
/* ecpri csu_dma搬数测试 */
void ecpri_csu_dma_test(void);
#endif /* _ECPRI_QUEUE_PROC_H_ */

152
public/ecs_rfm_spu0/driver/src/ecpri_csu.s.c
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@ -1,90 +1,25 @@
#include "ecpri_csu.h"
#if 0
char g_acEcpriCsuSendBuf[16384] = {
0X00, 0X1B, 0X21, 0X89, 0X67, 0X5C,
0X00, 0X0A, 0X09, 0X08, 0X07, 0X16,
0X81, 0X00, 0X00, 0X01, 0XAE, 0XFE,
0X45, 0X00, 0X00, 0XBE, 0X12, 0X34,
0X40, 0X00, 0XFF, 0X11, 0X40, 0XC9
};
#endif
char g_acEcpriDataHeaderBuf[30] = {
0X00, 0X1B, 0X21, 0X89, 0X67, 0X5C,
0XFF, 0XFA, 0XF9, 0XF8, 0XF7, 0XF6, //MAC地址不能重复 0X00, 0X0A, 0X09, 0X08, 0X07, 0X16
0X81, 0X00, 0X00, 0X01, 0XAE, 0XFE,
0X45, 0X00, 0X00, 0XBE, 0X12, 0X34,
0X40, 0X00, 0XFF, 0X11, 0X40, 0XC9
};
void ecpri_csu_send_data_init(void)
{
uint32_t i = 0;
for (i = 0; i < 30; i++)
{
do_write_byte(ECPRI_CSU_DATA_BUF_ADDR + i, g_acEcpriDataHeaderBuf[i]);
}
memset_ucp(ECPRI_CSU_DATA_BUF_ADDR + 30, 0x5A, (11264 - 30));
}
int32_t ecpri_csu_init(void)
{
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x55555555);
#if 0
memset_ucp((char *)&g_acEcpriCsuSendBuf[30], 0x5A, 11264);
#else
ecpri_csu_send_data_init();
#endif
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x11111111);
do_write(&JECS_CSU_EM_BS_SMSEL_PREDATANUM, ((0x1<<25) | (0x1<<14) | (0x5<<5) | 0x8)); // bit25: ecpri mode， bit14: FIFO1
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x10, do_read_volatile(&JECS_CSU_EM_BS_SMSEL_PREDATANUM));
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x22222222);
do_write(&JECS_CSU_FINDDMATAG, 0x60); // DMA搬移完成才能查到结束状态
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x14, do_read_volatile(&JECS_CSU_FINDDMATAG));
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x33333333);
do_write(&JECS_CSU_TAGMASK0, 0xFFFFFFFF);
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x18, do_read_volatile(&JECS_CSU_TAGMASK0));
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x44444444);
for (uint8_t i = 0; i < ECPRI_CSU_REG_NUM; i++)
{
uint8_t offset = (i<<3);
do_write(((uint32_t*)(&JECS_CSU_DMAADDRL0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x00, do_read_volatile(&JECS_CSU_DMAADDRL0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAADDRH0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x04, do_read_volatile(&JECS_CSU_DMAADDRH0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAYNUMXNUM0) + offset), ((4 << 16) | 1024));
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x08, do_read_volatile(&JECS_CSU_DMAYNUMXNUM0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAYSTEPL0) + offset), 1024);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x0C, do_read_volatile(&JECS_CSU_DMAYSTEPL0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAYSTEPH0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x10, do_read_volatile(&JECS_CSU_DMAYSTEPH0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAZSTEPL0) + offset), 4096);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x14, do_read_volatile(&JECS_CSU_DMAZSTEPL0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAZSTEPH0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x18, do_read_volatile(&JECS_CSU_DMAZSTEPH0 + offset));
do_write((&JECS_CSU_DMAADDRL0 + offset), 0);
do_write((&JECS_CSU_DMAADDRH0 + offset), 0);
do_write((&JECS_CSU_DMAYNUMXNUM0 + offset), ((4 << 16) | 1024));
do_write((&JECS_CSU_DMAYSTEPL0 + offset), 1024);
do_write((&JECS_CSU_DMAYSTEPH0 + offset), 0);
do_write((&JECS_CSU_DMAZSTEPL0 + offset), 4096);
do_write((&JECS_CSU_DMAZSTEPH0 + offset), 0);
}
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0xaaaaaaaa);
return 0;
}
@ -180,31 +115,32 @@ uint32_t ecpri_csu_send(uint64_t dataAddr, uint32_t dataLen, uint8_t isWait)
regGroup = temp & 0xFF;
tag = (temp>>8) & 0xFF;
uint16_t offset_w = regGroup << 4;
// src reg
do_write(((uint32_t*)(&JECS_CSU_DMAADDRL0) + offset_w), (dataAddr & 0xFFFFFFFF));
do_write(((uint32_t*)(&JECS_CSU_DMAADDRH0) + offset_w), (uint32_t)(dataAddr >> 32));
do_write(((uint32_t*)(&JECS_CSU_DMASIZEGRANALLNUM0) + offset_w), ((0xF<<28) | (0xE<<24) | dataLen)); // DM,CGran=1,Gran=6;size=0xF
// dst reg
//do_write(((uint32_t*)(&JECS_CSU_DMAADDRL1) + offset_w), 0);
//do_write(((uint32_t*)(&JECS_CSU_DMAADDRH1) + offset_w), 0);
//do_write(((uint32_t*)(&JECS_CSU_DMASIZEGRANALLNUM1) + offset_w), ((0x8<<28) | (0x0<<24) | dataLen)); // 1<<{GRAN[3],SIZE[3]}
do_write(((uint32_t*)(&JECS_CSU_DMASIZEGRANALLNUM1) + offset_w), ((0x9<<28) | (0x0<<24) | dataLen)); // 1<<{GRAN[3],SIZE[3]}, SIZE[2:0]->packet_end, GRAN[2:0]->section_end
uint16_t offset_w = regGroup << 4;
//src reg
do_write((&JECS_CSU_DMAADDRL0 + offset_w), (dataAddr & 0xFFFFFFFF));
do_write((&JECS_CSU_DMAADDRH0 + offset_w), (uint32_t)(dataAddr >> 32));
do_write((&JECS_CSU_DMASIZEGRANALLNUM0 + offset_w), ((0xF<<28) | (0xE<<24) | dataLen)); // DM,CGran=1,Gran=6;size=0xF
//dst reg
//do_write((&JECS_CSU_DMAADDRL1 + offset_w), 0);
//do_write((&JECS_CSU_DMAADDRH1 + offset_w), 0);
//do_write((&JECS_CSU_DMASIZEGRANALLNUM1 + offset_w), ((0x8<<28) | (0x0<<24) | dataLen)); // 1<<{GRAN[3],SIZE[3]}
do_write((&JECS_CSU_DMASIZEGRANALLNUM1 + offset_w), ((0x9<<28) | (0x0<<24) | dataLen)); // 1<<{GRAN[3],SIZE[3]}, SIZE[2:0]->packet_end, GRAN[2:0]->section_end
stCsuDmaCmdL dmaCmdL;
*(uint32_t *)(&dmaCmdL) = 0;
dmaCmdL.dmaType = 1;
dmaCmdL.idSrc = 0 + (regGroup<<1);
dmaCmdL.idDst = 1 + (regGroup<<1);
dmaCmdL.dmaTag = tag;
dmaCmdL.ecpriEnd = 1; // packet end
do_write(((stCsuDmaCmdL*)(&JECS_CSU_CMDFIFO1)), (*(uint32_t*)(&dmaCmdL)));
dmaCmdL.idSrc = 0 + (regGroup<<1);
dmaCmdL.idDst = 1 + (regGroup<<1);
dmaCmdL.dmaTag = tag;
dmaCmdL.ecpriEnd = 1; // packet end
do_write(((stCsuDmaCmdL *)(&JECS_CSU_CMDFIFO1)), (*(uint32_t *)(&dmaCmdL)));
if (1 == isWait)
{
while (0 == (do_read_volatile(&JECS_CSU_DMASTATUS) & (1 << tag)));
}
if (1 == isWait)
{
while (0 == (do_read_volatile((uint32_t*)(&JECS_CSU_DMASTATUS)) & (1 << tag)));
}
return tag;
}
@ -221,32 +157,18 @@ int32_t ecpri_csu_task_lookup(uint8_t task_tag, uint8_t isWait)
{
if (0 == isWait)
{
return (do_read_volatile((uint32_t*)(&JECS_CSU_DMASTATUS)) & (1 << task_tag));
}
else
{
while (0 == (do_read_volatile((uint32_t*)(&JECS_CSU_DMASTATUS)) & (1 << task_tag)))
{
ucp_nop(1);
}
return (do_read_volatile(&JECS_CSU_DMASTATUS) & (1 << task_tag));
}
else
{
while (0 == (do_read_volatile(&JECS_CSU_DMASTATUS) & (1 << task_tag)))
{
ucp_nop(1);
}
return 1;
}
}
uint32_t g_u32CsuSendCnt = 0;
void ecpri_csu_send_test(void)
{
uint32_t tag = 0xFFFFFFFF;
//tag = ecpri_csu_send((uint64_t)ECPRI_CSU_DATA_BUF_ADDR, 0x2C00, 1); //发送11KB
//tag = ecpri_csu_send((uint64_t)ECPRI_CSU_DATA_BUF_ADDR, 0x200, 1); //发送512B
tag = ecpri_csu_send((uint64_t)ECPRI_CSU_DATA_BUF_ADDR, 0x2580, 1); //发送512B
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x8000 + 0x10 + g_u32CsuSendCnt * 0x4, tag);
g_u32CsuSendCnt++;
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x8000 + 0x00, g_u32CsuSendCnt);
}

175
public/ecs_rfm_spu0/driver/src/ecpri_irq.s.c Normal file
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@ -0,0 +1,175 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_irq.s.c
* Create Date: 23/09/04
* Description: eCPRI Interrupt Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/04 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_irq.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
/* eCPRI send flag */
uint32_t g_ecpri_send_flag = 0; /* ECS_RFM0: 0xB7E30100(64) */
/* eCPRI send length */
uint32_t g_ecpri_send_len = 0; /* ECS_RFM0: 0xB7E30104(65) */
/* eCPRI symbol interrupt statistic */
EcpriSymIrqStats_t g_ecpri_sym_irq_stats = {0};
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: ecpri_sym_irq_handle
* Description: eCPRI symbol interrupt handle
* Input:
* <name> <type> <desc>
* slot_id uint8_t slot index
* sym_id uint8_t symbol index
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_sym_irq_handle(uint8_t slot_id, uint8_t sym_id)
{
/* slot type */
uint8_t slot_type = 0;
/* antenna index */
uint8_t ant_id = 0;
/* start cycle */
uint32_t start_cycle = 0;
/* end cycle */
uint32_t end_cycle = 0;
/* cycle number */
uint32_t cycle_num = 0;
g_ecpri_sym_irq_stats.handle_times++;
/* get eCPRI send flag */
g_ecpri_send_flag = do_read_volatile((void *)ECPRI_DBG_ADDR0(64)); /* ECS_RFM0: 0xB7E30100(64) */
if (0 == g_ecpri_send_flag)
{
g_ecpri_sym_irq_stats.handle_succ_times++;
debug_write(ECPRI_DBG_IDX0(68), g_ecpri_sym_irq_stats.handle_times); /* ECS_RFM0: 0xB7E30110(68) */
debug_write(ECPRI_DBG_IDX0(69), g_ecpri_sym_irq_stats.handle_succ_times); /* ECS_RFM0: 0xB7E30114(69) */
return SUCCESS;
}
/* input para check */
if ((ECPRI_SLOT_NUM <= slot_id) || (ECPRI_SYM_NUM <= sym_id))
{
g_ecpri_sym_irq_stats.handle_fail_times++;
debug_write(ECPRI_DBG_IDX0(68), g_ecpri_sym_irq_stats.handle_times); /* ECS_RFM0: 0xB7E30110(68) */
debug_write(ECPRI_DBG_IDX0(69), g_ecpri_sym_irq_stats.handle_succ_times); /* ECS_RFM0: 0xB7E30114(69) */
debug_write(ECPRI_DBG_IDX0(70), g_ecpri_sym_irq_stats.handle_fail_times); /* ECS_RFM0: 0xB7E30118(70) */
return ERROR;
}
/* calculate slot type(odd/even) */
slot_type = slot_id % ECPRI_SLOT_TYPE;
for (ant_id = 0; ant_id < ECPRI_ANT_NUM; ant_id++)
{
rdmcycle(&start_cycle);
(void)ecpri_sym_irq_send(ant_id, slot_type, sym_id);
rdmcycle(&end_cycle);
cycle_num = (end_cycle + STC_CYCLE_MAX - start_cycle) % STC_CYCLE_MAX + 1;
debug_write(ECPRI_DBG_IDX0(72 + ant_id), cycle_num); /* ECS_RFM0: 0xB7E30120(72) ~ 0xB7E3012C(75) */
}
g_ecpri_sym_irq_stats.handle_succ_times++;
debug_write(ECPRI_DBG_IDX0(68), g_ecpri_sym_irq_stats.handle_times); /* ECS_RFM0: 0xB7E30110(68) */
debug_write(ECPRI_DBG_IDX0(69), g_ecpri_sym_irq_stats.handle_succ_times); /* ECS_RFM0: 0xB7E30114(69) */
debug_write(ECPRI_DBG_IDX0(70), g_ecpri_sym_irq_stats.handle_fail_times); /* ECS_RFM0: 0xB7E30118(70) */
return SUCCESS;
}
/**********************************************************************************************************************
* Function: ecpri_sym_irq_send
* Description: eCPRI symbol interrupt send
* Input:
* <name> <type> <desc>
* ant_id uint8_t antenna index
* slot_type uint8_t slot type
* sym_id uint8_t symbol index
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_sym_irq_send(uint8_t ant_id, uint8_t slot_type, uint8_t sym_id)
{
/* config index */
uint32_t cfg_id = 0;
/* packet address */
uint32_t pkt_addr = 0;
/* packet length */
uint32_t pkt_len = 0;
g_ecpri_sym_irq_stats.send_times++;
/* input para check */
if ((ECPRI_ANT_NUM <= ant_id) || (ECPRI_SLOT_TYPE <= slot_type) || (ECPRI_SYM_NUM <= sym_id))
{
g_ecpri_sym_irq_stats.send_fail_times++;
debug_write(ECPRI_DBG_IDX0(80), g_ecpri_sym_irq_stats.send_times); /* ECS_RFM0: 0xB7E30140(80) */
debug_write(ECPRI_DBG_IDX0(82), g_ecpri_sym_irq_stats.send_fail_times); /* ECS_RFM0: 0xB7E30148(82) */
return ERROR;
}
/* config index */
cfg_id = ant_id * ECPRI_SLOT_TYPE * ECPRI_SYM_NUM + slot_type * ECPRI_SYM_NUM + sym_id;
/* get packet address */
pkt_addr = do_read_volatile((void *)(ECPRI_ANT_BUF_ADDR + cfg_id * ECPRI_SYM_INFO_LEN));
/* get eCPRI send length */
g_ecpri_send_len = do_read_volatile((void *)ECPRI_DBG_ADDR0(65)); /* ECS_RFM0: 0xB7E30104(65) */
if (0 == g_ecpri_send_len)
{
/* send real length */
pkt_len = do_read_volatile((void *)(ECPRI_ANT_BUF_ADDR + cfg_id * ECPRI_SYM_INFO_LEN + sizeof(uint32_t)));
}
else
{
/* send specify length */
pkt_len = g_ecpri_send_len;
}
/* check config info */
if ((0 == pkt_addr) || (0 == pkt_len) || (ECPRI_PKT_SIZE < pkt_len))
{
g_ecpri_sym_irq_stats.send_fail_times++;
debug_write(ECPRI_DBG_IDX0(80), g_ecpri_sym_irq_stats.send_times); /* ECS_RFM0: 0xB7E30140(80) */
debug_write(ECPRI_DBG_IDX0(82), g_ecpri_sym_irq_stats.send_fail_times); /* ECS_RFM0: 0xB7E30148(82) */
return ERROR;
}
/* eCPRI CSU send packet */
(void)ecpri_csu_send(pkt_addr, pkt_len, 0);
g_ecpri_sym_irq_stats.send_succ_times++;
debug_write(ECPRI_DBG_IDX0(80), g_ecpri_sym_irq_stats.send_times); /* ECS_RFM0: 0xB7E30140(80) */
debug_write(ECPRI_DBG_IDX0(81), g_ecpri_sym_irq_stats.send_succ_times); /* ECS_RFM0: 0xB7E30144(81) */
debug_write(ECPRI_DBG_IDX0(82), g_ecpri_sym_irq_stats.send_fail_times); /* ECS_RFM0: 0xB7E30148(82) */
return SUCCESS;
}

395
public/ecs_rfm_spu0/driver/src/ecpri_que.s.c Normal file
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@ -0,0 +1,395 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_que.s.c
* Create Date: 23/05/15
* Description: eCPRI Queue Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/05/15 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_que.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
/* eCPRI ring buffer management structure */
EcpriRingBuf_t g_ecpri_ring_buf = {0};
/* eCPRI callback function */
EcpriCallback g_ecpri_callback = NULL;
/* eCPRI queue poll count */
uint64_t g_ecpri_que_poll_cnt = 0;
/* PCS SerDes Loopback Flag */
bool g_pcs_loopback = true;
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: ecpri_que_init
* Description: eCPRI queue init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_que_init(void)
{
/* write position */
uint32_t wr_pos = 0;
/* write address */
uint32_t wr_addr = 0;
/* eCPRI ring buffer management structure clear */
memset_ucp((void *)&g_ecpri_ring_buf, 0x00, sizeof(g_ecpri_ring_buf));
/* get write position */
wr_pos = do_read_volatile(&DESC_PTR_2);
/* calculate write address and verify validity */
wr_addr = wr_pos * ECPRI_DESC_ADDR_UNIT;
if ((wr_addr < ECPRI_RX_BUF_ADDR) ||
(wr_addr >= (ECPRI_RX_BUF_ADDR + ECPRI_RX_BUF_SIZE)) ||
(((wr_addr - ECPRI_RX_BUF_ADDR) % ECPRI_PKT_SIZE) != 0))
{
debug_write(ECPRI_DBG_IDX0(0), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E30000(0) */
debug_write(ECPRI_DBG_IDX0(1), wr_pos); /* ECS_RFM0: 0xB7E30004(1) */
debug_write(ECPRI_DBG_IDX0(2), wr_addr); /* ECS_RFM0: 0xB7E30008(2) */
return ERROR;
}
/* update next valid address for descriptor */
do_write(&DESC_TAIL_ADDR_2, wr_pos);
/* update write/read index */
g_ecpri_ring_buf.wr_idx = (wr_addr - ECPRI_RX_BUF_ADDR) / ECPRI_PKT_SIZE;
g_ecpri_ring_buf.rd_idx = g_ecpri_ring_buf.wr_idx;
debug_write(ECPRI_DBG_IDX0(0), (uint32_t)SUCCESS); /* ECS_RFM0: 0xB7E30000(0) */
debug_write(ECPRI_DBG_IDX0(1), wr_pos); /* ECS_RFM0: 0xB7E30004(1) */
debug_write(ECPRI_DBG_IDX0(2), wr_addr); /* ECS_RFM0: 0xB7E30008(2) */
debug_write(ECPRI_DBG_IDX0(3), g_ecpri_ring_buf.wr_idx); /* ECS_RFM0: 0xB7E3000C(3) */
debug_write(ECPRI_DBG_IDX0(4), g_ecpri_ring_buf.rd_idx); /* ECS_RFM0: 0xB7E30010(4) */
return SUCCESS;
}
/**********************************************************************************************************************
* Function: ecpri_que_polling
* Description: eCPRI queue polling
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_que_polling(void)
{
/* write position */
uint32_t wr_pos = 0;
/* write address */
uint32_t wr_addr = 0;
/* read number */
uint32_t rd_num = 0;
/* read address */
uint32_t rd_addr = 0;
/* count index */
uint32_t i = 0;
if (g_pcs_loopback)
{
/* solve start packet impact, recover normal mode */
do_write(&MC_CFG_RX, BIT3 + BIT1); //rx_elastic_buffer_initial_fill 5
g_pcs_loopback = false;
}
/* update eCPRI queue poll count */
g_ecpri_que_poll_cnt++;
/* get write position */
wr_pos = do_read_volatile(&DESC_PTR_2);
/* calculate write address and verify validity */
wr_addr = wr_pos * ECPRI_DESC_ADDR_UNIT;
if ((wr_addr < ECPRI_RX_BUF_ADDR) ||
(wr_addr >= (ECPRI_RX_BUF_ADDR + ECPRI_RX_BUF_SIZE)) ||
(((wr_addr - ECPRI_RX_BUF_ADDR) % ECPRI_PKT_SIZE) != 0))
{
debug_write(ECPRI_DBG_IDX0(8), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E30020(8) */
debug_write(ECPRI_DBG_IDX0(10), g_ecpri_que_poll_cnt & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30028(10) */
debug_write(ECPRI_DBG_IDX0(11), (g_ecpri_que_poll_cnt >> 32) & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E3002C(11) */
debug_write(ECPRI_DBG_IDX0(12), wr_pos); /* ECS_RFM0: 0xB7E30030(12) */
debug_write(ECPRI_DBG_IDX0(13), wr_addr); /* ECS_RFM0: 0xB7E30034(13) */
return ERROR;
}
/* calculate write index */
g_ecpri_ring_buf.wr_idx = (wr_addr - ECPRI_RX_BUF_ADDR) / ECPRI_PKT_SIZE;
/* read index equals to write index, no packet need read */
if (g_ecpri_ring_buf.wr_idx == g_ecpri_ring_buf.rd_idx)
{
debug_write(ECPRI_DBG_IDX0(8), (uint32_t)SUCCESS); /* ECS_RFM0: 0xB7E30020(8) */
debug_write(ECPRI_DBG_IDX0(10), g_ecpri_que_poll_cnt & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30028(10) */
debug_write(ECPRI_DBG_IDX0(11), (g_ecpri_que_poll_cnt >> 32) & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E3002C(11) */
debug_write(ECPRI_DBG_IDX0(12), wr_pos); /* ECS_RFM0: 0xB7E30030(12) */
debug_write(ECPRI_DBG_IDX0(13), wr_addr); /* ECS_RFM0: 0xB7E30034(13) */
debug_write(ECPRI_DBG_IDX0(14), g_ecpri_ring_buf.wr_idx); /* ECS_RFM0: 0xB7E30038(14) */
debug_write(ECPRI_DBG_IDX0(15), g_ecpri_ring_buf.rd_idx); /* ECS_RFM0: 0xB7E3003C(15) */
return SUCCESS;
}
/* calculate number of packets need to read */
rd_num = (g_ecpri_ring_buf.wr_idx + ECPRI_PKT_MAX - g_ecpri_ring_buf.rd_idx) % ECPRI_PKT_MAX;
for (i = 0; i < rd_num; i++)
{
/* calculate read address */
rd_addr = ECPRI_RX_BUF_ADDR + g_ecpri_ring_buf.rd_idx * ECPRI_PKT_SIZE;
/* eCPRI packet process */
ecpri_pkt_proc(rd_addr);
/* update next valid address for descriptor */
do_write(&DESC_TAIL_ADDR_2, ((rd_addr + ECPRI_PKT_SIZE) / ECPRI_DESC_ADDR_UNIT));
/* update read index */
g_ecpri_ring_buf.rd_idx++;
g_ecpri_ring_buf.rd_idx %= ECPRI_PKT_MAX;
}
/* update total packets */
g_ecpri_ring_buf.ecpri_pkt_stats.total_pkts += rd_num;
debug_write(ECPRI_DBG_IDX0(8), (uint32_t)SUCCESS); /* ECS_RFM0: 0xB7E30020(8) */
debug_write(ECPRI_DBG_IDX0(10), g_ecpri_que_poll_cnt & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30028(10) */
debug_write(ECPRI_DBG_IDX0(11), (g_ecpri_que_poll_cnt >> 32) & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E3002C(11) */
debug_write(ECPRI_DBG_IDX0(12), wr_pos); /* ECS_RFM0: 0xB7E30030(12) */
debug_write(ECPRI_DBG_IDX0(13), wr_addr); /* ECS_RFM0: 0xB7E30034(13) */
debug_write(ECPRI_DBG_IDX0(14), g_ecpri_ring_buf.wr_idx); /* ECS_RFM0: 0xB7E30038(14) */
debug_write(ECPRI_DBG_IDX0(15), g_ecpri_ring_buf.rd_idx); /* ECS_RFM0: 0xB7E3003C(15) */
debug_write(ECPRI_DBG_IDX0(16), rd_num); /* ECS_RFM0: 0xB7E30040(16) */
debug_write(ECPRI_DBG_IDX0(18), g_ecpri_ring_buf.ecpri_pkt_stats.total_pkts & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30048(18)(LSB) */
debug_write(ECPRI_DBG_IDX0(19), (g_ecpri_ring_buf.ecpri_pkt_stats.total_pkts >> 32) & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E3004C(19)(MSB) */
return SUCCESS;
}
/**********************************************************************************************************************
* Function: ecpri_pkt_proc
* Description: eCPRI packet process
* Input:
* <name> <type> <desc>
* pkt_addr uint32_t packet address
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_pkt_proc(uint32_t pkt_addr)
{
/* ethernet type */
uint16_t ether_type = 0;
#ifdef ECPRI_STRIP_ETH_HEAD_ENABLE
/* payload address */
uint32_t payload_addr = 0;
#endif
/* payload length */
uint16_t payload_len = 0;
/* packet length */
uint16_t pkt_len = 0;
/* get ethernet type of packet */
ether_type = do_read_short(pkt_addr + ECPRI_PKT_TYPE_OFFSET);
ether_type = ((ether_type & 0xFF) << 8) | ((ether_type & 0xFF00) >> 8);
/* eCPRI packet */
if ((uint16_t)E_Ether_Type_ECPRI == ether_type)
{
/* update eCPRI packets */
g_ecpri_ring_buf.ecpri_pkt_stats.ecpri_pkts++;
debug_write(ECPRI_DBG_IDX0(24), g_ecpri_ring_buf.ecpri_pkt_stats.ecpri_pkts & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30060(24)(LSB) */
debug_write(ECPRI_DBG_IDX0(25), (g_ecpri_ring_buf.ecpri_pkt_stats.ecpri_pkts >> 32) & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30064(25)(MSB) */
/* get eCPRI packet payload length */
payload_len = do_read_short(pkt_addr + ECPRI_PKT_LEN_OFFSET);
payload_len = ((payload_len & 0xFF) << 8) | ((payload_len & 0xFF00) >> 8);
#ifdef ECPRI_STRIP_ETH_HEAD_ENABLE
/* calculate eCPRI packet payload address(strip ethernet head and eCPRI common head) */
payload_addr = pkt_addr + ECPRI_PKT_HEAD_LEN;
debug_write(ECPRI_DBG_IDX0(26), payload_addr); /* ECS_RFM0: 0xB7E30068(26) */
debug_write(ECPRI_DBG_IDX0(27), payload_len); /* ECS_RFM0: 0xB7E3006C(27) */
/* inform PL about eCPRI packet payload address and payload length */
(void)ecpri_inform_pl(payload_addr, payload_len);
#else
/* calculate eCPRI packet length */
pkt_len = payload_len + ECPRI_PKT_HEAD_LEN;
debug_write(ECPRI_DBG_IDX0(26), pkt_addr); /* ECS_RFM0: 0xB7E30068(26) */
debug_write(ECPRI_DBG_IDX0(27), pkt_len); /* ECS_RFM0: 0xB7E3006C(27) */
#ifndef TEST_ENABLE
/* inform PL about eCPRI packet address and packet length */
(void)ecpri_inform_pl(pkt_addr, pkt_len);
#else
/* eCPRI test PL packet process */
ecpri_test_pl_pkt_proc(pkt_addr, pkt_len);
#endif
#endif
}
else /* other packet */
{
/* update other packets */
g_ecpri_ring_buf.ecpri_pkt_stats.other_pkts++;
debug_write(ECPRI_DBG_IDX0(28), g_ecpri_ring_buf.ecpri_pkt_stats.other_pkts & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30070(28) */
debug_write(ECPRI_DBG_IDX0(29), (g_ecpri_ring_buf.ecpri_pkt_stats.other_pkts >> 32) & 0xFFFFFFFF); /* ECS_RFM0: 0xB7E30074(29) */
debug_write(ECPRI_DBG_IDX0(30), pkt_addr); /* ECS_RFM0: 0xB7E30078(30) */
/* inform ARM about other packet address */
(void)ecpri_inform_arm(pkt_addr);
}
}
/**********************************************************************************************************************
* Function: ecpri_inform_pl
* Description: eCPRI inform PL
* Input:
* <name> <type> <desc>
* pkt_addr uint32_t packet address
* pkt_len uint16_t packet length
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_inform_pl(uint32_t pkt_addr, uint16_t pkt_len)
{
/* input para check */
if ((pkt_addr < ECPRI_RX_BUF_ADDR) ||
(pkt_addr >= (ECPRI_RX_BUF_ADDR + ECPRI_RX_BUF_SIZE)) ||
(pkt_len > ECPRI_PKT_SIZE))
{
debug_write(ECPRI_DBG_IDX0(36), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E30090(36) */
debug_write(ECPRI_DBG_IDX0(37), pkt_addr); /* ECS_RFM0: 0xB7E30094(37) */
debug_write(ECPRI_DBG_IDX0(38), pkt_len); /* ECS_RFM0: 0xB7E30098(38) */
return ERROR;
}
/* check eCPRI callback function is NULL or not */
if (NULL == g_ecpri_callback)
{
debug_write(ECPRI_DBG_IDX0(36), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E30090(36) */
debug_write(ECPRI_DBG_IDX0(37), pkt_addr); /* ECS_RFM0: 0xB7E30094(37) */
debug_write(ECPRI_DBG_IDX0(38), pkt_len); /* ECS_RFM0: 0xB7E30098(38) */
debug_write(ECPRI_DBG_IDX0(39), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E3009C(39) */
return ERROR;
}
/* call eCPRI callback function */
g_ecpri_callback(pkt_addr, pkt_len);
debug_write(ECPRI_DBG_IDX0(36), (uint32_t)SUCCESS); /* ECS_RFM0: 0xB7E30090(36) */
debug_write(ECPRI_DBG_IDX0(37), pkt_addr); /* ECS_RFM0: 0xB7E30094(37) */
debug_write(ECPRI_DBG_IDX0(38), pkt_len); /* ECS_RFM0: 0xB7E30098(38) */
debug_write(ECPRI_DBG_IDX0(39), (uint32_t)SUCCESS); /* ECS_RFM0: 0xB7E3009C(39) */
return SUCCESS;
}
/**********************************************************************************************************************
* Function: ecpri_inform_arm
* Description: eCPRI inform ARM
* Input:
* <name> <type> <desc>
* pkt_addr uint32_t packet address
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_inform_arm(uint32_t pkt_addr)
{
/* return value */
int32_t ret = 0;
/* input para check */
if ((pkt_addr < ECPRI_RX_BUF_ADDR) ||
(pkt_addr >= (ECPRI_RX_BUF_ADDR + ECPRI_RX_BUF_SIZE)))
{
debug_write(ECPRI_DBG_IDX0(44), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E300B0(44) */
debug_write(ECPRI_DBG_IDX0(45), pkt_addr); /* ECS_RFM0: 0xB7E300B4(45) */
return ERROR;
}
/* smartos put data in hardware queue */
ret = smart_in_que((int)E_CORE_ID_ARM0, pkt_addr);
if (SUCCESS != ret)
{
debug_write(ECPRI_DBG_IDX0(44), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E300B0(44) */
debug_write(ECPRI_DBG_IDX0(45), pkt_addr); /* ECS_RFM0: 0xB7E300B4(45) */
debug_write(ECPRI_DBG_IDX0(46), (uint32_t)ret); /* ECS_RFM0: 0xB7E300B8(46) */
return ret;
}
debug_write(ECPRI_DBG_IDX0(44), (uint32_t)SUCCESS); /* ECS_RFM0: 0xB7E300B0(44) */
debug_write(ECPRI_DBG_IDX0(45), pkt_addr); /* ECS_RFM0: 0xB7E300B4(45) */
debug_write(ECPRI_DBG_IDX0(46), (uint32_t)ret); /* ECS_RFM0: 0xB7E300B8(46) */
return SUCCESS;
}
/**********************************************************************************************************************
* Function: ecpri_callback_register
* Description: eCPRI callback function register
* Input:
* <name> <type> <desc>
* ecpri_callback EcpriCallback eCPRI callback function
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_callback_register(EcpriCallback ecpri_callback)
{
/* register eCPRI callback function */
g_ecpri_callback = ecpri_callback;
}
/**********************************************************************************************************************
* Function: ecpri_pkt_stats_get
* Description: eCPRI packet statistic get
* Input:
* <name> <type> <desc>
* ecpri_pkt_stats EcpriPktStats_t * eCPRI packet statistic
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_pkt_stats_get(EcpriPktStats_t *ecpri_pkt_stats)
{
/* input para check */
if (NULL == ecpri_pkt_stats)
{
debug_write(ECPRI_DBG_IDX0(52), (uint32_t)ERROR); /* ECS_RFM0: 0xB7E300D0(52) */
return ERROR;
}
/* get eCPRI packet statistic info */
memcpy_ucp((void *)ecpri_pkt_stats,
(void *)&g_ecpri_ring_buf.ecpri_pkt_stats,
sizeof(EcpriPktStats_t));
debug_write(ECPRI_DBG_IDX0(52), (uint32_t)SUCCESS); /* ECS_RFM0: 0xB7E300D0(52) */
return SUCCESS;
}

603
public/ecs_rfm_spu0/driver/src/ecpri_queue_proc.s.c
View File

@ -1,603 +0,0 @@
#include "ecpri_queue_proc.h"
/* 循环队列结构 */
STRU_RING_BUF g_struRingBuf = {0};
/* 读取数据包总数 */
uint64_t g_u64RdPktTotal = 0;
/* 读取数据包循环计数 */
uint32_t g_u32RdPktCnt = 0;
/* ecpri循环队列初始化 */
void ecpri_queue_init(void)
{
/* 数据包存放位置，单位：32Byte */
uint32_t u32DescPtr = 0;
/* 数据包内存地址，单位：Byte */
uint32_t u32MemAddr = 0;
/* 初始化循环缓冲区管理结构 */
g_struRingBuf.u32WrIdx = 0;
g_struRingBuf.u32RdIdx = 0;
g_struRingBuf.pu8Buf= (uint8_t *)ECPRI_DATA_BUF_ADDR;
g_struRingBuf.u32BufSize = ECPRI_DATA_BUF_SIZE;
/* 初始化读取数据包总数 */
g_u64RdPktTotal = 0;
/* 获取数据包存放位置 */
u32DescPtr = do_read_volatile(&DESC_PTR_2);
/* 计算数据包内存地址并进行校验 */
u32MemAddr = u32DescPtr * ECPRI_DESC_ADDR_UNIT;
if ((u32MemAddr < ECPRI_DATA_BUF_ADDR) ||
(u32MemAddr >= (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)) ||
(((u32MemAddr - ECPRI_DATA_BUF_ADDR) % ECPRI_DATA_PKT_SIZE) != 0))
{
do_write(ECPRI_DBG_BUF_ADDR + 0x10, 0x11111111);
do_write(ECPRI_DBG_BUF_ADDR + 0x20, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x24, u32MemAddr);
return;
}
/* 更新描述符下一个地址和当前接收数据包存放位置相同 */
do_write(&DESC_TAIL_ADDR_2, u32DescPtr);
/* 更新读/写索引 */
g_struRingBuf.u32WrIdx = (u32MemAddr - ECPRI_DATA_BUF_ADDR) / ECPRI_DATA_PKT_SIZE;
g_struRingBuf.u32RdIdx = g_struRingBuf.u32WrIdx;
/* 清空eCPRI数据和调试缓冲区 */
memset_ucp(ECPRI_DATA_BUF_ADDR, 0x00, ECPRI_DATA_BUF_SIZE);
memset_ucp(ECPRI_DBG_BUF_ADDR, 0x00, ECPRI_DBG_BUF_SIZE);
do_write(ECPRI_DBG_BUF_ADDR + 0x10, 0x00000000);
do_write(ECPRI_DBG_BUF_ADDR + 0x20, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x24, u32MemAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x28, g_struRingBuf.u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x2C, g_struRingBuf.u32RdIdx);
}
/* ecpri循环队列轮询处理 */
void ecpri_queue_proc(void)
{
/* 数据包存放位置，单位：32Byte */
uint32_t u32DescPtr = 0;
/* 数据包内存地址，单位：Byte */
uint32_t u32MemAddr = 0;
/* 读取包数 */
uint32_t u32RdPktNum = 0;
/* 数据包地址 */
uint32_t u32PktAddr = 0;
/* 计数索引 */
uint32_t i = 0;
/* 获取数据包存放位置 */
u32DescPtr = do_read_volatile(&DESC_PTR_2);
/* 计算数据包内存地址并进行校验 */
u32MemAddr = u32DescPtr * ECPRI_DESC_ADDR_UNIT;
if ((u32MemAddr < ECPRI_DATA_BUF_ADDR) ||
(u32MemAddr >= (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)) ||
(((u32MemAddr - ECPRI_DATA_BUF_ADDR) % ECPRI_DATA_PKT_SIZE) != 0))
{
do_write(ECPRI_DBG_BUF_ADDR + 0x30, 0x11111111);
do_write(ECPRI_DBG_BUF_ADDR + 0x40, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x44, u32MemAddr);
return;
}
/* 计算写索引 */
g_struRingBuf.u32WrIdx = (u32MemAddr - ECPRI_DATA_BUF_ADDR) / ECPRI_DATA_PKT_SIZE;
/* 读/写索引相同，没有数据包要读 */
if (g_struRingBuf.u32WrIdx == g_struRingBuf.u32RdIdx)
{
do_write(ECPRI_DBG_BUF_ADDR + 0x30, 0x22222222);
do_write(ECPRI_DBG_BUF_ADDR + 0x40, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x44, u32MemAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x48, g_struRingBuf.u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x4C, g_struRingBuf.u32RdIdx);
return;
}
/* 计算所要读取的包数 */
u32RdPktNum = (g_struRingBuf.u32WrIdx + ECPRI_DATA_PKT_MAX - g_struRingBuf.u32RdIdx) % ECPRI_DATA_PKT_MAX;
for (i = 0; i < u32RdPktNum; i++)
{
/* 计算数据包地址 */
u32PktAddr = ECPRI_DATA_BUF_ADDR + g_struRingBuf.u32RdIdx * ECPRI_DATA_PKT_SIZE;
/* ecpri数据包处理 */
ecpri_packet_proc(u32PktAddr);
/* 更新描述符下一个地址 */
do_write(&DESC_TAIL_ADDR_2, ((u32PktAddr + ECPRI_DATA_PKT_SIZE) / ECPRI_DESC_ADDR_UNIT));
//printf("[ecpri_queue_proc] u32PktAddr[0x%08x], u32PktLen[0x%08x].\n", u32PktAddr, u32PktLen);
//printf("[ecpri_queue_proc] u32RdIdx[0x%08x], u32WrIdx[0x%08x].\n", u32RdIdx, u32WrIdx);
//UCP_PRINT_ERROR("[ecpri_queue_proc] u32PktAddr[0x%08x], u32PktLen[0x%08x].\n", u32PktAddr, u32PktLen);
//UCP_PRINT_ERROR("[ecpri_queue_proc] u32RdIdx[0x%08x], u32WrIdx[0x%08x].\n", u32RdIdx, u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x00, g_struRingBuf.u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x04, g_struRingBuf.u32RdIdx);
/* 更新读索引 */
g_struRingBuf.u32RdIdx++;
g_struRingBuf.u32RdIdx %= ECPRI_DATA_PKT_MAX;
/* 更新读取数据包循环计数 */
g_u32RdPktCnt++;
g_u32RdPktCnt %= ECPRI_DATA_PKT_MAX;
}
/* 更新读取数据包总数 */
g_u64RdPktTotal += u32RdPktNum;
do_write(ECPRI_DBG_BUF_ADDR + 0x30, 0x00000000);
do_write(ECPRI_DBG_BUF_ADDR + 0x34, ((g_u64RdPktTotal & 0xFFFFFFFF00000000) >> 8));
do_write(ECPRI_DBG_BUF_ADDR + 0x38, (g_u64RdPktTotal & 0xFFFFFFFF));
do_write(ECPRI_DBG_BUF_ADDR + 0x3C, u32RdPktNum);
do_write(ECPRI_DBG_BUF_ADDR + 0x40, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x44, u32MemAddr);
}
/* ecpri数据包处理 */
void ecpri_packet_proc(uint32_t u32PktAddr)
{
/* eCPRI包类型字段偏移 */
uint32_t u32TypeOffset = 16;
/* eCPRI包长字段偏移 */
uint32_t u32LenOffset = 20;
/* 数据包类型 */
uint16_t u16PktType = 0;
/* 数据包长度 */
uint16_t u16PktLen = 0;
#if 0
/* 净荷地址 */
uint32_t u32PayloadAddr = 0;
#endif
/* 判断包类型是否是eCPRI报文 */
u16PktType = do_read_short(u32PktAddr + u32TypeOffset);
u16PktType = ((u16PktType & 0xFF) << 8) | ((u16PktType & 0xFF00) >> 8);
if (ECPRI_PKT_TYPE_ECPRI == u16PktType)
{
/* 获取eCPRI数据包净荷长度，单位：Byte */
u16PktLen = do_read_short(u32PktAddr + u32LenOffset);
u16PktLen = ((u16PktLen & 0xFF) << 8) | ((u16PktLen & 0xFF00) >> 8);
#if 1
/* 计数eCPRI数据包总长度 */
u16PktLen += 18;
//TODO:
/* 将eCPRI数据包净荷地址和净荷长度发送给APE */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x08, u32PktAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x0C, u16PktLen);
(void)ecpri_inform_ape(u32PktAddr, u16PktLen);
#else
/* 计数eCPRI数据包净荷地址 */
u32PayloadAddr = u32PktAddr + 18;
//TODO:
/* 将eCPRI数据包净荷地址和净荷长度发送给APE */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x08, u32PayloadAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x0C, u16PktLen);
(void)ecpri_inform_ape(u32PayloadAddr, u16PktLen);
#endif
}
else
{
/* 获取非eCPRI数据包（如1588等）总长度，单位：Byte */
u32LenOffset = ECPRI_DATA_PKT_SIZE - 0x1C;
u16PktLen = do_read_short(u32PktAddr + u32LenOffset);
//TODO:
/* 将非eCPRI数据包地址和总长度发送给ARM */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x08, u32PktAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x0C, u16PktLen);
#if 0
(void)ecpri_inform_arm(u32PktAddr, u16PktLen);
#else
(void)ecpri_inform_arm_ex(u32PktAddr);
#endif
}
}
/* ecpri通知ape */
int32_t ecpri_inform_ape(uint32_t u32PktAddr, uint32_t u32PktLen)
{
/* 返回值 */
int32_t s32Ret = 0;
/* 消息长度 */
int32_t s32MsgSize = 8;
/* 消息地址 */
char *pcMsgAddr = NULL;
/* 通知消息 */
STRU_INFORM_MSG struInformMsg = {0};
/* 申请消息 */
pcMsgAddr = osp_alloc_msg(s32MsgSize);
if (NULL == pcMsgAddr)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-1));
return -1;
}
/* 组装通知消息 */
#if 1
struInformMsg.u32PktAddr = u32PktAddr;
struInformMsg.u32PktLen = u32PktLen;
memcpy_ucp(pcMsgAddr, &struInformMsg, sizeof(STRU_INFORM_MSG));
#else
do_write(pcMsgAddr, u32PktAddr);
do_write(pcMsgAddr + 4, u32PktLen);
#endif
s32Ret = osp_send_msg((uint32_t)pcMsgAddr,
(uint32_t)sizeof(STRU_INFORM_MSG),
(uint8_t)E_MSG_TYPE_APE,
(uint8_t)ECS_RFM_SPU0_CORE_ID,
(uint8_t)E_CORE_ID_APE0,
(uint8_t)0, // 40 //0
(uint8_t)61); // 40 //ECPRI_APE_TEST_TASK_ID
if (0 != s32Ret)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-2));
return -2;
}
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, 0);
/* 数据包类型-eCPRI */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x14, ECPRI_PKT_TYPE_ECPRI);
return 0;
}
/* ecpri通知arm */
int32_t ecpri_inform_arm(uint32_t u32PktAddr, uint32_t u32PktLen)
{
/* 返回值 */
int32_t s32Ret = 0;
/* 消息长度 */
int32_t s32MsgSize = 8;
/* 消息地址 */
char *pcMsgAddr = NULL;
/* 通知消息 */
STRU_INFORM_MSG struInformMsg = {0};
/* 申请消息 */
pcMsgAddr = osp_alloc_msg(s32MsgSize);
if (NULL == pcMsgAddr)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-1));
return -1;
}
/* 组装通知消息 */
#if 1
struInformMsg.u32PktAddr = u32PktAddr;
struInformMsg.u32PktLen = u32PktLen;
memcpy_ucp(pcMsgAddr, &struInformMsg, sizeof(STRU_INFORM_MSG));
#else
do_write(pcMsgAddr, u32PktAddr);
do_write(pcMsgAddr + 4, u32PktLen);
#endif
s32Ret = osp_send_msg((uint32_t)pcMsgAddr,
(uint32_t)sizeof(STRU_INFORM_MSG),
(uint8_t)E_MSG_TYPE_ARM,
(uint8_t)ECS_RFM_SPU0_CORE_ID,
(uint8_t)E_CORE_ID_ARM0,
(uint8_t)0, // 0
(uint8_t)0); // 61
if (0 != s32Ret)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-2));
return -2;
}
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, 0);
/* 数据包类型-Other */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x14, ECPRI_PKT_TYPE_1588);
return 0;
}
/* ecpri通知arm扩展接口 */
int32_t ecpri_inform_arm_ex(uint32_t u32PktAddr)
{
/* 返回值 */
int32_t s32Ret = 0;
/* 硬件队列入队 */
s32Ret = smart_in_que((int)E_CORE_ID_ARM0, u32PktAddr);
if (0 != s32Ret)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-2));
return -2;
}
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, 0);
/* 数据包类型-Other */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x14, ECPRI_PKT_TYPE_1588);
return 0;
}
/* ecpri内存拷贝测试DDR--->DDR */
void ecpri_memcpy_test(void)
{
/* 计数索引 */
uint32_t i = 0;
/* 计数索引 */
uint32_t j = 0;
/* 开始Cycle */
uint32_t u32StartCycle = 0;
/* 结束Cycle */
uint32_t u32EndCycle = 0;
/* Cycle计数 */
uint32_t u32CycleNum = 0;
/* 填充内存 */
for (i = 0; i < 0x4000; i++)
{
do_write_byte((ECPRI_DATA_BUF_ADDR + i), (i % 256));
}
/* 64Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 64);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x04, 64);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x08, u32CycleNum);
}
/* 128Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 128);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x04, 128);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x08, u32CycleNum);
}
/* 256Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 256);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x04, 256);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x08, u32CycleNum);
}
/* 512Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 512);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x04, 512);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x08, u32CycleNum);
}
/* 1024Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 1024);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x04, 1024);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x08, u32CycleNum);
}
/* 1514Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 1514);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x04, 1514);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x08, u32CycleNum);
}
/* 11264Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 11264);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x04, 11264);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x08, u32CycleNum);
}
}
/* ecpri csu_dma搬数测试 */
void ecpri_csu_dma_test(void)
{
/* 计数索引 */
uint32_t i = 0;
/* 计数索引 */
uint32_t j = 0;
/* 开始Cycle */
uint32_t u32StartCycle = 0;
/* 结束Cycle */
uint32_t u32EndCycle = 0;
/* Cycle计数 */
uint32_t u32CycleNum = 0;
/* 填充内存 */
for (i = 0; i < 0x4000; i++)
{
do_write_byte((ECPRI_DATA_BUF_ADDR + i), (i % 256));
}
/* 64Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000),
64, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x04, 64);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x08, u32CycleNum);
}
/* 128Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000),
128, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x04, 128);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x08, u32CycleNum);
}
/* 256Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000),
256, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x04, 256);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x08, u32CycleNum);
}
/* 512Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000),
512, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x04, 512);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x08, u32CycleNum);
}
/* 1024Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000),
1024, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x04, 1024);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x08, u32CycleNum);
}
/* 1514Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000),
1514, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x04, 1514);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x08, u32CycleNum);
}
/* 11264Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000),
11264, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x04, 11264);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x08, u32CycleNum);
}
}

37
public/ecs_rfm_spu0/driver/src/rfm0_drv.s.c
View File

@ -13,10 +13,13 @@
#include "spu_log.h"
#include "app_interface.h"
//#ifdef ECPRI_DISTRIBUTED_BS
#include "ecpri_queue_proc.h"
#include "ecpri_que.h"
#include "ecpri_csu.h"
//#endif
#ifdef TEST_ENABLE
#include "fh_test.h"
#endif
/*****************************************************/
void ecs_rfm0_drv_init(void)
@ -53,7 +56,6 @@ void ecs_rfm0_drv_init(void)
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#if 1
ctc_cal_intr_init();
UCP_PRINT_EMPTY("ctc cal intr init.\r\n");
#ifdef PALLADIUM_TEST
@ -61,24 +63,31 @@ void ecs_rfm0_drv_init(void)
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
rfm0_mtimer_int_init();
UCP_PRINT_EMPTY("set mtimer rfm0 int.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#endif
/* wait protocol type config finished */
while (PROTOCOL_NULL == get_protocol_sel());
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* wait ecpri serdes clk init finished */
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR)));
/* eCPRIÑ­»·¶ÓÁгõʼ»¯ */
ecpri_queue_init();
rfm0_mtimer_int_init();
/* eCPRI CSU³õʼ»¯ */
/* eCPRI queue init */
(void)ecpri_que_init();
/* eCPRI CSU init */
ecpri_csu_init();
#ifdef TEST_ENABLE
fh_test_init();
#endif
UCP_PRINT_EMPTY("eCPRI mtimer&queue&CSU init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
}
ecs_hw_que_init(apeId);

366
public/ecs_rfm_spu0/driver/src/rfm0_mtimer.s.c
View File

@ -1,181 +1,187 @@
#include "rfm0_mtimer.h"
#include "typedef.h"
#include "phy_para.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "ucp_mtimer.h"
#include "mtimer_com.h"
//#ifdef DISTRIBUTED_BS
#include "rfm0_cpri_timer.h"
#include "rfm0_ecpri_timer.h"
//#endif
stPhyCellPara* pPhyCellPara = (stPhyCellPara*)PHY_CELL_ADDR;
extern stPhyScsPara* phyPara;
//extern uint32_t gScsId;
//extern uint32_t gMtimerId;
extern stSfnPara gCellSfnPara[2];
int32_t rfm0_mtimer_int_init(void)
{
if (PROTOCOL_ECPRI == get_protocol_sel())
{
set_cpri_timer_rfm0_int();
set_ecpri_timer_rfm0_int();
}
return 0;
}
#include "rfm0_mtimer.h"
#include "typedef.h"
#include "phy_para.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "ucp_mtimer.h"
#include "mtimer_com.h"
//#ifdef DISTRIBUTED_BS
#include "rfm0_cpri_timer.h"
#include "rfm0_ecpri_timer.h"
//#endif
#include "ecpri_irq.h"
stPhyCellPara* pPhyCellPara = (stPhyCellPara*)PHY_CELL_ADDR;
extern stPhyScsPara* phyPara;
//extern uint32_t gScsId;
//extern uint32_t gMtimerId;
extern stSfnPara gCellSfnPara[2];
int32_t rfm0_mtimer_int_init(void)
{
set_cpri_timer_rfm0_int();
set_ecpri_timer_rfm0_int();
return 0;
}
int32_t gRfm0CalFlag = 0;
int32_t gRfm0CalCnt = 0;
int32_t ecs_rfm0_cal_sfn(uint8_t nTmrId)
{
int32_t apeId = get_core_id();
int32_t scsId = 0;
int32_t i = 0;
if (1 == gCellSfnPara[nTmrId].ctcIntFlag)
{
for (i = 0; i < PHY_SCS_MAX_NUM; i++)
{
if (nTmrId == do_read_volatile_short(&(phyPara[i].mtimerId))) // 已建了第一个子载波小区
{
gCellSfnPara[nTmrId].scsId = i;
scsId = i;
break;
}
}
if (PHY_SCS_MAX_NUM == i)
{
return -1;
}
gCellSfnPara[nTmrId].ctcIntFlag = 0;
gCellSfnPara[nTmrId].slotPeriod = do_read_volatile_short(&(phyPara[scsId].slotPeriod)); // 500; //
gCellSfnPara[nTmrId].tddSlotNum = do_read_volatile_short(&(phyPara[scsId].slotNumOfTdd)); // 10; //
gCellSfnPara[nTmrId].slotMaxNum = do_read_volatile_short(&(phyPara[scsId].slotNumOfSfn)); // 20; //
gCellSfnPara[nTmrId].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));
gCellSfnPara[nTmrId].rxSfnNum = do_read_volatile(&(phyPara[scsId].rxSfnNum));
gCellSfnPara[nTmrId].txSlotNum = do_read_volatile(&(phyPara[scsId].txSlotNum));
gCellSfnPara[nTmrId].rxSlotNum = do_read_volatile(&(phyPara[scsId].rxSlotNum));
gCellSfnPara[nTmrId].txSymbolNum = 0;
gCellSfnPara[nTmrId].txSymbolIntCnt = 0;
gCellSfnPara[nTmrId].txSlotIntCnt = 0;
gCellSfnPara[nTmrId].rxSlotIntCnt = 0;
gRfm0CalFlag = 1;
gRfm0CalCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+544+apeId), gRfm0CalCnt); // 0x880
debug_write((DBG_DDR_IDX_DRV_BASE+556+apeId), GET_STC_CNT()); // 0x8b0
#endif
}
return 0;
}
uint32_t lastTxStcCnt = 0;
uint32_t nowTxStcCnt = 0;
uint32_t rfm0SymbolErrCnt = 0;
uint32_t rfm0SymbolInterMax = 0;
int32_t mtimer_rfm0_symbol_callback(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = 0;
if (MTIMER_CPRI_ID == nTmrId)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
}
else
{
return -1;
}
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
uint32_t tEventAddr = 0;
uint32_t tFlagAddr = 0;
stSfnPara* pSfnPara = &gCellSfnPara[nTmrId];
int32_t apeId = get_core_id();
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG);
if ((tmrIntcFlag & (1 << MTMR_INT_RFM0_SLOT))) /* symbol int */
{
tFlagAddr = tmrBaseAddr + MTMR_TINTF00_REG + 6*(MTMR_INT_RFM0_SLOT<<2) + 2*((MTMR_ECPRI_TX_SYMBOL0>>5)<<2); // MTMR_TINTF01_REG
tEventAddr = tmrBaseAddr+MTMR_TEVENT0_REG + ((MTMR_ECPRI_TX_SYMBOL0>>5)<<2);
tEventFlag = do_read_volatile(tFlagAddr);
if (tEventFlag & 0x3FFF) // 14symbols // tx symbol offset int
{
do_write(tEventAddr, tEventFlag);
do_write(tFlagAddr, tEventFlag); // clear int flag
pSfnPara->txSymbolIntCnt++;
//uint32_t addr = 0;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+2048+32+nTmrId), pSfnPara->txSymbolIntCnt); // 0xb7e08080
#endif
ecs_rfm0_cal_sfn(nTmrId);
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* eCPRI symbol interrupt handle */
(void)ecpri_sym_irq_handle(pSfnPara->txSlotNum, pSfnPara->txSymbolNum);
}
pSfnPara->txSymbolNum++;
__ucps2_synch(0);
if (pSfnPara->txSymbolNum == SLOT_SYMBOL_NUM)
{
pSfnPara->txSlotNum++;
if (pSfnPara->txSlotNum == pSfnPara->slotMaxNum)
{
pSfnPara->txSfnNum++;
pSfnPara->txSfnNum &= 0x3FF;
pSfnPara->txSlotNum = 0;
}
pSfnPara->txSymbolNum = 0;
}
__ucps2_synch(0);
if (MTIMER_CPRI_ID == nTmrId)
{
do_write(SLOT_NUM_DEBUG_ADDR+(((apeId-1)<<2)<<2), pSfnPara->txSymbolNum);
do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2), pSfnPara->txSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((1+(apeId<<2))<<2), pSfnPara->txSlotNum);
do_write(SLOT_NUM_DEBUG_ADDR+((2+(apeId<<2))<<2), pSfnPara->rxSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((3+(apeId<<2))<<2), pSfnPara->rxSlotNum);
}
#if 1
nowTxStcCnt = GET_STC_CNT();
debug_write(((DBG_DDR_IDX_DRV_BASE+2048+128) + (gCellSfnPara[nTmrId].txSymbolIntCnt&0x3F)), nowTxStcCnt); // 0xb7e08200
//debug_write(((DBG_DDR_IDX_DRV_BASE+2048+192) + (gCellSfnPara[nTmrId].txSymbolIntCnt&0x3F)), get_tx_nr_slot(NR_SCS_30K)); // 0x800
if ((nowTxStcCnt > lastTxStcCnt) && (2 < gCellSfnPara[nTmrId].txSlotIntCnt))
{
uint32_t cost = nowTxStcCnt - lastTxStcCnt;
//debug_write(((DBG_DDR_IDX_DRV_BASE+576) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), nowTxStcCnt); // 0x900
//debug_write(((DBG_DDR_IDX_DRV_BASE+640) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), cost); // 0xa00
if (((gCellSfnPara[nTmrId].slotPeriod*1000+5000) < cost) || ((gCellSfnPara[nTmrId].slotPeriod*1000-5000) > cost))
{
rfm0SymbolErrCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+64+(nTmrId<<2)), rfm0SymbolErrCnt); // 0xb7e08100
}
if (rfm0SymbolInterMax < cost)
{
rfm0SymbolInterMax = cost;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+65+(nTmrId<<2)), rfm0SymbolInterMax); // 0xb7e08104
}
}
lastTxStcCnt = nowTxStcCnt;
#endif
tEventFlag = do_read_volatile(tFlagAddr);
}
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_RFM0_SLOT)); // clear int
}
return 0;
}
int32_t gRfm0CalFlag = 0;
int32_t gRfm0CalCnt = 0;
int32_t ecs_rfm0_cal_sfn(uint8_t nTmrId)
{
int32_t apeId = get_core_id();
int32_t scsId = 0;
int32_t i = 0;
if (1 == gCellSfnPara[nTmrId].ctcIntFlag)
{
for (i = 0; i < PHY_SCS_MAX_NUM; i++)
{
if (nTmrId == do_read_volatile_short(&(phyPara[i].mtimerId))) // 已建了第一个子载波小区
{
gCellSfnPara[nTmrId].scsId = i;
scsId = i;
break;
}
}
if (PHY_SCS_MAX_NUM == i)
{
return -1;
}
gCellSfnPara[nTmrId].ctcIntFlag = 0;
gCellSfnPara[nTmrId].slotPeriod = do_read_volatile_short(&(phyPara[scsId].slotPeriod)); // 500; //
gCellSfnPara[nTmrId].tddSlotNum = do_read_volatile_short(&(phyPara[scsId].slotNumOfTdd)); // 10; //
gCellSfnPara[nTmrId].slotMaxNum = do_read_volatile_short(&(phyPara[scsId].slotNumOfSfn)); // 20; //
gCellSfnPara[nTmrId].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));
gCellSfnPara[nTmrId].rxSfnNum = do_read_volatile(&(phyPara[scsId].rxSfnNum));
gCellSfnPara[nTmrId].txSlotNum = do_read_volatile(&(phyPara[scsId].txSlotNum));
gCellSfnPara[nTmrId].rxSlotNum = do_read_volatile(&(phyPara[scsId].rxSlotNum));
gCellSfnPara[nTmrId].txSymbolNum = 0;
gCellSfnPara[nTmrId].txSymbolIntCnt = 0;
gCellSfnPara[nTmrId].txSlotIntCnt = 0;
gCellSfnPara[nTmrId].rxSlotIntCnt = 0;
gRfm0CalFlag = 1;
gRfm0CalCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+544+apeId), gRfm0CalCnt); // 0x880
debug_write((DBG_DDR_IDX_DRV_BASE+556+apeId), GET_STC_CNT()); // 0x8b0
#endif
}
return 0;
}
uint32_t lastTxStcCnt = 0;
uint32_t nowTxStcCnt = 0;
uint32_t rfm0SymbolErrCnt = 0;
uint32_t rfm0SymbolInterMax = 0;
int32_t mtimer_rfm0_symbol_callback(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = 0;
if (MTIMER_CPRI_ID == nTmrId)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
}
else
{
return -1;
}
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
uint32_t tEventAddr = 0;
uint32_t tFlagAddr = 0;
stSfnPara* pSfnPara = &gCellSfnPara[nTmrId];
int32_t apeId = get_core_id();
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG);
if ((tmrIntcFlag & (1 << MTMR_INT_RFM0_SLOT))) /* symbol int */
{
tFlagAddr = tmrBaseAddr + MTMR_TINTF00_REG + 6*(MTMR_INT_RFM0_SLOT<<2) + 2*((MTMR_ECPRI_TX_SYMBOL0>>5)<<2); // MTMR_TINTF01_REG
tEventAddr = tmrBaseAddr+MTMR_TEVENT0_REG + ((MTMR_ECPRI_TX_SYMBOL0>>5)<<2);
tEventFlag = do_read_volatile(tFlagAddr);
if (tEventFlag & 0x3FFF) // 14symbols // tx symbol offset int
{
do_write(tEventAddr, tEventFlag);
do_write(tFlagAddr, tEventFlag); // clear int flag
pSfnPara->txSymbolIntCnt++;
//uint32_t addr = 0;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+2048+32+nTmrId), pSfnPara->txSymbolIntCnt); // 0xb7e08080
#endif
ecs_rfm0_cal_sfn(nTmrId);
pSfnPara->txSymbolNum++;
__ucps2_synch(0);
if (pSfnPara->txSymbolNum == SLOT_SYMBOL_NUM)
{
pSfnPara->txSlotNum++;
if (pSfnPara->txSlotNum == pSfnPara->slotMaxNum)
{
pSfnPara->txSfnNum++;
pSfnPara->txSfnNum &= 0x3FF;
pSfnPara->txSlotNum = 0;
}
pSfnPara->txSymbolNum = 0;
}
__ucps2_synch(0);
if (MTIMER_CPRI_ID == nTmrId)
{
do_write(SLOT_NUM_DEBUG_ADDR+(((apeId-1)<<2)<<2), pSfnPara->txSymbolNum);
do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2), pSfnPara->txSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((1+(apeId<<2))<<2), pSfnPara->txSlotNum);
do_write(SLOT_NUM_DEBUG_ADDR+((2+(apeId<<2))<<2), pSfnPara->rxSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((3+(apeId<<2))<<2), pSfnPara->rxSlotNum);
}
#if 1
nowTxStcCnt = GET_STC_CNT();
debug_write(((DBG_DDR_IDX_DRV_BASE+2048+128) + (gCellSfnPara[nTmrId].txSymbolIntCnt&0x3F)), nowTxStcCnt); // 0xb7e08200
//debug_write(((DBG_DDR_IDX_DRV_BASE+2048+192) + (gCellSfnPara[nTmrId].txSymbolIntCnt&0x3F)), get_tx_nr_slot(NR_SCS_30K)); // 0x800
if ((nowTxStcCnt > lastTxStcCnt) && (2 < gCellSfnPara[nTmrId].txSlotIntCnt))
{
uint32_t cost = nowTxStcCnt - lastTxStcCnt;
//debug_write(((DBG_DDR_IDX_DRV_BASE+576) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), nowTxStcCnt); // 0x900
//debug_write(((DBG_DDR_IDX_DRV_BASE+640) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), cost); // 0xa00
if (((gCellSfnPara[nTmrId].slotPeriod*1000+5000) < cost) || ((gCellSfnPara[nTmrId].slotPeriod*1000-5000) > cost))
{
rfm0SymbolErrCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+64+(nTmrId<<2)), rfm0SymbolErrCnt); // 0xb7e08100
}
if (rfm0SymbolInterMax < cost)
{
rfm0SymbolInterMax = cost;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+65+(nTmrId<<2)), rfm0SymbolInterMax); // 0xb7e08104
}
}
lastTxStcCnt = nowTxStcCnt;
#endif
tEventFlag = do_read_volatile(tFlagAddr);
}
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_RFM0_SLOT)); // clear int
}
return 0;
}

142
public/ecs_rfm_spu0/top/src/main.s.c
View File

@ -1,71 +1,71 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : main.c
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "ucp_printf.h"
#include "ecs_rfm_spu0_top.h"
#include "msg_transfer_queue.h"
#include "log_client.h"
#include "ucp_utility.h"
#include "spu_shell.h"
#include "hwque.h"
#include "phy_para.h"
#include "ecpri_queue_proc.h"
#include "ecpri_csu.h"
#include "lib_debug_init.h"
#include "ucp_heartbeat.h"
int32_t main(int32_t argc, char* argv[])
{
int32_t core_id = 0;
int32_t ret = 0;
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU0,coreId[0x%x]", get_core_id());
core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
ret = spu_lib_debug_init(core_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
spu_log_client_init();
ecs_rfm_spu0_drv_init();
ecs_rfm_spu0_msg_transfer_init();
spu_shell_init();
while (1)
{
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* eCPRI循环队列轮询处理 */
ecpri_queue_proc();
/* 手动触发eCPRI CSU发送数据测试 */
if (1 == do_read_volatile(ECPRI_DBG_BUF_ADDR + 0x0C))
{
ecpri_csu_send_test();
do_write(ECPRI_DBG_BUF_ADDR + 0x0C, 0x00);
}
}
/* update heartbeat count */
heart_beat_write();
}
return 0;
}
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : main.c
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "ucp_printf.h"
#include "ecs_rfm_spu0_top.h"
#include "msg_transfer_queue.h"
#include "log_client.h"
#include "ucp_utility.h"
#include "spu_shell.h"
//#include "hwque.h"
#include "phy_para.h"
#include "ecpri_que.h"
#include "ecpri_csu.h"
#include "lib_debug_init.h"
#include "ucp_heartbeat.h"
#ifdef TEST_ENABLE
#include "fh_test.h"
#endif
int32_t main(int32_t argc, char* argv[])
{
int32_t core_id = 0;
int32_t ret = 0;
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU0,coreId[0x%x]", get_core_id());
core_id = get_core_id();
debug_write(DBG_DDR_COMMON_IDX(core_id, 0), PLATFORM_BUILD_DATA);
ret = spu_lib_debug_init(core_id);
debug_write(DBG_DDR_COMMON_IDX(core_id, 1), ret);
spu_log_client_init();
ecs_rfm_spu0_drv_init();
ecs_rfm_spu0_msg_transfer_init();
spu_shell_init();
while (1)
{
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* eCPRI queue polling */
(void)ecpri_que_polling();
}
#ifdef TEST_ENABLE
check_test_outcome(0);
#endif
/* update heartbeat count */
heart_beat_write();
}
return 0;
}

28
public/ecs_rfm_spu1/driver/inc/ecpri_driver.h
View File

@ -15,32 +15,32 @@
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ucp_js_subcrg.h"
#include "ucp_param.h"
#include "ecpri_comm.h"
#include "ecpri_pma.h"
#include "ecpri_roec.h"
#include "ecpri_switch.h"
#include "ecpri_timer.h"
#include "hw_cpri.h"
#include "phy_para.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
void ecpri_init(uint8_t nOption);
void ecpri_cprimode_init();
extern void ecpri_init_ex(uint32_t ecpri_speed_sel);
/* eCPRI init */
void ecpri_init(uint32_t ecpri_option);
/* CPRI mode of eCPRI init */
void ecpri_cprimode_init(void);
/* eCPRI clock init */
void ecpri_clk_init(uint32_t ecpri_option);
/* eCPRI IP init */
void ecpri_ip_init(uint32_t ecpri_option);
/* eCPRI antenna config */
int32_t ecpri_ant_cfg(uint8_t ant_id, uint8_t slot_type, uint8_t sym_id, uint32_t pkt_addr, uint16_t pkt_len);
#endif /* _ECPRI_DRIVER_H_ */

27
public/ecs_rfm_spu1/driver/inc/ecpri_pma.h
View File

@ -18,17 +18,11 @@
#include "ucp_js_ctrl.h"
#include "ucp_utility.h"
#include "ucp_drv_common.h"
#include "phy_para.h"
#include "ecpri_comm.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
@ -37,13 +31,16 @@
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
extern DDR0 uint32_t pma_fw[16384*2];
/* eCPRI ROEC init */
extern void ecpri_pcs_rst_ctrl_ex(void);
extern void init_ecpri_pma_rst_ex(void);
extern void init_pma_commonconfig_ex(uint32_t ecpri_speed_sel);
extern void init_jecspma(uint32_t ecpri_speed_sel);
extern void init_jecspma_rxtx(void);
extern void ecpri_pma_rx_adapt(void);
/* eCPRI PMA reset */
void ecpri_pma_rst(void);
/* eCPRI PMA common config */
void ecpri_pma_cfg(uint32_t ecpri_option);
/* eCPRI PMA init */
void ecpri_pma_init(uint32_t ecpri_option);
/* eCPRI PMA RX/TX init */
void ecpri_pma_rxtx_init(void);
/* eCPRI PMA RX adapt */
void ecpri_pma_rx_adapt(void);
#endif /* _ECPRI_PMA_H_ */

32
public/ecs_rfm_spu1/driver/inc/ecpri_roec.h
View File

@ -16,34 +16,30 @@
#include "ucp_ecpri.h"
#include "ucp_param.h"
#include "ucp_utility.h"
#include "ecpri_comm.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* eCPRI buffer physical address */
#define ECPRI_BUF_PHY_ADDR 0xAEE00000
/* eCPRI buffer length */
#define ECPRI_BUF_LEN 0x04000000
/* 502 verify case define data */
#define OTHER_DES_ADDR 0xAEE00000ul // 0xAEE00000ul // 0x09d00000ul
#define OTHER_DES_SIZE 0x03E00000ul // 0x03F00000ul // 0x00100000ul
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* eCPRI descriptor shift enumeration */
typedef enum EcpriDescShift
{
E_DESC_SHIFT_128B = 0, /* 96Byte + 32Byte(descriptor) */
E_DESC_SHIFT_256B, /* 224Byte + 32Byte(descriptor) */
E_DESC_SHIFT_512B, /* 480Byte + 32Byte(descriptor) */
E_DESC_SHIFT_1KB, /* 992Byte + 32Byte(descriptor) */
E_DESC_SHIFT_2KB, /* 2016Byte + 32Byte(descriptor) */
E_DESC_SHIFT_4KB, /* 4064Byte + 32Byte(descriptor) */
E_DESC_SHIFT_8KB, /* 8160Byte + 32Byte(descriptor) */
E_DESC_SHIFT_16KB /* 16352Byte + 32Byte(descriptor) */
} EcpriDescShift_e;
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI ROEC init */
extern void ecpri_roec_init(void);
void ecpri_roec_init(void);
#endif /* _ECPRI_ROEC_H_ */

119
public/ecs_rfm_spu1/driver/inc/ecpri_switch.h
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@ -14,32 +14,127 @@
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include <stdbool.h>
#include "ucp_js_subcrg.h"
#include "ucp_ecpri.h"
#include "ucp_param.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "ecpri_comm.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
/* eCPRI MAC statistic consecutive register number 1 */
#define ECPRI_MAC_STATS_CONSEC_REG_NUM1 12
/* eCPRI MAC statistic consecutive register number 2 */
#define ECPRI_MAC_STATS_CONSEC_REG_NUM2 3
/* eCPRI MAC statistic consecutive register number 3 */
#define ECPRI_MAC_STATS_CONSEC_REG_NUM3 2
#ifndef ERROR
#define ERROR (-1)
#endif
/* eCPRI SWITCH port number */
#define ECPRI_SWITCH_PORT_NUM 3
/* eCPRI SWITCH port ID 0 */
#define ECPRI_SWITCH_PORT0 0
/* eCPRI SWITCH port ID 1 */
#define ECPRI_SWITCH_PORT1 1
/* eCPRI SWITCH port ID 2 */
#define ECPRI_SWITCH_PORT2 2
/* eCPRI SWITCH statistic consecutive register number 1 */
#define ECPRI_SWITCH_STATS_CONSEC_REG_NUM1 3
/* eCPRI SWITCH statistic consecutive register number 2 */
#define ECPRI_SWITCH_STATS_CONSEC_REG_NUM2 12
/* eCPRI SWITCH statistic consecutive register number 3 */
#define ECPRI_SWITCH_STATS_CONSEC_REG_NUM3 4
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* eCPRI MAC statistic structure */
typedef struct EcpriMacStats
{
uint32_t rx_pkts_64b; /* receive 64Bytes packets */
uint32_t rx_pkts_65b_127b; /* receive 65~127Bytes packets */
uint32_t rx_pkts_128b_255b; /* receive 128~255Bytes packets */
uint32_t rx_pkts_256b_511b; /* receive 256~511Bytes packets */
uint32_t rx_pkts_512b_1023b; /* receive 512~1023Bytes packets */
uint32_t rx_pkts_1024b_1518b; /* receive 1024~1518Bytes packets */
uint32_t rx_pkts_1519b_max; /* receive 1519~maxBytes packets */
uint32_t rx_pkts_under_64b; /* receive under 64Bytes packets */
uint32_t rx_pkts_over_max; /* receive over maxBytes packets */
uint32_t rx_pkts_total; /* receive total packets */
uint32_t rx_bytes_total_lsb; /* receive total bytes LSB */
uint32_t rx_bytes_total_msb; /* receive total bytes MSB */
uint32_t rx_pkts_crc_err; /* receive CRC error packets */
uint32_t rx_pkts_uc; /* receive unicast packets */
uint32_t rx_pkts_mc; /* receive multicast packets */
uint32_t rx_pkts_bc; /* receive broadcast packets */
uint32_t rx_pkts_discard; /* receive discard packets */
uint32_t rx_pkts_overflow; /* receive overflow packets */
uint32_t tx_pkts_64b; /* send 64Bytes packets */
uint32_t tx_pkts_65b_127b; /* send 65~127Bytes packets */
uint32_t tx_pkts_128b_255b; /* send 128~255Bytes packets */
uint32_t tx_pkts_256b_511b; /* send 256~511Bytes packets */
uint32_t tx_pkts_512b_1023b; /* send 512~1023Bytes packets */
uint32_t tx_pkts_1024b_1518b; /* send 1024~1518Bytes packets */
uint32_t tx_pkts_1519b_max; /* send 1519~maxBytes packets */
uint32_t tx_pkts_under_64b; /* send under 64Bytes packets */
uint32_t tx_pkts_over_max; /* send over maxBytes packets */
uint32_t tx_pkts_total; /* send total packets */
uint32_t tx_bytes_total_lsb; /* send total bytes LSB */
uint32_t tx_bytes_total_msb; /* send total bytes MSB */
} EcpriMacStats_t;
/* eCPRI SWITCH statistic structure */
typedef struct EcpriSwitchStats
{
uint32_t rx_pkts_fltr; /* receive filtered packets */
uint32_t rx_bytes_fltr; /* receive filtered bytes */
uint32_t tx_pkts_drop; /* send filtered packets */
uint32_t rx_pkts_voq_nq; /* receive enqueued packets */
uint32_t tx_pkts_voq_dq; /* send dequeued packets */
uint32_t rx_pkts_voq_drop; /* receive dropped packets */
uint32_t rx_bytes_voq_nq; /* receive enqueued bytes */
uint32_t tx_bytes_voq_dq; /* send dequeued bytes */
uint32_t rx_bytes_voq_drop; /* receive dropped bytes */
uint32_t rx_pkts_uc; /* receive unicast packets */
uint32_t tx_pkts_uc; /* send unicast packets */
uint32_t rx_bytes_uc; /* receive unicast bytes */
uint32_t tx_bytes_uc; /* send unicast bytes */
uint32_t rx_pkts_mc; /* receive multicast packets */
uint32_t tx_pkts_mc; /* send multicast packets */
uint32_t rx_bytes_mc; /* receive multicast bytes */
uint32_t tx_bytes_mc; /* send multicast bytes */
uint32_t rx_pkts_bc; /* receive broadcast packets */
uint32_t tx_pkts_bc; /* send broadcast packets */
uint32_t rx_bytes_bc; /* receive broadcast bytes */
uint32_t tx_bytes_bc; /* send broadcast bytes */
uint32_t rx_pkts_buf_ovfl; /* receive buffer-overflow dropped packets */
uint32_t rx_bytes_buf_ovfl; /* receive buffer-overflow dropped bytes */
uint32_t rx_pkts_err; /* receive error dropped packets */
uint32_t rx_bytes_err; /* receive error dropped bytes */
} EcpriSwitchStats_t;
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI ROEC init */
extern void ecpri_pcs_init(uint32_t ecpri_speed_sel);
extern void ecpri_mac_init(uint32_t ecpri_speed_sel);
extern void ecpri_switch_init(uint32_t ecpri_speed_sel);
/* eCPRI PCS reset */
void ecpri_pcs_rst(void);
/* eCPRI PCS init */
void ecpri_pcs_init(uint32_t ecpri_option);
/* eCPRI MAC init */
void ecpri_mac_init(void);
/* eCPRI SWITCH init */
void ecpri_switch_init(void);
/* eCPRI PCS link status get */
extern bool ecpri_pcs_link_status_get(void);
bool ecpri_pcs_link_status_get(void);
/* eCPRI MAC statistic start */
void ecpri_mac_stats_start(void);
/* eCPRI MAC statistic stop */
void ecpri_mac_stats_stop(void);
/* eCPRI MAC statistic clear */
void ecpri_mac_stats_clear(void);
/* eCPRI MAC statistic get */
int32_t ecpri_mac_stats_get(EcpriMacStats_t *ecpri_mac_stats_ptr);
/* eCPRI SWITCH statistic get */
int32_t ecpri_switch_stats_get(uint8_t port, EcpriSwitchStats_t *ecpri_switch_stats_ptr);
#endif /* _ECPRI_SWITCH_H_ */

339
public/ecs_rfm_spu1/driver/src/ecpri_driver.s.c
View File

@ -11,122 +11,269 @@
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_driver.h"
#include "hw_cpri.h"
#include "ecpri_timer.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: vnet_send_packet
* Description: vnet send packet
* Function: ecpri_init
* Description: eCPRI init
* Input:
* <name> <type> <desc>
* skb sk_buff * socket buffer
* dev net_device * network device
* <name> <type> <desc>
* ecpri_option uint32_t eCPRI option
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_init(uint32_t ecpri_option)
{
#ifdef PALLADIUM_TEST
uint32_t flag = 1;
debug_write(ECPRI_DBG_IDX1(0), flag); /* ECS_RFM1: 0xB7E31000(0) */
#endif
/* input para check */
if ((ECPRI_OPTION_10G != ecpri_option) && (ECPRI_OPTION_25G != ecpri_option))
{
return;
}
phy_para_init(PROTOCOL_ECPRI, ecpri_option);
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(0), flag); /* ECS_RFM1: 0xB7E31000(0) */
#endif
ecpri_ip_init(ecpri_option);
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(0), flag); /* ECS_RFM1: 0xB7E31000(0) */
#endif
cpri_ecprimode_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(0), flag); /* ECS_RFM1: 0xB7E31000(0) */
#endif
ecpri_mtimer_init(LTE_SCS_ID, 10);
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(0), flag); /* ECS_RFM1: 0xB7E31000(0) */
#endif
}
/**********************************************************************************************************************
* Function: ecpri_cprimode_init
* Description: CPRI mode of eCPRI init
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_cprimode_init(void)
{
// 扩皮模式下，ecpri timer使用cpri_div33_tx_clk，与cpri core clk同源
ecpri_timer_cprimode_clk_init();
ecpri_mtimer_init(LTE_SCS_ID, 10);
}
/**********************************************************************************************************************
* Function: ecpri_clk_init
* Description: eCPRI clock init
* Input:
* <name> <type> <desc>
* ecpri_option uint32_t eCPRI option
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_clk_init(uint32_t ecpri_option)
{
switch (ecpri_option)
{
case (ECPRI_OPTION_10G):
do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT31 + BIT19 + BIT18 + BIT17 + BIT16 + BIT11 + BIT5));
do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2 apb_aclk_i
//switch_core_clk_i,
//switch_sch_clk_i,
do_write(&JECS_CRG_CLK_CTRL7, 0x520000); //jecs_pma_tx0_ropll_div33_clk
//ecpri_switch_mae_core_clk
do_write(&JECS_CRG_CLK_CTRL8, 0x520000); //jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_tx_clk
do_write(&JECS_CRG_CLK_CTRL9, 0x521000); //jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_rx_clk
do_write(&JECS_CRG_CLK_CTRL0, 0x521000); //jecs_pma_rx0_div33_clk
do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
break;
case (ECPRI_OPTION_25G):
do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT19 + BIT18 + BIT17 + BIT16 + BIT11 + BIT5));
do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2 apb_aclk_i
//switch_core_clk_i,
//switch_sch_clk_i,
do_write(&JECS_CRG_CLK_CTRL7, 0x521000); //jecs_pma_tx0_ropll_div33_clk
//ecpri_switch_mae_core_clk
do_write(&JECS_CRG_CLK_CTRL8, 0x521000); //jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_tx_clk
do_write(&JECS_CRG_CLK_CTRL9, 0x521000); //jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_rx_clk
do_write(&JECS_CRG_CLK_CTRL0, 0x521000); //jecs_pma_rx0_div33_clk
do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
break;
default:
break;
}
}
/**********************************************************************************************************************
* Function: ecpri_ip_init
* Description: eCPRI IP init
* Input:
* <name> <type> <desc>
* ecpri_option uint32_t eCPRI option
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_ip_init(uint32_t ecpri_option)
{
#ifdef PALLADIUM_TEST
uint32_t flag = 1;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_clk_init(ecpri_option);
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_pma_rst();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_pma_init(ecpri_option);
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_pma_rxtx_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_pcs_rst();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_roec_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_pcs_init(ecpri_option);
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_mac_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_switch_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
ecpri_pma_rx_adapt();
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
do_write(SERDES_INIT_FLAG_ADDR, 1);
#ifdef PALLADIUM_TEST
flag++;
debug_write(ECPRI_DBG_IDX1(1), flag); /* ECS_RFM1: 0xB7E31004(1) */
#endif
}
/**********************************************************************************************************************
* Function: ecpri_ant_cfg
* Description: eCPRI antenna config
* Input:
* <name> <type> <desc>
* ant_id uint8_t antenna index
* slot_type uint8_t slot type
* sym_id uint8_t symbol index
* pkt_addr uint32_t packet address
* pkt_len uint16_t packet length
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void ecpri_init(uint8_t nOption)
{
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
phy_para_init(PROTOCOL_ECPRI, nOption);
ecpri_init_ex(nOption); // (10);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
cpri_ecprimode_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
ecpri_mtimer_init(LTE_SCS_ID, 10);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
}
void ecpri_cprimode_init()
{
// 扩皮模式下，ecpri timer使用cpri_div33_tx_clk，与cpri core clk同源
ecpri_timer_cprimode_clk_init();
ecpri_mtimer_init(LTE_SCS_ID, 10);
}
void ecpri_clk_init(uint32_t ecpri_speed_sel)
int32_t ecpri_ant_cfg(uint8_t ant_id, uint8_t slot_type, uint8_t sym_id, uint32_t pkt_addr, uint16_t pkt_len)
{
if (ecpri_speed_sel == 10) //10G
/* config index */
uint32_t cfg_id = 0;
/* input para check */
if ((ECPRI_ANT_NUM <= ant_id) || (ECPRI_SLOT_TYPE <= slot_type) || (ECPRI_SYM_NUM <= sym_id))
{
do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT11+BIT5+BIT31+BIT16+BIT17+BIT18+BIT19));
do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2 apb_aclk_i
//switch_core_clk_i,
//switch_sch_clk_i,
do_write(&JECS_CRG_CLK_CTRL7, 0x520000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_switch_mae_core_clk
do_write(&JECS_CRG_CLK_CTRL8, 0x520000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_tx_clk
do_write(&JECS_CRG_CLK_CTRL9, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_rx_clk
do_write(&JECS_CRG_CLK_CTRL0, 0x521000);//jecs_pma_rx0_div33_clk
do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
debug_write(ECPRI_DBG_IDX1(20), (uint32_t)ERROR); /* ECS_RFM1: 0xB7E31050(20) */
debug_write(ECPRI_DBG_IDX1(21), ant_id); /* ECS_RFM1: 0xB7E31054(21) */
debug_write(ECPRI_DBG_IDX1(22), slot_type); /* ECS_RFM1: 0xB7E31058(22) */
debug_write(ECPRI_DBG_IDX1(23), sym_id); /* ECS_RFM1: 0xB7E3105C(23) */
return ERROR;
}
else if (ecpri_speed_sel == 25) //25G
/* input para check */
if ((0 == pkt_addr) || (0 == pkt_len))
{
do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT11+BIT5+BIT16+BIT17+BIT18+BIT19));
do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2 apb_aclk_i
//switch_core_clk_i,
//switch_sch_clk_i,
do_write(&JECS_CRG_CLK_CTRL7, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_switch_mae_core_clk
do_write(&JECS_CRG_CLK_CTRL8, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_tx_clk
do_write(&JECS_CRG_CLK_CTRL9, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_rx_clk
do_write(&JECS_CRG_CLK_CTRL0, 0x521000);//jecs_pma_rx0_div33_clk
do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
debug_write(ECPRI_DBG_IDX1(20), (uint32_t)ERROR); /* ECS_RFM1: 0xB7E31050(20) */
debug_write(ECPRI_DBG_IDX1(24), pkt_addr); /* ECS_RFM1: 0xB7E31060(24) */
debug_write(ECPRI_DBG_IDX1(25), pkt_len); /* ECS_RFM1: 0xB7E31064(25) */
return ERROR;
}
}
void ecpri_init_ex(uint32_t ecpri_speed_sel)
{
ecpri_clk_init(10);
/* config index */
cfg_id = ant_id * ECPRI_SLOT_TYPE * ECPRI_SYM_NUM + slot_type * ECPRI_SYM_NUM + sym_id;
ecpri_pcs_rst_ctrl_ex();
/* config packet address */
do_write((void *)(ECPRI_ANT_BUF_ADDR + cfg_id * ECPRI_SYM_INFO_LEN), pkt_addr);
init_ecpri_pma_rst_ex();
/* config packet length */
do_write((void *)(ECPRI_ANT_BUF_ADDR + cfg_id * ECPRI_SYM_INFO_LEN + sizeof(uint32_t)), pkt_len);
init_jecspma(10);
debug_write(ECPRI_DBG_IDX1(20), (uint32_t)SUCCESS); /* ECS_RFM1: 0xB7E31050(20) */
debug_write(ECPRI_DBG_IDX1(21), ant_id); /* ECS_RFM1: 0xB7E31054(21) */
debug_write(ECPRI_DBG_IDX1(22), slot_type); /* ECS_RFM1: 0xB7E31058(22) */
debug_write(ECPRI_DBG_IDX1(23), sym_id); /* ECS_RFM1: 0xB7E3105C(23) */
debug_write(ECPRI_DBG_IDX1(24), pkt_addr); /* ECS_RFM1: 0xB7E31060(24) */
debug_write(ECPRI_DBG_IDX1(25), pkt_len); /* ECS_RFM1: 0xB7E31064(25) */
init_jecspma_rxtx();
ecpri_roec_init();
ecpri_pcs_init(10);
ecpri_mac_init(10);
ecpri_switch_init(10);
ecpri_pma_rx_adapt();
/* waiting for eCPRI PCS to link up */
while (!ecpri_pcs_link_status_get());
do_write(SERDES_INIT_FLAG_ADDR, 1);
return SUCCESS;
}

1090
public/ecs_rfm_spu1/driver/src/ecpri_pma.s.c
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File diff suppressed because it is too large Load Diff

34
public/ecs_rfm_spu1/driver/src/ecpri_roec.s.c
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@ -20,26 +20,34 @@
/**********************************************************************************************************************
* Function: ecpri_roec_init
* Description: eCPRI ROEC init
* Input:
* <name> <type> <desc>
* dev net_device * network device
* data uint8_t * data received
* len uint32_t data length
* Input: none
* Output: none
* Return: operation result - success or failure.
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_roec_init(void)
{
do_write(&ROEC_ENABLE, BIT0);
/* eCPRI buffer clear */
memset_ucp((void *)ECPRI_BUF_ADDR, 0x00, ECPRI_BUF_SIZE);
//配置收到包写入DDR里面
/* config address range for descriptor */
do_write(&DESC_BEGIN_ADDR_2, ECPRI_RX_BUF_ADDR / ECPRI_DESC_ADDR_UNIT);
do_write(&DESC_END_ADDR_2, (ECPRI_RX_BUF_ADDR + ECPRI_RX_BUF_SIZE) / ECPRI_DESC_ADDR_UNIT);
/* config next valid address for descriptor */
do_write(&DESC_TAIL_ADDR_2, (ECPRI_RX_BUF_ADDR + ECPRI_RX_BUF_SIZE) / ECPRI_DESC_ADDR_UNIT);
/* config descriptor shift */
do_write(&DESC_SHIFT_2, (uint32_t)E_DESC_SHIFT_16KB);
/* config pointer update interval for descriptor */
do_write(&DESC_PTR_CNT_2, 4);
do_write(&DESC_BEGIN_ADDR_2, (OTHER_DES_ADDR / 32));
do_write(&DESC_END_ADDR_2, (OTHER_DES_ADDR / 32 + OTHER_DES_SIZE / 32));
do_write(&DESC_SHIFT_2, 7);//16k
do_write(&DESC_TAIL_ADDR_2, (OTHER_DES_ADDR / 32) + OTHER_DES_SIZE / 32);
do_write(&DESC_START_2, 1);
/* descriptor work start */
do_write(&DESC_START_2, BIT0);
/* roe_ctrl module enable */
do_write(&ROEC_ENABLE, BIT0);
}

343
public/ecs_rfm_spu1/driver/src/ecpri_switch.s.c
View File

@ -17,125 +17,165 @@
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: ecpri_pcs_rst
* Description: eCPRI PCS reset
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_pcs_rst(void)
{
/* cancel eCPRI's reset */
do_write(&JECS_CRG_MANTICORE0_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE0_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE1_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE1_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE2_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE2_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE3_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE3_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE4_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE4_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE5_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE5_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE6_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE6_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE7_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE7_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE8_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE8_RST_CTRL) | BIT24);
do_write(&ECPRI_RST_CFG_REG, do_read_volatile(&ECPRI_RST_CFG_REG) | BIT24);
}
/**********************************************************************************************************************
* Function: ecpri_pcs_init
* Description: eCPRI PCS init
* Input:
* <name> <type> <desc>
* skb sk_buff * socket buffer
* dev net_device * network device
* <name> <type> <desc>
* skb sk_buff * socket buffer
* dev net_device * network device
* Output: none
* Return: operation result - success or failure.
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_pcs_init(uint32_t ecpri_speed_sel)
void ecpri_pcs_init(uint32_t ecpri_option)
{
if (ecpri_speed_sel == 10) //10G
switch (ecpri_option)
{
do_write(&MC_PCS_CONTROL_1, BIT13+BIT6+(0<<2));//0 0 0 0 = 10Gbps
do_write(&MC_PCS_CONTROL_2, 0);//0 0 0 0 = select 10GBASE-R PCS type
do_write(&MC_CFG_TX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_CFG_RX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_GENERAL_TX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_RX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_TX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
do_write(&MC_GENERAL_RX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
}
else if (ecpri_speed_sel == 25) //25G
{
do_write(&MC_PCS_CONTROL_1, BIT13+BIT6+(5<<2));//0 1 0 1 = 25Gbps
do_write(&MC_PCS_CONTROL_2, 0);//0 0 0 0 = select 10GBASE-R PCS type
do_write(&MC_CFG_TX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_CFG_RX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_GENERAL_TX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_RX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_TX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
do_write(&MC_GENERAL_RX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
case ECPRI_OPTION_10G:
do_write(&MC_PCS_CONTROL_1, BIT13 + BIT6 + (0 << 2)); //0 0 0 0 = 10Gbps
do_write(&MC_PCS_CONTROL_2, 0); //0 0 0 0 = select 10GBASE-R PCS type
do_write(&MC_CFG_TX, BIT3 + BIT1); //rx_elastic_buffer_initial_fill 5
/* solve start packet impact, config loopback mode */
do_write(&MC_CFG_RX, BIT11 + BIT3 + BIT1); //rx_elastic_buffer_initial_fill 5 + SerDes Loopback
do_write(&MC_GENERAL_TX, (32 << 7) + BIT3 + BIT0); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_RX, (32 << 7) + BIT3 + BIT0); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_TX, (32 << 7) + BIT3); //64b_xgmii_tx 32 SERDES WIDTH
do_write(&MC_GENERAL_RX, (32 << 7) + BIT3); //64b_xgmii_tx 32 SERDES WIDTH
break;
case ECPRI_OPTION_25G:
do_write(&MC_PCS_CONTROL_1, BIT13 + BIT6 + (5 << 2)); //0 1 0 1 = 25Gbps
do_write(&MC_PCS_CONTROL_2, 0); //0 0 0 0 = select 10GBASE-R PCS type
do_write(&MC_CFG_TX, BIT3 + BIT1); //rx_elastic_buffer_initial_fill 5
do_write(&MC_CFG_RX, BIT3 + BIT1); //rx_elastic_buffer_initial_fill 5
do_write(&MC_GENERAL_TX, (32 << 7) + BIT3 + BIT0); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_RX, (32 << 7) + BIT3 + BIT0); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_TX, (32 << 7) + BIT3); //64b_xgmii_tx 32 SERDES WIDTH
do_write(&MC_GENERAL_RX, (32 << 7) + BIT3); //64b_xgmii_tx 32 SERDES WIDTH
break;
default:
break;
}
}
/**********************************************************************************************************************
* Function: ecpri_mac_init
* Description: eCPRI MAC init
* Input:
* <name> <type> <desc>
* dev net_device * network device
* data uint8_t * data received
* len uint32_t data length
* Input: none
* Output: none
* Return: operation result - success or failure.
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_mac_init(uint32_t ecpri_speed_sel)
void ecpri_mac_init(void)
{
//设置manticore收到的最大jumbo帧的大小
/* max jumbo frame size */
do_write(&MC_MAXIMUM_FRAME_SIZE, 65535);
}
/**********************************************************************************************************************
* Function: ecpri_switch_init
* Description: eCPRI SWITCH init
* Input:
* <name> <type> <desc>
* dev net_device * network device
* addr void * network address
* Input: none
* Output: none
* Return: operation result - success or failure.
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_switch_init(uint32_t ecpri_speed_sel)
void ecpri_switch_init(void)
{
do_write(&MC_SWITCH_PORT0_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT0_CFG_VLAN) & (~(BIT12|BIT13|BIT14)));
do_write(&MC_SWITCH_PORT1_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT1_CFG_VLAN) & (~(BIT12|BIT13|BIT14)));
do_write(&MC_SWITCH_PORT2_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT2_CFG_VLAN) & (~(BIT12|BIT13|BIT14)));
do_write(&MC_SWITCH_PORT0_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT0_CFG_VLAN) & (~(BIT12 | BIT13 | BIT14)));
do_write(&MC_SWITCH_PORT1_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT1_CFG_VLAN) & (~(BIT12 | BIT13 | BIT14)));
do_write(&MC_SWITCH_PORT2_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT2_CFG_VLAN) & (~(BIT12 | BIT13 | BIT14)));
//do_write(&MC_SWITCH_PORT0_PORT_MAC_2, 0x0A);
//do_write(&MC_SWITCH_PORT1_PORT_MAC_2, 0x0A);
//do_write(&MC_SWITCH_PORT2_PORT_MAC_2, 0x0A);
//do_write(&MC_SWITCH_PORT0_PORT_MAC_2, 0x000A);
//do_write(&MC_SWITCH_PORT1_PORT_MAC_2, 0x000A);
//do_write(&MC_SWITCH_PORT2_PORT_MAC_2, 0x000A);
//do_write(&MC_SWITCH_PORT0_PORT_MAC_1, 0x09080706);
//do_write(&MC_SWITCH_PORT1_PORT_MAC_1, 0x09080716);
//do_write(&MC_SWITCH_PORT2_PORT_MAC_1, 0x09080726);
//enable vid 2 port 1-3
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
/* enable vid 2 port 0~2 */
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xF) != 0);
do_write(&MC_SWITCH_PORT_MASK_1, 0xffffffff);
do_write(&MC_SWITCH_PORT_MASK_2, 0xffffffff);
do_write(&MC_SWITCH_VLAN_ID, 0x10);
do_write(&MC_SWITCH_OP_CTRL, 0x110);
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
#if 0
/* config insert MAC for RX direction */
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xF) != 0);
do_write(&MC_SWITCH_PORT_MASK_1, 0x4);
do_write(&MC_SWITCH_PORT_MASK_2, 0x0);
do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x0a0908);
do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0726<<16)+0xf));
do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x000A0908);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0726 << 16) + 0xF));
do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0726 << 16) + 0x1));
do_write(&MC_SWITCH_OP_CTRL, 0x100);
//RX方向指定插入MAC方式进行转发过滤
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
/* config insert MAC for RX direction */
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xF) != 0);
do_write(&MC_SWITCH_PORT_MASK_1, 0x2);
do_write(&MC_SWITCH_PORT_MASK_2, 0x0);
do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x0a0908);
do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0716<<16)+0xf));
/* unicast */
do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x000A0908);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0716 << 16) + 0xF));
do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0716 << 16) + 0x1));
do_write(&MC_SWITCH_OP_CTRL, 0x100);
//while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
/* config insert MAC for RX direction */
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xF) != 0);
do_write(&MC_SWITCH_PORT_MASK_1, 0x2);
do_write(&MC_SWITCH_PORT_MASK_2, 0x0);
/* multicast */
do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x011B1900);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0000 << 16) + 0xF));
do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0000 << 16) + 0x1));
do_write(&MC_SWITCH_OP_CTRL, 0x100);
/* config insert MAC for RX direction */
//while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xF) != 0);
//do_write(&MC_SWITCH_PORT_MASK_1, 0x1);
//do_write(&MC_SWITCH_PORT_MASK_2, 0x0);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x0a0908);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0706<<16)+0xf));
//do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x000A0908);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0706 << 16) + 0xF));
//do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0706 << 16) + 0x1));
//do_write(&MC_SWITCH_OP_CTRL, 0x100);
do_write(&MC_SWITCH_CFG_MAE, 0XFFFF0002);
#if 1 //10G
//do_write(&MC_SWITCH_FLOOD_MASK_1, 0xffffffff);
do_write(&MC_SWITCH_FLOOD_MASK_1, 0xfffffff8); //0xfffffff1
#else
do_write(&MC_SWITCH_FLOOD_MASK_1, 0xfffffff1);
/* config TRAP for RX direction(PORT0->PORT1) */
do_write(&MC_SWITCH_PORT0_CFG_TRAP, 0x00000101);
#endif
//TX方向指定TRAP方式进行转发（强制转发）
do_write(&MC_SWITCH_CFG_MAE, 0xFFFF0002);
do_write(&MC_SWITCH_FLOOD_MASK_1, 0xFFFFFFF8);
/* config TRAP for TX direction(PORT1->PORT0) */
do_write(&MC_SWITCH_PORT1_CFG_TRAP, 0x00000001);
}
@ -160,5 +200,178 @@ bool ecpri_pcs_link_status_get(void)
return link_status;
}
/**********************************************************************************************************************
* Function: ecpri_mac_stats_start
* Description: eCPRI MAC statistic start
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_mac_stats_start(void)
{
/* start MAC statistic */
do_write(&MC_STATISTIC_CONFIGURATION, do_read_volatile(&MC_STATISTIC_CONFIGURATION) & (~BIT4));
}
/**********************************************************************************************************************
* Function: ecpri_mac_stats_stop
* Description: eCPRI MAC statistic stop
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_mac_stats_stop(void)
{
/* stop MAC statistic */
do_write(&MC_STATISTIC_CONFIGURATION, do_read_volatile(&MC_STATISTIC_CONFIGURATION) | BIT4);
}
/**********************************************************************************************************************
* Function: ecpri_mac_stats_clear
* Description: eCPRI MAC statistic clear
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_mac_stats_clear(void)
{
/* clear MAC statistic */
do_write(&MC_STATISTIC_CONFIGURATION, do_read_volatile(&MC_STATISTIC_CONFIGURATION) | BIT0);
}
/**********************************************************************************************************************
* Function: ecpri_mac_stats_get
* Description: eCPRI MAC statistic get
* Input: none
* Output:
* <name> <type> <desc>
* ecpri_mac_stats_ptr EcpriMacStats_t * eCPRI MAC statistic pointer
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_mac_stats_get(EcpriMacStats_t *ecpri_mac_stats_ptr)
{
/* input para check */
if (NULL == ecpri_mac_stats_ptr)
{
debug_write(ECPRI_DBG_IDX1(32), ERROR); /* ECS_RFM1: 0xB7E31080(32) */
return ERROR;
}
/* get receive packets of different length and total bytes */
memcpy_ucp((void *)&ecpri_mac_stats_ptr->rx_pkts_64b,
(void *)&MC_STAT_TOT_RX_64B_PKTS,
ECPRI_MAC_STATS_CONSEC_REG_NUM1 * sizeof(uint32_t));
/* get receive packets of CRC error */
ecpri_mac_stats_ptr->rx_pkts_crc_err = do_read_volatile(&MC_STAT_RX_BAD_CRC_PKTS);
/* get receive packets of unicast/multicast/broadcast */
memcpy_ucp((void *)&ecpri_mac_stats_ptr->rx_pkts_uc,
(void *)&MC_STAT_TOT_RX_UC_PKTS,
ECPRI_MAC_STATS_CONSEC_REG_NUM2 * sizeof(uint32_t));
/* get receive packets of discard/overflow */
memcpy_ucp((void *)&ecpri_mac_stats_ptr->rx_pkts_discard,
(void *)&MC_STAT_TOT_RX_DISCARD_PKTS,
ECPRI_MAC_STATS_CONSEC_REG_NUM3 * sizeof(uint32_t));
/* get send packets of different length and total bytes */
memcpy_ucp((void *)&ecpri_mac_stats_ptr->tx_pkts_64b,
(void *)&MC_STAT_TOT_TX_64B_PKTS_1,
ECPRI_MAC_STATS_CONSEC_REG_NUM1 * sizeof(uint32_t));
return SUCCESS;
}
/**********************************************************************************************************************
* Function: ecpri_switch_stats_get
* Description: eCPRI SWITCH statistic get
* Input: none
* Output:
* <name> <type> <desc>
* port uint8_t port ID
* ecpri_switch_stats_ptr EcpriSwitchStats_t * eCPRI SWITCH statistic pointer
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t ecpri_switch_stats_get(uint8_t port, EcpriSwitchStats_t *ecpri_switch_stats_ptr)
{
uint32_t *rx_pkts_fltr_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_PKT_FLTR_RX);
uint32_t *rx_pkts_voq_nq_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_PKT_VOQ_NQ);
uint32_t *tx_pkts_voq_dq_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_PKT_VOQ_DQ);
uint32_t *rx_pkts_voq_drop_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_PKT_VOQ_DROP);
uint32_t *rx_bytes_voq_nq_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_BYTES_VOQ_NQ);
uint32_t *tx_bytes_voq_dq_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_BYTES_VOQ_DQ);
uint32_t *rx_bytes_voq_drop_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_BYTES_VOQ_DROP);
uint32_t *rx_pkts_uc_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_UCAST_PKT_RX);
uint32_t *rx_pkts_buf_ovfl_ptr = (uint32_t *)(&MC_SWITCH_PORT0_STAT_PKT_BUF_OVFL);
/* input para check */
if ((ECPRI_SWITCH_PORT_NUM <= port) || (NULL == ecpri_switch_stats_ptr))
{
debug_write(ECPRI_DBG_IDX1(33), ERROR); /* ECS_RFM1: 0xB7E31084(33) */
return ERROR;
}
switch (port)
{
case ECPRI_SWITCH_PORT1:
rx_pkts_fltr_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_PKT_FLTR_RX);
rx_pkts_voq_nq_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_PKT_VOQ_NQ);
tx_pkts_voq_dq_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_PKT_VOQ_DQ);
rx_pkts_voq_drop_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_PKT_VOQ_DROP);
rx_bytes_voq_nq_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_BYTES_VOQ_NQ);
tx_bytes_voq_dq_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_BYTES_VOQ_DQ);
rx_bytes_voq_drop_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_BYTES_VOQ_DROP);
rx_pkts_uc_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_UCAST_PKT_RX);
rx_pkts_buf_ovfl_ptr = (uint32_t *)(&MC_SWITCH_PORT1_STAT_PKT_BUF_OVFL);
break;
case ECPRI_SWITCH_PORT2:
rx_pkts_fltr_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_PKT_FLTR_RX);
rx_pkts_voq_nq_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_PKT_VOQ_NQ);
tx_pkts_voq_dq_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_PKT_VOQ_DQ);
rx_pkts_voq_drop_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_PKT_VOQ_DROP);
rx_bytes_voq_nq_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_BYTES_VOQ_NQ);
tx_bytes_voq_dq_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_BYTES_VOQ_DQ);
rx_bytes_voq_drop_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_BYTES_VOQ_DROP);
rx_pkts_uc_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_UCAST_PKT_RX);
rx_pkts_buf_ovfl_ptr = (uint32_t *)(&MC_SWITCH_PORT2_STAT_PKT_BUF_OVFL);
break;
default:
break;
}
/* get TRX packets/bytes of filtered */
memcpy_ucp((void *)&ecpri_switch_stats_ptr->rx_pkts_fltr,
(void *)rx_pkts_fltr_ptr,
ECPRI_SWITCH_STATS_CONSEC_REG_NUM1 * sizeof(uint32_t));
/* get TRX packets/bytes of enqueued/dequeued/dropped */
ecpri_switch_stats_ptr->rx_pkts_voq_nq = do_read_volatile(rx_pkts_voq_nq_ptr);
ecpri_switch_stats_ptr->tx_pkts_voq_dq = do_read_volatile(tx_pkts_voq_dq_ptr);
ecpri_switch_stats_ptr->rx_pkts_voq_drop = do_read_volatile(rx_pkts_voq_drop_ptr);
ecpri_switch_stats_ptr->rx_bytes_voq_nq = do_read_volatile(rx_bytes_voq_nq_ptr);
ecpri_switch_stats_ptr->tx_bytes_voq_dq = do_read_volatile(tx_bytes_voq_dq_ptr);
ecpri_switch_stats_ptr->rx_bytes_voq_drop = do_read_volatile(rx_bytes_voq_drop_ptr);
/* get TRX packets/bytes of unicast/multicast/broadcast */
memcpy_ucp((void *)&ecpri_switch_stats_ptr->rx_pkts_uc,
(void *)rx_pkts_uc_ptr,
ECPRI_SWITCH_STATS_CONSEC_REG_NUM2 * sizeof(uint32_t));
/* get receive packets/bytes of buffer-overflow/error dropped */
memcpy_ucp((void *)&ecpri_switch_stats_ptr->rx_pkts_buf_ovfl,
(void *)rx_pkts_buf_ovfl_ptr,
ECPRI_SWITCH_STATS_CONSEC_REG_NUM3 * sizeof(uint32_t));
return SUCCESS;
}

908
public/ecs_rfm_spu1/driver/src/mtimer_drv.s.c
View File

@ -1,454 +1,454 @@
//#include "ucp_cpri.h"
#include "ucp_param.h"
#include "ucp_csu.h"
//#include "ucp_js_ctrl.h"
#include "ucp_mtimer.h"
#include "mtimer_com.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "phy_para.h"
#include "ctc_intr.h"
#include "inter_vector.h"
#include "HeaderRam.h"
#include "dw_apb_gpio.h"
#include "ecs_rfm_dm_mgt.h"
#include "mtimer_drv.h"
extern stPhyScsPara* phyPara;
stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];
int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
uint8_t nBsType = get_protocol_sel();
uint32_t coreClk = 0;
memset(pMtimerPara, 0, sizeof(stMtimerPara));
if (PROTOCOL_CPRI == nBsType)
{
coreClk = pEcsDmLocalMgt->pCpriPara->core_clk;
}
else if (PROTOCOL_JESD == nBsType)
{
coreClk = do_read_volatile(JESD_RX_SAMPLE_RATE+(nTmrId<<5)); // 122880000;
}
else if (PROTOCOL_ECPRI == nBsType)
{
coreClk = 402832000;
}
else
{
return -1;
}
if (0 == coreClk)
{
return -1;
}
pMtimerPara->tmrClk = coreClk;
pMtimerPara->tmrMsPeriod = coreClk / 1000;
pMtimerPara->tmr100UsPeriod = pMtimerPara->tmrMsPeriod / 10;
pMtimerPara->tmrUsPeriod = pMtimerPara->tmrMsPeriod / 1000;
// init slot, tdd value, and config timer period
pMtimerPara->scsId = nScsId;
pMtimerPara->slotPeriod = do_read_volatile_short(&(phyPara[nScsId].slotPeriod));
pMtimerPara->tddSlotNum = nTddSlotNum;
pMtimerPara->tddPeriod = pMtimerPara->slotPeriod * nTddSlotNum;
debug_write((DBG_DDR_IDX_DRV_BASE+42), pMtimerPara->tmrClk); // 0xb7e060A8
debug_write((DBG_DDR_IDX_DRV_BASE+43), pMtimerPara->slotPeriod); // 0xb7e060Ac
return 0;
}
uint32_t mtimer_get_baseaddr(uint8_t nTmrId)
{
uint8_t nBsType = get_protocol_sel();
uint8_t nRateOption = get_protocol_opt();
uint32_t tmrBaseAddr = 0;
if (PROTOCOL_JESD == nBsType)
{
if (nTmrId >= MTIMER_INTEGRATED_MAX_NUM)
{
return 0;
}
if (JESD_OPTION_204B == nRateOption)
{
tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
}
else if (JESD_OPTION_204C == nRateOption)
{
if (MTIMER_JESD_RX0_ID == nTmrId)
{
tmrBaseAddr = JS_RX1_TMR_BASE;
}
else if (MTIMER_JESD_RX1_ID == nTmrId)
{
tmrBaseAddr = JS_RX0_TMR_BASE;
}
else if (MTIMER_JESD_TX0_ID == nTmrId)
{
tmrBaseAddr = JS_TX1_TMR_BASE;
}
else if (MTIMER_JESD_TX1_ID == nTmrId)
{
tmrBaseAddr = JS_TX0_TMR_BASE;
}
}
else
{
return 0;
}
}
else
{
if (MTIMER_CPRI_ID == nTmrId)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
}
else
{
return 0;
}
}
return tmrBaseAddr;
}
int32_t mtimer_clear_all_event(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
// 配置MTimer
do_write(tmrBaseAddr + MTMR_CTRL_REG, 0x0);// 计时清零
// T-EVENT
do_write(tmrBaseAddr + MTMR_TEVENT0_REG, 0xFFFFFFFF); // 清除96个定时点事件
do_write(tmrBaseAddr + MTMR_TEVENT1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TEVENT2_REG, 0xFFFFFFFF);
// clear TINT
do_write(tmrBaseAddr + MTMR_TINTF00_REG, 0xFFFFFFFF); /* INT0 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF01_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF02_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF10_REG, 0xFFFFFFFF); /* INT1 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF11_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF12_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF20_REG, 0xFFFFFFFF); /* INT2 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF21_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF22_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF30_REG, 0xFFFFFFFF); /* INT3 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF31_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF32_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF40_REG, 0xFFFFFFFF); /* INT4 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF41_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF42_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF50_REG, 0xFFFFFFFF); /* INT5 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF51_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF52_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF60_REG, 0xFFFFFFFF); /* INT6 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF61_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF62_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF70_REG, 0xFFFFFFFF); /* INT7 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF71_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF72_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF80_REG, 0xFFFFFFFF); /* INT8 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF81_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF82_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF90_REG, 0xFFFFFFFF); /* INT9 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF91_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF92_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFA0_REG, 0xFFFFFFFF); /* INTA flag clear */
do_write(tmrBaseAddr + MTMR_TINTFA1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFA2_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFB0_REG, 0xFFFFFFFF); /* INTB flag clear */
do_write(tmrBaseAddr + MTMR_TINTFB1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFB2_REG, 0xFFFFFFFF);
// C-EVENT
do_write(tmrBaseAddr + MTMR_CEVENT_REG, 0xFFFFFFFF);
// clear CINT
do_write(tmrBaseAddr + MTMR_CINTF0_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF2_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF3_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF4_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF5_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF6_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF7_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF8_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF9_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTFA_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTFB_REG, 0xFFFFFFFF);
__ucps2_synch(0);
return 0;
}
int32_t set_mtimer_period(uint8_t nTmrId, uint32_t nTmrL, uint32_t nTmrM, uint32_t nTmrH)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
// 设置计数器溢出值
uint32_t tempL = nTmrL;
uint32_t tempM = nTmrM;
uint32_t tempH = nTmrH;
tempL = (tempL > 0) ? (tempL - 1) : (0);
tempM = (tempM > 0) ? (tempM - 1) : (0);
tempH = (tempH > 0) ? (tempH - 1) : (0);
pMtimerPara->tempL_max = tempL;
pMtimerPara->tempM_max = tempM;
pMtimerPara->tempH_max = tempH;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+128+(nTmrId<<7)), tempL); // 0x200
debug_write((DBG_DDR_IDX_DRV_BASE+128+1+(nTmrId<<7)), tempM); // 0x204
debug_write((DBG_DDR_IDX_DRV_BASE+128+2+(nTmrId<<7)), tempH); // 0x208
#endif
do_write(tmrBaseAddr + MTMR_OVFL_REG, tempL);
do_write(tmrBaseAddr + MTMR_OVFH_REG, ((0x1<<31) + (tempH<<16) + tempM)); // WREQ, 10ms, all slot
__ucps2_synch(0);
while(do_read_volatile(tmrBaseAddr + MTMR_OVFH_REG) & BIT31); // RWC reg, wait until the OVF value set finished
return 0;
}
int32_t set_mtimer_1pps_scratch(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
uint32_t val = do_read_volatile(addr);
do_write(addr, (val|BIT1)); // 1pps抓取使能
//addr = tmrBaseAddr + MTMR_CINTE0_REG + 2*(MTMR_INT_10ms<<2);
//val = do_read_volatile(addr);
//do_write(addr, (val|BIT17)); // int enable
enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_1PPS, MTMR_INT_10ms); // int enable
return 0;
}
// nTmrPoint: us as unit
int32_t set_mtimer_tmrpoint(uint8_t nTmrId, uint8_t nPointId, int32_t nTmrPoint, uint8_t mask)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
//uint32_t periodL = pMtimerPara->tempL_max + 1;
uint32_t periodM = pMtimerPara->tempM_max + 1;
//uint32_t periodH = pMtimerPara->tempH_max + 1;
if (nTmrPoint < 0)
{
nTmrPoint += SFN_PERIOD;
}
uint32_t tempL = pMtimerPara->tmrMsPeriod * (nTmrPoint % pMtimerPara->slotPeriod) / 1000;
uint32_t tempM = (nTmrPoint / pMtimerPara->slotPeriod) % periodM;
uint32_t tempH = (nTmrPoint / pMtimerPara->slotPeriod) / periodM;
if ((0 == tempM) && (0 == tempL))
{
tempH = (tempH > 0) ? (tempH - 1) : (pMtimerPara->tempH_max);
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
else if (0 == tempL)
{
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
if (MTIMER_MASK_32BIT == mask)
{
tempH = 0;
tempM = 0;
}
else if (MTIMER_MASK_48BIT == mask)
{
tempH = 0;
}
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+128+4+(nPointId<<2)+(nTmrId<<7)), nTmrPoint); // 0x210
debug_write((DBG_DDR_IDX_DRV_BASE+128+5+(nPointId<<2)+(nTmrId<<7)), tempL); // 0x214
debug_write((DBG_DDR_IDX_DRV_BASE+128+6+(nPointId<<2)+(nTmrId<<7)), tempM); // 0x218
debug_write((DBG_DDR_IDX_DRV_BASE+128+7+(nPointId<<2)+(nTmrId<<7)), tempH); // 0x21c
#endif
do_write((tmrBaseAddr + MTMR_TnL_REG0 + (nPointId<<3)), tempL);
do_write((tmrBaseAddr + MTMR_TnH_REG0 + (nPointId<<3)), ((mask<<30) + (tempH<<16) + tempM));
do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)), (1<<(nPointId&0x1F)));
__ucps2_synch(0);
while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)) & (1<<(nPointId&0x1F))); // REQ reg, wait until the T0L and T0H set finished
return 0;
}
int32_t enable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
do_write(addr, (do_read_volatile(addr) | (1 << (nPointId&0x1F))));
return 0;
}
int32_t disable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
do_write(addr, (do_read_volatile(addr) & (~(1 << (nPointId&0x1F)))));
return 0;
}
int32_t enable_mtimer_cevent_int(uint8_t nTmrId, uint8_t nCEvtId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CINTE0_REG + (nIntcId<<3);
uint32_t val = do_read_volatile(addr);
val |= (1 << nCEvtId);
do_write(addr, val);
return 0;
}
int32_t disable_mtimer_cevent_int(uint8_t nTmrId, uint8_t nCEvtId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CINTE0_REG + (nIntcId<<3);
uint32_t val = do_read_volatile(addr);
val &= (~(1 << nCEvtId));
do_write(addr, val);
return 0;
}
int32_t set_cpri_tmr_ctrl()
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
if (0 == tmrBaseAddr)
{
return -1;
}
do_write((tmrBaseAddr + MTMR_CPRI_10MS_CLR), 0x1); // count clear
do_write((tmrBaseAddr + MTMR_CPRI_10MS_CTRL), ((0x1<<9) + (MTMR_10ms_OFFSET<<2) + (0x0<<1) + 0x1 + (MTMR_CSU_CH << 10)));
return 0;
}
int32_t start_mtimer(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
pMtimerPara->tmrScrCnt = 0;
uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
do_write(addr, ((do_read_volatile(addr))|BIT0)); // start timer
return 0;
}
int32_t stop_mtimer(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
do_write(addr, ((do_read_volatile(addr))&(~BIT0))); // stop timer and clear the count
return 0;
}
uint64_t get_mtimer_rt_scr_value(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint64_t scrval = 0;
uint64_t hval = 0;
uint32_t addr = tmrBaseAddr + MTMR_SCR_CTRL_REG;
do_write(addr, ((do_read_volatile(addr)) | BIT31));
while (do_read_volatile(addr) & BIT31) // 抓取完成
{
ucp_nop(1);
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
pMtimerPara->tmrScrCnt++;
if (pMtimerPara->tmrScrCnt & 0x1)
{
hval = do_read_volatile(tmrBaseAddr + MTMR_SCRATH0H_REG);
scrval = (hval<<32) | do_read_volatile(tmrBaseAddr + MTMR_SCRATH0L_REG);
}
else
{
hval = do_read_volatile(tmrBaseAddr + MTMR_SCRATH1H_REG);
scrval = (hval<<32) | do_read_volatile(tmrBaseAddr + MTMR_SCRATH1L_REG);
}
return scrval;
}
//#include "ucp_cpri.h"
#include "ucp_param.h"
#include "ucp_csu.h"
//#include "ucp_js_ctrl.h"
#include "ucp_mtimer.h"
#include "mtimer_com.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "phy_para.h"
#include "ctc_intr.h"
#include "inter_vector.h"
#include "HeaderRam.h"
#include "dw_apb_gpio.h"
#include "ecs_rfm_dm_mgt.h"
#include "mtimer_drv.h"
extern stPhyScsPara* phyPara;
stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];
int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
uint8_t nBsType = get_protocol_sel();
uint32_t coreClk = 0;
memset(pMtimerPara, 0, sizeof(stMtimerPara));
if (PROTOCOL_CPRI == nBsType)
{
coreClk = pEcsDmLocalMgt->pCpriPara->core_clk;
}
else if (PROTOCOL_JESD == nBsType)
{
coreClk = do_read_volatile(JESD_RX_SAMPLE_RATE+(nTmrId<<5)); // 122880000;
}
else if (PROTOCOL_ECPRI == nBsType)
{
coreClk = 156240000; // 161132000; // 402832000;
}
else
{
return -1;
}
if (0 == coreClk)
{
return -1;
}
pMtimerPara->tmrClk = coreClk;
pMtimerPara->tmrMsPeriod = coreClk / 1000;
pMtimerPara->tmr100UsPeriod = pMtimerPara->tmrMsPeriod / 10;
pMtimerPara->tmrUsPeriod = pMtimerPara->tmrMsPeriod / 1000;
// init slot, tdd value, and config timer period
pMtimerPara->scsId = nScsId;
pMtimerPara->slotPeriod = do_read_volatile_short(&(phyPara[nScsId].slotPeriod));
pMtimerPara->tddSlotNum = nTddSlotNum;
pMtimerPara->tddPeriod = pMtimerPara->slotPeriod * nTddSlotNum;
debug_write((DBG_DDR_IDX_DRV_BASE+42), pMtimerPara->tmrClk); // 0xb7e060A8
debug_write((DBG_DDR_IDX_DRV_BASE+43), pMtimerPara->slotPeriod); // 0xb7e060Ac
return 0;
}
uint32_t mtimer_get_baseaddr(uint8_t nTmrId)
{
uint8_t nBsType = get_protocol_sel();
uint8_t nRateOption = get_protocol_opt();
uint32_t tmrBaseAddr = 0;
if (PROTOCOL_JESD == nBsType)
{
if (nTmrId >= MTIMER_INTEGRATED_MAX_NUM)
{
return 0;
}
if (JESD_OPTION_204B == nRateOption)
{
tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
}
else if (JESD_OPTION_204C == nRateOption)
{
if (MTIMER_JESD_RX0_ID == nTmrId)
{
tmrBaseAddr = JS_RX1_TMR_BASE;
}
else if (MTIMER_JESD_RX1_ID == nTmrId)
{
tmrBaseAddr = JS_RX0_TMR_BASE;
}
else if (MTIMER_JESD_TX0_ID == nTmrId)
{
tmrBaseAddr = JS_TX1_TMR_BASE;
}
else if (MTIMER_JESD_TX1_ID == nTmrId)
{
tmrBaseAddr = JS_TX0_TMR_BASE;
}
}
else
{
return 0;
}
}
else
{
if (MTIMER_CPRI_ID == nTmrId)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
}
else
{
return 0;
}
}
return tmrBaseAddr;
}
int32_t mtimer_clear_all_event(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
// 配置MTimer
do_write(tmrBaseAddr + MTMR_CTRL_REG, 0x0);// 计时清零
// T-EVENT
do_write(tmrBaseAddr + MTMR_TEVENT0_REG, 0xFFFFFFFF); // 清除96个定时点事件
do_write(tmrBaseAddr + MTMR_TEVENT1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TEVENT2_REG, 0xFFFFFFFF);
// clear TINT
do_write(tmrBaseAddr + MTMR_TINTF00_REG, 0xFFFFFFFF); /* INT0 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF01_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF02_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF10_REG, 0xFFFFFFFF); /* INT1 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF11_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF12_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF20_REG, 0xFFFFFFFF); /* INT2 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF21_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF22_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF30_REG, 0xFFFFFFFF); /* INT3 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF31_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF32_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF40_REG, 0xFFFFFFFF); /* INT4 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF41_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF42_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF50_REG, 0xFFFFFFFF); /* INT5 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF51_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF52_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF60_REG, 0xFFFFFFFF); /* INT6 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF61_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF62_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF70_REG, 0xFFFFFFFF); /* INT7 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF71_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF72_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF80_REG, 0xFFFFFFFF); /* INT8 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF81_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF82_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF90_REG, 0xFFFFFFFF); /* INT9 flag clear */
do_write(tmrBaseAddr + MTMR_TINTF91_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTF92_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFA0_REG, 0xFFFFFFFF); /* INTA flag clear */
do_write(tmrBaseAddr + MTMR_TINTFA1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFA2_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFB0_REG, 0xFFFFFFFF); /* INTB flag clear */
do_write(tmrBaseAddr + MTMR_TINTFB1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_TINTFB2_REG, 0xFFFFFFFF);
// C-EVENT
do_write(tmrBaseAddr + MTMR_CEVENT_REG, 0xFFFFFFFF);
// clear CINT
do_write(tmrBaseAddr + MTMR_CINTF0_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF1_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF2_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF3_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF4_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF5_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF6_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF7_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF8_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTF9_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTFA_REG, 0xFFFFFFFF);
do_write(tmrBaseAddr + MTMR_CINTFB_REG, 0xFFFFFFFF);
__ucps2_synch(0);
return 0;
}
int32_t set_mtimer_period(uint8_t nTmrId, uint32_t nTmrL, uint32_t nTmrM, uint32_t nTmrH)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
// 设置计数器溢出值
uint32_t tempL = nTmrL;
uint32_t tempM = nTmrM;
uint32_t tempH = nTmrH;
tempL = (tempL > 0) ? (tempL - 1) : (0);
tempM = (tempM > 0) ? (tempM - 1) : (0);
tempH = (tempH > 0) ? (tempH - 1) : (0);
pMtimerPara->tempL_max = tempL;
pMtimerPara->tempM_max = tempM;
pMtimerPara->tempH_max = tempH;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+128+(nTmrId<<7)), tempL); // 0x200
debug_write((DBG_DDR_IDX_DRV_BASE+128+1+(nTmrId<<7)), tempM); // 0x204
debug_write((DBG_DDR_IDX_DRV_BASE+128+2+(nTmrId<<7)), tempH); // 0x208
#endif
do_write(tmrBaseAddr + MTMR_OVFL_REG, tempL);
do_write(tmrBaseAddr + MTMR_OVFH_REG, ((0x1<<31) + (tempH<<16) + tempM)); // WREQ, 10ms, all slot
__ucps2_synch(0);
while(do_read_volatile(tmrBaseAddr + MTMR_OVFH_REG) & BIT31); // RWC reg, wait until the OVF value set finished
return 0;
}
int32_t set_mtimer_1pps_scratch(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
uint32_t val = do_read_volatile(addr);
do_write(addr, (val|BIT1)); // 1pps抓取使能
//addr = tmrBaseAddr + MTMR_CINTE0_REG + 2*(MTMR_INT_10ms<<2);
//val = do_read_volatile(addr);
//do_write(addr, (val|BIT17)); // int enable
enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_1PPS, MTMR_INT_10ms); // int enable
return 0;
}
// nTmrPoint: us as unit
int32_t set_mtimer_tmrpoint(uint8_t nTmrId, uint8_t nPointId, int32_t nTmrPoint, uint8_t mask)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
//uint32_t periodL = pMtimerPara->tempL_max + 1;
uint32_t periodM = pMtimerPara->tempM_max + 1;
//uint32_t periodH = pMtimerPara->tempH_max + 1;
if (nTmrPoint < 0)
{
nTmrPoint += SFN_PERIOD;
}
uint32_t tempL = pMtimerPara->tmrMsPeriod * (nTmrPoint % pMtimerPara->slotPeriod) / 1000;
uint32_t tempM = (nTmrPoint / pMtimerPara->slotPeriod) % periodM;
uint32_t tempH = (nTmrPoint / pMtimerPara->slotPeriod) / periodM;
if ((0 == tempM) && (0 == tempL))
{
tempH = (tempH > 0) ? (tempH - 1) : (pMtimerPara->tempH_max);
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
else if (0 == tempL)
{
tempM = (tempM > 0) ? (tempM - 1) : (pMtimerPara->tempM_max);
}
tempL = (tempL > 0) ? (tempL - 1) : (pMtimerPara->tempL_max);
if (MTIMER_MASK_32BIT == mask)
{
tempH = 0;
tempM = 0;
}
else if (MTIMER_MASK_48BIT == mask)
{
tempH = 0;
}
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+128+4+(nPointId<<2)+(nTmrId<<7)), nTmrPoint); // 0x210
debug_write((DBG_DDR_IDX_DRV_BASE+128+5+(nPointId<<2)+(nTmrId<<7)), tempL); // 0x214
debug_write((DBG_DDR_IDX_DRV_BASE+128+6+(nPointId<<2)+(nTmrId<<7)), tempM); // 0x218
debug_write((DBG_DDR_IDX_DRV_BASE+128+7+(nPointId<<2)+(nTmrId<<7)), tempH); // 0x21c
#endif
do_write((tmrBaseAddr + MTMR_TnL_REG0 + (nPointId<<3)), tempL);
do_write((tmrBaseAddr + MTMR_TnH_REG0 + (nPointId<<3)), ((mask<<30) + (tempH<<16) + tempM));
do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)), (1<<(nPointId&0x1F)));
__ucps2_synch(0);
while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)) & (1<<(nPointId&0x1F))); // REQ reg, wait until the T0L and T0H set finished
return 0;
}
int32_t enable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
do_write(addr, (do_read_volatile(addr) | (1 << (nPointId&0x1F))));
return 0;
}
int32_t disable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
do_write(addr, (do_read_volatile(addr) & (~(1 << (nPointId&0x1F)))));
return 0;
}
int32_t enable_mtimer_cevent_int(uint8_t nTmrId, uint8_t nCEvtId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CINTE0_REG + (nIntcId<<3);
uint32_t val = do_read_volatile(addr);
val |= (1 << nCEvtId);
do_write(addr, val);
return 0;
}
int32_t disable_mtimer_cevent_int(uint8_t nTmrId, uint8_t nCEvtId, uint8_t nIntcId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CINTE0_REG + (nIntcId<<3);
uint32_t val = do_read_volatile(addr);
val &= (~(1 << nCEvtId));
do_write(addr, val);
return 0;
}
int32_t set_cpri_tmr_ctrl()
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
if (0 == tmrBaseAddr)
{
return -1;
}
do_write((tmrBaseAddr + MTMR_CPRI_10MS_CLR), 0x1); // count clear
do_write((tmrBaseAddr + MTMR_CPRI_10MS_CTRL), ((0x1<<9) + (MTMR_10ms_OFFSET<<2) + (0x0<<1) + 0x1 + (MTMR_CSU_CH << 10)));
return 0;
}
int32_t start_mtimer(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
pMtimerPara->tmrScrCnt = 0;
uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
do_write(addr, ((do_read_volatile(addr))|BIT0)); // start timer
return 0;
}
int32_t stop_mtimer(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_CTRL_REG;
do_write(addr, ((do_read_volatile(addr))&(~BIT0))); // stop timer and clear the count
return 0;
}
uint64_t get_mtimer_rt_scr_value(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = mtimer_get_baseaddr(nTmrId);
if (0 == tmrBaseAddr)
{
return -1;
}
uint64_t scrval = 0;
uint64_t hval = 0;
uint32_t addr = tmrBaseAddr + MTMR_SCR_CTRL_REG;
do_write(addr, ((do_read_volatile(addr)) | BIT31));
while (do_read_volatile(addr) & BIT31) // 抓取完成
{
ucp_nop(1);
}
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
pMtimerPara->tmrScrCnt++;
if (pMtimerPara->tmrScrCnt & 0x1)
{
hval = do_read_volatile(tmrBaseAddr + MTMR_SCRATH0H_REG);
scrval = (hval<<32) | do_read_volatile(tmrBaseAddr + MTMR_SCRATH0L_REG);
}
else
{
hval = do_read_volatile(tmrBaseAddr + MTMR_SCRATH1H_REG);
scrval = (hval<<32) | do_read_volatile(tmrBaseAddr + MTMR_SCRATH1L_REG);
}
return scrval;
}

738
public/ecs_rfm_spu1/driver/src/stc_timer.s.c
View File

@ -1,369 +1,369 @@
#include "ucp_cpri.h"
#include "ucp_js_subcrg.h"
#include "ucp_js_ctrl.h"
#include "ucp_sfr_c.h"
#include "jesd_timer.h"
#include "stc_timer.h"
#include "phy_para.h"
#include "ucp_drv_common.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
stStcTimerPara gStcTimerPara;
extern stPhyScsPara* phyPara;
void rfm_stc_init()
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0x4
#endif
uint32_t pClk = stc_pclk_init();
if (0 == pClk)
{
UCP_PRINT_EMPTY("stc_init: pClk get error! \r\n");
#ifdef PALLADIUM_TEST
flag = -1;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
return;
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
stc_timer_init(pClk, STC_RT);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
do_write(&(TOD_REG_NF), (0xC0000000 | pClk)); // init finished
}
uint32_t stc_pclk_init()
{
uint32_t pClk = 0;
int32_t protoSel = get_protocol_sel();
int32_t protoOpt = get_protocol_opt();
if (PROTOCOL_CPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait cpri serdes clk init finished
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (CPRI_OPTION_7):
{
serdesTxClk = 491520000;
break;
}
case (CPRI_OPTION_8):
{
serdesTxClk = 316800000;
break;
}
case (CPRI_OPTION_9):
{
serdesTxClk = 380160000;
break;
}
case (CPRI_OPTION_10):
{
serdesTxClk = 760320000;
break;
}
default:
{
serdesTxClk = 316800000;
break;
}
}
JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
//JECS_CTRL_PROTOCOL_SEL &= (~0x1); // jecs_protocol_sel = 0, sel cpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_ECPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait ecpri serdes clk init finished
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (ECPRI_OPTION_10G):
{
serdesTxClk = 322264000; // 805664000; //
break;
}
case (ECPRI_OPTION_25G):
{
serdesTxClk = 805664000; // 2014160000; //
break;
}
default:
{
serdesTxClk = 322264000; // 805664000; //
break;
}
}
// JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
//JECS_CTRL_PROTOCOL_SEL |= 0x2; // jecs_protocol_sel = 2, sel ecpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
__ucps2_synch(0);
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_JESD == protoSel)
{
while (JESD_CLK_INIT > (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait jesd serdes clk init finished
JECS_CRG_PLLSEL |= (0x6 << 7); // stc_src_clk_sel[2:0]=0x6
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
// laneRate = IQ_sample_rate * M * N' * (10/8)/L // max_laneRate = 12.5Gbps
// serdesTxClk = laneRate/40;
// pClk = serdesTxClk;
uint32_t samClk = do_read_volatile(JESD_TX_SAMPLE_RATE);
uint32_t jesdPara = do_read_volatile(JESD_TX_CH_PARA);
uint8_t paraL = jesdPara & 0xFF;
uint8_t paraM = (jesdPara >> 8) & 0xFF;
uint8_t paraN = (jesdPara >> 16) & 0xFF;
if ((0 == samClk) || (0 == jesdPara))
{
pClk = 0;
}
else
{
pClk = (uint64_t)(samClk/paraL/40)*paraM*paraN*10/8; // (uint64_t)(122880000/4/40)*8*16*10/8;
}
}
else
{
PETP_CLK_CFG_REG = 0x523000; // ECS_PCLK=1G/4=250M
JECS_CRG_CLK_CTRL3 = 0x520000; // STC_PCLK=ECS_PCLK/1=250M
// JECS_CRG_PLLSEL &= (~(1 << 9)); // stc_src_clk_sel2=0
pClk = 250000000; // 100000000;
UCP_PRINT_EMPTY("stc_pclk_init: use soc_crg to generate pclk, 250M. \r\n");
}
return pClk;
}
int32_t gcd_stein(uint32_t x, uint32_t y)
{
if (x < y)
{
int32_t tmp = x;
x = y;
y = tmp;
}
if (0 == (x%y))
{
return y;
}
if ((0 == (x%2)) && (0 == (y%2)))
{
return (2*gcd_stein(x>>1, y>>1));
}
else if ((0 == (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x>>1, y));
}
else if ((0 != (x%2)) && (0 == (y%2)))
{
return (gcd_stein(x, y>>1));
}
else if ((0 != (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x, ((x-y)>>1)));
}
else
{
return 0;
}
}
void stc_timer_init(uint32_t pClk, uint32_t valR)
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0x8
#endif
stc_timer_tod_init(pClk);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
#if 0
stc_pp1s_src_init(STC_PP1S_SRC_GPS); // select gps pp1s as stc ppls input
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(apeId<<2)), flag);
#endif
#endif
stc_timer_para_init(pClk, valR);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer_local_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer0_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer1_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
}
void stc_timer_para_init(uint32_t pClk, uint32_t valR)
{
//int apeId = get_core_id();
uint32_t remain = 0;
uint32_t gcd = 0;
memset(&gStcTimerPara, 0, sizeof(stStcTimerPara));
gStcTimerPara.pClk = pClk;
gStcTimerPara.R = valR;
gStcTimerPara.usR = valR / 1000000;
gStcTimerPara.N1 = valR/pClk;
if (gStcTimerPara.N1 * pClk == valR)
{
gStcTimerPara.N1 -= 1;
}
gStcTimerPara.N = gStcTimerPara.N1 + 1;
debug_write((DBG_DDR_IDX_DRV_BASE+24), gStcTimerPara.pClk); // 0x60
debug_write((DBG_DDR_IDX_DRV_BASE+25), gStcTimerPara.N); // 0x64
remain = valR-gStcTimerPara.N1*pClk;
gcd = gcd_stein(pClk, remain);
if (0 == gcd)
{
UCP_PRINT_EMPTY("gcd error! \r\n");
return;
}
gStcTimerPara.A = remain / gcd;
gStcTimerPara.C = pClk / gcd;
UCP_PRINT_EMPTY("pclk = 0x%x. \r\n", gStcTimerPara.pClk);
UCP_PRINT_EMPTY("R = 0x%x. \r\n", gStcTimerPara.R);
UCP_PRINT_EMPTY("N = 0x%x. \r\n", gStcTimerPara.N);
UCP_PRINT_EMPTY("N1 = 0x%x. \r\n", gStcTimerPara.N1);
UCP_PRINT_EMPTY("A = 0x%x. \r\n", gStcTimerPara.A);
UCP_PRINT_EMPTY("C = 0x%x. \r\n", gStcTimerPara.C);
debug_write((DBG_DDR_IDX_DRV_BASE+26), gStcTimerPara.A); // 0x68
debug_write((DBG_DDR_IDX_DRV_BASE+27), gStcTimerPara.C); // 0x6c
}
void stc_timer_tod_init(uint32_t pClk)
{
JECS_CRG_STC_RST_CTRL |= BIT24;
stc_tod_para_init(pClk);
//stc_timer_todint_init();
//do_write(STC_TOD_INT_ADDR, 0); // clear tod int flag
}
void stc_pp1s_src_init(uint8_t srcId)
{
// gnss_sel stc_sel cpri_sel
//JECS_CTRL_CPRI_GMAC_PHY_INT = (0x0 << 4) | (0x5 << 7) | (0x6<<10);
JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 7);
JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 7); // select gps pp1s as stc ppls input
}
void stc_timer_local_init()
{
LTBG_REG_R = gStcTimerPara.R;
LTBG_TIME_SET = 0;
LTBG_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG_REG_A = gStcTimerPara.A;
LTBG_REG_N = gStcTimerPara.N;
LTBG_REG_N1 = gStcTimerPara.N1;
}
void stc_timer0_para_init()
{
LTBG0_REG_R = gStcTimerPara.R;
LTBG0_TIME_SET = 0;
LTBG0_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG0_REG_A = gStcTimerPara.A;
LTBG0_REG_N = gStcTimerPara.N;
LTBG0_REG_N1 = gStcTimerPara.N1;
}
void stc_timer1_para_init()
{
LTBG1_REG_R = gStcTimerPara.R;
LTBG1_TIME_SET = 0;
LTBG1_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG1_REG_A = gStcTimerPara.A;
LTBG1_REG_N = gStcTimerPara.N;
LTBG1_REG_N1 = gStcTimerPara.N1;
}
void stc_tod_para_init(uint32_t pClk)
{
//TOD_REG_FT_LO = 0; // 0xB0AAAAAA; // 0x11AAAAAA; //
//TOD_REG_FT_HI = 40; // 40; //4; //
double nsOfClk = 1000000000.0 / pClk;
uint32_t hiOfFt = 1000000000 / pClk;
uint64_t coff = (1ULL<<32);
uint32_t loOfFt = (uint32_t)((double)(nsOfClk - hiOfFt) * coff); // ???
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+5), loOfFt); // 0x8
debug_write((DBG_DDR_IDX_DRV_BASE+6), hiOfFt); // 0xc
#endif
do_write((&TOD_REG_FT_LO), loOfFt);
do_write((&TOD_REG_FT_HI), hiOfFt);
uint32_t loOfRt = 0;
uint32_t hiOfRt = 0;
//#ifdef PALLADIUM_TEST
// hiOfRt = STC_RT_PALLADIUM; // one tod period: 100ms
// do_write(STC_RT_ADDR, STC_RT_PALLADIUM);
//#else
hiOfRt = STC_RT;
do_write(STC_RT_ADDR, STC_RT);
//#endif
UCP_PRINT_EMPTY("RT LO = 0x%x. \r\n", loOfRt);
UCP_PRINT_EMPTY("RT HI = 0x%x. \r\n", hiOfRt);
do_write((&TOD_REG_RT_LO), loOfRt);
do_write((&TOD_REG_RT_HI), hiOfRt);
TOD_REG_CONFIG |= (1<<3); // onepps_output_enable
do_write(STC_ONEPPS_OUT_ADDR, 1);
}
#include "ucp_cpri.h"
#include "ucp_js_subcrg.h"
#include "ucp_js_ctrl.h"
#include "ucp_sfr_c.h"
#include "jesd_timer.h"
#include "stc_timer.h"
#include "phy_para.h"
#include "ucp_drv_common.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
stStcTimerPara gStcTimerPara;
extern stPhyScsPara* phyPara;
void rfm_stc_init()
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0x4
#endif
uint32_t pClk = stc_pclk_init();
if (0 == pClk)
{
UCP_PRINT_EMPTY("stc_init: pClk get error! \r\n");
#ifdef PALLADIUM_TEST
flag = -1;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
return;
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
stc_timer_init(pClk, STC_RT);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
do_write(&(TOD_REG_NF), (0xC0000000 | pClk)); // init finished
}
uint32_t stc_pclk_init()
{
uint32_t pClk = 0;
int32_t protoSel = get_protocol_sel();
int32_t protoOpt = get_protocol_opt();
if (PROTOCOL_CPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait cpri serdes clk init finished
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (CPRI_OPTION_7):
{
serdesTxClk = 491520000;
break;
}
case (CPRI_OPTION_8):
{
serdesTxClk = 316800000;
break;
}
case (CPRI_OPTION_9):
{
serdesTxClk = 380160000;
break;
}
case (CPRI_OPTION_10):
{
serdesTxClk = 760320000;
break;
}
default:
{
serdesTxClk = 316800000;
break;
}
}
JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
//JECS_CTRL_PROTOCOL_SEL &= (~0x1); // jecs_protocol_sel = 0, sel cpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_ECPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait ecpri serdes clk init finished
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (ECPRI_OPTION_10G):
{
serdesTxClk = 322265625; // 322264000; // 805664000; // 156250000; //
break;
}
case (ECPRI_OPTION_25G):
{
serdesTxClk = 805664000; // 2014160000; // 390625000;
break;
}
default:
{
serdesTxClk = 322265625; // 322264000; // 805664000; // 156250000;
break;
}
}
// JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
//JECS_CTRL_PROTOCOL_SEL |= 0x2; // jecs_protocol_sel = 2, sel ecpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
__ucps2_synch(0);
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_JESD == protoSel)
{
while (JESD_CLK_INIT > (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait jesd serdes clk init finished
JECS_CRG_PLLSEL |= (0x6 << 7); // stc_src_clk_sel[2:0]=0x6
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
// laneRate = IQ_sample_rate * M * N' * (10/8)/L // max_laneRate = 12.5Gbps
// serdesTxClk = laneRate/40;
// pClk = serdesTxClk;
uint32_t samClk = do_read_volatile(JESD_TX_SAMPLE_RATE);
uint32_t jesdPara = do_read_volatile(JESD_TX_CH_PARA);
uint8_t paraL = jesdPara & 0xFF;
uint8_t paraM = (jesdPara >> 8) & 0xFF;
uint8_t paraN = (jesdPara >> 16) & 0xFF;
if ((0 == samClk) || (0 == jesdPara))
{
pClk = 0;
}
else
{
pClk = (uint64_t)(samClk/paraL/40)*paraM*paraN*10/8; // (uint64_t)(122880000/4/40)*8*16*10/8;
}
}
else
{
PETP_CLK_CFG_REG = 0x523000; // ECS_PCLK=1G/4=250M
JECS_CRG_CLK_CTRL3 = 0x520000; // STC_PCLK=ECS_PCLK/1=250M
// JECS_CRG_PLLSEL &= (~(1 << 9)); // stc_src_clk_sel2=0
pClk = 250000000; // 100000000;
UCP_PRINT_EMPTY("stc_pclk_init: use soc_crg to generate pclk, 250M. \r\n");
}
return pClk;
}
int32_t gcd_stein(uint32_t x, uint32_t y)
{
if (x < y)
{
int32_t tmp = x;
x = y;
y = tmp;
}
if (0 == (x%y))
{
return y;
}
if ((0 == (x%2)) && (0 == (y%2)))
{
return (2*gcd_stein(x>>1, y>>1));
}
else if ((0 == (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x>>1, y));
}
else if ((0 != (x%2)) && (0 == (y%2)))
{
return (gcd_stein(x, y>>1));
}
else if ((0 != (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x, ((x-y)>>1)));
}
else
{
return 0;
}
}
void stc_timer_init(uint32_t pClk, uint32_t valR)
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0x8
#endif
stc_timer_tod_init(pClk);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
#if 0
stc_pp1s_src_init(STC_PP1S_SRC_GPS); // select gps pp1s as stc ppls input
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(apeId<<2)), flag);
#endif
#endif
stc_timer_para_init(pClk, valR);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer_local_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer0_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer1_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
}
void stc_timer_para_init(uint32_t pClk, uint32_t valR)
{
//int apeId = get_core_id();
uint32_t remain = 0;
uint32_t gcd = 0;
memset(&gStcTimerPara, 0, sizeof(stStcTimerPara));
gStcTimerPara.pClk = pClk;
gStcTimerPara.R = valR;
gStcTimerPara.usR = valR / 1000000;
gStcTimerPara.N1 = valR/pClk;
if (gStcTimerPara.N1 * pClk == valR)
{
gStcTimerPara.N1 -= 1;
}
gStcTimerPara.N = gStcTimerPara.N1 + 1;
debug_write((DBG_DDR_IDX_DRV_BASE+24), gStcTimerPara.pClk); // 0x60
debug_write((DBG_DDR_IDX_DRV_BASE+25), gStcTimerPara.N); // 0x64
remain = valR-gStcTimerPara.N1*pClk;
gcd = gcd_stein(pClk, remain);
if (0 == gcd)
{
UCP_PRINT_EMPTY("gcd error! \r\n");
return;
}
gStcTimerPara.A = remain / gcd;
gStcTimerPara.C = pClk / gcd;
UCP_PRINT_EMPTY("pclk = 0x%x. \r\n", gStcTimerPara.pClk);
UCP_PRINT_EMPTY("R = 0x%x. \r\n", gStcTimerPara.R);
UCP_PRINT_EMPTY("N = 0x%x. \r\n", gStcTimerPara.N);
UCP_PRINT_EMPTY("N1 = 0x%x. \r\n", gStcTimerPara.N1);
UCP_PRINT_EMPTY("A = 0x%x. \r\n", gStcTimerPara.A);
UCP_PRINT_EMPTY("C = 0x%x. \r\n", gStcTimerPara.C);
debug_write((DBG_DDR_IDX_DRV_BASE+26), gStcTimerPara.A); // 0x68
debug_write((DBG_DDR_IDX_DRV_BASE+27), gStcTimerPara.C); // 0x6c
}
void stc_timer_tod_init(uint32_t pClk)
{
JECS_CRG_STC_RST_CTRL |= BIT24;
stc_tod_para_init(pClk);
//stc_timer_todint_init();
//do_write(STC_TOD_INT_ADDR, 0); // clear tod int flag
}
void stc_pp1s_src_init(uint8_t srcId)
{
// gnss_sel stc_sel cpri_sel
//JECS_CTRL_CPRI_GMAC_PHY_INT = (0x0 << 4) | (0x5 << 7) | (0x6<<10);
JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 7);
JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 7); // select gps pp1s as stc ppls input
}
void stc_timer_local_init()
{
LTBG_REG_R = gStcTimerPara.R;
LTBG_TIME_SET = 0;
LTBG_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG_REG_A = gStcTimerPara.A;
LTBG_REG_N = gStcTimerPara.N;
LTBG_REG_N1 = gStcTimerPara.N1;
}
void stc_timer0_para_init()
{
LTBG0_REG_R = gStcTimerPara.R;
LTBG0_TIME_SET = 0;
LTBG0_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG0_REG_A = gStcTimerPara.A;
LTBG0_REG_N = gStcTimerPara.N;
LTBG0_REG_N1 = gStcTimerPara.N1;
}
void stc_timer1_para_init()
{
LTBG1_REG_R = gStcTimerPara.R;
LTBG1_TIME_SET = 0;
LTBG1_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG1_REG_A = gStcTimerPara.A;
LTBG1_REG_N = gStcTimerPara.N;
LTBG1_REG_N1 = gStcTimerPara.N1;
}
void stc_tod_para_init(uint32_t pClk)
{
//TOD_REG_FT_LO = 0; // 0xB0AAAAAA; // 0x11AAAAAA; //
//TOD_REG_FT_HI = 40; // 40; //4; //
double nsOfClk = 1000000000.0 / pClk;
uint32_t hiOfFt = 1000000000 / pClk;
uint64_t coff = (1ULL<<32);
uint32_t loOfFt = (uint32_t)((double)(nsOfClk - hiOfFt) * coff); // ???
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+5), loOfFt); // 0x8
debug_write((DBG_DDR_IDX_DRV_BASE+6), hiOfFt); // 0xc
#endif
do_write((&TOD_REG_FT_LO), loOfFt);
do_write((&TOD_REG_FT_HI), hiOfFt);
uint32_t loOfRt = 0;
uint32_t hiOfRt = 0;
//#ifdef PALLADIUM_TEST
// hiOfRt = STC_RT_PALLADIUM; // one tod period: 100ms
// do_write(STC_RT_ADDR, STC_RT_PALLADIUM);
//#else
hiOfRt = STC_RT;
do_write(STC_RT_ADDR, STC_RT);
//#endif
UCP_PRINT_EMPTY("RT LO = 0x%x. \r\n", loOfRt);
UCP_PRINT_EMPTY("RT HI = 0x%x. \r\n", hiOfRt);
do_write((&TOD_REG_RT_LO), loOfRt);
do_write((&TOD_REG_RT_HI), hiOfRt);
TOD_REG_CONFIG |= (1<<3); // onepps_output_enable
do_write(STC_ONEPPS_OUT_ADDR, 1);
}

16
public/make/makefile.ecs_rfm_spu0
View File

@ -36,10 +36,16 @@ DIRS_SRC_FOLDER += $(DIR_ECS_SPU0)/top
# ==============================================================================
# common: Output Files and Compilation Rules
# ==============================================================================
#ifeq ($(fronthaul_option),ecpri)
# DEFINES += ECPRI_DISTRIBUTED_BS
#else
# $(info "error fronthaul_option=" $(fronthaul_option))
#endif
ifeq ($(fronthaul_option),ecpri)
DEFINES += ECPRI_DISTRIBUTED_BS
DEFINES += ECS_RFM0
ifeq ($(test_option),yes)
DEFINES += TEST_ENABLE
include $(MAKE_DIR)/makefile.test_fh
endif
else
$(info "error fronthaul_option=" $(fronthaul_option))
endif
include $(MAKE_DIR)/makefile.common

1
public/make/makefile.ecs_rfm_spu1
View File

@ -43,6 +43,7 @@ ifeq ($(fronthaul_option),cpri)
DEFINES += DISTRIBUTED_BS
else ifeq ($(fronthaul_option),ecpri)
DEFINES += ECPRI_DISTRIBUTED_BS
DEFINES += ECS_RFM1
else ifeq ($(fronthaul_option),jesd)
DEFINES += INTEGRATED_BS
else

33
public/test/testbench/fronthaul/inc/ecpri_test.h
View File

@ -14,22 +14,39 @@
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "typedef.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "ecpri_comm.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
typedef struct EcpriTestResult
{
uint32_t test_times; /* test times */
uint32_t succ_times; /* success times */
uint32_t fail_times; /* fail times */
} EcpriTestResult_t;
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* eCPRI test result structure */
typedef struct EcpriTestResult
{
uint32_t test_times; /* test times */
uint32_t succ_times; /* success times */
uint32_t fail_times; /* fail times */
} EcpriTestResult_t;
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI test status check */
extern void ecpri_test_status_check(void);
/* fronthaul data init */
int32_t fh_data_init(void);
/* fronthaul driver init */
int32_t fh_drv_init(void);
/* fronthaul CSU test init */
int32_t fh_csu_test_init(void);
#ifdef ECS_RFM0
/* eCPRI test PL packet process */
extern void ecpri_test_pl_pkt_proc(uint32_t pkt_addr, uint16_t pkt_len);
#endif
/* fronthaul data check */
void fh_data_check(uint32_t times);
/* fronthaul test case */
void fh_test_case(void);
#endif /* _ECPRI_TEST_H_ */

47
public/test/testcases/case100/fronthaul/inc/ecpri_test_case100.h Normal file
View File

@ -0,0 +1,47 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case100.h
* Create Date: 23/08/23
* Description: eCPRI Test Case100 Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/23 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_TEST_CASE100_H_
#define _ECPRI_TEST_CASE100_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_test.h"
#ifdef ECS_RFM0
#include "ecpri_csu.h"
//#include "ecpri_que.h"
#endif
#ifdef ECS_RFM1
#include "ecpri_driver.h"
#endif
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* eCPRI loopback test result structure */
typedef struct EcpriLBTestResult
{
EcpriTestResult_t pl_stat; /* PL statistic */
} EcpriLBTestResult_t;
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
#ifdef ECS_RFM0
/* eCPRI test result update */
void ecpri_test_result_update(void);
#endif
#endif /* _ECPRI_TEST_CASE100_H_ */

2
public/test/testcases/case100/fronthaul/readme.txt Normal file
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@ -0,0 +1,2 @@
场景：eCPRI数据包外环回测试
模式：10G速率

199
public/test/testcases/case100/fronthaul/src/ecpri_test_case100.s.c Normal file
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@ -0,0 +1,199 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case100.s.c
* Create Date: 23/08/23
* Description: eCPRI Test Case100 Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/23 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_test_case100.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
#ifdef ECS_RFM0
/* eCPRI test flag */
uint32_t g_ecpri_test_flag = 0; /* ECS_RFM0: 0xB7E32000(0) */
/* eCPRI loopback test result */
EcpriLBTestResult_t g_ecpri_lb_test_result = {0};
#endif
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: fh_data_init
* Description: fronthaul data init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_data_init(void)
{
#ifdef ECS_RFM0
memset_ucp((void *)&g_ecpri_lb_test_result, 0, sizeof(g_ecpri_lb_test_result));
/* send flag init(symbol interrupt) */
debug_write(ECPRI_DBG_IDX0(64), 0); /* ECS_RFM0: 0xB7E30100(64) */
/* send length init */
debug_write(ECPRI_DBG_IDX0(65), 0); /* ECS_RFM0: 0xB7E30104(65) */
/* eCPRI test flag init */
debug_write(ECPRI_TEST_IDX0(0), g_ecpri_test_flag); /* ECS_RFM0: 0xB7E32000(0) */
#endif
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_drv_init
* Description: fronthaul driver init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_drv_init(void)
{
#ifdef ECS_RFM1
/* eCPRI init */
ecpri_init(ECPRI_OPTION_10G);
#endif
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_csu_test_init
* Description: fronthaul CSU test init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_csu_test_init(void)
{
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_data_check
* Description: fronthaul data check
* Input:
* <name> <type> <desc>
* times uint32_t check times
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void fh_data_check(uint32_t times)
{
#ifdef ECS_RFM0
/* get eCPRI test flag */
g_ecpri_test_flag = do_read_volatile(ECPRI_TEST_ADDR0(0)); /* ECS_RFM0: 0xB7E32000(0) */
if (0 == g_ecpri_test_flag)
{
return;
}
/* eCPRI test result update */
ecpri_test_result_update();
/* clear eCPRI test flag */
g_ecpri_test_flag = 0;
debug_write(ECPRI_TEST_IDX0(0), g_ecpri_test_flag); /* ECS_RFM0: 0xB7E32000(0) */
#endif
}
/**********************************************************************************************************************
* Function: fh_test_case
* Description: fronthaul test case
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void fh_test_case(void)
{
return;
}
#ifdef ECS_RFM0
/**********************************************************************************************************************
* Function: ecpri_test_pl_pkt_proc
* Description: eCPRI test PL packet process
* Input:
* <name> <type> <desc>
* pkt_addr uint32_t packet address
* pkt_len uint16_t packet length
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_pl_pkt_proc(uint32_t pkt_addr, uint16_t pkt_len)
{
/* counter index */
uint8_t i = 0;
/* source MAC */
uint8_t src_mac = 0;
/* destination MAC */
uint8_t dst_mac = 0;
g_ecpri_lb_test_result.pl_stat.test_times++;
/* input para check */
if ((NULL == (void *)pkt_addr) || (ECPRI_PKT_SIZE < pkt_len))
{
g_ecpri_lb_test_result.pl_stat.fail_times++;
return;
}
/* data temporary storage */
(void)ape_csu_dma_1D_G2L_ch2ch3_transfer(pkt_addr,
ECPRI_TEST_ADDR0(4),
pkt_len,
1,
1); /* ECS_RFM0: 0xB7E32010(4) ~ 0xB7E3600C(4099) */
//__ucps2_synch(0);
/* exchange source/destination MAC address */
for (i = 0; i < MAC_ADDR_LEN; i++)
{
dst_mac = do_read_volatile_byte((void *)(ECPRI_TEST_ADDR0(4) + i));
src_mac = do_read_volatile_byte((void *)(ECPRI_TEST_ADDR0(4) + i + MAC_ADDR_LEN));
//__ucps2_synch(0);
do_write_byte((void *)(ECPRI_TEST_ADDR0(4) + i), src_mac);
do_write_byte((void *)(ECPRI_TEST_ADDR0(4) + i + MAC_ADDR_LEN), dst_mac);
}
/* eCPRI CSU send packet */
(void)ecpri_csu_send(ECPRI_TEST_ADDR0(4), pkt_len, 0); /* ECS_RFM0: 0xB7E32010(4) ~ 0xB7E3600C(4099) */
g_ecpri_lb_test_result.pl_stat.succ_times++;
}
/**********************************************************************************************************************
* Function: ecpri_test_result_update
* Description: eCPRI test result update
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_result_update(void)
{
debug_write(ECPRI_TEST_IDX(4100), g_ecpri_lb_test_result.pl_stat.test_times); /* ECS_RFM0: 0xB7E36010(4100) */
debug_write(ECPRI_TEST_IDX(4101), g_ecpri_lb_test_result.pl_stat.succ_times); /* ECS_RFM0: 0xB7E36014(4101) */
debug_write(ECPRI_TEST_IDX(4102), g_ecpri_lb_test_result.pl_stat.fail_times); /* ECS_RFM0: 0xB7E36018(4102) */
}
#endif

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// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case100.s.c
// Author :
// Created On : 2023-12-13
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

56
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/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case101.h
* Create Date: 23/09/07
* Description: eCPRI Test Case101 Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/07 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_TEST_CASE101_H_
#define _ECPRI_TEST_CASE101_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_test.h"
#ifdef ECS_RFM0
#include "ecpri_irq.h"
#endif
#ifdef ECS_RFM1
#include "ecpri_test_case101_antdata.h"
#include "ecpri_driver.h"
#endif
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
#ifdef ECS_RFM0
/* eCPRI test ECS_RFM0 init */
void ecpri_test_ecs0_init(void);
/* eCPRI test PL packet process */
void ecpri_test_pl_pkt_proc(uint32_t pkt_addr, uint16_t pkt_len);
/* eCPRI test ECS_RFM0 status check */
void ecpri_test_ecs0_status_check(void);
/* eCPRI test ECS_RFM0 result update */
void ecpri_test_ecs0_result_update(void);
#endif
#ifdef ECS_RFM1
/* eCPRI test ECS_RFM1 init */
void ecpri_test_ecs1_init(void);
/* eCPRI test ECS_RFM1 status check */
void ecpri_test_ecs1_status_check(void);
/* eCPRI test ECS_RFM1 result update */
void ecpri_test_ecs1_result_update(void);
#endif
#endif /* _ECPRI_TEST_CASE101_H_ */

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/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case101_antdata.h
* Create Date: 23/09/07
* Description: eCPRI Test Case101 Antenna Data Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/07 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_TEST_CASE101_ANTDATA_H_
#define _ECPRI_TEST_CASE101_ANTDATA_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#ifdef ECS_RFM1
#include "mem_sections.h"
#include "ecpri_comm.h"
#endif
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* TDD eCPRI IQ 10bit compress enable */
//#define TDD_ECPRI_COMP_10BIT_EN
/* TDD eCPRI symbol0 length */
#define TDD_ECPRI_SYM0_LEN 4448
/* TDD eCPRI symbol1~symbol13 length */
#define TDD_ECPRI_SYMX_LEN 4384
/* TDD eCPRI symbol0 compress length */
#define TDD_ECPRI_SYM0_COMP_LEN (TDD_ECPRI_SYM0_LEN * 10 / 16)
/* TDD eCPRI symbol1~symbol13 compress length */
#define TDD_ECPRI_SYMX_COMP_LEN (TDD_ECPRI_SYMX_LEN * 10 / 16)
/* TDD eCPRI symbol0 packet length(11,152) */
#define TDD_ECPRI_SYM0_PKT_LEN (TDD_ECPRI_SYM0_COMP_LEN * 4 + 32)
/* TDD eCPRI symbol1~symbol13 packet length(10,992) */
#define TDD_ECPRI_SYMX_PKT_LEN (TDD_ECPRI_SYMX_COMP_LEN * 4 + 32)
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
#ifdef ECS_RFM1
/* TDD eCPRI head structure */
typedef struct TddEcpriHead
{
/* ethernet head */
uint8_t dst_mac[MAC_ADDR_LEN]; /* destination MAC address */
uint8_t src_mac[MAC_ADDR_LEN]; /* source MAC address */
uint32_t vlan_tag; /* VLAN tag */
uint16_t ether_type; /* ethernet type */
/* common head */
uint8_t pkt_concat : 1; /* packet concatenation[0] */
uint8_t reserved : 3; /* reserved[3:1] */
uint8_t ecpri_ver : 4; /* eCPRI version[7:4] */
uint8_t msg_type; /* message type */
uint16_t payload_size; /* payload size */
/* custom head */
uint8_t sector_id : 4; /* sector index[3:0] */
uint8_t cu_port_id : 4; /* CU port index[7:4] */
uint8_t ant_id : 4; /* antenna index[3:0] */
uint8_t cc_id : 4; /* carrier unit[7:4] */
uint8_t seq_id; /* sequence index */
uint8_t subseq_id : 7; /* subsequence index[6:0] */
uint8_t seq_end : 1; /* sequence end flag[7] */
uint8_t fltr_id : 4; /* filter index[3:0] */
uint8_t payload_ver : 3; /* payload version[6:4] */
uint8_t data_dir : 1; /* data direction[7] */
uint8_t frame_id_l; /* frame index low */
uint8_t slot_id : 4; /* slot index[3:0] */
uint8_t subframe_id : 4; /* subframe index[7:4] */
uint8_t sym_id : 6; /* symbol index[5:0] */
uint8_t frame_id_h : 2; /* frame index high[7:6] */
uint8_t udcomp_meth : 4; /* IQ compress method[3:0] */
uint8_t udiq_width : 4; /* IQ bit width indication[7:4] */
uint8_t udcomp_para; /* IQ compress parameter */
} TddEcpriHead_t;
/* TDD eCPRI symbol0 packet structure */
typedef struct TddEcpriSym0Pkt
{
TddEcpriHead_t tdd_ecpri_head; /* TDD ethernet head */
uint32_t tdd_sym0_data[TDD_ECPRI_SYM0_COMP_LEN];
/* TDD symbol0 data */
} TddEcpriSym0Pkt_t;
/* TDD eCPRI symbol1~symbol13 packet structure */
typedef struct TddEcpriSymXPkt
{
TddEcpriHead_t tdd_ecpri_head; /* TDD ethernet head */
uint32_t tdd_symx_data[TDD_ECPRI_SYMX_COMP_LEN];
/* TDD symbol1~symbol13 data */
} TddEcpriSymXPkt_t;
/* TDD eCPRI antenna config data structure */
typedef struct TddEcpriAntCfgData
{
TddEcpriSym0Pkt_t tdd_sym0; /* TDD symbol0 */
TddEcpriSymXPkt_t tdd_symx[ECPRI_SYM_NUM - 1];
/* TDD symbol1~symbol13 */
} TddEcpriAntCfgData_t;
#endif
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
#ifdef ECS_RFM1
/* TDD eCPRI antenna config data */
extern DDR0 TddEcpriAntCfgData_t g_tdd_ecpri_ant_cfg_data[ECPRI_ANT_NUM];
#endif
#endif /* _ECPRI_TEST_CASE101_ANTDATA_H_ */

2
public/test/testcases/case101/fronthaul/readme.txt Normal file
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场景：eCPRI发包测试
模式：10G速率，TDD。

385
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/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case101.s.c
* Create Date: 23/09/07
* Description: eCPRI Test Case101 Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/07 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_test_case101.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
#ifdef ECS_RFM0
/* eCPRI test ECS_RFM0 flag */
uint32_t g_ecpri_test_flag0 = 0; /* ECS_RFM0: 0xB7E32000(0) */
/* eCPRI test antenna index */
uint32_t g_ecpri_test_ant_id = 0; /* ECS_RFM0: 0xB7E32004(1) */
/* eCPRI test symbol index */
uint32_t g_ecpri_test_sym_id = 0; /* ECS_RFM0: 0xB7E32008(2) */
/* eCPRI test ECS_RFM0 result */
EcpriTestResult_t g_ecpri_test_result0 = {0};
#endif
#ifdef ECS_RFM1
/* eCPRI test ECS_RFM1 flag */
uint32_t g_ecpri_test_flag1 = 0; /* ECS_RFM1: 0xB7E42000(0) */
/* eCPRI test ECS_RFM1 result */
EcpriTestResult_t g_ecpri_test_result1 = {0};
#endif
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: fh_data_init
* Description: fronthaul data init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_data_init(void)
{
#ifdef ECS_RFM0
ecpri_test_ecs0_init();
#endif
#ifdef ECS_RFM1
ecpri_test_ecs1_init();
#endif
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_drv_init
* Description: fronthaul driver init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_drv_init(void)
{
#ifdef ECS_RFM1
/* eCPRI init */
ecpri_init(ECPRI_OPTION_10G);
#endif
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_csu_test_init
* Description: fronthaul CSU test init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_csu_test_init(void)
{
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_data_check
* Description: fronthaul data check
* Input:
* <name> <type> <desc>
* times uint32_t check times
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void fh_data_check(uint32_t times)
{
#ifdef ECS_RFM0
ecpri_test_ecs0_status_check();
#endif
#ifdef ECS_RFM1
ecpri_test_ecs1_status_check();
#endif
}
/**********************************************************************************************************************
* Function: fh_test_case
* Description: fronthaul test case
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void fh_test_case(void)
{
return;
}
#ifdef ECS_RFM0
/**********************************************************************************************************************
* Function: ecpri_test_ecs0_init
* Description: eCPRI test ECS_RFM0 init
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs0_init(void)
{
memset_ucp((void *)&g_ecpri_test_result0, 0, sizeof(g_ecpri_test_result0));
/* send flag init(symbol interrupt) */
debug_write(ECPRI_DBG_IDX0(64), 0); /* ECS_RFM0: 0xB7E30100(64) */
/* send length init */
debug_write(ECPRI_DBG_IDX0(65), 0); /* ECS_RFM0: 0xB7E30104(65) */
/* ECS_RFM0 test flag init */
debug_write(ECPRI_TEST_IDX0(0), g_ecpri_test_flag0); /* ECS_RFM0: 0xB7E32000(0) */
/* antenna index init */
debug_write(ECPRI_TEST_IDX0(1), g_ecpri_test_ant_id); /* ECS_RFM0: 0xB7E32004(1) */
/* symbol index init */
debug_write(ECPRI_TEST_IDX0(2), g_ecpri_test_sym_id); /* ECS_RFM0: 0xB7E32008(2) */
}
/**********************************************************************************************************************
* Function: ecpri_test_pl_pkt_proc
* Description: eCPRI test PL packet process
* Input:
* <name> <type> <desc>
* pkt_addr uint32_t packet address
* pkt_len uint16_t packet length
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_pl_pkt_proc(uint32_t pkt_addr, uint16_t pkt_len)
{
return;
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs0_status_check
* Description: eCPRI test ECS_RFM0 status check
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs0_status_check(void)
{
/* return value */
int32_t ret = 0;
/* antenna number */
uint32_t ant_num = 1;
/* symbol number */
uint32_t sym_num = 1;
/* count index */
uint8_t i = 0;
uint8_t j = 0;
/* get ECS_RFM0 test flag */
g_ecpri_test_flag0 = do_read_volatile((void *)ECPRI_TEST_ADDR0(0)); /* ECS_RFM0: 0xB7E32000(0) */
if (0 == g_ecpri_test_flag0)
{
return;
}
/* get test antenna index */
g_ecpri_test_ant_id = do_read_volatile((void *)ECPRI_TEST_ADDR0(1)); /* ECS_RFM0: 0xB7E32004(1) */
if (ECPRI_ANT_NUM <= g_ecpri_test_ant_id)
{
ant_num = ECPRI_ANT_NUM;
}
/* get test symbol index */
g_ecpri_test_sym_id = do_read_volatile((void *)ECPRI_TEST_ADDR0(2)); /* ECS_RFM0: 0xB7E32008(2) */
if (ECPRI_SYM_NUM <= g_ecpri_test_sym_id)
{
sym_num = ECPRI_SYM_NUM;
}
for (i = 0; i < ant_num; i++)
{
for (j = 0; j < sym_num; j++)
{
g_ecpri_test_result0.test_times++;
if ((1 == ant_num) && (1 == sym_num))
{
ret = ecpri_sym_irq_send(g_ecpri_test_ant_id, 0, g_ecpri_test_sym_id);
}
else if ((1 == ant_num) && (ECPRI_SYM_NUM == sym_num))
{
ret = ecpri_sym_irq_send(g_ecpri_test_ant_id, 0, j);
}
else if ((ECPRI_ANT_NUM == ant_num) && (1 == sym_num))
{
ret = ecpri_sym_irq_send(i, 0, g_ecpri_test_sym_id);
}
else
{
ret = ecpri_sym_irq_send(i, 0, j);
}
if (SUCCESS == ret)
{
g_ecpri_test_result0.succ_times++;
}
else
{
g_ecpri_test_result0.fail_times++;
}
}
}
/* eCPRI test ECS_RFM0 result update */
ecpri_test_ecs0_result_update();
/* clear ECS_RFM0 test flag */
g_ecpri_test_flag0 = 0;
debug_write(ECPRI_TEST_IDX0(0), g_ecpri_test_flag0); /* ECS_RFM0: 0xB7E32000(0) */
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs0_result_update
* Description: eCPRI test ECS_RFM0 result update
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs0_result_update(void)
{
debug_write(ECPRI_TEST_IDX0(4), g_ecpri_test_result0.test_times); /* ECS_RFM0: 0xB7E32010(4) */
debug_write(ECPRI_TEST_IDX0(5), g_ecpri_test_result0.succ_times); /* ECS_RFM0: 0xB7E32014(5) */
debug_write(ECPRI_TEST_IDX0(6), g_ecpri_test_result0.fail_times); /* ECS_RFM0: 0xB7E32018(6) */
}
#endif
#ifdef ECS_RFM1
/**********************************************************************************************************************
* Function: ecpri_test_ecs1_init
* Description: eCPRI test ECS_RFM1 init
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs1_init(void)
{
/* antenna index */
uint8_t ant_id = 0;
/* slot type */
uint8_t slot_type = 0;
/* symbol index */
uint8_t sym_id = 0;
/* count index */
uint16_t i = 0;
/* data conversion */
for (ant_id = 0; ant_id < ECPRI_ANT_NUM; ant_id++)
{
for (sym_id = 0; sym_id < ECPRI_SYM_NUM; sym_id++)
{
if (0 == sym_id)
{
HTON_L(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_sym0.tdd_ecpri_head.vlan_tag);
HTON_S(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_sym0.tdd_ecpri_head.ether_type);
HTON_S(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_sym0.tdd_ecpri_head.payload_size);
for (i = 0; i < TDD_ECPRI_SYM0_COMP_LEN; i++)
{
HTON_L(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_sym0.tdd_sym0_data[i]);
}
}
else
{
HTON_L(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_symx[sym_id - 1].tdd_ecpri_head.vlan_tag);
HTON_S(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_symx[sym_id - 1].tdd_ecpri_head.ether_type);
HTON_S(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_symx[sym_id - 1].tdd_ecpri_head.payload_size);
for (i = 0; i < TDD_ECPRI_SYMX_COMP_LEN; i++)
{
HTON_L(g_tdd_ecpri_ant_cfg_data[ant_id].tdd_symx[sym_id - 1].tdd_symx_data[i]);
}
}
}
}
/* eCPRI antenna config */
for (ant_id = 0; ant_id < ECPRI_ANT_NUM; ant_id++)
{
for (slot_type = 0; slot_type < ECPRI_SLOT_TYPE; slot_type++)
{
for (sym_id = 0; sym_id < ECPRI_SYM_NUM; sym_id++)
{
if (0 == sym_id)
{
ecpri_ant_cfg(ant_id, slot_type, sym_id,
(uint32_t)(&g_tdd_ecpri_ant_cfg_data[ant_id].tdd_sym0), TDD_ECPRI_SYM0_PKT_LEN);
}
else
{
ecpri_ant_cfg(ant_id, slot_type, sym_id,
(uint32_t)(&g_tdd_ecpri_ant_cfg_data[ant_id].tdd_symx[sym_id - 1]), TDD_ECPRI_SYMX_PKT_LEN);
}
}
}
}
memset_ucp((void *)&g_ecpri_test_result1, 0, sizeof(g_ecpri_test_result1));
/* ECS_RFM1 test flag init */
debug_write(ECPRI_TEST_IDX1(0), g_ecpri_test_flag1); /* ECS_RFM1: 0xB7E42000(0) */
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs1_status_check
* Description: eCPRI test ECS_RFM1 status check
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs1_status_check(void)
{
/* get ECS_RFM1 test flag */
g_ecpri_test_flag1 = do_read_volatile((void *)ECPRI_TEST_ADDR1(0)); /* ECS_RFM1: 0xB7E42000(0) */
if (0 == g_ecpri_test_flag1)
{
return;
}
/* eCPRI test ECS_RFM1 result update */
ecpri_test_ecs1_result_update();
/* clear ECS_RFM1 test flag */
g_ecpri_test_flag1 = 0;
debug_write(ECPRI_TEST_IDX1(0), g_ecpri_test_flag1); /* ECS_RFM1: 0xB7E42000(0) */
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs1_result_update
* Description: eCPRI test ECS_RFM1 result update
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs1_result_update(void)
{
debug_write(ECPRI_TEST_IDX1(4), g_ecpri_test_result1.test_times); /* ECS_RFM1: 0xB7E42010(4) */
debug_write(ECPRI_TEST_IDX1(5), g_ecpri_test_result1.succ_times); /* ECS_RFM1: 0xB7E42014(5) */
debug_write(ECPRI_TEST_IDX1(6), g_ecpri_test_result1.fail_times); /* ECS_RFM1: 0xB7E42018(6) */
}
#endif

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// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case101.s.c
// Author :
// Created On : 2023-12-13
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

56
public/test/testcases/case102/fronthaul/inc/ecpri_test_case102.h Normal file
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/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case102.h
* Create Date: 23/09/20
* Description: eCPRI Test Case102 Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/20 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_TEST_CASE102_H_
#define _ECPRI_TEST_CASE102_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_test.h"
#ifdef ECS_RFM0
#include "ecpri_irq.h"
#endif
#ifdef ECS_RFM1
#include "ecpri_test_case102_antdata.h"
#include "ecpri_driver.h"
#endif
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
#ifdef ECS_RFM0
/* eCPRI test ECS_RFM0 init */
void ecpri_test_ecs0_init(void);
/* eCPRI test PL packet process */
void ecpri_test_pl_pkt_proc(uint32_t pkt_addr, uint16_t pkt_len);
/* eCPRI test ECS_RFM0 status check */
void ecpri_test_ecs0_status_check(void);
/* eCPRI test ECS_RFM0 result update */
void ecpri_test_ecs0_result_update(void);
#endif
#ifdef ECS_RFM1
/* eCPRI test ECS_RFM1 init */
void ecpri_test_ecs1_init(void);
/* eCPRI test ECS_RFM1 status check */
void ecpri_test_ecs1_status_check(void);
/* eCPRI test ECS_RFM1 result update */
void ecpri_test_ecs1_result_update(void);
#endif
#endif /* _ECPRI_TEST_CASE102_H_ */

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/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case102_antdata.h
* Create Date: 23/09/20
* Description: eCPRI Test Case102 Antenna Data Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/20 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_TEST_CASE102_ANTDATA_H_
#define _ECPRI_TEST_CASE102_ANTDATA_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#ifdef ECS_RFM1
#include "mem_sections.h"
#include "ecpri_comm.h"
#endif
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* FDD eCPRI IQ 10bit compress enable */
//#define FDD_ECPRI_COMP_10BIT_EN
/* FDD eCPRI PRB number */
#define FDD_ECPRI_PRB_NUM 273
/* FDD eCPRI RE number per PRB */
#define FDD_ECPRI_PRB_RE_NUM 12
/* FDD eCPRI symbol0~symbol13 length */
#define FDD_ECPRI_SYMX_LEN (FDD_ECPRI_PRB_NUM * FDD_ECPRI_PRB_RE_NUM)
/* FDD eCPRI symbol0~symbol13 compress length(2,048) */
#define FDD_ECPRI_SYMX_COMP_LEN ((uint32_t)(FDD_ECPRI_SYMX_LEN * 10 / 16 + 1))
/* FDD eCPRI symbol0~symbol13 packet length(8,228) */
#define FDD_ECPRI_SYMX_PKT_LEN (FDD_ECPRI_SYMX_COMP_LEN * 4 + 36)
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
#ifdef ECS_RFM1
/* FDD eCPRI head structure */
typedef struct FddEcpriHead
{
/* ethernet head */
uint8_t dst_mac[MAC_ADDR_LEN]; /* destination MAC address */
uint8_t src_mac[MAC_ADDR_LEN]; /* source MAC address */
uint32_t vlan_tag; /* VLAN tag */
uint16_t ether_type; /* ethernet type */
/* common head */
uint8_t pkt_concat : 1; /* packet concatenation[0] */
uint8_t ecpri_rsv : 3; /* eCPRI reserved[3:1] */
uint8_t ecpri_ver : 4; /* eCPRI version[7:4] */
uint8_t msg_type; /* message type */
uint16_t payload_size; /* payload size */
/* custom head */
uint8_t sector_id : 4; /* sector index[3:0] */
uint8_t cu_port_id : 4; /* CU port index[7:4] */
uint8_t ant_id : 4; /* antenna index[3:0] */
uint8_t cc_id : 4; /* carrier unit[7:4] */
uint8_t seq_id; /* sequence index */
uint8_t subseq_id : 7; /* subsequence index[6:0] */
uint8_t seq_end : 1; /* sequence end flag[7] */
uint8_t fltr_id : 4; /* filter index[3:0] */
uint8_t payload_ver : 3; /* payload version[6:4] */
uint8_t data_dir : 1; /* data direction[7] */
uint8_t frame_id; /* frame index */
uint32_t startPrbc_h : 2; /* start PRB high[1:0] */
uint32_t symInc : 1; /* symbol increase[2] */
uint32_t rb : 1; /* resource block[3] */
uint32_t sectionId : 12; /* section index[15:4] */
uint32_t sym_id : 6; /* symbol index[21:16] */
uint32_t slot_id : 6; /* slot index[27:22] */
uint32_t subframe_id : 4; /* subframe index[31:28] */
uint8_t startPrbc_l; /* start PRB low */
uint8_t numPrbc; /* PRB number */
uint8_t udCompHdr; /* user data compress header */
uint8_t reserved; /* reserved */
} FddEcpriHead_t;
/* FDD eCPRI symbol0~symbol13 packet structure */
typedef struct FddEcpriSymXPkt
{
FddEcpriHead_t fdd_ecpri_head; /* FDD ethernet head */
uint32_t fdd_symx_data[FDD_ECPRI_SYMX_COMP_LEN];
/* FDD symbol0~symbol13 data */
} FddEcpriSymXPkt_t;
/* FDD eCPRI antenna config data structure */
typedef struct FddEcpriAntCfgData
{
FddEcpriSymXPkt_t fdd_symx[ECPRI_SYM_NUM]; /* FDD symbol0~symbol13 */
} FddEcpriAntCfgData_t;
#endif
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
#ifdef ECS_RFM1
/* FDD eCPRI antenna config data */
extern DDR0 FddEcpriAntCfgData_t g_fdd_ecpri_ant_cfg_data[ECPRI_ANT_NUM];
#endif
#endif /* _ECPRI_TEST_CASE102_ANTDATA_H_ */

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场景：eCPRI发包测试
模式：10G速率，FDD。

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/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test_case102.s.c
* Create Date: 23/09/20
* Description: eCPRI Test Case102 Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/09/20 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_test_case102.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
#ifdef ECS_RFM0
/* eCPRI test ECS_RFM0 flag */
uint32_t g_ecpri_test_flag0 = 0; /* ECS_RFM0: 0xB7E32000(0) */
/* eCPRI test antenna index */
uint32_t g_ecpri_test_ant_id = 0; /* ECS_RFM0: 0xB7E32004(1) */
/* eCPRI test symbol index */
uint32_t g_ecpri_test_sym_id = 0; /* ECS_RFM0: 0xB7E32008(2) */
/* eCPRI test ECS_RFM0 result */
EcpriTestResult_t g_ecpri_test_result0 = {0};
#endif
#ifdef ECS_RFM1
/* eCPRI test ECS_RFM1 flag */
uint32_t g_ecpri_test_flag1 = 0; /* ECS_RFM1: 0xB7E42000(0) */
/* eCPRI test ECS_RFM1 result */
EcpriTestResult_t g_ecpri_test_result1 = {0};
#endif
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: fh_data_init
* Description: fronthaul data init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_data_init(void)
{
#ifdef ECS_RFM0
ecpri_test_ecs0_init();
#endif
#ifdef ECS_RFM1
ecpri_test_ecs1_init();
#endif
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_drv_init
* Description: fronthaul driver init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_drv_init(void)
{
#ifdef ECS_RFM1
/* eCPRI init */
ecpri_init(ECPRI_OPTION_10G);
#endif
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_csu_test_init
* Description: fronthaul CSU test init
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
int32_t fh_csu_test_init(void)
{
return SUCCESS;
}
/**********************************************************************************************************************
* Function: fh_data_check
* Description: fronthaul data check
* Input:
* <name> <type> <desc>
* times uint32_t check times
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void fh_data_check(uint32_t times)
{
#ifdef ECS_RFM0
ecpri_test_ecs0_status_check();
#endif
#ifdef ECS_RFM1
ecpri_test_ecs1_status_check();
#endif
}
/**********************************************************************************************************************
* Function: fh_test_case
* Description: fronthaul test case
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void fh_test_case(void)
{
return;
}
#ifdef ECS_RFM0
/**********************************************************************************************************************
* Function: ecpri_test_ecs0_init
* Description: eCPRI test ECS_RFM0 init
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs0_init(void)
{
memset_ucp((void *)&g_ecpri_test_result0, 0, sizeof(g_ecpri_test_result0));
/* send flag init(symbol interrupt) */
debug_write(ECPRI_DBG_IDX0(64), 0); /* ECS_RFM0: 0xB7E30100(64) */
/* send length init */
debug_write(ECPRI_DBG_IDX0(65), 0); /* ECS_RFM0: 0xB7E30104(65) */
/* ECS_RFM0 test flag init */
debug_write(ECPRI_TEST_IDX0(0), g_ecpri_test_flag0); /* ECS_RFM0: 0xB7E32000(0) */
/* antenna index init */
debug_write(ECPRI_TEST_IDX0(1), g_ecpri_test_ant_id); /* ECS_RFM0: 0xB7E32004(1) */
/* symbol index init */
debug_write(ECPRI_TEST_IDX0(2), g_ecpri_test_sym_id); /* ECS_RFM0: 0xB7E32008(2) */
}
/**********************************************************************************************************************
* Function: ecpri_test_pl_pkt_proc
* Description: eCPRI test PL packet process
* Input:
* <name> <type> <desc>
* pkt_addr uint32_t packet address
* pkt_len uint16_t packet length
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_pl_pkt_proc(uint32_t pkt_addr, uint16_t pkt_len)
{
return;
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs0_status_check
* Description: eCPRI test ECS_RFM0 status check
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs0_status_check(void)
{
/* return value */
int32_t ret = 0;
/* antenna number */
uint32_t ant_num = 1;
/* symbol number */
uint32_t sym_num = 1;
/* count index */
uint8_t i = 0;
uint8_t j = 0;
/* get ECS_RFM0 test flag */
g_ecpri_test_flag0 = do_read_volatile((void *)ECPRI_TEST_ADDR0(0)); /* ECS_RFM0: 0xB7E32000(0) */
if (0 == g_ecpri_test_flag0)
{
return;
}
/* get test antenna index */
g_ecpri_test_ant_id = do_read_volatile((void *)ECPRI_TEST_ADDR0(1)); /* ECS_RFM0: 0xB7E32004(1) */
if (ECPRI_ANT_NUM <= g_ecpri_test_ant_id)
{
ant_num = ECPRI_ANT_NUM;
}
/* get test symbol index */
g_ecpri_test_sym_id = do_read_volatile((void *)ECPRI_TEST_ADDR0(2)); /* ECS_RFM0: 0xB7E32008(2) */
if (ECPRI_SYM_NUM <= g_ecpri_test_sym_id)
{
sym_num = ECPRI_SYM_NUM;
}
for (i = 0; i < ant_num; i++)
{
for (j = 0; j < sym_num; j++)
{
g_ecpri_test_result0.test_times++;
if ((1 == ant_num) && (1 == sym_num))
{
ret = ecpri_sym_irq_send(g_ecpri_test_ant_id, 0, g_ecpri_test_sym_id);
}
else if ((1 == ant_num) && (ECPRI_SYM_NUM == sym_num))
{
ret = ecpri_sym_irq_send(g_ecpri_test_ant_id, 0, j);
}
else if ((ECPRI_ANT_NUM == ant_num) && (1 == sym_num))
{
ret = ecpri_sym_irq_send(i, 0, g_ecpri_test_sym_id);
}
else
{
ret = ecpri_sym_irq_send(i, 0, j);
}
if (SUCCESS == ret)
{
g_ecpri_test_result0.succ_times++;
}
else
{
g_ecpri_test_result0.fail_times++;
}
}
}
/* eCPRI test ECS_RFM0 result update */
ecpri_test_ecs0_result_update();
/* clear ECS_RFM0 test flag */
g_ecpri_test_flag0 = 0;
debug_write(ECPRI_TEST_IDX0(0), g_ecpri_test_flag0); /* ECS_RFM0: 0xB7E32000(0) */
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs0_result_update
* Description: eCPRI test ECS_RFM0 result update
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs0_result_update(void)
{
debug_write(ECPRI_TEST_IDX0(4), g_ecpri_test_result0.test_times); /* ECS_RFM0: 0xB7E32010(4) */
debug_write(ECPRI_TEST_IDX0(5), g_ecpri_test_result0.succ_times); /* ECS_RFM0: 0xB7E32014(5) */
debug_write(ECPRI_TEST_IDX0(6), g_ecpri_test_result0.fail_times); /* ECS_RFM0: 0xB7E32018(6) */
}
#endif
#ifdef ECS_RFM1
/**********************************************************************************************************************
* Function: ecpri_test_ecs1_init
* Description: eCPRI test ECS_RFM1 init
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs1_init(void)
{
/* antenna index */
uint8_t ant_id = 0;
/* slot type */
uint8_t slot_type = 0;
/* symbol index */
uint8_t sym_id = 0;
/* count index */
uint16_t i = 0;
/* data conversion */
for (ant_id = 0; ant_id < ECPRI_ANT_NUM; ant_id++)
{
for (sym_id = 0; sym_id < ECPRI_SYM_NUM; sym_id++)
{
HTON_L(g_fdd_ecpri_ant_cfg_data[ant_id].fdd_symx[sym_id].fdd_ecpri_head.vlan_tag);
HTON_S(g_fdd_ecpri_ant_cfg_data[ant_id].fdd_symx[sym_id].fdd_ecpri_head.ether_type);
HTON_S(g_fdd_ecpri_ant_cfg_data[ant_id].fdd_symx[sym_id].fdd_ecpri_head.payload_size);
for (i = 0; i < FDD_ECPRI_SYMX_COMP_LEN; i++)
{
HTON_L(g_fdd_ecpri_ant_cfg_data[ant_id].fdd_symx[sym_id].fdd_symx_data[i]);
}
}
}
/* eCPRI antenna config */
for (ant_id = 0; ant_id < ECPRI_ANT_NUM; ant_id++)
{
for (slot_type = 0; slot_type < ECPRI_SLOT_TYPE; slot_type++)
{
for (sym_id = 0; sym_id < ECPRI_SYM_NUM; sym_id++)
{
ecpri_ant_cfg(ant_id, slot_type, sym_id,
(uint32_t)(&g_fdd_ecpri_ant_cfg_data[ant_id].fdd_symx[sym_id]), FDD_ECPRI_SYMX_PKT_LEN);
}
}
}
memset_ucp((void *)&g_ecpri_test_result1, 0, sizeof(g_ecpri_test_result1));
/* ECS_RFM1 test flag init */
debug_write(ECPRI_TEST_IDX1(0), g_ecpri_test_flag1); /* ECS_RFM1: 0xB7E42000(0) */
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs1_status_check
* Description: eCPRI test ECS_RFM1 status check
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs1_status_check(void)
{
/* get ECS_RFM1 test flag */
g_ecpri_test_flag1 = do_read_volatile((void *)ECPRI_TEST_ADDR1(0)); /* ECS_RFM1: 0xB7E42000(0) */
if (0 == g_ecpri_test_flag1)
{
return;
}
/* eCPRI test ECS_RFM1 result update */
ecpri_test_ecs1_result_update();
/* clear ECS_RFM1 test flag */
g_ecpri_test_flag1 = 0;
debug_write(ECPRI_TEST_IDX1(0), g_ecpri_test_flag1); /* ECS_RFM1: 0xB7E42000(0) */
}
/**********************************************************************************************************************
* Function: ecpri_test_ecs1_result_update
* Description: eCPRI test ECS_RFM1 result update
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_test_ecs1_result_update(void)
{
debug_write(ECPRI_TEST_IDX1(4), g_ecpri_test_result1.test_times); /* ECS_RFM1: 0xB7E42010(4) */
debug_write(ECPRI_TEST_IDX1(5), g_ecpri_test_result1.succ_times); /* ECS_RFM1: 0xB7E42014(5) */
debug_write(ECPRI_TEST_IDX1(6), g_ecpri_test_result1.fail_times); /* ECS_RFM1: 0xB7E42018(6) */
}
#endif

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// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case102.s.c
// Author :
// Created On : 2023-12-13
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}