cpri 相关testcase入库

public/test/testcases/case37/fronthaul/DATA/265_slot0/dl_cpri_comp.dat

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public/test/testcases/case37/fronthaul/inc/cpri_test_case37.h

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+#ifndef _CPRI_TEST_CASE35_H_
+#define _CPRI_TEST_CASE35_H_
+
+// 4 ant, 7DS2U
+#define CPRI_CASE35_IDNUM					6
+#define CPRI_CASE35_SLOT_NUM				20
+
+#define CPRI_CASE35_ID0_SIZE				1
+#define CPRI_CASE35_ID1_SIZE				8
+#define CPRI_CASE35_ID2_SIZE				8
+#define CPRI_CASE35_ID3_SIZE				8
+#define CPRI_CASE35_ID4_SIZE				8
+#define CPRI_CASE35_ID5_SIZE				1
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+#define CPRI_CASE35_TX_SLOT_EVEN_F7SYMBOL_TAG		0
+#define CPRI_CASE35_TX_SLOT_ODD_F7SYMBOL_TAG		1
+#define CPRI_CASE35_TX_SLOT_EVEN_B7SYMBOL_TAG		2
+#define CPRI_CASE35_TX_SLOT_ODD_B7SYMBOL_TAG		3
+
+#define CPRI_CASE35_RX_SLOT_EVEN_F7SYMBOL_TAG		4
+#define CPRI_CASE35_RX_SLOT_ODD_F7SYMBOL_TAG		5
+#define CPRI_CASE35_RX_SLOT_EVEN_B7SYMBOL_TAG		6
+#define CPRI_CASE35_RX_SLOT_ODD_B7SYMBOL_TAG		7
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+#endif
+

public/test/testcases/case37/fronthaul/readme.txt

@@ -0,0 +1,3 @@
+CK的自研rru：
+
+OTIC协议中图12，10g速率下4T4R单NR小区 模式：NR TDD 256QAM测试

public/test/testcases/case37/fronthaul/src/cpri_test_case37.s.c

@@ -0,0 +1,431 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case35.c
+// Author        : xinxin.li
+// Created On    : 2023-01-12s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+#include "cpri_csu_nr_7ds2u.h"
+#include "cpri_test_case37.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+extern uint32_t compressData[1920];
+extern uint32_t antData0[61440];
+extern uint32_t antData1[61440];
+extern uint32_t antData2[61440];
+extern uint32_t antData3[61440];
+
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t gCpriTestMode;
+//extern uint32_t           CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+extern volatile uint32_t gVendorFlag;
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag = 0;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+	//Get_Cpri_OptionId();//get cpri option value
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_LOG("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	stCpriCsuCmdFifoInfo		txTestCmdFifo;
+	stCpriCsuCmdFifoInfo		rxTestCmdFifo;
+	
+	cpri_csu_axc_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
+	cpri_csu_axcctrl_init_timing();
+	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
+
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
+void HeaderTxRam_data_init()
+{
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)//NS=3,each BF only bit[127:0]
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#endif
+	for(int i=0;i<48*2;i++)//NS=8~19,each BF only bit[31:0]
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;
+	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;
+
+	uint32_t cpyCnt = 0;
+	// valid data
+	// compress factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;
+		
+		if (0 == idSlot)	// even slot
+		{
+			srcAddr = (uint32_t)(&compressData[0]);
+			dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
+		}
+		else				// odd slot
+		{
+			srcAddr = (uint32_t)(&compressData[1920>>1]);
+			dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+	}
+
+	// IQ data	
+	for (idID = 1; idID < 5; idID++)
+//	for (idID = 1; idID < 2; idID++)
+	{
+		bfByteCnt = 64;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[0]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[0]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[0]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[0]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[0]);	
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[15376]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[15376]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[15376]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[15376]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[15376]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[30720]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[30720]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[30720]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[30720]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[30720+15376]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[30720+15376]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[30720+15376]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[30720+15376]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720+15376]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+				cpyCnt++;
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+			}
+		}
+	}
+}
+
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t dstAddr = 0;
+	uint32_t dataLen = 0;
+	uint8_t bitOffset = 0;
+	uint32_t totalSlotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	uint32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	uint32_t *pAntData = antData0;
+	for (uint32_t i = 0; i < 5; i++)
+	{
+		gCompSlotIdCnt++;
+		slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+		idVal = i;
+		bfStart = 0;
+
+		switch(i)
+		{
+			case 1:
+				pAntData = antData0;break;
+			case 2:
+				pAntData = antData1;break;	
+			case 3:
+				pAntData = antData2;break;
+			case 4:
+				pAntData = antData3;break;
+		}
+
+		
+		if ((slotId >=0) && (slotId <= 6))
+		{
+			slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+			slotVal = slotId & 0x1;
+			
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else
+			{
+				bitOffset = 6;	// one BF, 64B
+				bfWordCnt = 64>>2;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (7 == slotId)		// compare S slot, odd slot
+		{
+			bfStart = 0;
+			slotBfCnt = LONGCP_BF_CNT + 5 * SHORTCP_BF_CNT;
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset);
+			}
+			else
+			{
+				bitOffset = 6;	// one BF, 64B
+				bfWordCnt = (64>>2);
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+		}
+
+		if (0 == i)	// compress factor
+		{
+			for (uint32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if (7 == slotId)
+					{
+						dstAddr = 960 + idBf*bfWordCnt + idWord;
+					}
+					else
+					{
+						dstAddr = slotVal*(1920>>1) + idBf*bfWordCnt + idWord;
+					}
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					recvVal = *((uint32_t*)recvAddr);
+					compVal = compressData[dstAddr];
+					if ((recvVal != compVal) || (recvVal != compVal))
+					{
+//						debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr);		// 0x320
+//						debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr);		// 0x324
+//						debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+//						debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal);		// 0x32c
+//						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+			//		do_write(a, gCompSlotIdCnt); // addr 
+			//		do_write(a, gErrSlotIdCnt);
+				}
+			}
+		}
+		else		// axc data
+		{
+			for (uint32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if (7 == slotId)
+					{
+						dstAddr = 30720 +idBf*bfWordCnt + idWord;
+					}
+					else
+					{
+						dstAddr = slotVal*30720 + idBf*bfWordCnt + idWord;
+					}
+//					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord + 0x10);
+					//recvVal = *((uint32_t*)recvAddr);
+					recvVal = do_read_volatile(recvAddr);
+					//compVal = pAntData[dstAddr];
+					compVal = do_read_volatile(pAntData+dstAddr);
+
+					
+					if (recvVal != compVal)
+					{
+						//debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr);		// 0x320
+						//debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr);		// 0x324
+						//debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+						//debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal);		// 0x32c
+
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), srcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), dstAddr);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt); // 0x314
+	}
+}
+
+void Cpri_Header_Rx(void)
+{
+	
+}
+
+
+
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (40 <= pMtimerInt->csuEnCnt)
+	{
+	#if 0
+		if (64 == gCpriTimerPara.csuEnCnt)
+		{
+			AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+			//AUX_Rx_enable(0x2);
+		}
+	#endif		
+		gCompWordCnt = 0;
+		for (int i = 0; i < 7; i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		Cpri_Header_Rx();
+	}
+	
+}
+
+
+

public/test/testcases/case37/osp/src/ape_test_case37.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case38/fronthaul/DATA/265_slot0/dl_cpri_comp.dat

@@ -0,0 +1,961 @@
+0x00050004, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00060005, 
+0x00050005, 
+0x00050005, 
+0x00040004, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050004, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050004, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050004, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00040004, 
+0x00050004, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
+0x00040005, 
+0x00050005, 
+0x00060005, 
+0x00050004, 
+0x00050005, 
+0x00050005, 
+0x00050005, 
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+          , 

public/test/testcases/case38/fronthaul/inc/cpri_test_case38.h

@@ -0,0 +1,52 @@
+#ifndef _CPRI_TEST_CASE38_H_
+#define _CPRI_TEST_CASE38_H_
+
+// 4 ant, 7DS2U
+#define CPRI_CASE38_IDNUM					6
+#define CPRI_CASE38_SLOT_NUM				20
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+#if 0
+#define CPRI_CASE38_ID0_SIZE				1
+#define CPRI_CASE38_ID1_SIZE				8
+#define CPRI_CASE38_ID2_SIZE				8
+#define CPRI_CASE38_ID3_SIZE				8
+#define CPRI_CASE38_ID4_SIZE				8
+#define CPRI_CASE38_ID5_SIZE				1
+
+#define CPRI_CASE38_TX_SLOT_EVEN_F7SYMBOL_TAG		0
+#define CPRI_CASE38_TX_SLOT_ODD_F7SYMBOL_TAG		1
+#define CPRI_CASE38_TX_SLOT_EVEN_B7SYMBOL_TAG		2
+#define CPRI_CASE38_TX_SLOT_ODD_B7SYMBOL_TAG		3
+
+#define CPRI_CASE38_RX_SLOT_EVEN_F7SYMBOL_TAG		4
+#define CPRI_CASE38_RX_SLOT_ODD_F7SYMBOL_TAG		5
+#define CPRI_CASE38_RX_SLOT_EVEN_B7SYMBOL_TAG		6
+#define CPRI_CASE38_RX_SLOT_ODD_B7SYMBOL_TAG		7
+#endif
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+#endif
+

public/test/testcases/case38/fronthaul/note.txt

@@ -0,0 +1,4 @@
+CK 典格的pru
+1. 偶时隙发256QAM数据；
+2. 只有天线0有数据，每个数据文件都包含2个时隙：偶时隙+奇时隙数据，一共61440个字；
+3. #if 1 条件下，该工程中运行的数据是物理层提供的3.1.A的slot0数据；#if 0条件下，运行的数据是算法部提供的256QAM数据

public/test/testcases/case38/fronthaul/src/cpri_test_case38.s.c

@@ -0,0 +1,428 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case35.c
+// Author        : xinxin.li
+// Created On    : 2023-01-12s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+#include "cpri_csu_nr_7ds2u.h"
+#include "cpri_test_case38.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+extern uint32_t compressData[1920];
+extern uint32_t antData0[61440];
+extern uint32_t antData1[61440];
+extern uint32_t antData2[61440];
+extern uint32_t antData3[61440];
+
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t gCpriTestMode;
+//extern uint32_t           CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+extern volatile uint32_t gVendorFlag;
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag = 0;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+	//Get_Cpri_OptionId();//get cpri option value
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_LOG("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	stCpriCsuCmdFifoInfo		txTestCmdFifo;
+	stCpriCsuCmdFifoInfo		rxTestCmdFifo;
+	
+	cpri_csu_axc_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
+	cpri_csu_axcctrl_init_timing();
+	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
+
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
+void HeaderTxRam_data_init()
+{
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)//NS=3,each BF only bit[127:0]
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#endif
+	for(int i=0;i<48*2;i++)//NS=8~19,each BF only bit[31:0]
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;
+	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;
+
+	uint32_t cpyCnt = 0;
+	// valid data
+	// compress factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;
+		
+		if (0 == idSlot)	// even slot
+		{
+			srcAddr = (uint32_t)(&compressData[0]);
+			dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
+		}
+		else				// odd slot
+		{
+			srcAddr = (uint32_t)(&compressData[1920>>1]);
+			dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+	}
+
+	// IQ data	
+	for (idID = 1; idID < 5; idID++)
+//	for (idID = 1; idID < 2; idID++)
+	{
+		bfByteCnt = 64;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[0]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[0]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[0]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[0]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[0]);	
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[15376]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[15376]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[15376]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[15376]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[15376]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[30720]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[30720]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[30720]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[30720]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[30720+15376]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[30720+15376]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[30720+15376]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[30720+15376]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720+15376]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+				cpyCnt++;
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+			}
+		}
+	}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t dstAddr = 0;
+	uint32_t dataLen = 0;
+	uint8_t bitOffset = 0;
+	uint32_t totalSlotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	uint32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	uint32_t *pAntData = antData0;
+	for (uint32_t i = 0; i < 5; i++)
+	{
+		gCompSlotIdCnt++;
+		slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+		idVal = i;
+		bfStart = 0;
+
+		switch(i)
+		{
+			case 1:
+				pAntData = antData0;break;
+			case 2:
+				pAntData = antData1;break;	
+			case 3:
+				pAntData = antData2;break;
+			case 4:
+				pAntData = antData3;break;
+		}
+
+		
+		if ((slotId >=0) && (slotId <= 6))
+		{
+			slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+			slotVal = slotId & 0x1;
+			
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else
+			{
+				bitOffset = 6;	// one BF, 64B
+				bfWordCnt = 64>>2;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (7 == slotId)		// compare S slot, odd slot
+		{
+			bfStart = 0;
+			slotBfCnt = LONGCP_BF_CNT + 5 * SHORTCP_BF_CNT;
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset);
+			}
+			else
+			{
+				bitOffset = 6;	// one BF, 64B
+				bfWordCnt = (64>>2);
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+		}
+
+		if (0 == i)	// compress factor
+		{
+			for (uint32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if (7 == slotId)
+					{
+						dstAddr = 960 + idBf*bfWordCnt + idWord;
+					}
+					else
+					{
+						dstAddr = slotVal*(1920>>1) + idBf*bfWordCnt + idWord;
+					}
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					recvVal = *((uint32_t*)recvAddr);
+					compVal = compressData[dstAddr];
+					if ((recvVal != compVal) || (recvVal != compVal))
+					{
+//						debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr);		// 0x320
+//						debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr);		// 0x324
+//						debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+//						debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal);		// 0x32c
+//						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+			//		do_write(a, gCompSlotIdCnt); // addr 
+			//		do_write(a, gErrSlotIdCnt);
+				}
+			}
+		}
+		else		// axc data
+		{
+			for (uint32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if (7 == slotId)
+					{
+						dstAddr = 30720 +idBf*bfWordCnt + idWord;
+					}
+					else
+					{
+						dstAddr = slotVal*30720 + idBf*bfWordCnt + idWord;
+					}
+//					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord + 0x10);
+					//recvVal = *((uint32_t*)recvAddr);
+					recvVal = do_read_volatile(recvAddr);
+					//compVal = pAntData[dstAddr];
+					compVal = do_read_volatile(pAntData+dstAddr);
+
+					
+					if (recvVal != compVal)
+					{
+						//debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr);		// 0x320
+						//debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr);		// 0x324
+						//debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+						//debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal);		// 0x32c
+
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), srcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), dstAddr);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt); // 0x314
+	}
+}
+
+
+void Cpri_Header_Rx(void)
+{
+	
+}
+
+
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (40 <= pMtimerInt->csuEnCnt)
+	{
+	#if 0
+		if (64 == gCpriTimerPara.csuEnCnt)
+		{
+			AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+			//AUX_Rx_enable(0x2);
+		}
+	#endif		
+		gCompWordCnt = 0;
+		for (int i = 0; i < 7; i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		Cpri_Header_Rx();
+	}
+	
+}
+
+

public/test/testcases/case38/osp/src/ape_test_case38.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case39/fronthaul/inc/cpri_test_case39.h

@@ -0,0 +1,51 @@
+#ifndef _CPRI_TEST_CASE39_H_
+#define _CPRI_TEST_CASE39_H_
+
+// 4 ant, 7DS2U
+#define CPRI_CASE39_IDNUM					6
+#define CPRI_CASE39_SLOT_NUM				20
+
+#define CPRI_CASE39_ID0_SIZE				1
+#define CPRI_CASE39_ID1_SIZE				8
+#define CPRI_CASE39_ID2_SIZE				8
+#define CPRI_CASE39_ID3_SIZE				8
+#define CPRI_CASE39_ID4_SIZE				8
+#define CPRI_CASE39_ID5_SIZE				1
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+#define CPRI_CASE39_TX_SLOT_EVEN_F7SYMBOL_TAG		0
+#define CPRI_CASE39_TX_SLOT_ODD_F7SYMBOL_TAG		1
+#define CPRI_CASE39_TX_SLOT_EVEN_B7SYMBOL_TAG		2
+#define CPRI_CASE39_TX_SLOT_ODD_B7SYMBOL_TAG		3
+
+#define CPRI_CASE39_RX_SLOT_EVEN_F7SYMBOL_TAG		4
+#define CPRI_CASE39_RX_SLOT_ODD_F7SYMBOL_TAG		5
+#define CPRI_CASE39_RX_SLOT_EVEN_B7SYMBOL_TAG		6
+#define CPRI_CASE39_RX_SLOT_ODD_B7SYMBOL_TAG		7
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+#endif
+

public/test/testcases/case39/fronthaul/note.txt

@@ -0,0 +1,3 @@
+单音，带压缩，奇偶时隙数据一样
+四个天线的频点不一样，分别是：120K，150K，180K，210K
+四个天线的压缩因子不一样

public/test/testcases/case39/fronthaul/src/cpri_test_case39.s.c

@@ -0,0 +1,426 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case39.c
+// Author        : xinxin.li
+// Created On    : 2023-05-06s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+#include "cpri_csu_nr_7ds2u.h"
+#include "cpri_test_case39.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+extern uint32_t compressData[1920];
+extern uint32_t antData0[61440];
+extern uint32_t antData1[61440];
+extern uint32_t antData2[61440];
+extern uint32_t antData3[61440];
+
+extern uint32_t 		gCpriTestMode;
+//extern stCpriTimerPara	gCpriTimerPara;
+extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t gCpriTestMode;
+//extern uint32_t           CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+extern volatile uint32_t gVendorFlag;
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag = 0;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+	//Get_Cpri_OptionId();//get cpri option value
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_LOG("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	stCpriCsuCmdFifoInfo		txTestCmdFifo;
+	stCpriCsuCmdFifoInfo		rxTestCmdFifo;
+	
+	cpri_csu_axc_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
+	cpri_csu_axcctrl_init_timing();
+	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
+
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
+void HeaderTxRam_data_init()
+{
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)//NS=3,each BF only bit[127:0]
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#endif
+	for(int i=0;i<48*2;i++)//NS=8~19,each BF only bit[31:0]
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;
+	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;
+
+	uint32_t cpyCnt = 0;
+	// valid data
+	// compress factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;
+		
+		if (0 == idSlot)	// even slot
+		{
+			srcAddr = (uint32_t)(&compressData[0]);
+			dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
+		}
+		else				// odd slot
+		{
+			srcAddr = (uint32_t)(&compressData[1920>>1]);
+			dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+	}
+
+	// IQ data	
+	for (idID = 1; idID < 5; idID++)
+//	for (idID = 1; idID < 2; idID++)
+	{
+		bfByteCnt = 64;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[0]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[0]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[0]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[0]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[0]);	
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[15376]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[15376]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[15376]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[15376]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[15376]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[30720]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[30720]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[30720]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[30720]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[30720+15376]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[30720+15376]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[30720+15376]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[30720+15376]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720+15376]);
+					dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + (idID-1)*dataLen;
+				}
+				
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+				cpyCnt++;
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+			}
+		}
+	}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t dstAddr = 0;
+	uint32_t dataLen = 0;
+	uint8_t bitOffset = 0;
+	uint32_t totalSlotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	uint32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	uint32_t *pAntData = antData0;
+	for (uint32_t i = 0; i < 5; i++)
+	{
+		gCompSlotIdCnt++;
+		slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+		idVal = i;
+		bfStart = 0;
+
+		switch(i)
+		{
+			case 1:
+				pAntData = antData0;break;
+			case 2:
+				pAntData = antData1;break;	
+			case 3:
+				pAntData = antData2;break;
+			case 4:
+				pAntData = antData3;break;
+		}
+
+		
+		if ((slotId >=0) && (slotId <= 6))
+		{
+			slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+			slotVal = slotId & 0x1;
+			
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else
+			{
+				bitOffset = 6;	// one BF, 64B
+				bfWordCnt = 64>>2;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (7 == slotId)		// compare S slot, odd slot
+		{
+			bfStart = 0;
+			slotBfCnt = LONGCP_BF_CNT + 5 * SHORTCP_BF_CNT;
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_COMPRESS_ADDR+slotId*(totalSlotBfCnt<<bitOffset);
+			}
+			else
+			{
+				bitOffset = 6;	// one BF, 64B
+				bfWordCnt = (64>>2);
+				srcAddr = CPRI_NR7DS2U_RX_DUMMY_AXC1DATA_ADDR+((i-1)*CPRI_NR7DS2U_RX_DUMMY_AXCDATA_LEN)+slotId*(totalSlotBfCnt<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+		}
+
+		if (0 == i)	// compress factor
+		{
+			for (uint32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if (7 == slotId)
+					{
+						dstAddr = 960 + idBf*bfWordCnt + idWord;
+					}
+					else
+					{
+						dstAddr = slotVal*(1920>>1) + idBf*bfWordCnt + idWord;
+					}
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					recvVal = *((uint32_t*)recvAddr);
+					compVal = compressData[dstAddr];
+					if ((recvVal != compVal) || (recvVal != compVal))
+					{
+//						debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr);		// 0x320
+//						debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr);		// 0x324
+//						debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+//						debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal);		// 0x32c
+//						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+			//		do_write(a, gCompSlotIdCnt); // addr 
+			//		do_write(a, gErrSlotIdCnt);
+				}
+			}
+		}
+		else		// axc data
+		{
+			for (uint32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if (7 == slotId)
+					{
+						dstAddr = 30720 +idBf*bfWordCnt + idWord;
+					}
+					else
+					{
+						dstAddr = slotVal*30720 + idBf*bfWordCnt + idWord;
+					}
+//					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord + 0x10);
+					//recvVal = *((uint32_t*)recvAddr);
+					recvVal = do_read_volatile(recvAddr);
+					//compVal = pAntData[dstAddr];
+					compVal = do_read_volatile(pAntData+dstAddr);
+
+					
+					if (recvVal != compVal)
+					{
+						//debug_write((DBG_DDR_IDX_DRV_BASE+200+((gErrSlotIdCnt<<2)&0x3F)), dstAddr);		// 0x320
+						//debug_write((DBG_DDR_IDX_DRV_BASE+201+((gErrSlotIdCnt<<2)&0x3F)), recvAddr);		// 0x324
+						//debug_write((DBG_DDR_IDX_DRV_BASE+202+((gErrSlotIdCnt<<2)&0x3F)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+						//debug_write((DBG_DDR_IDX_DRV_BASE+203+((gErrSlotIdCnt<<2)&0x3F)), recvVal);		// 0x32c
+
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), srcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), dstAddr);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt); // 0x314
+	}
+}
+
+
+void Cpri_Header_Rx(void)
+{
+	
+}
+
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (40 <= pMtimerInt->csuEnCnt)
+	{
+	#if 0
+		if (64 == gCpriTimerPara.csuEnCnt)
+		{
+			AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+			//AUX_Rx_enable(0x2);
+		}
+	#endif		
+		gCompWordCnt = 0;
+		for (int i = 0; i < 7; i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		Cpri_Header_Rx();
+	}
+	
+}

public/test/testcases/case39/osp/src/ape_test_case39.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case60/fronthaul/inc/cpri_test_case60.h

@@ -0,0 +1,33 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE60_SLOT_NUM				20
+
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcases/case60/fronthaul/inc/lte_mem_def.h

@@ -0,0 +1,199 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+typedef struct
+{
+    uint32_t sampling_rate;
+
+
+    uint8_t tatol_tx_ants;
+    uint8_t tatol_rx_ants;
+    uint16_t rev;
+
+
+    uint8_t num_tx0_ants;
+    uint8_t num_tx1_ants;
+    uint8_t num_rx0_ants;
+    uint8_t num_rx1_ants;
+
+
+    //tx的链表地址
+    uint32_t tx_even_link_addr;
+    uint32_t tx_odd_link_addr;
+    uint32_t tx_last_link_addr;
+
+
+    //rx的链表地址
+    uint32_t rx_first_link_addr;
+    uint32_t rx_even_link_addr;
+    uint32_t rx_odd_link_addr;
+}phy_csu_link_info_t;
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0--1M*********************************************/
+//len define(Byte)
+#define SM0_PHY_MSG_BUFFER_LEN               0x00000400  //1024
+#define SM0_PHY_TASKS_MGR_LEN                0x00000100  //256
+#define SM0_LTE_CELL0_FAPI_MSG_LEN           0x00004B00  //19200，实际使用17588
+#define SM0_LTE_PBCH_REMAPPING_LUT_LEN       0x00000C64  //4+2*288*4+72*4+72*2*4=3172
+#define SM0_LTE_PDCCH_REMAPPING_LUT_LEN      0x00003840  //(1200+2400+3600)*2=14400
+#define SM0_LTE_PHICH_REMAPPING_LUT_LEN      0x00000480  //6*50*4=1200
+#define SM0_LTE_PCFICH_REMAPPING_LUT_LEN     0x00000020  //8*4=32
+#define SM0_LTE_CRS_REMAPPING_LUT_LEN        0x00000A50  //2*110*3*4=2640
+//#define SM0_LTE_PDSCH_RBG_SUBSET_TABLE_LEN   0x00000064  //100
+//#define SM0_LTE_PDSCH_VRB_PRB_TABLE_LEN      0x00000190  //400
+#define SM0_LTE_CELL0_EVEN_TX_LEN            0x0003C000  //30720*2*4=245760
+#define SM0_LTE_CELL0_ODD_TX_LEN             0x0003C000  //30720*2*4=245760
+#define SM0_ERROR_RECORD_CNT_LEN             0x00003000  //12288
+#define SM0_STATE_RECORD_CNT_LEN             0x00002600  //9728
+
+//addr base define
+#define SM0_PHY_MSG_BUFFER_ADDR              (SM0_BASE)
+#define SM0_PHY_TASKS_MGR_ADDR               (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+#define SM0_LTE_CELL0_FAPI_MSG_ADDR          (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_LTE_PBCH_REMAPPING_LUT_ADDR      (SM0_LTE_CELL0_FAPI_MSG_ADDR + SM0_LTE_CELL0_FAPI_MSG_LEN)
+#define SM0_LTE_PDCCH_REMAPPING_LUT_ADDR     (SM0_LTE_PBCH_REMAPPING_LUT_ADDR + SM0_LTE_PBCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PHICH_REMAPPING_LUT_ADDR     (SM0_LTE_PDCCH_REMAPPING_LUT_ADDR + SM0_LTE_PDCCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PCFICH_REMAPPING_LUT_ADDR    (SM0_LTE_PHICH_REMAPPING_LUT_ADDR + SM0_LTE_PHICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CRS_REMAPPING_LUT_ADDR       (SM0_LTE_PCFICH_REMAPPING_LUT_ADDR + SM0_LTE_PCFICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_EVEN_TX_ADDR           (SM0_LTE_CRS_REMAPPING_LUT_ADDR + SM0_LTE_CRS_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_ODD_TX_ADDR            (SM0_LTE_CELL0_EVEN_TX_ADDR + SM0_LTE_CELL0_EVEN_TX_LEN)
+//方便联查询，先写死，后续改动需计算地址
+#define SM0_ERROR_RECORD_CNT_ADDR            (0x9DE0000)//(SM0_LTE_CELL0_ODD_TX_ADDR + SM0_LTE_CELL0_ODD_TX_LEN)
+#define SM0_STATE_RECORD_CNT_ADDR            (0x9DF0000)//(SM0_ERROR_RECORD_CNT_ADDR + SM0_ERROR_RECORD_CNT_LEN)
+
+/************************************SM1---1M ***********************************************/ 
+//len define(Byte)
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN    0x00020D00  //14*2*1200*4=134400
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_LEN     0x00020D00  //14*2*1200*4=134400
+
+//addr base define
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR   (SM1_BASE)
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_ADDR    (SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR + SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN)
+
+#define SM1_PHY_USED_ADDR                    (SM1_BASE + 0x50000) //PHY使用的SM结束地址，暂时写死
+/************************************SM2--1.5M***********************************************/
+
+
+/************************************SM3--1.5M***********************************************/
+
+
+/************************************SM4--1.5M***********************************************/
+
+
+/************************************SM5--1.5M***********************************************/
+
+
+/**************************************DDR***************************************************/
+//base
+#define DDR_PHY_BASE                         (0x6BC00000) //共579M可用0x6BC00000-0x8FFFFFFF
+
+//len
+#define DDR_LTE_CELL0_RX_LEN                 0x0003C000   //一体化(30720*2)*4 = 240K
+#define DDR_LTE_PDSCH_CODING_TABLE_LEN       0x002665D0   //PDSCH编码表 2.4M
+
+//addr
+#define DDR_LTE_CELL0_RX_ADDR                (0x89000000) //TESTMAC测试阶段暂时写死，后续根据使用情况规划到SM或DDR
+#define DDR_LTE_PDSCH_CODING_TABLE_ADDR      (DDR_LTE_CELL0_RX_ADDR + DDR_LTE_CELL0_RX_LEN)
+
+// 6BEB0000 = 0x6BC00000 + 0x2B0000
+#define DDR_PHY_UESD_ADDR                    (DDR_PHY_BASE + 0x2B0000) //PHY使用的DDR结束地址，暂时写死
+#define DDR_PDSCH_DUMP_DATA_START            (DDR_PHY_UESD_ADDR) 
+
+/*************test addr start*************/
+
+#define LTE_TX_BASE_ADDR     (0xB4500000)  // 
+#define LTE_RX_BASE_ADDR     (0xB4800000)  // 
+
+#define NR_COM_FACT_LEN      (0x1E00) //NR压缩因子长度
+#define LTE_COM_FACT_LEN     (0xF00) //LTE压缩因子长度
+
+#define NR_AXC_DATA_LEN      (0x78000) //NR天线数据长度
+#define LTE_AXC_DATA_LEN     (0x1E000) //LTE天线数据长度
+
+//#define NR_AGC_LEN           (0x1E00) //NR AGC长度
+//#define LTE_AGC_LEN          (0xF00) //LTE AGC长度
+#define    AGC_LEN           (0x2D00) //NR AGC长度
+
+//Tx
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_TX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4500000
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI      (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR+ LTE_COM_FACT_LEN )  // LTE偶时隙天线数据 0xB4500F00
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI + LTE_AXC_DATA_LEN )  // LTE奇时隙压缩因子 0xB451EF00
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI       (SM0_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN )  // LTE奇时隙天线数据 0xB451FE00
+
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI      + LTE_AXC_DATA_LEN ) // NR偶时隙压缩因子 0xB453DE00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0  (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN )  // NR偶时隙天线数据0和1 0xB453FC00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1  (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN )  // NR偶时隙天线数据2和3 0xB45B7C00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )  // NR偶时隙AGC 0xB462FC00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR  + NR_AGC_LEN )       // LTE偶时隙AGC 0xB4631A00
+#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )         //AGC 0xB462FC00
+
+
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR  +  AGC_LEN )         // NR奇时隙压缩因子        0xB4632900
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0   (SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR  + NR_COM_FACT_LEN )  // NR奇时隙天线数据0和1         0xB4634700
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1   (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0  + NR_AXC_DATA_LEN )  // NR奇时隙天线数据2和3         0xB46AC700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // NR奇时隙AGC         0xB4724700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR  + NR_AGC_LEN )        // LTE奇时隙AGC       0xB4726500
+#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // 奇时隙AGC         0xB4724700
+
+//Rx
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_RX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4800000
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI      (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR + LTE_COM_FACT_LEN)   // LTE偶时隙天线数据          0xB4800F00
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)    // LTE奇时隙压缩因子          0xB481EF00
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI       (SM1_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN)    // LTE奇时隙天线数据          0xB481FE00
+
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)      // NR偶时隙压缩因子            0xB483DE00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0  (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)  // NR偶时隙天线数据0和1 0xB483FC00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1  (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)  // NR偶时隙天线数据2和3 0xB48B7C00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)  // NR偶时隙AGC             0xB492FC00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR + NR_AGC_LEN)        // LTE偶时隙AGC            0xB4931A00
+#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   //  偶时隙AGC             0xB492FC00
+
+
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR + AGC_LEN)          // NR奇时隙压缩因子            0xB4932900
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0   (SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)   // NR奇时隙天线数据0和1         0xB4934700
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1   (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)   // NR奇时隙天线数据2和3 0xB49AC700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // NR奇时隙AGC             0xB4a24700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR + NR_AGC_LEN)         // LTE奇时隙AGC            0xB4a26500
+#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // 奇时隙AGC             0xB4a24700
+
+/*************test addr end***************/
+
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+void Config_Cpri_Csu_Lte();
+
+
+#endif

public/test/testcases/case60/fronthaul/src/cpri_test_case60.s.c

@@ -0,0 +1,813 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case60.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "lte_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+extern volatile uint32_t gVendorFlag;
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+//	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+//	uint8_t idSymbol = 0;
+	uint16_t idBF = 0;
+	uint16_t idWord = 0;
+
+	uint32_t* pSrcAddr = 0;
+//	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	//uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;//1920
+	uint32_t  slotBfCnt = 256*15;//3840,1ms是一个时隙
+//	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//961
+//	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//959
+//	uint32_t  symbolBfCnt = 0;
+//	uint32_t  idSlotBf = 0;
+	uint32_t  val = 0;
+	
+	//uint32_t* srcImData = dmalloc(10240, DM0);
+	
+	//debug_write((DBG_DDR_IDX_DRV_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304
+
+	uint32_t cpyCnt = 0;
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	cpyCnt++;
+
+	// valid data
+	/******* compress factor********/
+	//NR
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;//NR:2B		
+		//pSrcAddr = srcImData;
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+		}
+		pSrcAddr = ((uint32_t*)dstAddr);
+		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
+	//	for (idBF = 0; idBF < slotBfCnt; idBF++)	// basic frame
+		{
+			val = (idSlot<<28) | (0<<24) | ((idBF<<1)<<8) | (0);
+		//	*pSrcAddr = val;
+			do_write(((uint32_t)pSrcAddr), val);			
+			pSrcAddr++;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		
+//		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+	}
+	//LTE
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			bfByteCnt = 1;//LTE:1B		
+		//	pSrcAddr = srcImData;
+			if (0 == idSlot)	// even slot
+			{
+				dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR;
+			}
+			else				// odd slot
+			{
+				dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR;
+			}
+			pSrcAddr = ((uint32_t*)dstAddr);
+			for (idBF = 0; idBF < (slotBfCnt>>2); idBF++)	// basic frame
+		//	for (idBF = 0; idBF < slotBfCnt; idBF++)	// basic frame
+			{
+				val = (idSlot<<28) | (1<<24) | ((idBF<<2)<<8) | (0);
+			//	*pSrcAddr = val;
+				do_write(((uint32_t)pSrcAddr), val);
+				pSrcAddr++;
+			}
+			dataLen = (bfByteCnt*slotBfCnt); 
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+	//		cpyCnt++;
+			
+		//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+		}
+
+	// IQ data	
+//	for (idID = 1; idID < (CPRI_LTEFDD_AXCID_NUM-1); idID++)//NR:4AXC;LTE:2AXC
+	for (idID = 2; idID < 5; idID++)//NR:4AXC;LTE:2AXC
+	{
+		if(idID < 4)//nr
+		{
+			bfByteCnt = 64*2;//2个天线合并
+		}
+		else//lte
+		{
+			bfByteCnt = 16*2;//2个天线合并
+		}
+		
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+//			idSlotBf = 0;
+			if (1 == idSlot) //奇时隙
+			{
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI;
+				}
+				
+			}
+			else//偶时隙
+			{	
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI;
+				}
+				
+			}
+		//	for (idSymbol = 0; idSymbol < 7; idSymbol++)
+			{
+			//	pSrcAddr = srcImData;
+				pSrcAddr = ((uint32_t*)dstAddr);
+				#if 0
+				if ((0 == idSymbol) && (0 == idSymbolBlock))
+				{
+					symbolBfCnt = LONGCP_BF_CNT;
+				}
+				else
+				{
+					symbolBfCnt = SHORTCP_BF_CNT;
+				}
+				#endif
+			//	for (idBF = 0; idBF < symbolBfCnt; idBF++)	// basic frame
+				for (idBF = 0; idBF < slotBfCnt; idBF++)	// basic frame
+		 		{
+					for (idWord = 0; idWord < (bfByteCnt>>2); idWord++)
+					{
+					//		val = (idSlot<<28) | (idID<<24) | ((idSlotBf++)<<8) | (idWord);
+							val = (idSlot<<28) | (idID<<24) | (idBF<<8) | (idWord);
+						//	*pSrcAddr = val;
+							do_write(((uint32_t)pSrcAddr), val);
+							pSrcAddr++;
+					}
+		 		}
+				dataLen = slotBfCnt*bfByteCnt;
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//					cpyCnt++;
+			//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+			//	dstAddr += dataLen;
+			}
+		}
+	}
+	
+	// agc factor
+	//NR	
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 3;
+	//	pSrcAddr = srcImData;
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_AGC_ADDR;
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_AGC_ADDR;
+		}
+		pSrcAddr = ((uint32_t*)dstAddr);
+		for (idBF = 0; idBF < ((slotBfCnt*bfByteCnt)>>2); idBF++)	// basic frame
+	//	for (idBF = 0; idBF < slotBfCnt; idBF++)	// basic frame
+		{
+	//		val = (idSlot<<28) | (8<<24) | ((idBF<<1)<<8) | (0);
+			val = (idSlot<<28) | (8<<24) | ((idBF<<2)<<8) | (0);
+		//	*pSrcAddr = val;
+			do_write(((uint32_t)pSrcAddr), val);
+			pSrcAddr++;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		
+	//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	}
+
+}
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE60_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+		#endif
+		Cpri_Header_Rx();
+	}
+}
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	// move data from sm to ddr
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+//	uint32_t srcAddr1 = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t dataLen = 0;
+//	uint8_t bitOffset = 0;
+//	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
+	uint32_t slotBfCnt = 3840;//1ms：1个slot，基本帧数
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			/********
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			***********/
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			/******
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			*********/
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (0<<24) | ((idBf<<1)<<8) | (idWord);
+					
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if(1 == i)// compress factor:lte
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (1<<24) | ((idBf<<2)<<8) | (idWord);
+					
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 < i) && (5 > i))		// axc data
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(4 == i)//LTE
+					{
+					// 	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<3)+idWord)<<8) | (idWord);
+						compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+					}
+					else
+					{
+					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+						compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+					}
+					
+//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (1372 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
+						realSrcAddr = srcAddr1;
+						if (0 > (idBf-bfStart))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else// if(5 == i) //NR:AGC
+		{
+		   	for (int32_t idBf = 0; idBf <((slotBfCnt*3) >> 2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<1)<<8) | (idWord);
+					compVal = (slotVal<<28) | (8<<24) | ((idBf<<2)<<8) | (idWord);
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+	//						break;
+	//						break;
+					}
+	//					__ucps2_synch(0);
+				}
+			}
+		}
+		#if 0
+		else
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (9<<24) | ((idBf<<2)<<8) | (idWord);
+					
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		#endif
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}
+

public/test/testcases/case60/osp/src/ape_test_case60.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case61/fronthaul/inc/cpri_test_case61.h

@@ -0,0 +1,34 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE61_SLOT_NUM				20
+
+
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcases/case61/fronthaul/inc/lte_mem_def.h

@@ -0,0 +1,199 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+typedef struct
+{
+    uint32_t sampling_rate;
+
+
+    uint8_t tatol_tx_ants;
+    uint8_t tatol_rx_ants;
+    uint16_t rev;
+
+
+    uint8_t num_tx0_ants;
+    uint8_t num_tx1_ants;
+    uint8_t num_rx0_ants;
+    uint8_t num_rx1_ants;
+
+
+    //tx的链表地址
+    uint32_t tx_even_link_addr;
+    uint32_t tx_odd_link_addr;
+    uint32_t tx_last_link_addr;
+
+
+    //rx的链表地址
+    uint32_t rx_first_link_addr;
+    uint32_t rx_even_link_addr;
+    uint32_t rx_odd_link_addr;
+}phy_csu_link_info_t;
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0--1M*********************************************/
+//len define(Byte)
+#define SM0_PHY_MSG_BUFFER_LEN               0x00000400  //1024
+#define SM0_PHY_TASKS_MGR_LEN                0x00000100  //256
+#define SM0_LTE_CELL0_FAPI_MSG_LEN           0x00004B00  //19200，实际使用17588
+#define SM0_LTE_PBCH_REMAPPING_LUT_LEN       0x00000C64  //4+2*288*4+72*4+72*2*4=3172
+#define SM0_LTE_PDCCH_REMAPPING_LUT_LEN      0x00003840  //(1200+2400+3600)*2=14400
+#define SM0_LTE_PHICH_REMAPPING_LUT_LEN      0x00000480  //6*50*4=1200
+#define SM0_LTE_PCFICH_REMAPPING_LUT_LEN     0x00000020  //8*4=32
+#define SM0_LTE_CRS_REMAPPING_LUT_LEN        0x00000A50  //2*110*3*4=2640
+//#define SM0_LTE_PDSCH_RBG_SUBSET_TABLE_LEN   0x00000064  //100
+//#define SM0_LTE_PDSCH_VRB_PRB_TABLE_LEN      0x00000190  //400
+#define SM0_LTE_CELL0_EVEN_TX_LEN            0x0003C000  //30720*2*4=245760
+#define SM0_LTE_CELL0_ODD_TX_LEN             0x0003C000  //30720*2*4=245760
+#define SM0_ERROR_RECORD_CNT_LEN             0x00003000  //12288
+#define SM0_STATE_RECORD_CNT_LEN             0x00002600  //9728
+
+//addr base define
+#define SM0_PHY_MSG_BUFFER_ADDR              (SM0_BASE)
+#define SM0_PHY_TASKS_MGR_ADDR               (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+#define SM0_LTE_CELL0_FAPI_MSG_ADDR          (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_LTE_PBCH_REMAPPING_LUT_ADDR      (SM0_LTE_CELL0_FAPI_MSG_ADDR + SM0_LTE_CELL0_FAPI_MSG_LEN)
+#define SM0_LTE_PDCCH_REMAPPING_LUT_ADDR     (SM0_LTE_PBCH_REMAPPING_LUT_ADDR + SM0_LTE_PBCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PHICH_REMAPPING_LUT_ADDR     (SM0_LTE_PDCCH_REMAPPING_LUT_ADDR + SM0_LTE_PDCCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PCFICH_REMAPPING_LUT_ADDR    (SM0_LTE_PHICH_REMAPPING_LUT_ADDR + SM0_LTE_PHICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CRS_REMAPPING_LUT_ADDR       (SM0_LTE_PCFICH_REMAPPING_LUT_ADDR + SM0_LTE_PCFICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_EVEN_TX_ADDR           (SM0_LTE_CRS_REMAPPING_LUT_ADDR + SM0_LTE_CRS_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_ODD_TX_ADDR            (SM0_LTE_CELL0_EVEN_TX_ADDR + SM0_LTE_CELL0_EVEN_TX_LEN)
+//方便联查询，先写死，后续改动需计算地址
+#define SM0_ERROR_RECORD_CNT_ADDR            (0x9DE0000)//(SM0_LTE_CELL0_ODD_TX_ADDR + SM0_LTE_CELL0_ODD_TX_LEN)
+#define SM0_STATE_RECORD_CNT_ADDR            (0x9DF0000)//(SM0_ERROR_RECORD_CNT_ADDR + SM0_ERROR_RECORD_CNT_LEN)
+
+/************************************SM1---1M ***********************************************/ 
+//len define(Byte)
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN    0x00020D00  //14*2*1200*4=134400
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_LEN     0x00020D00  //14*2*1200*4=134400
+
+//addr base define
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR   (SM1_BASE)
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_ADDR    (SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR + SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN)
+
+#define SM1_PHY_USED_ADDR                    (SM1_BASE + 0x50000) //PHY使用的SM结束地址，暂时写死
+/************************************SM2--1.5M***********************************************/
+
+
+/************************************SM3--1.5M***********************************************/
+
+
+/************************************SM4--1.5M***********************************************/
+
+
+/************************************SM5--1.5M***********************************************/
+
+
+/**************************************DDR***************************************************/
+//base
+#define DDR_PHY_BASE                         (0x6BC00000) //共579M可用0x6BC00000-0x8FFFFFFF
+
+//len
+#define DDR_LTE_CELL0_RX_LEN                 0x0003C000   //一体化(30720*2)*4 = 240K
+#define DDR_LTE_PDSCH_CODING_TABLE_LEN       0x002665D0   //PDSCH编码表 2.4M
+
+//addr
+#define DDR_LTE_CELL0_RX_ADDR                (0x89000000) //TESTMAC测试阶段暂时写死，后续根据使用情况规划到SM或DDR
+#define DDR_LTE_PDSCH_CODING_TABLE_ADDR      (DDR_LTE_CELL0_RX_ADDR + DDR_LTE_CELL0_RX_LEN)
+
+// 6BEB0000 = 0x6BC00000 + 0x2B0000
+#define DDR_PHY_UESD_ADDR                    (DDR_PHY_BASE + 0x2B0000) //PHY使用的DDR结束地址，暂时写死
+#define DDR_PDSCH_DUMP_DATA_START            (DDR_PHY_UESD_ADDR) 
+
+/*************test addr start*************/
+
+#define LTE_TX_BASE_ADDR     (0xB4500000)  // 
+#define LTE_RX_BASE_ADDR     (0xB4800000)  // 
+
+#define NR_COM_FACT_LEN      (0x1E00) //NR压缩因子长度
+#define LTE_COM_FACT_LEN     (0xF00) //LTE压缩因子长度
+
+#define NR_AXC_DATA_LEN      (0x78000) //NR天线数据长度
+#define LTE_AXC_DATA_LEN     (0x1E000) //LTE天线数据长度
+
+//#define NR_AGC_LEN           (0x1E00) //NR AGC长度
+//#define LTE_AGC_LEN          (0xF00) //LTE AGC长度
+#define    AGC_LEN           (0x2D00) //NR AGC长度
+
+//Tx
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_TX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4500000
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI      (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR+ LTE_COM_FACT_LEN )  // LTE偶时隙天线数据 0xB4500F00
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI + LTE_AXC_DATA_LEN )  // LTE奇时隙压缩因子 0xB451EF00
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI       (SM0_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN )  // LTE奇时隙天线数据 0xB451FE00
+
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI      + LTE_AXC_DATA_LEN ) // NR偶时隙压缩因子 0xB453DE00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0  (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN )  // NR偶时隙天线数据0和1 0xB453FC00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1  (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN )  // NR偶时隙天线数据2和3 0xB45B7C00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )  // NR偶时隙AGC 0xB462FC00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR  + NR_AGC_LEN )       // LTE偶时隙AGC 0xB4631A00
+#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )         //AGC 0xB462FC00
+
+
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR  +  AGC_LEN )         // NR奇时隙压缩因子        0xB4632900
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0   (SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR  + NR_COM_FACT_LEN )  // NR奇时隙天线数据0和1         0xB4634700
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1   (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0  + NR_AXC_DATA_LEN )  // NR奇时隙天线数据2和3         0xB46AC700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // NR奇时隙AGC         0xB4724700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR  + NR_AGC_LEN )        // LTE奇时隙AGC       0xB4726500
+#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // 奇时隙AGC         0xB4724700
+
+//Rx
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_RX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4800000
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI      (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR + LTE_COM_FACT_LEN)   // LTE偶时隙天线数据          0xB4800F00
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)    // LTE奇时隙压缩因子          0xB481EF00
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI       (SM1_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN)    // LTE奇时隙天线数据          0xB481FE00
+
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)      // NR偶时隙压缩因子            0xB483DE00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0  (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)  // NR偶时隙天线数据0和1 0xB483FC00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1  (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)  // NR偶时隙天线数据2和3 0xB48B7C00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)  // NR偶时隙AGC             0xB492FC00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR + NR_AGC_LEN)        // LTE偶时隙AGC            0xB4931A00
+#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   //  偶时隙AGC             0xB492FC00
+
+
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR + AGC_LEN)          // NR奇时隙压缩因子            0xB4932900
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0   (SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)   // NR奇时隙天线数据0和1         0xB4934700
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1   (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)   // NR奇时隙天线数据2和3 0xB49AC700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // NR奇时隙AGC             0xB4a24700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR + NR_AGC_LEN)         // LTE奇时隙AGC            0xB4a26500
+#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // 奇时隙AGC             0xB4a24700
+
+/*************test addr end***************/
+
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+void Config_Cpri_Csu_Lte();
+
+
+#endif

public/test/testcases/case61/fronthaul/src/cpri_test_case61.s.c

@@ -0,0 +1,743 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case61.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "lte_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+extern volatile uint32_t gVendorFlag;
+
+extern uint32_t Nr_CompressData[1920];
+extern uint32_t Lte_compressData[960];
+extern uint32_t Nr_antData01[122880];
+extern uint32_t Nr_antData23[122880];
+extern uint32_t Lte_antData[30720];
+extern uint32_t Agc_Data[2280];
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+//	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+//	uint8_t idSymbol = 0;
+//	uint16_t idBF = 0;
+//	uint16_t idWord = 0;
+
+//	uint32_t* pSrcAddr = 0;
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	//uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;//1920
+	uint32_t  slotBfCnt = 256*15;//3840,1ms是一个时隙
+//	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//961
+//	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//959
+//	uint32_t  symbolBfCnt = 0;
+//	uint32_t  idSlotBf = 0;
+//	uint32_t  val = 0;
+	
+	//uint32_t* srcImData = dmalloc(10240, DM0);
+	
+	//debug_write((DBG_DDR_IDX_DRV_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304
+
+	uint32_t cpyCnt = 0;
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	cpyCnt++;
+
+	// valid data
+	/******* compress factor********/
+	//NR
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;//NR:2B	
+		dataLen = (bfByteCnt*slotBfCnt); 
+		//pSrcAddr = srcImData;
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+			
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+			
+		}
+		srcAddr =  (uint32_t)(&Nr_CompressData[0]);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+	}
+	//LTE
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			bfByteCnt = 1;//LTE:1B	
+			dataLen = (bfByteCnt*slotBfCnt); 
+		//	pSrcAddr = srcImData;
+			if (0 == idSlot)	// even slot
+			{
+				dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR;
+				
+			}
+			else				// odd slot
+			{
+				dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR;
+				
+			}
+			
+			srcAddr = (uint32_t)(&Lte_compressData[0]);//Lte_compressData;
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+	//		cpyCnt++;
+			memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+		//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+		}
+
+	// IQ data	
+//	for (idID = 1; idID < (CPRI_LTEFDD_AXCID_NUM-1); idID++)//NR:4AXC;LTE:2AXC
+	for (idID = 2; idID < 5; idID++)//NR:4AXC;LTE:2AXC
+	{
+		if(idID < 4)//nr
+		{
+			bfByteCnt = 64*2;//2个天线合并
+		}
+		else//lte
+		{
+			bfByteCnt = 16*2;//2个天线合并
+		}
+		dataLen = slotBfCnt*bfByteCnt;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+//			idSlotBf = 0;
+			if (1 == idSlot) //奇时隙
+			{
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0;
+					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1;
+					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI;
+					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
+				}
+				
+			}
+			else//偶时隙
+			{	
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0;
+					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1;
+					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI;
+					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
+				}
+				
+			}
+		//	for (idSymbol = 0; idSymbol < 7; idSymbol++)
+			{
+				
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//					cpyCnt++;
+			//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+			//	dstAddr += dataLen;
+			}
+		}
+	}
+	
+	// agc factor
+	//NR	
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 3;
+	//	pSrcAddr = srcImData;
+		dataLen = (bfByteCnt*slotBfCnt); 
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_AGC_ADDR;
+			
+		}
+		srcAddr = (uint32_t)(&Agc_Data[0]);//srcAddr = Agc_Data;	
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		
+	//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	}
+
+}
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE61_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+		#endif
+		Cpri_Header_Rx();
+	}
+}
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	// move data from sm to ddr
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+//	uint32_t srcAddr1 = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t dataLen = 0;
+//	uint8_t bitOffset = 0;
+//	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
+	uint32_t slotBfCnt = 3840;//1ms：1个slot，基本帧数
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			/********
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			***********/
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			/******
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			*********/
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (0<<24) | ((idBf<<1)<<8) | (idWord);
+					compVal = do_read_volatile(Nr_CompressData+idBf*bfWordCnt + idWord);//Nr_CompressData[idBf*bfWordCnt + idWord];
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if(1 == i)// compress factor:lte
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (1<<24) | ((idBf<<2)<<8) | (idWord);
+					compVal =do_read_volatile(Lte_compressData+idBf*bfWordCnt + idWord);// Lte_compressData[idBf*bfWordCnt + idWord];
+				
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 < i) && (5 > i))		// axc data
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(4 == i)//LTE
+					{
+					// 	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<3)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Lte_antData+idBf*bfWordCnt + idWord);//Lte_antData[idBf*bfWordCnt + idWord];
+					}
+					else if(3 == i)
+					{
+					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Nr_antData23+idBf*bfWordCnt + idWord);//Nr_antData23[idBf*bfWordCnt + idWord];
+					}
+					else //if (2 == i)
+					{
+					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Nr_antData01+idBf*bfWordCnt + idWord);//Nr_antData01[idBf*bfWordCnt + idWord];
+					}
+					
+//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (1372 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
+						realSrcAddr = srcAddr1;
+						if (0 > (idBf-bfStart))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else// if(5 == i) //NR:AGC
+		{
+		   	for (int32_t idBf = 0; idBf <((slotBfCnt*3) >> 2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<1)<<8) | (idWord);
+				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<2)<<8) | (idWord);
+					compVal = do_read_volatile(Agc_Data + idBf*bfWordCnt + idWord);//Agc_Data[idBf*bfWordCnt + idWord];
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+	//						break;
+	//						break;
+					}
+	//					__ucps2_synch(0);
+				}
+			}
+		}
+	
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}
+

public/test/testcases/case61/fronthaul/src/cpri_test_case61_AGC.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Agc_Data[2880] = {
+	0
+};
+

public/test/testcases/case61/fronthaul/src/cpri_test_case61_NrAntdata01.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_antData01[122880] = {
+	0
+};
+

public/test/testcases/case61/fronthaul/src/cpri_test_case61_NrAntdata23.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_antData23[122880] = {
+	0
+};
+

public/test/testcases/case61/fronthaul/src/cpri_test_case61_NrComfactor.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_CompressData[1920] = {
+	0
+};
+

public/test/testcases/case61/osp/src/ape_test_case61.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case66/fronthaul/inc/cpri_test_case66.h

@@ -0,0 +1,34 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE61_SLOT_NUM				20
+
+
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcases/case66/fronthaul/inc/lte_mem_def.h

@@ -0,0 +1,199 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+typedef struct
+{
+    uint32_t sampling_rate;
+
+
+    uint8_t tatol_tx_ants;
+    uint8_t tatol_rx_ants;
+    uint16_t rev;
+
+
+    uint8_t num_tx0_ants;
+    uint8_t num_tx1_ants;
+    uint8_t num_rx0_ants;
+    uint8_t num_rx1_ants;
+
+
+    //tx的链表地址
+    uint32_t tx_even_link_addr;
+    uint32_t tx_odd_link_addr;
+    uint32_t tx_last_link_addr;
+
+
+    //rx的链表地址
+    uint32_t rx_first_link_addr;
+    uint32_t rx_even_link_addr;
+    uint32_t rx_odd_link_addr;
+}phy_csu_link_info_t;
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0--1M*********************************************/
+//len define(Byte)
+#define SM0_PHY_MSG_BUFFER_LEN               0x00000400  //1024
+#define SM0_PHY_TASKS_MGR_LEN                0x00000100  //256
+#define SM0_LTE_CELL0_FAPI_MSG_LEN           0x00004B00  //19200，实际使用17588
+#define SM0_LTE_PBCH_REMAPPING_LUT_LEN       0x00000C64  //4+2*288*4+72*4+72*2*4=3172
+#define SM0_LTE_PDCCH_REMAPPING_LUT_LEN      0x00003840  //(1200+2400+3600)*2=14400
+#define SM0_LTE_PHICH_REMAPPING_LUT_LEN      0x00000480  //6*50*4=1200
+#define SM0_LTE_PCFICH_REMAPPING_LUT_LEN     0x00000020  //8*4=32
+#define SM0_LTE_CRS_REMAPPING_LUT_LEN        0x00000A50  //2*110*3*4=2640
+//#define SM0_LTE_PDSCH_RBG_SUBSET_TABLE_LEN   0x00000064  //100
+//#define SM0_LTE_PDSCH_VRB_PRB_TABLE_LEN      0x00000190  //400
+#define SM0_LTE_CELL0_EVEN_TX_LEN            0x0003C000  //30720*2*4=245760
+#define SM0_LTE_CELL0_ODD_TX_LEN             0x0003C000  //30720*2*4=245760
+#define SM0_ERROR_RECORD_CNT_LEN             0x00003000  //12288
+#define SM0_STATE_RECORD_CNT_LEN             0x00002600  //9728
+
+//addr base define
+#define SM0_PHY_MSG_BUFFER_ADDR              (SM0_BASE)
+#define SM0_PHY_TASKS_MGR_ADDR               (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+#define SM0_LTE_CELL0_FAPI_MSG_ADDR          (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_LTE_PBCH_REMAPPING_LUT_ADDR      (SM0_LTE_CELL0_FAPI_MSG_ADDR + SM0_LTE_CELL0_FAPI_MSG_LEN)
+#define SM0_LTE_PDCCH_REMAPPING_LUT_ADDR     (SM0_LTE_PBCH_REMAPPING_LUT_ADDR + SM0_LTE_PBCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PHICH_REMAPPING_LUT_ADDR     (SM0_LTE_PDCCH_REMAPPING_LUT_ADDR + SM0_LTE_PDCCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PCFICH_REMAPPING_LUT_ADDR    (SM0_LTE_PHICH_REMAPPING_LUT_ADDR + SM0_LTE_PHICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CRS_REMAPPING_LUT_ADDR       (SM0_LTE_PCFICH_REMAPPING_LUT_ADDR + SM0_LTE_PCFICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_EVEN_TX_ADDR           (SM0_LTE_CRS_REMAPPING_LUT_ADDR + SM0_LTE_CRS_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_ODD_TX_ADDR            (SM0_LTE_CELL0_EVEN_TX_ADDR + SM0_LTE_CELL0_EVEN_TX_LEN)
+//方便联查询，先写死，后续改动需计算地址
+#define SM0_ERROR_RECORD_CNT_ADDR            (0x9DE0000)//(SM0_LTE_CELL0_ODD_TX_ADDR + SM0_LTE_CELL0_ODD_TX_LEN)
+#define SM0_STATE_RECORD_CNT_ADDR            (0x9DF0000)//(SM0_ERROR_RECORD_CNT_ADDR + SM0_ERROR_RECORD_CNT_LEN)
+
+/************************************SM1---1M ***********************************************/ 
+//len define(Byte)
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN    0x00020D00  //14*2*1200*4=134400
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_LEN     0x00020D00  //14*2*1200*4=134400
+
+//addr base define
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR   (SM1_BASE)
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_ADDR    (SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR + SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN)
+
+#define SM1_PHY_USED_ADDR                    (SM1_BASE + 0x50000) //PHY使用的SM结束地址，暂时写死
+/************************************SM2--1.5M***********************************************/
+
+
+/************************************SM3--1.5M***********************************************/
+
+
+/************************************SM4--1.5M***********************************************/
+
+
+/************************************SM5--1.5M***********************************************/
+
+
+/**************************************DDR***************************************************/
+//base
+#define DDR_PHY_BASE                         (0x6BC00000) //共579M可用0x6BC00000-0x8FFFFFFF
+
+//len
+#define DDR_LTE_CELL0_RX_LEN                 0x0003C000   //一体化(30720*2)*4 = 240K
+#define DDR_LTE_PDSCH_CODING_TABLE_LEN       0x002665D0   //PDSCH编码表 2.4M
+
+//addr
+#define DDR_LTE_CELL0_RX_ADDR                (0x89000000) //TESTMAC测试阶段暂时写死，后续根据使用情况规划到SM或DDR
+#define DDR_LTE_PDSCH_CODING_TABLE_ADDR      (DDR_LTE_CELL0_RX_ADDR + DDR_LTE_CELL0_RX_LEN)
+
+// 6BEB0000 = 0x6BC00000 + 0x2B0000
+#define DDR_PHY_UESD_ADDR                    (DDR_PHY_BASE + 0x2B0000) //PHY使用的DDR结束地址，暂时写死
+#define DDR_PDSCH_DUMP_DATA_START            (DDR_PHY_UESD_ADDR) 
+
+/*************test addr start*************/
+
+#define LTE_TX_BASE_ADDR     (0xB4500000)  // 
+#define LTE_RX_BASE_ADDR     (0xB4800000)  // 
+
+#define NR_COM_FACT_LEN      (0x1E00) //NR压缩因子长度
+#define LTE_COM_FACT_LEN     (0xF00) //LTE压缩因子长度
+
+#define NR_AXC_DATA_LEN      (0x78000) //NR天线数据长度
+#define LTE_AXC_DATA_LEN     (0x1E000) //LTE天线数据长度
+
+//#define NR_AGC_LEN           (0x1E00) //NR AGC长度
+//#define LTE_AGC_LEN          (0xF00) //LTE AGC长度
+#define    AGC_LEN           (0x2D00) //NR AGC长度
+
+//Tx
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_TX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4500000
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI      (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR+ LTE_COM_FACT_LEN )  // LTE偶时隙天线数据 0xB4500F00
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI + LTE_AXC_DATA_LEN )  // LTE奇时隙压缩因子 0xB451EF00
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI       (SM0_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN )  // LTE奇时隙天线数据 0xB451FE00
+
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI      + LTE_AXC_DATA_LEN ) // NR偶时隙压缩因子 0xB453DE00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0  (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN )  // NR偶时隙天线数据0和1 0xB453FC00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1  (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN )  // NR偶时隙天线数据2和3 0xB45B7C00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )  // NR偶时隙AGC 0xB462FC00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR  + NR_AGC_LEN )       // LTE偶时隙AGC 0xB4631A00
+#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )         //AGC 0xB462FC00
+
+
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR  +  AGC_LEN )         // NR奇时隙压缩因子        0xB4632900
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0   (SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR  + NR_COM_FACT_LEN )  // NR奇时隙天线数据0和1         0xB4634700
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1   (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0  + NR_AXC_DATA_LEN )  // NR奇时隙天线数据2和3         0xB46AC700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // NR奇时隙AGC         0xB4724700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR  + NR_AGC_LEN )        // LTE奇时隙AGC       0xB4726500
+#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // 奇时隙AGC         0xB4724700
+
+//Rx
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_RX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4800000
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI      (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR + LTE_COM_FACT_LEN)   // LTE偶时隙天线数据          0xB4800F00
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)    // LTE奇时隙压缩因子          0xB481EF00
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI       (SM1_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN)    // LTE奇时隙天线数据          0xB481FE00
+
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)      // NR偶时隙压缩因子            0xB483DE00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0  (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)  // NR偶时隙天线数据0和1 0xB483FC00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1  (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)  // NR偶时隙天线数据2和3 0xB48B7C00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)  // NR偶时隙AGC             0xB492FC00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR + NR_AGC_LEN)        // LTE偶时隙AGC            0xB4931A00
+#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   //  偶时隙AGC             0xB492FC00
+
+
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR + AGC_LEN)          // NR奇时隙压缩因子            0xB4932900
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0   (SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)   // NR奇时隙天线数据0和1         0xB4934700
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1   (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)   // NR奇时隙天线数据2和3 0xB49AC700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // NR奇时隙AGC             0xB4a24700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR + NR_AGC_LEN)         // LTE奇时隙AGC            0xB4a26500
+#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // 奇时隙AGC             0xB4a24700
+
+/*************test addr end***************/
+
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+void Config_Cpri_Csu_Lte();
+
+
+#endif

public/test/testcases/case66/fronthaul/src/cpri_test_case66.s.c

@@ -0,0 +1,743 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case66.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "lte_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+extern volatile uint32_t gVendorFlag;
+
+extern uint32_t Nr_CompressData[1920];
+extern uint32_t Lte_compressData[960];
+extern uint32_t Nr_antData01[122880];
+extern uint32_t Nr_antData23[122880];
+extern uint32_t Lte_antData[30720];
+extern uint32_t Agc_Data[2280];
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+//	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+//	uint8_t idSymbol = 0;
+//	uint16_t idBF = 0;
+//	uint16_t idWord = 0;
+
+//	uint32_t* pSrcAddr = 0;
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	//uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;//1920
+	uint32_t  slotBfCnt = 256*15;//3840,1ms是一个时隙
+//	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//961
+//	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//959
+//	uint32_t  symbolBfCnt = 0;
+//	uint32_t  idSlotBf = 0;
+//	uint32_t  val = 0;
+	
+	//uint32_t* srcImData = dmalloc(10240, DM0);
+	
+	//debug_write((DBG_DDR_IDX_DRV_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304
+
+	uint32_t cpyCnt = 0;
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	cpyCnt++;
+
+	// valid data
+	/******* compress factor********/
+	//NR
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;//NR:2B	
+		dataLen = (bfByteCnt*slotBfCnt); 
+		//pSrcAddr = srcImData;
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+			
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+			
+		}
+		srcAddr =  (uint32_t)(&Nr_CompressData[0]);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+	}
+	//LTE
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			bfByteCnt = 1;//LTE:1B	
+			dataLen = (bfByteCnt*slotBfCnt); 
+		//	pSrcAddr = srcImData;
+			if (0 == idSlot)	// even slot
+			{
+				dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR;
+				
+			}
+			else				// odd slot
+			{
+				dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR;
+				
+			}
+			
+			srcAddr = (uint32_t)(&Lte_compressData[0]);//Lte_compressData;
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+	//		cpyCnt++;
+			memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+		//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+		}
+
+	// IQ data	
+//	for (idID = 1; idID < (CPRI_LTEFDD_AXCID_NUM-1); idID++)//NR:4AXC;LTE:2AXC
+	for (idID = 2; idID < 5; idID++)//NR:4AXC;LTE:2AXC
+	{
+		if(idID < 4)//nr
+		{
+			bfByteCnt = 64*2;//2个天线合并
+		}
+		else//lte
+		{
+			bfByteCnt = 16*2;//2个天线合并
+		}
+		dataLen = slotBfCnt*bfByteCnt;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+//			idSlotBf = 0;
+			if (1 == idSlot) //奇时隙
+			{
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0;
+					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1;
+					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI;
+					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
+				}
+				
+			}
+			else//偶时隙
+			{	
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0;
+					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1;
+					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI;
+					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
+				}
+				
+			}
+		//	for (idSymbol = 0; idSymbol < 7; idSymbol++)
+			{
+				
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//					cpyCnt++;
+			//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+			//	dstAddr += dataLen;
+			}
+		}
+	}
+	
+	// agc factor
+	//NR	
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 3;
+	//	pSrcAddr = srcImData;
+		dataLen = (bfByteCnt*slotBfCnt); 
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_AGC_ADDR;
+			
+		}
+		srcAddr = (uint32_t)(&Agc_Data[0]);//srcAddr = Agc_Data;	
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		
+	//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	}
+
+}
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE61_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+		#endif
+		Cpri_Header_Rx();
+	}
+}
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	// move data from sm to ddr
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+//	uint32_t srcAddr1 = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t dataLen = 0;
+//	uint8_t bitOffset = 0;
+//	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
+	uint32_t slotBfCnt = 3840;//1ms：1个slot，基本帧数
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			/********
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			***********/
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			/******
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			*********/
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (0<<24) | ((idBf<<1)<<8) | (idWord);
+					compVal = do_read_volatile(Nr_CompressData+idBf*bfWordCnt + idWord);//Nr_CompressData[idBf*bfWordCnt + idWord];
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if(1 == i)// compress factor:lte
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (1<<24) | ((idBf<<2)<<8) | (idWord);
+					compVal =do_read_volatile(Lte_compressData+idBf*bfWordCnt + idWord);// Lte_compressData[idBf*bfWordCnt + idWord];
+				
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 < i) && (5 > i))		// axc data
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(4 == i)//LTE
+					{
+					// 	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<3)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Lte_antData+idBf*bfWordCnt + idWord);//Lte_antData[idBf*bfWordCnt + idWord];
+					}
+					else if(3 == i)
+					{
+					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Nr_antData23+idBf*bfWordCnt + idWord);//Nr_antData23[idBf*bfWordCnt + idWord];
+					}
+					else //if (2 == i)
+					{
+					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Nr_antData01+idBf*bfWordCnt + idWord);//Nr_antData01[idBf*bfWordCnt + idWord];
+					}
+					
+//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (1372 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
+						realSrcAddr = srcAddr1;
+						if (0 > (idBf-bfStart))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else// if(5 == i) //NR:AGC
+		{
+		   	for (int32_t idBf = 0; idBf <((slotBfCnt*3) >> 2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<1)<<8) | (idWord);
+				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<2)<<8) | (idWord);
+					compVal = do_read_volatile(Agc_Data + idBf*bfWordCnt + idWord);//Agc_Data[idBf*bfWordCnt + idWord];
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+	//						break;
+	//						break;
+					}
+	//					__ucps2_synch(0);
+				}
+			}
+		}
+	
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}
+

public/test/testcases/case66/fronthaul/src/cpri_test_case66_AGC.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Agc_Data[2880] = {
+	0	
+};
+

public/test/testcases/case66/fronthaul/src/cpri_test_case66_NrAntdata01.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_antData01[122880] = {
+	0
+};
+

public/test/testcases/case66/fronthaul/src/cpri_test_case66_NrAntdata23.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_antData23[122880] = {
+	0
+};
+

public/test/testcases/case66/fronthaul/src/cpri_test_case66_NrComfactor.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_CompressData[1920] = {
+	0
+};
+

public/test/testcases/case66/osp/src/ape_test_case66.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case68/fronthaul/inc/cpri_test_case68.h

@@ -0,0 +1,34 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE61_SLOT_NUM				20
+
+
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcases/case68/fronthaul/inc/lte_mem_def.h

@@ -0,0 +1,199 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+typedef struct
+{
+    uint32_t sampling_rate;
+
+
+    uint8_t tatol_tx_ants;
+    uint8_t tatol_rx_ants;
+    uint16_t rev;
+
+
+    uint8_t num_tx0_ants;
+    uint8_t num_tx1_ants;
+    uint8_t num_rx0_ants;
+    uint8_t num_rx1_ants;
+
+
+    //tx的链表地址
+    uint32_t tx_even_link_addr;
+    uint32_t tx_odd_link_addr;
+    uint32_t tx_last_link_addr;
+
+
+    //rx的链表地址
+    uint32_t rx_first_link_addr;
+    uint32_t rx_even_link_addr;
+    uint32_t rx_odd_link_addr;
+}phy_csu_link_info_t;
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0--1M*********************************************/
+//len define(Byte)
+#define SM0_PHY_MSG_BUFFER_LEN               0x00000400  //1024
+#define SM0_PHY_TASKS_MGR_LEN                0x00000100  //256
+#define SM0_LTE_CELL0_FAPI_MSG_LEN           0x00004B00  //19200，实际使用17588
+#define SM0_LTE_PBCH_REMAPPING_LUT_LEN       0x00000C64  //4+2*288*4+72*4+72*2*4=3172
+#define SM0_LTE_PDCCH_REMAPPING_LUT_LEN      0x00003840  //(1200+2400+3600)*2=14400
+#define SM0_LTE_PHICH_REMAPPING_LUT_LEN      0x00000480  //6*50*4=1200
+#define SM0_LTE_PCFICH_REMAPPING_LUT_LEN     0x00000020  //8*4=32
+#define SM0_LTE_CRS_REMAPPING_LUT_LEN        0x00000A50  //2*110*3*4=2640
+//#define SM0_LTE_PDSCH_RBG_SUBSET_TABLE_LEN   0x00000064  //100
+//#define SM0_LTE_PDSCH_VRB_PRB_TABLE_LEN      0x00000190  //400
+#define SM0_LTE_CELL0_EVEN_TX_LEN            0x0003C000  //30720*2*4=245760
+#define SM0_LTE_CELL0_ODD_TX_LEN             0x0003C000  //30720*2*4=245760
+#define SM0_ERROR_RECORD_CNT_LEN             0x00003000  //12288
+#define SM0_STATE_RECORD_CNT_LEN             0x00002600  //9728
+
+//addr base define
+#define SM0_PHY_MSG_BUFFER_ADDR              (SM0_BASE)
+#define SM0_PHY_TASKS_MGR_ADDR               (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+#define SM0_LTE_CELL0_FAPI_MSG_ADDR          (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_LTE_PBCH_REMAPPING_LUT_ADDR      (SM0_LTE_CELL0_FAPI_MSG_ADDR + SM0_LTE_CELL0_FAPI_MSG_LEN)
+#define SM0_LTE_PDCCH_REMAPPING_LUT_ADDR     (SM0_LTE_PBCH_REMAPPING_LUT_ADDR + SM0_LTE_PBCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PHICH_REMAPPING_LUT_ADDR     (SM0_LTE_PDCCH_REMAPPING_LUT_ADDR + SM0_LTE_PDCCH_REMAPPING_LUT_LEN)
+#define SM0_LTE_PCFICH_REMAPPING_LUT_ADDR    (SM0_LTE_PHICH_REMAPPING_LUT_ADDR + SM0_LTE_PHICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CRS_REMAPPING_LUT_ADDR       (SM0_LTE_PCFICH_REMAPPING_LUT_ADDR + SM0_LTE_PCFICH_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_EVEN_TX_ADDR           (SM0_LTE_CRS_REMAPPING_LUT_ADDR + SM0_LTE_CRS_REMAPPING_LUT_LEN)
+#define SM0_LTE_CELL0_ODD_TX_ADDR            (SM0_LTE_CELL0_EVEN_TX_ADDR + SM0_LTE_CELL0_EVEN_TX_LEN)
+//方便联查询，先写死，后续改动需计算地址
+#define SM0_ERROR_RECORD_CNT_ADDR            (0x9DE0000)//(SM0_LTE_CELL0_ODD_TX_ADDR + SM0_LTE_CELL0_ODD_TX_LEN)
+#define SM0_STATE_RECORD_CNT_ADDR            (0x9DF0000)//(SM0_ERROR_RECORD_CNT_ADDR + SM0_ERROR_RECORD_CNT_LEN)
+
+/************************************SM1---1M ***********************************************/ 
+//len define(Byte)
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN    0x00020D00  //14*2*1200*4=134400
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_LEN     0x00020D00  //14*2*1200*4=134400
+
+//addr base define
+#define SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR   (SM1_BASE)
+#define SM1_LTE_RX_FREQ_ODD_SUBFRAME_ADDR    (SM1_LTE_RX_FREQ_EVEN_SUBFRAME_ADDR + SM1_LTE_RX_FREQ_EVEN_SUBFRAME_LEN)
+
+#define SM1_PHY_USED_ADDR                    (SM1_BASE + 0x50000) //PHY使用的SM结束地址，暂时写死
+/************************************SM2--1.5M***********************************************/
+
+
+/************************************SM3--1.5M***********************************************/
+
+
+/************************************SM4--1.5M***********************************************/
+
+
+/************************************SM5--1.5M***********************************************/
+
+
+/**************************************DDR***************************************************/
+//base
+#define DDR_PHY_BASE                         (0x6BC00000) //共579M可用0x6BC00000-0x8FFFFFFF
+
+//len
+#define DDR_LTE_CELL0_RX_LEN                 0x0003C000   //一体化(30720*2)*4 = 240K
+#define DDR_LTE_PDSCH_CODING_TABLE_LEN       0x002665D0   //PDSCH编码表 2.4M
+
+//addr
+#define DDR_LTE_CELL0_RX_ADDR                (0x89000000) //TESTMAC测试阶段暂时写死，后续根据使用情况规划到SM或DDR
+#define DDR_LTE_PDSCH_CODING_TABLE_ADDR      (DDR_LTE_CELL0_RX_ADDR + DDR_LTE_CELL0_RX_LEN)
+
+// 6BEB0000 = 0x6BC00000 + 0x2B0000
+#define DDR_PHY_UESD_ADDR                    (DDR_PHY_BASE + 0x2B0000) //PHY使用的DDR结束地址，暂时写死
+#define DDR_PDSCH_DUMP_DATA_START            (DDR_PHY_UESD_ADDR) 
+
+/*************test addr start*************/
+
+#define LTE_TX_BASE_ADDR     (0xB4500000)  // 
+#define LTE_RX_BASE_ADDR     (0xB4800000)  // 
+
+#define NR_COM_FACT_LEN      (0x1E00) //NR压缩因子长度
+#define LTE_COM_FACT_LEN     (0xF00) //LTE压缩因子长度
+
+#define NR_AXC_DATA_LEN      (0x78000) //NR天线数据长度
+#define LTE_AXC_DATA_LEN     (0x1E000) //LTE天线数据长度
+
+//#define NR_AGC_LEN           (0x1E00) //NR AGC长度
+//#define LTE_AGC_LEN          (0xF00) //LTE AGC长度
+#define    AGC_LEN           (0x2D00) //NR AGC长度
+
+//Tx
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_TX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4500000
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI      (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR+ LTE_COM_FACT_LEN )  // LTE偶时隙天线数据 0xB4500F00
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI + LTE_AXC_DATA_LEN )  // LTE奇时隙压缩因子 0xB451EF00
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI       (SM0_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN )  // LTE奇时隙天线数据 0xB451FE00
+
+#define SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI      + LTE_AXC_DATA_LEN ) // NR偶时隙压缩因子 0xB453DE00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0  (SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN )  // NR偶时隙天线数据0和1 0xB453FC00
+#define SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1  (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN )  // NR偶时隙天线数据2和3 0xB45B7C00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )  // NR偶时隙AGC 0xB462FC00
+//#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR_NR  + NR_AGC_LEN )       // LTE偶时隙AGC 0xB4631A00
+#define SM0_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN )         //AGC 0xB462FC00
+
+
+#define SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM0_LTE_CELL0_EVEN_COM_AGC_ADDR  +  AGC_LEN )         // NR奇时隙压缩因子        0xB4632900
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0   (SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR  + NR_COM_FACT_LEN )  // NR奇时隙天线数据0和1         0xB4634700
+#define SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1   (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0  + NR_AXC_DATA_LEN )  // NR奇时隙天线数据2和3         0xB46AC700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // NR奇时隙AGC         0xB4724700
+//#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_COM_AGC_ADDR_NR  + NR_AGC_LEN )        // LTE奇时隙AGC       0xB4726500
+#define SM0_LTE_CELL0_ODD_COM_AGC_ADDR       (SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1  + NR_AXC_DATA_LEN )  // 奇时隙AGC         0xB4724700
+
+//Rx
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR     (LTE_RX_BASE_ADDR)  // LTE偶时隙压缩因子 0xB4800000
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI      (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR + LTE_COM_FACT_LEN)   // LTE偶时隙天线数据          0xB4800F00
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)    // LTE奇时隙压缩因子          0xB481EF00
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI       (SM1_LTE_CELL0_ODD_COM_FACT_ADDR + LTE_COM_FACT_LEN)    // LTE奇时隙天线数据          0xB481FE00
+
+#define SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR  (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI + LTE_AXC_DATA_LEN)      // NR偶时隙压缩因子            0xB483DE00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0  (SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)  // NR偶时隙天线数据0和1 0xB483FC00
+#define SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1  (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)  // NR偶时隙天线数据2和3 0xB48B7C00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR   (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)  // NR偶时隙AGC             0xB492FC00
+//#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR_NR + NR_AGC_LEN)        // LTE偶时隙AGC            0xB4931A00
+#define SM1_LTE_CELL0_EVEN_COM_AGC_ADDR      (SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   //  偶时隙AGC             0xB492FC00
+
+
+#define SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR   (SM1_LTE_CELL0_EVEN_COM_AGC_ADDR + AGC_LEN)          // NR奇时隙压缩因子            0xB4932900
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0   (SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR + NR_COM_FACT_LEN)   // NR奇时隙天线数据0和1         0xB4934700
+#define SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1   (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0 + NR_AXC_DATA_LEN)   // NR奇时隙天线数据2和3 0xB49AC700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR    (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // NR奇时隙AGC             0xB4a24700
+//#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_COM_AGC_ADDR_NR + NR_AGC_LEN)         // LTE奇时隙AGC            0xB4a26500
+#define SM1_LTE_CELL0_ODD_COM_AGC_ADDR       (SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1 + NR_AXC_DATA_LEN)   // 奇时隙AGC             0xB4a24700
+
+/*************test addr end***************/
+
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+void Config_Cpri_Csu_Lte();
+
+
+#endif

public/test/testcases/case68/fronthaul/src/cpri_test_case68.s.c

@@ -0,0 +1,742 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case68.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "lte_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+extern volatile uint32_t gVendorFlag;
+
+extern uint32_t Nr_CompressData[1920];
+extern uint32_t Lte_compressData[960];
+extern uint32_t Nr_antData01[122880];
+extern uint32_t Nr_antData23[122880];
+extern uint32_t Lte_antData[30720];
+extern uint32_t Agc_Data[2280];
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+//	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+//	uint8_t idSymbol = 0;
+//	uint16_t idBF = 0;
+//	uint16_t idWord = 0;
+
+//	uint32_t* pSrcAddr = 0;
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	//uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;//1920
+	uint32_t  slotBfCnt = 256*15;//3840,1ms是一个时隙
+//	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//961
+//	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//959
+//	uint32_t  symbolBfCnt = 0;
+//	uint32_t  idSlotBf = 0;
+//	uint32_t  val = 0;
+	
+	//uint32_t* srcImData = dmalloc(10240, DM0);
+	
+	//debug_write((DBG_DDR_IDX_DRV_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304
+
+	uint32_t cpyCnt = 0;
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	cpyCnt++;
+
+	// valid data
+	/******* compress factor********/
+	//NR
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;//NR:2B	
+		dataLen = (bfByteCnt*slotBfCnt); 
+		//pSrcAddr = srcImData;
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+			
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+			
+		}
+		srcAddr =  (uint32_t)(&Nr_CompressData[0]);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+	}
+	//LTE
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			bfByteCnt = 1;//LTE:1B	
+			dataLen = (bfByteCnt*slotBfCnt); 
+		//	pSrcAddr = srcImData;
+			if (0 == idSlot)	// even slot
+			{
+				dstAddr = SM0_LTE_CELL0_EVEN_COM_FACT_ADDR;
+				
+			}
+			else				// odd slot
+			{
+				dstAddr = SM0_LTE_CELL0_ODD_COM_FACT_ADDR;
+				
+			}
+			
+			srcAddr = (uint32_t)(&Lte_compressData[0]);//Lte_compressData;
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+	//		cpyCnt++;
+			memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+		//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+		}
+
+	// IQ data	
+//	for (idID = 1; idID < (CPRI_LTEFDD_AXCID_NUM-1); idID++)//NR:4AXC;LTE:2AXC
+	for (idID = 2; idID < 5; idID++)//NR:4AXC;LTE:2AXC
+	{
+		if(idID < 4)//nr
+		{
+			bfByteCnt = 64*2;//2个天线合并
+		}
+		else//lte
+		{
+			bfByteCnt = 16*2;//2个天线合并
+		}
+		dataLen = slotBfCnt*bfByteCnt;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+//			idSlotBf = 0;
+			if (1 == idSlot) //奇时隙
+			{
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR0;
+					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI_NR1;
+					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					dstAddr = SM0_LTE_CELL0_ODD_TX_ADDR_CPRI;
+					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
+				}
+				
+			}
+			else//偶时隙
+			{	
+				if(2 == idID) //NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR0;
+					srcAddr = (uint32_t)(&Nr_antData01[0]);//Nr_antData01;
+				}
+				else if(3 == idID)//NR :2条天线数据交织:64*2B
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI_NR1;
+					srcAddr = (uint32_t)(&Nr_antData23[0]);// Nr_antData23;
+				}
+				else //LTE :2条天线数据交织:16*2B 
+				{
+					
+					dstAddr = SM0_LTE_CELL0_EVEN_TX_ADDR_CPRI;
+					srcAddr = (uint32_t)(&Lte_antData[0]);//Lte_antData;
+				}
+				
+			}
+		//	for (idSymbol = 0; idSymbol < 7; idSymbol++)
+			{
+				
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//					cpyCnt++;
+			//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+			//	dstAddr += dataLen;
+			}
+		}
+	}
+	
+	// agc factor
+	//NR	
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 3;
+	//	pSrcAddr = srcImData;
+		dataLen = (bfByteCnt*slotBfCnt); 
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM0_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			
+		}
+		else				// odd slot
+		{
+			dstAddr = SM0_LTE_CELL0_ODD_COM_AGC_ADDR;
+			
+		}
+		srcAddr = (uint32_t)(&Agc_Data[0]);//srcAddr = Agc_Data;	
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		
+	//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	}
+
+}
+
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE61_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+		#endif
+	}
+}
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	// move data from sm to ddr
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+//	uint32_t srcAddr1 = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t dataLen = 0;
+//	uint8_t bitOffset = 0;
+//	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
+	uint32_t slotBfCnt = 3840;//1ms：1个slot，基本帧数
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_ODD_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			/********
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_ODD_COM_AGC_ADDR;
+			}
+			***********/
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR_NR;
+			}		
+			else if(1 == i) //LTE :压缩因子:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_FACT_ADDR;
+			}
+			else if(2 == i) //NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR0;
+			}
+			else if(3 == i)//NR :2条天线数据交织:64*2B
+			{
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI_NR1;
+			}
+			else if(4 == i)//LTE :2条天线数据交织:16*2B 
+			{
+				bfWordCnt = (32>>2);
+				srcAddr = SM1_LTE_CELL0_EVEN_RX_ADDR_CPRI;
+			}
+			else// if(5 == i)//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			/******
+			else//LTE :AGC:1B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_LTE_CELL0_EVEN_COM_AGC_ADDR;
+			}
+			*********/
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (0<<24) | ((idBf<<1)<<8) | (idWord);
+					compVal = do_read_volatile(Nr_CompressData+idBf*bfWordCnt + idWord);//Nr_CompressData[idBf*bfWordCnt + idWord];
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if(1 == i)// compress factor:lte
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (1<<24) | ((idBf<<2)<<8) | (idWord);
+					compVal =do_read_volatile(Lte_compressData+idBf*bfWordCnt + idWord);// Lte_compressData[idBf*bfWordCnt + idWord];
+				
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 < i) && (5 > i))		// axc data
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(4 == i)//LTE
+					{
+					// 	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<3)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Lte_antData+idBf*bfWordCnt + idWord);//Lte_antData[idBf*bfWordCnt + idWord];
+					}
+					else if(3 == i)
+					{
+					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Nr_antData23+idBf*bfWordCnt + idWord);//Nr_antData23[idBf*bfWordCnt + idWord];
+					}
+					else //if (2 == i)
+					{
+					//	compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					//	compVal = (slotVal<<28) | (idVal<<24) | (idBf<<8) | (idWord);
+						compVal = do_read_volatile(Nr_antData01+idBf*bfWordCnt + idWord);//Nr_antData01[idBf*bfWordCnt + idWord];
+					}
+					
+//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (1372 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
+						realSrcAddr = srcAddr1;
+						if (0 > (idBf-bfStart))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else// if(5 == i) //NR:AGC
+		{
+		   	for (int32_t idBf = 0; idBf <((slotBfCnt*3) >> 2); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<1)<<8) | (idWord);
+				//	compVal = (slotVal<<28) | (8<<24) | ((idBf<<2)<<8) | (idWord);
+					compVal = do_read_volatile(Agc_Data + idBf*bfWordCnt + idWord);//Agc_Data[idBf*bfWordCnt + idWord];
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					#if 0
+					if ((7 == slotId) && (686 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+						if (0 > (idBf-(bfStart>>1)))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+						realSrcAddr = srcAddr1;
+					}
+					else
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					#endif
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+	//						break;
+	//						break;
+					}
+	//					__ucps2_synch(0);
+				}
+			}
+		}
+	
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}
+

public/test/testcases/case68/fronthaul/src/cpri_test_case68_AGC.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Agc_Data[2880] = {
+	0	
+};
+

public/test/testcases/case68/fronthaul/src/cpri_test_case68_NrAntdata01.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_antData01[122880] = {
+	0
+};
+

public/test/testcases/case68/fronthaul/src/cpri_test_case68_NrAntdata23.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_antData23[122880] = {
+	0
+};
+

public/test/testcases/case68/fronthaul/src/cpri_test_case68_NrComfactor.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Nr_CompressData[1920] = {
+	0
+};
+

public/test/testcases/case68/osp/src/ape_test_case68.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case70/fronthaul/inc/cpri_test_case70.h

@@ -0,0 +1,39 @@
+#ifndef _CPRI_TEST_CASE70_H_
+#define _CPRI_TEST_CASE70_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE70_SLOT_NUM				20
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+
+#define CPRI_NR7DS2U_RX_DUMMY_COM_LEN			0x73B8
+#define CPRI_NR7DS2U_RX_DUMMY_AXC_LEN			0x1CEE00
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcases/case70/fronthaul/inc/nr_mem_def.h

@@ -0,0 +1,233 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl.h"
+//#include "interface_fapi_deofdm.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_pdcch.h"
+//#include "interface_fapi_ssb.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+#define SM0_BASE_1                    	(0x009D00000)//1M
+#define SM1_BASE_1                    	(0x009E00000)//1M
+#define SM2_BASE_1                    	(0x009F00000)//1.5M
+#define SM3_BASE_1                    	(0x00A080000)//1.5M
+#define SM4_BASE_1                    	(0x00A200000)//1.5M
+#define SM5_BASE_1                    	(0x00A380000)//1.5M
+
+/***************************************SM0-SM1--2M*********************************************/
+//len define
+//SM0
+#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
+#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
+#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K
+
+#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
+#define SM0_RESERVED0_LEN                          0X00000400  //1K
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED1_LEN                          0x00000400  //1K
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED2_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
+#define SM0_RESERVED3_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED4_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED5_LEN                          0x00005900  //22.25
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079400  //485k (480k+3.75k+1.25K)
+#define SM1_RESERVED0_LEN                          0x0001EC00  //123k
+
+#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE_1)
+#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
+#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+
+#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
+#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
+#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 
+
+#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
+#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
+#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
+#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
+#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)
+
+/***************************************SM2-SM5--6M*********************************************/
+
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM5_RESERVED0_LEN                          0x00034400  //209k
+#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x00010000  //64k
+#define SM5_ERROR_RECORD_CNT_LEN                   0x00003000  //12k
+#define SM5_NR_STATISTIC_CNT_LEN                   0x00000120  //288byte
+#define SM5_STATE_RECORD_CNT_LEN                   0x4E0 //1248byte
+#define SM5_COMMON_DEBUG_LEN                       0x400 //1K
+#define SM5_PDCCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PDSCH_DEBUG_LEN                        0x400 //1K
+#define SM5_SSB_DEBUG_LEN                          0x400 //1K
+#define SM5_CSIRS_DEBUG_LEN                        0x400 //1K
+#define SM5_DEOFDM_DEBUG_LEN                       0x400 //1K
+#define SM5_PUCCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PUSCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PRACH_DEBUG_LEN                        0x400 //1K
+#define SM5_SRS_DEBUG_LEN                          0x400 //1K
+#define SM5_RESERVED3_LEN                          0x00011000  //76.5K
+
+
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE_1)
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
+#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
+#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
+#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
+#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)
+#define SM5_ERROR_RECORD_CNT_ADDR                  (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)
+#define SM5_NR_STATISTIC_CNT_ADDR                  (SM5_ERROR_RECORD_CNT_ADDR + SM5_ERROR_RECORD_CNT_LEN)
+#define SM5_STATE_RECORD_CNT_ADDR                  (SM5_NR_STATISTIC_CNT_ADDR + SM5_NR_STATISTIC_CNT_LEN)
+#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_CNT_ADDR + SM5_STATE_RECORD_CNT_LEN)
+#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
+#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
+#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
+#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
+#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
+#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
+#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
+#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
+#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)
+#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
+
+#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
+/**************************************DDR***************************************************/
+/*******************************共180M可用0x84C00000-0x8FFFFFFF******************************/
+
+#define DDR_NR_CELL0_RX_LEN            (0xA00000)//为多小区预留10M, NR单小区CPRI:120*1024*4*3//120K 4ant 3slot
+#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
+#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
+#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
+#define JESD_CSU_LINK_TX_TABLE_LEN     (0x8000)//JESD TX link 32k
+#define JESD_CSU_LINK_RX_TABLE_LEN     (0x8000)//JESD RX link 32k
+#define DDR_TEST_MAC_DL_DATA_BUF_LEN  (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+#define DDR_WRITE_MONITOR_LEN         (0x400000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_ELN          (0X400000)//预留4M空间给读DDR检查功能
+
+
+//#define DDR_PHY_BASE                   (0x6BC00000) //共180M可用0x84C00000-0x8FFFFFFF
+#define DDR_PHY_BASE                   (0x84C00000) 
+
+#define DDR_PHY_RECORD_ADDR            (DDR_PHY_BASE + DDR_NR_CELL0_RX_LEN)//0x85600000
+#define DDR_NR_DL_RECORD_ADDR          (DDR_PHY_RECORD_ADDR)             //0x85600000 - 0x87600000
+#define DDR_NR_UL_RECORD_ADDR          (DDR_NR_DL_RECORD_ADDR + DDR_NR_DL_RECORD_LEN)//0x87600000 - 0x89600000
+
+#define DDR_TEST_MAC_NR_CELL0_EVEN_RX_DATA_ADDR   (0x89600000)//0x89600000
+#define DDR_TEST_MAC_NR_CELL0_ODD_RX_DATA_ADDR    (0x89700000)//0x89700000
+#define DDR_TEST_MAC_NR_CELL1_EVEN_RX_DATA_ADDR   (0x89800000)//0x89600000
+#define DDR_TEST_MAC_NR_CELL1_ODD_RX_DATA_ADDR    (0x89900000)//0x89700000
+#define JESD_CSU_LINK_TX_TABLE_ADDR    (0x8A000000)//jesd 模式下Tx 链表地址 32k
+#define JESD_CSU_LINK_RX_TABLE_ADDR    (0x8A008000)//jesd 模式下Rx 链表地址 32k
+
+#define DDR_TEST_MAC_DL_DATA_BUF_ADDR  (0x8A010000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+
+#define DDR_WRITE_MONITOR_ADDR         (0x8B410000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_ADDR          (0x8B810000)//预留4M空间给读DDR检查功能
+
+#define FAPI_PDCCH_MSG_ADDR            (0x8BC10000)
+#define FAPI_SSB_MSG_ADDR              (0x8BC10400)
+#define FAPI_CSIRS_MSG_ADDR            (0x8BC10800)
+
+#define DDR_NR_CELL0_RX_ADDR           (DDR_PHY_BASE)//0x84C00000-0x85600000 10M
+#define DDR_NR_CELL0_RX_AGC_ADDR       (DDR_NR_CELL0_RX_ADDR + DDR_NR_CELL0_RX_LEN*2)
+
+#define DDR_MAX_ADDR                   (0X90000000)
+
+#define CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR                  (0xB4200000)
+#define CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR                  (0XB4230000)
+
+#define CPRI_NRCELL_TXDUMMY_SLOTS_COMPRESS_ADDR             (0xB4260000)
+#define CPRI_NRCELL_TXDUMMY_SLOTS_AGC_ADDR                  (0XB4265000)
+#define CPRI_NRCELL_TXDUMMY_SLOTS_AXCDATA_ADDR              (0XB426f000)//len:0x269000
+
+#define CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR             (0xB44D8000)//0xE770
+#define CPRI_NRCELL_RXDUMMY_SLOTS_AGC_ADDR                  (0XB44E6770)//0x1CEE0
+#define CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR              (0XB4503650)//len:0x73B800  --0xB4C3EE50
+
+
+#endif

public/test/testcases/case70/fronthaul/inc/phy_timer_csu_config.h

@@ -0,0 +1,120 @@
+/******************************************************************
+ * @file  phy_timer_csu_config.h
+ * @brief:    [file description] 
+ * @author: guicheng.liu
+ * @Date 2022年7月7日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
+ * Change_date         Owner         Change_content
+ * 2022年7月7日        guicheng.liu       create file
+
+*****************************************************************/
+
+#ifndef     FPHY_TIMER_CSU_CONFIG_H
+#define     FPHY_TIMER_CSU_CONFIG_H
+//#include <type_define.h>
+#include "typedef.h"
+#include "phy_para.h"
+
+//#include "phy_nr_context.h"
+//#include "drv_rfm.h"
+
+#define CPRI_LINK_START_ADDR						0x721E800 //ECS SM后8K
+
+#define NR_LONGCP_SAM_CNT								4448
+#define NR_SHORTCP_SAM_CNT								4384
+
+typedef struct
+{
+    uint16_t period;//=t_us*num_t;
+    uint16_t rev;
+
+    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
+    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
+}timer_info_t;
+
+typedef struct
+{
+    uint8_t flag;//0:default timer, 1:inuse timer
+    uint8_t rev[3];
+
+    timer_info_t default_timer;
+    timer_info_t inuse_timer;
+}phy_timer_t;
+
+typedef struct
+{
+    uint8_t total_ants;
+    uint8_t scs;
+    uint8_t num_dl_symbols;
+    uint8_t rev;
+
+    uint16_t num_dl_tti;
+    uint16_t rev1;
+
+    phy_timer_config_ind_t jesd_timer;
+    phy_timer_config_ind_t cpri_timer;
+}phy_csu_timer_t;
+
+typedef struct
+{
+    uint32_t sampling_rate;
+
+    uint8_t tatol_tx_ants;
+    uint8_t tatol_rx_ants;
+    uint16_t rev;
+
+    uint8_t num_tx0_ants;
+    uint8_t num_tx1_ants;
+    uint8_t num_rx0_ants;
+    uint8_t num_rx1_ants;
+
+    //tx的链表地址
+    uint32_t tx0_even_f7_link_addr;
+    uint32_t tx0_even_b7_link_addr;
+    uint32_t tx0_odd_f7_link_addr;
+    uint32_t tx0_odd_b7_link_addr;
+    uint32_t tx0_s_link_addr;
+    uint32_t tx0_1st_dummy_link_addr;
+    uint32_t tx0_2nd_dummy_link_addr;
+
+    //rx的链表地址
+    uint32_t rx0_1st_dummy_link_addr;
+    uint32_t rx0_2nd_dummy_link_addr;
+    uint32_t rx0_s_link_addr;
+    uint32_t rx0_normal0_link_addr;
+    uint32_t rx0_normal1_link_addr;
+    uint32_t rx0_normal2_link_addr;
+}phy_csu_link_info_t;
+
+
+void Phy_Timer_Csu_Init();
+
+//void Csu_Dma_Init();
+//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx0_ants, 
+//                                uint16_t num_rx_tti);
+//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx1_ants, 
+//                                uint16_t num_rx_tti);
+void Config_Csu_Timer(uint16_t dl_bw,
+                            uint16_t num_tx_ants,
+                            uint8_t nrOfSlots,
+                            uint16_t num_dl_tti,
+                            uint8_t num_dl_symbols,
+                            uint8_t num_ul_symbols,
+                            uint8_t scs,
+                            uint32_t run_core_id_map);
+//void Update_Phy_Timer(uint8_t tdd_period);
+//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
+//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);
+void Phy_Timer_Csu_Config_Nr();
+void Phy_Timer_Csu_Config_Lte();
+
+
+#endif

public/test/testcases/case70/fronthaul/src/cpri_test_case70.s.c

@@ -0,0 +1,810 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+#include "cpri_csu_api.h"
+#include "cpri_test_case70.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "nr_mem_def.h"
+#include "phy_timer_csu_config.h"
+#include "mem_sections.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+
+#include <malloc.h>
+//DDR0 uint32_t srcImData[5*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t gCpriTestMode;
+//extern uint32_t           CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_10, OTIC_MAP_FIGURE16);
+
+	return 0;
+}
+
+
+int32_t fh_csu_test_init(void)
+{
+	 Phy_Timer_Csu_Config_Nr();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint8_t idSymbol = 0;
+	uint16_t idBF = 0;
+	uint16_t idWord = 0;
+
+	uint32_t* pSrcAddr = NULL;
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//前7symbol
+	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//后7symbol
+	uint32_t  symbolBfCnt = 0;
+	uint32_t  idSlotBf = 0;
+	uint32_t  val = 0;
+	
+	//uint32_t* srcImData = dmalloc(10240, DM0);
+	
+	//debug_write((DBG_DDR_IDX_DRV_BASE+192), (uint32_t)(&txCmdFifo)); // 0x300
+	//debug_write((DBG_DDR_IDX_DRV_BASE+193), (uint32_t)(&rxCmdFifo)); // 0x304
+
+	uint32_t cpyCnt = 0;
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+	//debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+	cpyCnt++;
+
+	// valid data
+	/********** compress factor*********/
+	for(idID =0 ; idID < 2; idID++)
+	{
+     	for (idSlot = 0; idSlot <= 1; idSlot++)//NR cell
+		{
+			bfByteCnt = 2;
+			
+		//	pSrcAddr = srcImData;
+			if (0 == idSlot)	// even slot
+			{
+				if(0 == idID)
+				{
+					dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;
+				}
+				else
+				{
+					dstAddr = SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR;
+				}
+				
+			}
+			else				// odd slot
+			{
+				if(0 == idID)
+				{
+					dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
+				}
+				else
+				{
+					dstAddr = SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR;
+				}
+				
+			}
+			pSrcAddr = ((uint32_t*)dstAddr);
+			for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
+			{
+				val = (idSlot<<28) | (idID<<24)| ((idBF<<1)<<8)  | (idID);
+			//	*pSrcAddr = val;
+				do_write(((uint32_t)pSrcAddr), val);	
+				pSrcAddr++;
+			}
+			dataLen = (bfByteCnt*slotBfCnt); 
+		
+		//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+		}
+	}
+	
+	// IQ data	NR 
+	for (idID = 2; idID < 6; idID++)
+	{
+		bfByteCnt = 64*2;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			idSlotBf = 0;
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					if((2 == idID) || (3 == idID))//NR cell0
+					{
+						dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+					}
+					else
+					{
+						dstAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+					}
+					
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					if((2 == idID) || (3 == idID))//NR cell0
+					{
+						dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+					}
+					else
+					{
+						dstAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+					}
+					
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					if((2 == idID) || (3 == idID))//NR cell0
+					{
+						dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+					}
+					else
+					{
+						dstAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+					}
+					
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					if((2 == idID) || (3 == idID))//NR cell0
+					{
+						dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+					}
+					else
+					{
+						dstAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+					}
+					
+				}
+				
+				for (idSymbol = 0; idSymbol < 7; idSymbol++)
+				{
+		//			pSrcAddr = srcImData;
+					pSrcAddr = ((uint32_t*)dstAddr);
+					if ((0 == idSymbol) && (0 == idSymbolBlock))
+					{
+						symbolBfCnt = LONGCP_BF_CNT;
+					}
+					else
+					{
+						symbolBfCnt = SHORTCP_BF_CNT;
+					}
+					for (idBF = 0; idBF < symbolBfCnt; idBF++)	// basic frame
+			 		{
+						for (idWord = 0; idWord < (bfByteCnt>>2); idWord++)
+						{
+								val = (idSlot<<28) | (idID<<24) | ((idSlotBf++)<<8) | (idWord);
+								//*pSrcAddr = val;
+								do_write(((uint32_t)pSrcAddr), val);	
+								pSrcAddr++;
+						}
+			 		}
+					dataLen = symbolBfCnt*bfByteCnt;
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//					cpyCnt++;
+				//	memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+					dstAddr += dataLen;
+				}
+			}
+		}
+	}
+
+
+/************
+	// agc factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 4;
+		
+		pSrcAddr = srcImData;
+		if (0 == idSlot)	// even slot
+		{
+			dstAddr = SM5_RESERVED3_ADDR;
+		}
+		else				// odd slot
+		{
+			dstAddr = SM5_RESERVED3_ADDR;
+		}
+		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
+		{
+			val = (idSlot<<28) | (6<<24) | ((idBF<<1)<<8) | (0);
+			*pSrcAddr = val;
+			//do_write(((uint32_t)pSrcAddr), val);
+			pSrcAddr++;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//		cpyCnt++;
+		
+		memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+//		ape_csu_dma_1D_L2G_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	}
+**********/
+
+#if 1
+	/***************dummy data***********/
+	/***************compress factor***********/
+	uint8_t bitOffset = 1; // one bf, 2B
+	//NR小区 0
+	
+	// S slot, symbol6~13, odd slot
+	srcAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
+	dstAddr = CPRI_NRCELL_TXDUMMY_SLOTS_COMPRESS_ADDR;
+	dataLen = (SHORTCP_BF_CNT*8)<<bitOffset;
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	// slot8, even slot
+	srcAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;
+	dstAddr += dataLen;
+	dataLen = slotBfCnt<<bitOffset;
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	// slot9, odd slot
+	srcAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
+	dstAddr += dataLen;
+	dataLen = slotBfCnt<<bitOffset;
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+
+	//NR小区 1
+	// S slot, symbol6~13, odd slot
+	srcAddr = SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
+	dstAddr = CPRI_NRCELL_TXDUMMY_SLOTS_COMPRESS_ADDR+(4936<<bitOffset);//CPRI_NR7DS2U_TX_DUMMY_COMP_FACTOR_LEN;
+	dataLen = (SHORTCP_BF_CNT*8)<<bitOffset;
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	// slot8, even slot
+	srcAddr = SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR;
+	dstAddr += dataLen;
+	dataLen = slotBfCnt<<bitOffset;
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	// slot9, odd slot
+	srcAddr = SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR;
+	dstAddr += dataLen;
+	dataLen = slotBfCnt<<bitOffset;
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+
+	/***************axc data***********/
+	bitOffset = 7;		// one bf, 128B
+	for (uint8_t antId = 0; antId < 4; antId++)//NR CELL0 ,NR CELL1
+	{
+		// S slot, symbol 6, odd slot
+		if(2> antId)//cell 0
+		{
+			srcAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + (antId*(f7BfCnt<<bitOffset)) + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
+		}
+		else  //cell 1
+		{
+			srcAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + ((antId-2)*(f7BfCnt<<bitOffset)) + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
+		}
+		
+		dstAddr = CPRI_NRCELL_TXDUMMY_SLOTS_AXCDATA_ADDR + antId*(4936<<bitOffset);//CPRI_NR7DS2U_TX_DUMMY_AXCDATA_LEN;
+		dataLen = (SHORTCP_BF_CNT)<<bitOffset;	
+		cpyCnt++;
+		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+		// S slot, symbol7~13
+		if(2> antId)
+		{
+			srcAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + (antId*(b7BfCnt<<bitOffset));
+		}
+		else
+		{
+			srcAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + ((antId-2)*(b7BfCnt<<bitOffset));
+		}		
+		dstAddr += dataLen;
+		dataLen = b7BfCnt<<bitOffset;	
+		cpyCnt++;
+		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+		// slot8, even slot, symbol0~6	
+		if(2> antId)
+		{
+			srcAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + (antId*(f7BfCnt<<bitOffset));
+		}
+		else
+		{
+			srcAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + ((antId-2)*(f7BfCnt<<bitOffset));
+		}	
+		dstAddr += dataLen;
+		dataLen = f7BfCnt<<bitOffset;		
+		cpyCnt++;
+		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+		// slot8, even slot, symbol7~13
+		if(2> antId)
+		{
+			srcAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + (antId*(b7BfCnt<<bitOffset));
+		}
+		else
+		{
+			srcAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + ((antId-2)*(b7BfCnt<<bitOffset));
+		}	
+		dstAddr += dataLen;
+		dataLen = b7BfCnt<<bitOffset;	
+		cpyCnt++;
+		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+		// slot9, odd slot, symbol0~6
+		if(2> antId)
+		{
+			srcAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + (antId*(f7BfCnt<<bitOffset));
+		}
+		else
+		{
+			srcAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + ((antId-2)*(f7BfCnt<<bitOffset));
+		}	
+		dstAddr += dataLen;
+		dataLen = f7BfCnt<<bitOffset;		
+		cpyCnt++;
+		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+		// slot9, odd slot, symbol7~13	
+		if(2> antId)
+		{
+			srcAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + (antId*(b7BfCnt<<bitOffset));
+		}
+		else
+		{
+			srcAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + ((antId-2)*(b7BfCnt<<bitOffset));
+		}
+		dstAddr += dataLen;
+		dataLen = b7BfCnt<<bitOffset;		
+		cpyCnt++;
+		spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	}
+#endif
+
+/********************
+	// AGC factor
+//	bitOffset = 1; // one bf, 2B
+	bitOffset = 2; // one bf, 4B
+	// S slot, symbol6~13, odd slot
+	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR + ((LONGCP_BF_CNT + SHORTCP_BF_CNT*5)<<bitOffset);
+	dstAddr = CPRI_NR7DS2U_TX_DUMMY_AGC_ADDR;
+	dataLen = (SHORTCP_BF_CNT*8)<<bitOffset;
+	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	// slot8, even slot
+	srcAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_AGC_ADDR;
+	dstAddr += dataLen;
+	dataLen = slotBfCnt<<bitOffset;
+	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	// slot9, odd slot
+	srcAddr = CPRI_NR7DS2U_TX_SLOT_ODD_AGC_ADDR;
+	dstAddr += dataLen;
+	dataLen = slotBfCnt<<bitOffset;
+	//ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, tag++, 1);
+	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
+	*****************/
+}
+
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
+}
+
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE70_SLOT_NUM>>1); i++)
+	//	for (int32_t i = 7; i < (CPRI_CASE70_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}
+		}
+#endif
+	}
+	Cpri_Header_Rx();
+}
+
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	// move data from sm to ddr
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t srcAddr1 = 0;
+	uint32_t realSrcAddr = 0;
+	uint32_t dataLen = 0;
+	uint8_t bitOffset = 0;
+	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+	
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)//no agc
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		if ((slotId >=0) && (slotId <= 6))
+		{
+			slotVal = slotId & 0x1;
+#if 1
+			if (2 > i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN; //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+#endif
+		}
+		else if (7 == slotId)		// compare S slot, odd slot
+		{
+			bfStart = (LONGCP_BF_CNT+SHORTCP_BF_CNT*9);
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset);//Rx symbol 0~5地址
+				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR;//Rx symbol 6~13地址
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN;
+				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
+				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR + 0x448+(i-2)*((SHORTCP_BF_CNT*4)<<bitOffset);//0x448是cell0的压缩因子的长度
+			}
+			else //if((4 == i)||(5 == i))
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
+				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR +  0x448+(i-4)*((SHORTCP_BF_CNT*4)<<bitOffset);
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (8 == slotId)		// current slot is even slot, compare even slot, slot8
+		{
+			slotVal = 0;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR + 0xF00 +((i-2)*(slotBfCnt<<bitOffset));
+			}
+			else// if((4 == i)||(5 == i))
+			{
+			    bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR + 0xF00 + ((i-4)*(slotBfCnt<<bitOffset));
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (9 == slotId)	// compare odd slot, slot9
+		{
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_ODD_COMPRESS_ADDR;
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR +  0xF00 +((i-2)*(slotBfCnt<<bitOffset));
+			}
+			else //if((4 == i)||(5 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR +  0xF00+ ((i-4)*(slotBfCnt<<bitOffset));
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+
+		//if (2 > i)	// NR cell compress factor
+		if (0  == i)
+		{
+			for (int32_t idBf = 0; idBf <  (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (idVal<<24) | ((idBf<<1)<<8) | (i);
+					
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+								
+						if ((7 == slotId) && (686 <= idBf))
+						{
+							recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+							if (0 > (idBf-(bfStart>>1)))
+							{
+								gBfStartErr++;
+								debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+							}
+							realSrcAddr = srcAddr1;
+						}
+						else 
+						{
+							recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+							realSrcAddr = srcAddr;
+						}
+					
+						recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+						__ucps2_synch(0);
+						if (recvVal != compVal)
+						{
+							if (gErrSlotIdCnt < 0x100)
+							{
+								debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+								debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+								debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+								debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+								debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+								debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+								debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+							}
+							gErrSlotIdCnt++;
+						}				
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		//else //if((1 < i)	&& (6 > i))// NR CELL0
+		else if ((2 == i) || (3 == i))
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					
+//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					
+					if ((7 == slotId) && (1372 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
+						realSrcAddr = srcAddr1;
+						if (0 > (idBf-bfStart))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+					}
+					else 
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					
+//					__ucps2_synch(0);
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+					}
+				}
+			}
+		}
+		else
+		{
+		}
+		
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}
+

public/test/testcases/case70/osp/src/ape_test_case70.s.c

@@ -0,0 +1,60 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : ape_test_case1.s.c
+// Author        : 
+// Created On    : 2022-10-26
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "osp_task.h"
+#include "osp_timer.h"
+#include "ucp_printf.h"
+
+
+void ape0_test_task_reg(void)
+{
+    return ;
+}
+
+void ape1_test_task_reg(void)
+{
+    return ;
+}
+
+void ape2_test_task_reg(void)
+{
+    return ;
+}
+
+void ape3_test_task_reg(void)
+{
+    return ;
+}
+
+void ape4_test_task_reg(void)
+{
+    return ;
+}
+
+void ape5_test_task_reg(void)
+{
+    return ;
+}
+
+void ape6_test_task_reg(void)
+{
+    return ;
+}
+
+void ape7_test_task_reg(void)
+{
+    return ;
+}
+

public/test/testcases/case71/fronthaul/inc/cpri_test_case71.h

@@ -0,0 +1,39 @@
+#ifndef _CPRI_TEST_CASE70_H_
+#define _CPRI_TEST_CASE70_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE70_SLOT_NUM				20
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+
+#define CPRI_NR7DS2U_RX_DUMMY_COM_LEN			0x73B8
+#define CPRI_NR7DS2U_RX_DUMMY_AXC_LEN			0x1CEE00
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcases/case71/fronthaul/inc/nr_mem_def.h

@@ -0,0 +1,233 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl.h"
+//#include "interface_fapi_deofdm.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_pdcch.h"
+//#include "interface_fapi_ssb.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+#define SM0_BASE_1                    	(0x009D00000)//1M
+#define SM1_BASE_1                    	(0x009E00000)//1M
+#define SM2_BASE_1                    	(0x009F00000)//1.5M
+#define SM3_BASE_1                    	(0x00A080000)//1.5M
+#define SM4_BASE_1                    	(0x00A200000)//1.5M
+#define SM5_BASE_1                    	(0x00A380000)//1.5M
+
+/***************************************SM0-SM1--2M*********************************************/
+//len define
+//SM0
+#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
+#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
+#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K
+
+#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
+#define SM0_RESERVED0_LEN                          0X00000400  //1K
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED1_LEN                          0x00000400  //1K
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED2_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
+#define SM0_RESERVED3_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED4_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED5_LEN                          0x00005900  //22.25
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079400  //485k (480k+3.75k+1.25K)
+#define SM1_RESERVED0_LEN                          0x0001EC00  //123k
+
+#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE_1)
+#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
+#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+
+#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
+#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
+#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 
+
+#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
+#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
+#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
+#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
+#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)
+
+/***************************************SM2-SM5--6M*********************************************/
+
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM5_RESERVED0_LEN                          0x00034400  //209k
+#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x00010000  //64k
+#define SM5_ERROR_RECORD_CNT_LEN                   0x00003000  //12k
+#define SM5_NR_STATISTIC_CNT_LEN                   0x00000120  //288byte
+#define SM5_STATE_RECORD_CNT_LEN                   0x4E0 //1248byte
+#define SM5_COMMON_DEBUG_LEN                       0x400 //1K
+#define SM5_PDCCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PDSCH_DEBUG_LEN                        0x400 //1K
+#define SM5_SSB_DEBUG_LEN                          0x400 //1K
+#define SM5_CSIRS_DEBUG_LEN                        0x400 //1K
+#define SM5_DEOFDM_DEBUG_LEN                       0x400 //1K
+#define SM5_PUCCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PUSCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PRACH_DEBUG_LEN                        0x400 //1K
+#define SM5_SRS_DEBUG_LEN                          0x400 //1K
+#define SM5_RESERVED3_LEN                          0x00011000  //76.5K
+
+
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE_1)
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
+#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
+#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
+#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
+#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)
+#define SM5_ERROR_RECORD_CNT_ADDR                  (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)
+#define SM5_NR_STATISTIC_CNT_ADDR                  (SM5_ERROR_RECORD_CNT_ADDR + SM5_ERROR_RECORD_CNT_LEN)
+#define SM5_STATE_RECORD_CNT_ADDR                  (SM5_NR_STATISTIC_CNT_ADDR + SM5_NR_STATISTIC_CNT_LEN)
+#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_CNT_ADDR + SM5_STATE_RECORD_CNT_LEN)
+#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
+#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
+#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
+#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
+#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
+#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
+#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
+#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
+#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)
+#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
+
+#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
+/**************************************DDR***************************************************/
+/*******************************共180M可用0x84C00000-0x8FFFFFFF******************************/
+
+#define DDR_NR_CELL0_RX_LEN            (0xA00000)//为多小区预留10M, NR单小区CPRI:120*1024*4*3//120K 4ant 3slot
+#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
+#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
+#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
+#define JESD_CSU_LINK_TX_TABLE_LEN     (0x8000)//JESD TX link 32k
+#define JESD_CSU_LINK_RX_TABLE_LEN     (0x8000)//JESD RX link 32k
+#define DDR_TEST_MAC_DL_DATA_BUF_LEN  (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+#define DDR_WRITE_MONITOR_LEN         (0x400000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_ELN          (0X400000)//预留4M空间给读DDR检查功能
+
+
+//#define DDR_PHY_BASE                   (0x6BC00000) //共180M可用0x84C00000-0x8FFFFFFF
+#define DDR_PHY_BASE                   (0x84C00000) 
+
+#define DDR_PHY_RECORD_ADDR            (DDR_PHY_BASE + DDR_NR_CELL0_RX_LEN)//0x85600000
+#define DDR_NR_DL_RECORD_ADDR          (DDR_PHY_RECORD_ADDR)             //0x85600000 - 0x87600000
+#define DDR_NR_UL_RECORD_ADDR          (DDR_NR_DL_RECORD_ADDR + DDR_NR_DL_RECORD_LEN)//0x87600000 - 0x89600000
+
+#define DDR_TEST_MAC_NR_CELL0_EVEN_RX_DATA_ADDR   (0x89600000)//0x89600000
+#define DDR_TEST_MAC_NR_CELL0_ODD_RX_DATA_ADDR    (0x89700000)//0x89700000
+#define DDR_TEST_MAC_NR_CELL1_EVEN_RX_DATA_ADDR   (0x89800000)//0x89600000
+#define DDR_TEST_MAC_NR_CELL1_ODD_RX_DATA_ADDR    (0x89900000)//0x89700000
+#define JESD_CSU_LINK_TX_TABLE_ADDR    (0x8A000000)//jesd 模式下Tx 链表地址 32k
+#define JESD_CSU_LINK_RX_TABLE_ADDR    (0x8A008000)//jesd 模式下Rx 链表地址 32k
+
+#define DDR_TEST_MAC_DL_DATA_BUF_ADDR  (0x8A010000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+
+#define DDR_WRITE_MONITOR_ADDR         (0x8B410000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_ADDR          (0x8B810000)//预留4M空间给读DDR检查功能
+
+#define FAPI_PDCCH_MSG_ADDR            (0x8BC10000)
+#define FAPI_SSB_MSG_ADDR              (0x8BC10400)
+#define FAPI_CSIRS_MSG_ADDR            (0x8BC10800)
+
+#define DDR_NR_CELL0_RX_ADDR           (DDR_PHY_BASE)//0x84C00000-0x85600000 10M
+#define DDR_NR_CELL0_RX_AGC_ADDR       (DDR_NR_CELL0_RX_ADDR + DDR_NR_CELL0_RX_LEN*2)
+
+#define DDR_MAX_ADDR                   (0X90000000)
+
+#define CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR                  (0xB4200000)
+#define CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR                  (0XB4230000)
+
+#define CPRI_NRCELL_TXDUMMY_SLOTS_COMPRESS_ADDR             (0xB4260000)
+#define CPRI_NRCELL_TXDUMMY_SLOTS_AGC_ADDR                  (0XB4265000)
+#define CPRI_NRCELL_TXDUMMY_SLOTS_AXCDATA_ADDR              (0XB426f000)//len:0x269000
+
+#define CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR             (0xB44D8000)//0xE770
+#define CPRI_NRCELL_RXDUMMY_SLOTS_AGC_ADDR                  (0XB44E6770)//0x1CEE0
+#define CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR              (0XB4503650)//len:0x73B800  --0xB4C3EE50
+
+
+#endif

public/test/testcases/case71/fronthaul/inc/phy_timer_csu_config.h

@@ -0,0 +1,120 @@
+/******************************************************************
+ * @file  phy_timer_csu_config.h
+ * @brief:    [file description] 
+ * @author: guicheng.liu
+ * @Date 2022年7月7日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
+ * Change_date         Owner         Change_content
+ * 2022年7月7日        guicheng.liu       create file
+
+*****************************************************************/
+
+#ifndef     FPHY_TIMER_CSU_CONFIG_H
+#define     FPHY_TIMER_CSU_CONFIG_H
+//#include <type_define.h>
+#include "typedef.h"
+#include "phy_para.h"
+
+//#include "phy_nr_context.h"
+//#include "drv_rfm.h"
+
+#define CPRI_LINK_START_ADDR						0x721E800 //ECS SM后8K
+
+#define NR_LONGCP_SAM_CNT								4448
+#define NR_SHORTCP_SAM_CNT								4384
+
+typedef struct
+{
+    uint16_t period;//=t_us*num_t;
+    uint16_t rev;
+
+    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
+    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
+}timer_info_t;
+
+typedef struct
+{
+    uint8_t flag;//0:default timer, 1:inuse timer
+    uint8_t rev[3];
+
+    timer_info_t default_timer;
+    timer_info_t inuse_timer;
+}phy_timer_t;
+
+typedef struct
+{
+    uint8_t total_ants;
+    uint8_t scs;
+    uint8_t num_dl_symbols;
+    uint8_t rev;
+
+    uint16_t num_dl_tti;
+    uint16_t rev1;
+
+    phy_timer_config_ind_t jesd_timer;
+    phy_timer_config_ind_t cpri_timer;
+}phy_csu_timer_t;
+
+typedef struct
+{
+    uint32_t sampling_rate;
+
+    uint8_t tatol_tx_ants;
+    uint8_t tatol_rx_ants;
+    uint16_t rev;
+
+    uint8_t num_tx0_ants;
+    uint8_t num_tx1_ants;
+    uint8_t num_rx0_ants;
+    uint8_t num_rx1_ants;
+
+    //tx的链表地址
+    uint32_t tx0_even_f7_link_addr;
+    uint32_t tx0_even_b7_link_addr;
+    uint32_t tx0_odd_f7_link_addr;
+    uint32_t tx0_odd_b7_link_addr;
+    uint32_t tx0_s_link_addr;
+    uint32_t tx0_1st_dummy_link_addr;
+    uint32_t tx0_2nd_dummy_link_addr;
+
+    //rx的链表地址
+    uint32_t rx0_1st_dummy_link_addr;
+    uint32_t rx0_2nd_dummy_link_addr;
+    uint32_t rx0_s_link_addr;
+    uint32_t rx0_normal0_link_addr;
+    uint32_t rx0_normal1_link_addr;
+    uint32_t rx0_normal2_link_addr;
+}phy_csu_link_info_t;
+
+
+void Phy_Timer_Csu_Init();
+
+//void Csu_Dma_Init();
+//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx0_ants, 
+//                                uint16_t num_rx_tti);
+//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx1_ants, 
+//                                uint16_t num_rx_tti);
+void Config_Csu_Timer(uint16_t dl_bw,
+                            uint16_t num_tx_ants,
+                            uint8_t nrOfSlots,
+                            uint16_t num_dl_tti,
+                            uint8_t num_dl_symbols,
+                            uint8_t num_ul_symbols,
+                            uint8_t scs,
+                            uint32_t run_core_id_map);
+//void Update_Phy_Timer(uint8_t tdd_period);
+//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
+//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);
+void Phy_Timer_Csu_Config_Nr();
+void Phy_Timer_Csu_Config_Lte();
+
+
+#endif

public/test/testcases/case71/fronthaul/src/cpri_test_case71.s.c

@@ -0,0 +1,628 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+#include "cpri_csu_api.h"
+#include "cpri_test_case71.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "nr_mem_def.h"
+#include "phy_timer_csu_config.h"
+#include "mem_sections.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+
+extern uint32_t compressData0[1920];
+extern uint32_t compressData1[1920];
+extern uint32_t antData0[122880];
+extern uint32_t antData1[122880];
+extern uint32_t antData2[122880];
+extern uint32_t antData3[122880];
+
+//DDR0 uint32_t srcImData[5*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t gCpriTestMode;
+//extern uint32_t           CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_10, OTIC_MAP_FIGURE16);
+
+	return 0;
+}
+
+
+int32_t fh_csu_test_init(void)
+{
+	 Phy_Timer_Csu_Config_Nr();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+//	uint8_t idSymbol = 0;
+//	uint16_t idBF = 0;
+//	uint16_t idWord = 0;
+
+	uint32_t* pSrcAddr = NULL;
+//	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//前7symbol
+	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//后7symbol
+//	uint32_t  symbolBfCnt = 0;
+	uint32_t  idSlotBf = 0;
+//	uint32_t  val = 0;
+	uint32_t cpyCnt = 0;
+	
+	cpyCnt++;
+	// valid data
+	/********** compress factor*********/
+	for(idID =0 ; idID < 2; idID++)
+	{
+     	for (idSlot = 0; idSlot <= 1; idSlot++)//NR cell
+		{
+			bfByteCnt = 2;
+			if (0 == idSlot)	// even slot
+			{
+				if(0 == idID)
+				{
+					pSrcAddr =compressData0;
+					dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;				
+				}
+				else
+				{
+					dstAddr = SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR;
+					pSrcAddr =compressData1;
+				}			
+			}
+			else				// odd slot
+			{
+				if(0 == idID)
+				{
+					dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
+					pSrcAddr =compressData0;// + (1920>>1);
+				}
+				else
+				{
+					dstAddr = SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR;
+					pSrcAddr =compressData1;// + (1920>>1);
+				}
+				
+			}
+			dataLen = (bfByteCnt*slotBfCnt); 
+		    memcpy_ucp((void*)dstAddr,(void*)pSrcAddr, dataLen);
+		}
+	}
+	
+	// IQ data	NR 
+	for (idID = 2; idID < 6; idID++)
+	{
+		bfByteCnt = 64*2;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			idSlotBf = 0;
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0;
+							dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1;
+							dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2;
+							dstAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3;
+							dstAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+					}
+					dataLen = f7BfCnt*bfByteCnt;
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0 + 30752;
+							dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1  + 30752;
+							dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2  + 30752;
+							dstAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3  + 30752;
+							dstAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+					}
+					dataLen = b7BfCnt*bfByteCnt;
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0;// + 61440;
+							dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1;//  + 61440;
+							dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2;//  + 61440;
+							dstAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3;//  + 61440;
+							dstAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+					}
+					dataLen = f7BfCnt*bfByteCnt;
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0 + 30752;// + 61440 + 30752 ;
+							dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1 + 30752;//+ 61440 + 30752;
+							dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2 + 30752;//+ 61440 + 30752;
+							dstAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3 + 30752;//+ 61440 + 30752;
+							dstAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+					}
+					dataLen = b7BfCnt*bfByteCnt;
+				}
+			    memcpy_ucp((void*)dstAddr,(void*)pSrcAddr, dataLen);
+			}
+		}
+	}
+
+}
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
+}
+
+
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE70_SLOT_NUM>>1); i++)
+	//	for (int32_t i = 7; i < (CPRI_CASE70_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}
+		}
+#endif
+	}
+	Cpri_Header_Rx();
+}
+
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	// move data from sm to ddr
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t srcAddr1 = 0;
+	uint32_t realSrcAddr = 0;
+	uint32_t dataLen = 0;
+	uint8_t bitOffset = 0;
+	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+	
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)//no agc
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		if ((slotId >=0) && (slotId <= 6))
+		{
+			slotVal = slotId & 0x1;
+#if 1
+			if (2 > i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN; //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+#endif
+		}
+		else if (7 == slotId)		// compare S slot, odd slot
+		{
+			bfStart = (LONGCP_BF_CNT+SHORTCP_BF_CNT*9);
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset);//Rx symbol 0~5地址
+				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR;//Rx symbol 6~13地址
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN;
+				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
+				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR + 0x448+(i-2)*((SHORTCP_BF_CNT*4)<<bitOffset);//0x448是cell0的压缩因子的长度
+			}
+			else //if((4 == i)||(5 == i))
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
+				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR +  0x448+(i-4)*((SHORTCP_BF_CNT*4)<<bitOffset);
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (8 == slotId)		// current slot is even slot, compare even slot, slot8
+		{
+			slotVal = 0;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR + 0xF00 +((i-2)*(slotBfCnt<<bitOffset));
+			}
+			else// if((4 == i)||(5 == i))
+			{
+			    bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR + 0xF00 + ((i-4)*(slotBfCnt<<bitOffset));
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (9 == slotId)	// compare odd slot, slot9
+		{
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_ODD_COMPRESS_ADDR;
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR +  0xF00 +((i-2)*(slotBfCnt<<bitOffset));
+			}
+			else //if((4 == i)||(5 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR +  0xF00+ ((i-4)*(slotBfCnt<<bitOffset));
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+
+		if (2 > i)	// NR cell compress factor
+		{
+			for (int32_t idBf = 0; idBf <  (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (idVal<<24) | ((idBf<<1)<<8) | (i);
+					
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+								
+						if ((7 == slotId) && (686 <= idBf))
+						{
+							recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+							if (0 > (idBf-(bfStart>>1)))
+							{
+								gBfStartErr++;
+								debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+							}
+							realSrcAddr = srcAddr1;
+						}
+						else 
+						{
+							recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+							realSrcAddr = srcAddr;
+						}
+					
+						recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+						__ucps2_synch(0);
+						if (recvVal != compVal)
+						{
+							if (gErrSlotIdCnt < 0x100)
+							{
+								debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+								debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+								debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+								debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+								debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+								debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+								debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+							}
+							gErrSlotIdCnt++;
+						}				
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else //if((1 < i)	&& (6 > i))// NR CELL0
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					
+//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					
+					if ((7 == slotId) && (1372 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
+						realSrcAddr = srcAddr1;
+						if (0 > (idBf-bfStart))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+					}
+					else 
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					
+//					__ucps2_synch(0);
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+					}
+				}
+			}
+		}
+		
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}
+