From 9cc9b0b094687a2732b71f5e7034df9d9dc2afa0 Mon Sep 17 00:00:00 2001 From: "xinxin.li" Date: Sat, 20 Apr 2024 17:09:54 +0800 Subject: [PATCH] 1. fix UCP4008-SL feature enhancement #1854; 2. delete tx/rx slot int on ecs_rfm1 for jesd version; 3. modify sfn updating algorithm for jesd version; 4. optimize jesd gpio on/off code; 5. test case: case24/34/44/45/41/42. --- public/common/ecs_dm/inc/gpio_drv.h | 12 +++ public/ecs_rfm_spu1/driver/src/cpri_timer.s.c | 15 ++-- .../ecs_rfm_spu1/driver/src/ecpri_timer.s.c | 23 +++--- public/ecs_rfm_spu1/driver/src/gpio_drv.s.c | 55 +++++++++++++ .../driver/src/jesd_orx_timer.s.c | 2 +- public/ecs_rfm_spu1/driver/src/jesd_timer.s.c | 81 ++++++++++++------- 6 files changed, 138 insertions(+), 50 deletions(-) diff --git a/public/common/ecs_dm/inc/gpio_drv.h b/public/common/ecs_dm/inc/gpio_drv.h index ddef74d..4acbbf3 100644 --- a/public/common/ecs_dm/inc/gpio_drv.h +++ b/public/common/ecs_dm/inc/gpio_drv.h @@ -40,8 +40,18 @@ typedef struct _tagGpioInfo uint8_t vaFlag; // 0: low as valid; 1: high as valid }stGpioInfo; +typedef struct _tagRfGpioInfo +{ + uint32_t pinInfo; // 1 bit 1 pin + uint32_t validInfo; // 0: low as valid; 1: high as valid +}stRfGpioInfo; + typedef struct _tagGpioJesd { + stRfGpioInfo txRfGpioInfo[JESD_RF_CH_NUM]; + stRfGpioInfo rxRfGpioInfo[JESD_RF_CH_NUM]; + stRfGpioInfo orxRfGpioInfo[JESD_RF_CH_NUM]; + stGpioInfo txTransGpioInfo[JESD_RF_CH_NUM]; stGpioInfo txGpioInfo[JESD_RF_CH_NUM]; stGpioInfo txAntGpioInfo[JESD_RF_CH_NUM]; @@ -63,6 +73,8 @@ int32_t hw_gpio_init(); int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState); +int32_t set_jesd_all_rf_state(uint8_t nTRCh, uint8_t nState); // tx, rx, orx + int32_t set_trigger_state(uint8_t nState); #if 0 diff --git a/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c b/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c index 6cc9941..b40fee2 100644 --- a/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/cpri_timer.s.c @@ -144,9 +144,9 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr) pCpriDelay->cpriTddOffset = pCpriDelay->cpri10msOffset + EDMA_OFFSET; + do_write(CPRI_DELAY_ADDR, pCpriDelay->cpri10msRxOffset); do_write(CPRI_ADVANCE_ADDR, pCpriDelay->cpri10msOffset); do_write(CPRI_TDD_ADVANCE_ADDR, pCpriDelay->cpriTddOffset); - do_write(CPRI_DELAY_ADDR, pCpriDelay->cpri10msRxOffset); uint32_t addr = (uint32_t)&(phyPara[my_cpritmr->scsId].gpsOffset); uint16_t gpsOffset = do_read_volatile_short(addr); @@ -178,7 +178,7 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr) do_write(CPRI_RX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sRxOffset); do_write(CPRI_TDD_ADVANCE_PP1S_ADDR, pCpriDelay->cpriTdd2PP1sOffset); - enable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int + //enable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int #ifdef PALLADIUM_TEST flag++; debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); @@ -339,6 +339,7 @@ void cpri_timer_rcfg_act() } reCfgFlag = 5; + disable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // disable 10ms int debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum); // 0xE50 debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT()); // 0xE54 } @@ -551,15 +552,15 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId) volatile uint32_t h1Pos = 0; uint8_t apeId = 0; int32_t tmrId = 0; -//#ifdef INTEGRATED_BS -//#else + EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt(); stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID]; stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID]; pMtimerPara->runCoreId = apeCoreId; txOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset; rxOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset; -//#endif + + enable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int uint32_t tmr3Point = SFN_PERIOD*1000 - txOffset; // us uint32_t tmr4Point = 0; // offset; // us @@ -574,7 +575,6 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId) // ape tmrpoints h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数 - __ucps2_synch(0); while (32 > h1Pos) { apeId = 31 - h1Pos; @@ -593,7 +593,6 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId) runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); - __ucps2_synch(0); } reCfgFlag = 4; @@ -612,7 +611,6 @@ int32_t clear_cpri_ape_slot_offset(uint32_t apeCoreId) // ape tmrpoints h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数 - __ucps2_synch(0); while (32 > h1Pos) { apeId = 31 - h1Pos; @@ -629,7 +627,6 @@ int32_t clear_cpri_ape_slot_offset(uint32_t apeCoreId) runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); - __ucps2_synch(0); } return 0; diff --git a/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c b/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c index 6e0024b..397fa2d 100644 --- a/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c @@ -91,7 +91,7 @@ void ecpri_timer_reconfig(phy_timer_config_ind_t *my_ecpritmr) //set_ecpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status //set_ecpri_tdd_offset(); // 5ms int, tevent2 for all ape cores, dma - enable_mtimer_cevent_int(MTIMER_ECPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int + //enable_mtimer_cevent_int(MTIMER_ECPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int set_ecpri_tx_slot_offset(); set_ecpri_rx_slot_offset(); @@ -140,8 +140,9 @@ void ecpri_timer_rcfg_act() if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell { + pMtimerSfn->txSfnNum++; + pMtimerSfn->txSfnNum &= 0x3FF; pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum; - //pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1; } addr = (uint32_t)&(phyPara[nScsId].txSfnNum); do_write(addr, pMtimerSfn->txSfnNum); @@ -180,6 +181,7 @@ void ecpri_timer_rcfg_act() } reCfgFlag = 5; + disable_mtimer_cevent_int(MTIMER_ECPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // disable 10ms int } void ecpri_1pps_src_init(uint8_t srcId) @@ -305,9 +307,10 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId) EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt(); txOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset; rxOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset; + enable_mtimer_cevent_int(MTIMER_ECPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int } - uint32_t tmr3Point = SFN_PERIOD - txOffset; // us + uint32_t tmr3Point = SFN_PERIOD*1000 - txOffset; // us uint32_t tmr4Point = 0; // offset; // us if (rxOffset < 0) { @@ -315,12 +318,11 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId) } else { - tmr4Point = SFN_PERIOD - rxOffset; // us + tmr4Point = SFN_PERIOD*1000 - rxOffset; // us } // ape tmrpoints h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数 - __ucps2_synch(0); while (32 > h1Pos) { apeId = 31 - h1Pos; @@ -330,16 +332,15 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId) } // tx slot int tmrId = MTMR_APE0_TXSLOT + (apeId<<1); - set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT); + set_mtimer_tmrpoint_ns(MTIMER_ECPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT); enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); // rx slot int tmrId = MTMR_APE0_RXSLOT + (apeId<<1); - set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT); + set_mtimer_tmrpoint_ns(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT); enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_APE0_SLOT+apeId)); runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); - __ucps2_synch(0); } reCfgFlag = 4; @@ -356,7 +357,6 @@ int32_t clear_ecpri_ape_slot_offset(uint32_t apeCoreId) // ape tmrpoints h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数 - __ucps2_synch(0); while (32 > h1Pos) { apeId = 31 - h1Pos; @@ -373,7 +373,6 @@ int32_t clear_ecpri_ape_slot_offset(uint32_t apeCoreId) runCore &= (~(1 << apeId)); h1Pos = __builtin_clz(runCore); - __ucps2_synch(0); } return 0; @@ -386,8 +385,8 @@ int32_t set_ecpri_tx_symbol_offset(uint8_t symbolId) return -1; } - uint32_t longCp = (uint32_t)4448*500000/(4448+4384); // ns - uint32_t shortCp = (uint32_t)4384*500000/(4448+4384); // ns + uint32_t longCp = (uint32_t)4448*500000/(4448+13*4384); // ns + uint32_t shortCp = (uint32_t)4384*500000/(4448+13*4384); // ns uint32_t tmrPoint = SFN_PERIOD*1000 - CPRI_INT_DELAY; if (1 >= symbolId) diff --git a/public/ecs_rfm_spu1/driver/src/gpio_drv.s.c b/public/ecs_rfm_spu1/driver/src/gpio_drv.s.c index 3c09f81..0b0e68b 100644 --- a/public/ecs_rfm_spu1/driver/src/gpio_drv.s.c +++ b/public/ecs_rfm_spu1/driver/src/gpio_drv.s.c @@ -52,6 +52,26 @@ int32_t hw_gpio_init() } } + stRfGpioInfo* pRfGpio = NULL; + uint32_t pinNum = 0; + uint32_t pinValid = 0; + for (i = 0; i < JESD_GPIOGROUP_NUM; i++) // tx, rx, orx, trans_tx, trans_rx, trans_orx + { + for (j = 0; j < JESD_RF_CH_NUM; j++) + { + pRfGpio = pGpioInfo->jesdGpioInfo.txRfGpioInfo + ((i/3)*JESD_RF_CH_NUM+j); //*sizeof(stRfGpioInfo); + pinNum = do_read_volatile(GPIO_JESD_RF_BIT + (i<<5) + (j<<2)); + pRfGpio->pinInfo |= pinNum; + pinValid = do_read_volatile(GPIO_JESD_RF_VALID + (i<<5) + (j<<2)); + pRfGpio->validInfo |= pinValid; + __ucps2_synch(0); + do_write((0x0A4F4000+((i*4+j)<<2)), (uint32_t)(&(pRfGpio->pinInfo))); + do_write((0x0A4F4100+((i*4+j)<<2)), (pRfGpio->pinInfo)); + do_write((0x0A4F4200+((i*4+j)<<2)), (GPIO_JESD_RF_BIT + (i<<5) + (j<<2))); + do_write((0x0A4F4300+((i*4+j)<<2)), (pinNum)); + } + } + k = 0; for (j = 0; j < 4; j++) { @@ -136,6 +156,41 @@ int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState) return 0; } +int32_t set_jesd_all_rf_state(uint8_t nTRCh, uint8_t nState) // tx, rx, orx +{ + EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt(); + stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo; + uint32_t regData = 0; + uint32_t tempData = 0; + uint32_t gpioVal = 0; + + stRfGpioInfo* pRfGpio = pGpioInfo->jesdGpioInfo.txRfGpioInfo + nTRCh*JESD_RF_CH_NUM; //*sizeof(stRfGpioInfo); + + for (uint8_t i = 0; i < JESD_RF_CH_NUM; i++) // 128pin, 4 group + { + regData = do_read_volatile(gGpioDataAddr[i]); + tempData = regData & (~pRfGpio[i].pinInfo); + + if (GPIO_ON == nState) + { + gpioVal = pRfGpio[i].pinInfo & pRfGpio[i].validInfo; + } + else if (GPIO_OFF == nState) + { + gpioVal = pRfGpio[i].pinInfo ^ pRfGpio[i].validInfo; + } + else + { + return -1; + } + + regData = tempData | gpioVal; + do_write(gGpioDataAddr[i], regData); + } + + return 0; +} + int32_t set_trigger_state(uint8_t nState) { if ((GPIO_ON != nState) && (GPIO_OFF != nState)) diff --git a/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c b/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c index 134e8bd..4c941d0 100644 --- a/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c @@ -42,7 +42,7 @@ int32_t jesd_orx_timer_init(void) jesd_orx_1pps_src_init(MTIMER_PP1S_SRC_TOD); //mtimer_clear_all_event(MTIMER_JESD_RX1_ID); set_jesd_orx_tmr_period(); - set_jesd_orx_1pps_scratch(); + //set_jesd_orx_1pps_scratch(); //set_jesd_orx_tmr_point(25000); // 25ms jesd_orx_pin_ctrl(); diff --git a/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c b/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c index e292f98..f4e7958 100644 --- a/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c +++ b/public/ecs_rfm_spu1/driver/src/jesd_timer.s.c @@ -27,7 +27,7 @@ #endif extern stPhyScsPara* phyPara; -extern stSfnPara gCellSfnPara[2]; +//extern stSfnPara gCellSfnPara[2]; extern uint32_t gScsId; uint32_t gJesdTestMode = 0; @@ -401,8 +401,9 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr) uint16_t gpsOffset = do_read_volatile_short(addr); pJesdDelay->gps_offset = gpsOffset; - pJesdDelay->tx_offset = pMtimerInt->tmrPP1sCost * 2; - pJesdDelay->rx_offset = pMtimerInt->tmrPP1sCost * 2; + pJesdDelay->tx_offset = pMtimerInt->tmrPP1sCost * 5; + pJesdDelay->rx_offset = pMtimerInt->tmrPP1sCost * 5; + pJesdDelay->tdd_offset = pMtimerInt->tmrPP1sCost * 5 + EDMA_OFFSET; do_write(CPRI_ADVANCE_ADDR, pJesdDelay->tx_offset); do_write(CPRI_DELAY_ADDR, pJesdDelay->rx_offset); @@ -469,7 +470,7 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr) pMtimerTxPara->tempM_max = pMtimerPara->tddSlotNum-1; pMtimerTxPara->tempH_max = SFN_PERIOD / pMtimerPara->slotPeriod / pMtimerPara->tddSlotNum - 1; - enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int + //enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int #ifdef PALLADIUM_TEST flag++; debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC @@ -481,8 +482,8 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr) debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC #endif - set_jesd_tx_slot_offset(nTmrId); - set_jesd_rx_slot_offset(nTmrId); + //set_jesd_tx_slot_offset(nTmrId); + //set_jesd_rx_slot_offset(nTmrId); #ifdef PALLADIUM_TEST flag++; debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC @@ -584,10 +585,11 @@ void jesd_timer_rcfg_act(int32_t nTmrId) //pMtimerSfn->rxSfnNum = 0; // 1023; pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1; - if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell + //if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell + if (0 == pMtimerSfn->slotNumPP1s) // no frame header offset, and the first cell { - pMtimerSfn->txSfnNum++; - pMtimerSfn->txSfnNum &= 0x3FF; + //pMtimerSfn->txSfnNum++; + //pMtimerSfn->txSfnNum &= 0x3FF; pMtimerSfn->rxSfnNum = pMtimerSfn->txSfnNum; //pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1; } @@ -625,7 +627,8 @@ void jesd_timer_rcfg_act(int32_t nTmrId) __ucps2_synch(0); } - reCfgFlag = 5; + reCfgFlag = 0; // 5; + disable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // disable 10ms int debug_write((DBG_DDR_IDX_DRV_BASE+916), pMtimerSfn->txSfnNum); // 0xE50 debug_write((DBG_DDR_IDX_DRV_BASE+917), GET_STC_CNT()); // 0xE54 } @@ -799,6 +802,8 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId) txOffset = pJesdDelay->jesd_10ms2pp1s_txoffset; rxOffset = pJesdDelay->jesd_10ms2pp1s_txoffset; + enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int + uint32_t tmr3Point = SFN_PERIOD*1000 - txOffset; // ns uint32_t tmr4Point = SFN_PERIOD*1000 - txOffset; // ns if (rxOffset < 0) @@ -1220,7 +1225,7 @@ uint32_t gRxCsuOnCnt = 0; uint32_t gRxCsuOffCnt = 0; uint32_t gTxCsuOnCnt = 0; uint32_t gTxCsuOffCnt = 0; -//extern int32_t gPP1sLockCnt; +uint32_t gPP1sFlag = 0; void jesd_10ms_callback(uint8_t nTmrId) { uint32_t tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId*0x1000; @@ -1257,12 +1262,13 @@ void jesd_10ms_callback(uint8_t nTmrId) if (MTIMER_JESD_RX0_ID == nTmrId) { start_jesd_timer(MTIMER_JESD_TX0_ID); - debug_write((DBG_DDR_IDX_DRV_BASE+57), GET_STC_CNT()); + //debug_write((DBG_DDR_IDX_DRV_BASE+57), GET_STC_CNT()); } pMtimerSfn->txSfnNum = 0; - pMtimerInt->tmrPP1sCost = GET_STC_CNT(); + pMtimerInt->tmrPP1sCost = JESD_INT_DELAY; // GET_STC_CNT(); } - + gPP1sFlag = 1; + debug_write((DBG_DDR_IDX_DRV_BASE+70), GET_STC_CNT()); // 0x118 //if (MTIMER_JESD_RX1_ID == nTmrId) if (MTIMER_JESD_RX0_ID == nTmrId) { @@ -1280,7 +1286,7 @@ void jesd_10ms_callback(uint8_t nTmrId) debug_write((DBG_DDR_IDX_DRV_BASE+64+1+(nTmrId<<2)), pMtimerInt->pp1sIntCnt); // 0x104, 0x114 -#if 0 //def PALLADIUM_TEST +#ifdef PALLADIUM_TEST uint32_t val = 0; for (int32_t core = 0; core < 12; core++) { @@ -1313,6 +1319,11 @@ void jesd_10ms_callback(uint8_t nTmrId) } #ifdef PALLADIUM_TEST debug_write((DBG_DDR_IDX_DRV_BASE+64+3+(nTmrId<<2)), pMtimerInt->sfnOffsetIntCnt); // 0x10C + if (6 > gPP1sFlag) + { + debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (1<<30))); // 0xD0 + gPP1sFlag++; + } #endif if ((MTIMER_JESD_RX0_ID == nTmrId) && (0 == (pMtimerInt->sfnOffsetIntCnt&0x3))) { @@ -1446,9 +1457,10 @@ void jesd_tdd_callback(uint8_t nTmrId) gRxOnCnt++; debug_write((DBG_DDR_IDX_DRV_BASE+78), gRxOnCnt); // 0x138 - set_jesd_rf_state(JESD_ANT_RX, GPIO_ON); - set_jesd_rf_state(JESD_RF_RX, GPIO_ON); - set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); + set_jesd_all_rf_state(1, GPIO_ON); + //set_jesd_rf_state(JESD_ANT_RX, GPIO_ON); + //set_jesd_rf_state(JESD_RF_RX, GPIO_ON); + //set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); uint8_t nListId = 0; if ((TDD_2500US_DOUBLE == pMtimerPara->frameType) && (pMtimerInt->tddOffsetIntCnt&0x1)) @@ -1463,10 +1475,16 @@ void jesd_tdd_callback(uint8_t nTmrId) do_write(tFlagAddr, (1< gPP1sFlag) + { + debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (2<<30))); // 0xD0 + gPP1sFlag++; + } - set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF); - set_jesd_rf_state(JESD_RF_RX, GPIO_OFF); - set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF); + set_jesd_all_rf_state(1, GPIO_OFF); + //set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF); + //set_jesd_rf_state(JESD_RF_RX, GPIO_OFF); + //set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF); } if (tEventFlag & (1< gPP1sFlag) + { + debug_write((DBG_DDR_IDX_DRV_BASE+51+gPP1sFlag), (GET_STC_CNT() | (3<<30))); // 0xD0 + gPP1sFlag++; + } uint32_t startTick = 0; uint32_t cost = 0; startTick = GET_STC_CNT(); - set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); - set_jesd_rf_state(JESD_RF_TX, GPIO_ON); - set_jesd_rf_state(JESD_ANT_TX, GPIO_ON); + set_jesd_all_rf_state(0, GPIO_ON); + //set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); + //set_jesd_rf_state(JESD_RF_TX, GPIO_ON); + //set_jesd_rf_state(JESD_ANT_TX, GPIO_ON); cost = GET_STC_CNT() - startTick; debug_write((DBG_DDR_IDX_DRV_BASE+120), cost); // 0x1e0 //jesd_csu_start(); @@ -1530,9 +1554,10 @@ void jesd_tdd_callback(uint8_t nTmrId) do_write(tFlagAddr, (1<txSlotTiming = GET_STC_CNT(); pMtimerSfn->txSlotNum++;