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1. fix UCP4008_SL feature enhancement #1296;

Browse Source 
2. add jesd gpio pins;
3. add jesd orx test case(45);
4. add jesd 200M test case(48);
This commit is contained in:
xinxin.li 2023-11-16 14:23:38 +08:00
parent 7dafcd3d11
commit a02bf422ff
38 changed files with 2703926 additions and 491607 deletions
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40
public/common/driver/inc/phy_para.h
View File

@ -8,6 +8,7 @@
#define SLOT_SYMBOL_NUM 14
#define SPU_DRV_SM_ADDR (0x0A4F2000) // (0x0A4D7000) //
#define SPU_DRV_SM_LEN (56*1024) // 56KB
#define PROTO_SEL_ADDR (SPU_DRV_SM_ADDR+0x0)
#define PROTO_OPT_ADDR (SPU_DRV_SM_ADDR+0x4)
@ -43,15 +44,6 @@
#define SERDES_INIT_FLAG_ADDR (SPU_DRV_SM_ADDR+0x240) // cpri or jesd clk init finished
#define STC_ONEPPS_OUT_ADDR (SPU_DRV_SM_ADDR+0x244)
#define JESD_RX_CH_PARA (SPU_DRV_SM_ADDR+0x248)
#define JESD_RX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x24C)
#define JESD_ORX_CH_PARA (SPU_DRV_SM_ADDR+0x250)
#define JESD_ORX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x254)
#define JESD_TX_CH_PARA (SPU_DRV_SM_ADDR+0x258)
#define JESD_TX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x25C)
#define CPRI_TX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x260)
#define CPRI_RX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x264)
#define CPRI_TDD_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x268)
@ -62,15 +54,29 @@
#define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // us as unit
#define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C)
// GPIO JESD TX/RX/ORX bit
#define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280)
#define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0)
#define GPIO_JESD_RF_VALID (GPIO_FROM_CFG_FILE+0x10)
#define GPIO_JESD_TRIGGER_BIT (GPIO_FROM_CFG_FILE+0x60)
#define GPIO_JESD_TRIGGER_VALID (GPIO_FROM_CFG_FILE+0x70)
#define SLOT_NUM_DEBUG_ADDR (SPU_DRV_SM_ADDR+0x300)
#define APE_INT_INFO_ADDR (SPU_DRV_SM_ADDR+0x400)
#define SLOT_NUM_DEBUG_ADDR (0x0A4D7300)
#define APE_INT_INFO_ADDR (0x0A4D7400)
// GPIO JESD TX/RX/ORX bit
#define JESD_CFG_ADDR (SPU_DRV_SM_ADDR+0x1000) // 4KB
#define JESD_RX_CH_PARA (JESD_CFG_ADDR+0x10)
#define JESD_RX_SAMPLE_RATE (JESD_CFG_ADDR+0x20)
#define JESD_ORX_CH_PARA (JESD_CFG_ADDR+0x30)
#define JESD_ORX_SAMPLE_RATE (JESD_CFG_ADDR+0x40)
#define JESD_TX_CH_PARA (JESD_CFG_ADDR+0x50)
#define JESD_TX_SAMPLE_RATE (JESD_CFG_ADDR+0x60)
#define JESD_TX1_CH_PARA (JESD_CFG_ADDR+0x70)
#define JESD_TX1_SAMPLE_RATE (JESD_CFG_ADDR+0x80)
#define GPIO_JESD_TRIGGER_BIT (JESD_CFG_ADDR+0x100)
#define GPIO_JESD_TRIGGER_VALID (JESD_CFG_ADDR+0x110)
#define GPIO_JESD_RF_BIT (JESD_CFG_ADDR+0x120)
#define GPIO_JESD_RF_VALID (JESD_CFG_ADDR+0x130)
#define PHY_CELL_FLAG 0xAFAFAFAF
#define ARM_SFN_UPDATE_FLAG 0xA5A5A5A5

2
public/common/driver/src/phy_para.s.c
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@ -25,7 +25,7 @@ void phy_para_init(int32_t protocol, int32_t option)
{
int32_t i = 0;
memset_ext((void*)PROTO_SEL_ADDR, 0, 0x1000); // init sm for drv, 0x0a4d7000~0x0a4d7FFF
memset_ext((void*)SPU_DRV_SM_ADDR, 0, SPU_DRV_SM_LEN); // init sm for drv, 0x0a4d7000~0x0a4d7FFF
__ucps2_synch(0);
do_write(PROTO_SEL_ADDR, protocol);

22
public/common/ecs_dm/inc/gpio_drv.h
View File

@ -6,6 +6,8 @@
#define JESD_RF_CH_NUM 4
#define JESD_GPIOGROUP_NUM 9
typedef enum _tagGpioLValid
{
LOW_AS_VALID = 0,
@ -14,10 +16,16 @@ typedef enum _tagGpioLValid
typedef enum _tagJesdGpioTRCH
{
JESD_RF_TX = 0,
JESD_RF_RX = 1,
JESD_RF_ORX = 2,
JESD_TRCH_MAXNUM = 3
JESD_TRANS_TX = 0,
JESD_RF_TX = 1,
JESD_ANT_TX = 2,
JESD_TRANS_RX = 3,
JESD_RF_RX = 4,
JESD_ANT_RX = 5,
JESD_TRANS_ORX = 6,
JESD_RF_ORX = 7,
JESD_ANT_ORX = 8,
JESD_TRCH_MAXNUM = 9
}jesdGpioTRch;
typedef enum _tagGpioState
@ -34,9 +42,15 @@ typedef struct _tagGpioInfo
typedef struct _tagGpioJesd
{
stGpioInfo txTransGpioInfo[JESD_RF_CH_NUM];
stGpioInfo txGpioInfo[JESD_RF_CH_NUM];
stGpioInfo txAntGpioInfo[JESD_RF_CH_NUM];
stGpioInfo rxTransGpioInfo[JESD_RF_CH_NUM];
stGpioInfo rxGpioInfo[JESD_RF_CH_NUM];
stGpioInfo rxAntGpioInfo[JESD_RF_CH_NUM];
stGpioInfo orxTransGpioInfo[JESD_RF_CH_NUM];
stGpioInfo orxGpioInfo[JESD_RF_CH_NUM];
stGpioInfo orxAntGpioInfo[JESD_RF_CH_NUM];
}stGpioJesd;
typedef struct _tagGpioOnBoard

2
public/common/ecs_dm/src/ecs_rfm_dm_mgt.s.c
View File

@ -47,7 +47,7 @@ int32_t ecs_rfm_dm_alloc(void)
return -1;
}
//stGpioOnBoard* pGpioInfo = (stGpioOnBoard*)0x0A4D7400;
//pEcsDmLocalMgt->pGpioInfo = (stGpioOnBoard*)0x0A4F4000;
pEcsDmLocalMgt->pGpioInfo = (stGpioOnBoard*)memSectionAlloc(pMemSection, sizeof(stGpioOnBoard), MEM_ALIGNED_4BYTES, "pGpioInfo"); // (stGpioOnBoard*)0x0A4D7400;
if (NULL == pEcsDmLocalMgt->pGpioInfo)
{

13
public/ecs_rfm_spu1/driver/inc/jesd_csu_nr_7ds2u.h
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@ -12,7 +12,7 @@
#define JESD_NR7DS2U_RX_NODENUM 3
#define JESD_2500US_DOUBLE_TX_NODENUM1 7
#define JESD_2500US_DOUBLE_TX_NODENUM2 3
#define JESD_2500US_DOUBLE_TX_NODENUM2 5
#define JESD_2500US_DOUBLE_RX_NODENUM1 2
#define JESD_2500US_DOUBLE_RX_NODENUM2 3
@ -54,14 +54,16 @@
#define JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
#define JESD_98_NR7DS2U_MARGIN 3
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x60F00000 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x60FF0400 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0x61380000 // SM5
#define JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0x61290400 // SM4
#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR 0x6BC00000 // 0x89000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC89000 // 0x1E0000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BE69000 // 0x1E0000 // 0x6c049000
#define JESD_ORX_DATA_ADDR 0x60000000
#define JESD_ORX_DATA_LEN 12288000
@ -71,7 +73,10 @@ int32_t jesd_csu_init_nr_7d2u_slot0();
int32_t jesd_csu_init_nr_7ds2u_iomode();
int32_t jesd_csu_init_nr_7ds2u_8t8r();
int32_t jesd_csu_init_nr_7ds2u_4t4r_98();
// 4t4r, 245.76M
int32_t jesd_csu_init_nr_2500us_double();
// 4t4r, 245.76M, slot0
int32_t jesd_csu_init_nr_2500us_double_slot0();
int32_t jesd_sniffer_orx_csu_init();
int32_t jesd_csu_start_nr_7ds2u();

8
public/ecs_rfm_spu1/driver/src/gpio_drv.s.c
View File

@ -26,7 +26,7 @@ int32_t hw_gpio_init()
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
for (i = 0; i < 3; i++) // tx, rx, orx
for (i = 0; i < JESD_GPIOGROUP_NUM; i++) // tx, rx, orx, trans_tx, trans_rx, trans_orx
{
k = 0;
for (j = 0; j < 4; j++)
@ -36,7 +36,7 @@ int32_t hw_gpio_init()
while (32 > h1Pos)
{
pinId = 31 - h1Pos;
pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[k].pinId) + sizeof(stGpioInfo) * JESD_RF_CH_NUM * i;
pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txTransGpioInfo[k].pinId) + sizeof(stGpioInfo) * JESD_RF_CH_NUM * i;
do_write_byte(pinAddr, (pinId + (j<<5)));
do_write_byte((pinAddr+1), ((do_read_volatile(GPIO_JESD_RF_VALID + (i<<5) + (j<<2)) >> pinId) & 0x1));
do_write(gGpioDirAddr[j], (do_read_volatile(gGpioDirAddr[j])|(1<<pinId)));
@ -105,8 +105,8 @@ int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState)
for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
{
pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[i].pinId) + sizeof(stGpioInfo)*JESD_RF_CH_NUM*nTRCh;
validAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[i].vaFlag) + sizeof(stGpioInfo)*JESD_RF_CH_NUM*nTRCh;
pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txTransGpioInfo[i].pinId) + sizeof(stGpioInfo)*JESD_RF_CH_NUM*nTRCh;
validAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txTransGpioInfo[i].vaFlag) + sizeof(stGpioInfo)*JESD_RF_CH_NUM*nTRCh;
pinId = do_read_volatile_byte(pinAddr);
valid = do_read_volatile_byte(validAddr);
pinGroup = pinId >> 5;

119
public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c
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@ -351,7 +351,7 @@ int32_t jesd_csu_init_nr_7ds2u_8t8r()
int32_t jesd_csu_init_nr_7ds2u_4t4r_98()
{
jesd_csu_init(4, 4);
jesd_csu_init(4, JESD_98_NR7DS2U_MARGIN);
stJesdCsuNodePara txCsuNode[JESD_NR7DS2U_TX_NODENUM];
stJesdCsuNodePara rxCsuNode[JESD_NR7DS2U_RX_NODENUM];
//tx的链表地址
@ -423,7 +423,7 @@ int32_t jesd_csu_init_nr_7ds2u_4t4r_98()
// 4t4r, 245.76M
int32_t jesd_csu_init_nr_2500us_double()
{
jesd_csu_init(4, 4);
jesd_csu_init(4, JESD_98_NR7DS2U_MARGIN);
stJesdCsuNodePara txCsuNode1[JESD_2500US_DOUBLE_TX_NODENUM1];
stJesdCsuNodePara rxCsuNode1[JESD_2500US_DOUBLE_RX_NODENUM1];
stJesdCsuNodePara txCsuNode2[JESD_2500US_DOUBLE_TX_NODENUM2];
@ -535,6 +535,121 @@ int32_t jesd_csu_init_nr_2500us_double()
return 0;
}
// 4t4r, 245.76M, slot0
int32_t jesd_csu_init_nr_2500us_double_slot0()
{
jesd_csu_init(4, JESD_98_NR7DS2U_MARGIN);
stJesdCsuNodePara txCsuNode1[JESD_2500US_DOUBLE_TX_NODENUM1];
stJesdCsuNodePara rxCsuNode1[JESD_2500US_DOUBLE_RX_NODENUM1];
stJesdCsuNodePara txCsuNode2[JESD_2500US_DOUBLE_TX_NODENUM2];
stJesdCsuNodePara rxCsuNode2[JESD_2500US_DOUBLE_RX_NODENUM2];
//tx的链表地址
uint32_t tx1ListAddr = JESD_TX_LIST_ADDR;
uint32_t tx2ListAddr = JESD_TX_LIST2_ADDR;
//rx的链表地址
uint32_t rx1ListAddr = JESD_RX_LIST_ADDR;
uint32_t rx2ListAddr = JESD_RX_LIST2_ADDR;
int32_t i = 0;
// tx, slot0~2
for (i = 0; i < (JESD_2500US_DOUBLE_TX_NODENUM1-1); i++)
{
if (0 == (i&0x3))
{
txCsuNode1[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR; // JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR;
txCsuNode1[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode1[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4)*2;
}
else if (1 == (i&0x3))
{
txCsuNode1[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR;
txCsuNode1[i].yStep = ((7*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode1[i].allNum = ((7*SHORTCP_SAM_CNT)<<4)*2;
}
else if (2 == (i&0x3))
{
txCsuNode1[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode1[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode1[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4)*2;
}
else if (3 == (i&0x3))
{
txCsuNode1[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR;
txCsuNode1[i].yStep = ((7*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode1[i].allNum = ((7*SHORTCP_SAM_CNT)<<4)*2;
}
}
// slot3, slots
txCsuNode1[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode1[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode1[i].allNum = ((LONGCP_SAM_CNT+5*SHORTCP_SAM_CNT)<<4)*2;
// rx list nodes
// slot3, slots
rxCsuNode1[0].dataAddr = JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR;
rxCsuNode1[0].yStep = ((SHORTCP_SAM_CNT*4)<<2)*2;
rxCsuNode1[0].allNum = ((SHORTCP_SAM_CNT*4)<<4)*2;
// slot4
rxCsuNode1[1].dataAddr = JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode1[1].yStep = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<2)*2;
rxCsuNode1[1].allNum = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4)*2;
jesd_csu_tx_cfg(tx1ListAddr, 2, txCsuNode1, JESD_CSU_CH0, 0);
jesd_csu_rx_cfg(rx1ListAddr, JESD_2500US_DOUBLE_RX_NODENUM1, rxCsuNode1, JESD_CSU_CH0, 0);
// tx, slot5~6
for (i = 0; i < (JESD_2500US_DOUBLE_TX_NODENUM2-1); i++)
{
if (0 == (i&0x3))
{
txCsuNode2[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR; // JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR;
txCsuNode2[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode2[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4)*2;
}
else if (1 == (i&0x3))
{
txCsuNode2[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR;
txCsuNode2[i].yStep = ((7*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode2[i].allNum = ((7*SHORTCP_SAM_CNT)<<4)*2;
}
else if (2 == (i&0x3))
{
txCsuNode2[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode2[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode2[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4)*2;
}
else if (3 == (i&0x3))
{
txCsuNode2[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR;
txCsuNode2[i].yStep = ((7*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode2[i].allNum = ((7*SHORTCP_SAM_CNT)<<4)*2;
}
}
// slot7, slots
txCsuNode2[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode2[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode2[i].allNum = ((LONGCP_SAM_CNT+5*SHORTCP_SAM_CNT)<<4)*2;
// rx list nodes
// slot7, slots
rxCsuNode2[0].dataAddr = JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR;
rxCsuNode2[0].yStep = ((SHORTCP_SAM_CNT*4)<<2)*2;
rxCsuNode2[0].allNum = ((SHORTCP_SAM_CNT*4)<<4)*2;
// slot8
rxCsuNode2[1].dataAddr = JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode2[1].yStep = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<2)*2;
rxCsuNode2[1].allNum = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4)*2;
// slot9
rxCsuNode2[2].dataAddr = JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode2[2].yStep = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<2)*2;
rxCsuNode2[2].allNum = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4)*2;
jesd_csu_tx_cfg(tx2ListAddr, 0, txCsuNode2, JESD_CSU_CH0, 1);
jesd_csu_rx_cfg(rx2ListAddr, JESD_2500US_DOUBLE_RX_NODENUM2, rxCsuNode2, JESD_CSU_CH0, 1);
return 0;
}
int32_t jesd_sniffer_orx_csu_init()
{
jesd_orx_csu_init();

2
public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c
View File

@ -153,7 +153,9 @@ int32_t jesd_orx_pin_ctrl(void)
do_write((tmrBaseAddr+MTMR_PIN_CTRL_REG), 0x1); //CTRL_SEL
do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), (1<<(4+(MTIMER_JESD_RX1_ID>>1)))); //IO ctrl
set_jesd_rf_state(JESD_ANT_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_RF_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_TRANS_ORX, GPIO_OFF);
return 0;
}

33
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -349,14 +349,23 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
pMtimerTxPara->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
pMtimerSfn->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
do_write_short((&(phyPara[scsId].slotNumOfTdd)), my_jesdtmr->num_tti);
do_write_short((&(phyPara[scsId].mtimerId)), nTmrId);
if (FDD_MODE == my_jesdtmr->frameType)
{
gJesdIOMode = JESD_IO_CTRL;
gJesdTFMode = FDD_MODE;
}
do_write_short((&(phyPara[scsId].slotNumOfTdd)), my_jesdtmr->num_tti);
do_write_short((&(phyPara[scsId].mtimerId)), nTmrId);
else if (TDD_2500US_DOUBLE == my_jesdtmr->frameType)
{
pMtimerPara->tddPeriod = my_jesdtmr->t_period >> 1; // us
pMtimerPara->tddSlotNum = my_jesdtmr->num_tti >> 1;
pMtimerTxPara->tddPeriod = my_jesdtmr->t_period >> 1; // us
pMtimerTxPara->tddSlotNum = my_jesdtmr->num_tti >> 1;
//do_write_short((&(phyPara[scsId].slotNumOfTdd)), (my_jesdtmr->num_tti>>1));
}
__ucps2_synch(0);
jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
@ -548,8 +557,12 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
{
#if 1
set_jesd_rf_state(JESD_RF_RX, GPIO_OFF); // RxOff();
set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF); // RxOff();
set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF); // RxOff();
ucp_nop(100000);
set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_ANT_TX, GPIO_ON); // TxOn();
#else
set_jesd_rf_state(JESD_RF_TX, GPIO_OFF);
ucp_nop(100000);
@ -558,8 +571,12 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
}
else if (FDD_MODE == gJesdTFMode)
{
set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_ANT_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_ANT_RX, GPIO_ON); // RxOn();
set_jesd_rf_state(JESD_RF_RX, GPIO_ON); // RxOn();
set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn();
}
else
{
@ -1189,7 +1206,9 @@ void jesd_10ms_callback(uint8_t nTmrId)
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), pMtimerInt->insOffsetIntCnt); // 0x118
#endif
set_jesd_rf_state(JESD_ANT_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_RF_ORX, GPIO_OFF);
set_jesd_rf_state(JESD_TRANS_ORX, GPIO_OFF);
stop_jesd_orx_timer();
// phy callback
phy_sniffer_data_proc();
@ -1270,7 +1289,9 @@ void jesd_tdd_callback(uint8_t nTmrId)
gRxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+78), gRxOnCnt); // 0x138
set_jesd_rf_state(JESD_ANT_RX, GPIO_ON);
set_jesd_rf_state(JESD_RF_RX, GPIO_ON);
set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON);
uint8_t nListId = 0;
if ((TDD_2500US_DOUBLE == pMtimerPara->frameType) && (pMtimerInt->tddOffsetIntCnt&0x1))
@ -1286,7 +1307,9 @@ void jesd_tdd_callback(uint8_t nTmrId)
gRxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+79), gRxOffCnt); // 0x13C
set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF);
set_jesd_rf_state(JESD_RF_RX, GPIO_OFF);
set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF);
}
if (tEventFlag & (1<<MTMR_JESD_TXON)) // tx on int
{
@ -1298,7 +1321,9 @@ void jesd_tdd_callback(uint8_t nTmrId)
uint32_t startTick = 0;
uint32_t cost = 0;
//startTick = GET_STC_CNT();
set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON);
set_jesd_rf_state(JESD_RF_TX, GPIO_ON);
set_jesd_rf_state(JESD_ANT_TX, GPIO_ON);
//cost = GET_STC_CNT() - startTick;
//debug_write((DBG_DDR_IDX_DRV_BASE+120), cost); // 0x1e0
//jesd_csu_start();
@ -1348,7 +1373,9 @@ void jesd_tdd_callback(uint8_t nTmrId)
do_write(tFlagAddr, (1<<MTMR_JESD_TXOFF)); // clear int flag
gTxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+77), gTxOffCnt); // 0x134
set_jesd_rf_state(JESD_TRANS_TX, GPIO_OFF);
set_jesd_rf_state(JESD_RF_TX, GPIO_OFF);
set_jesd_rf_state(JESD_ANT_TX, GPIO_OFF);
}
if (cEventFlag & (1<<MTMR_CEVENT_RXEN2CSU0))
{

2
public/ecs_rfm_spu1/driver/src/mtimer_cal.s.c
View File

@ -207,7 +207,9 @@ int32_t mtimer_orx_adjust(void)
if (1 == orx_para_ptr->orx_start_flag)
{
set_jesd_rf_state(JESD_ANT_ORX, GPIO_ON);
set_jesd_rf_state(JESD_RF_ORX, GPIO_ON);
set_jesd_rf_state(JESD_TRANS_ORX, GPIO_ON);
start_jesd_orx_timer();
jesd_csu_orx_start(0);
orx_para_ptr->orx_start_flag = 0;

2
public/ecs_rfm_spu1/driver/src/mtimer_drv.s.c
View File

@ -35,7 +35,7 @@ int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
}
else if (PROTOCOL_JESD == nBsType)
{
coreClk = do_read_volatile(JESD_RX_SAMPLE_RATE+(nTmrId<<3)); // 122880000;
coreClk = do_read_volatile(JESD_RX_SAMPLE_RATE+(nTmrId<<5)); // 122880000;
}
else if (PROTOCOL_ECPRI == nBsType)
{

16
public/ecs_rfm_spu1/top/src/main.s.c
View File

@ -90,12 +90,28 @@ int32_t main(int32_t argc, char* argv[])
#endif
ecs_rfm_spu1_msg_transfer_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
spu_shell_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
spu_shell_cpri_cmd();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
oam_msg_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
while (1)
{

49
public/ecs_rfm_spu1/top/src/phy_init.s.c
View File

@ -18,8 +18,10 @@
#include "app_interface.h"
#include "phy_para.h"
#include "rfm1_drv.h"
#include "jesd_orx_timer.h"
#define CELL_SETUP_TYPE_SIMULATION (0x5a6b7c8d)
#define ORX_MSG_TYPE_SIMULATION (0xaabb7788)
#define ECS_RFM1_TEST_MSG_SIZE (8)
#define ECS_RFM1_MSG_TYPE (0)
@ -116,7 +118,7 @@ void ecs_rfm1_send_del_task_info(uint8_t dst_core_id)
return ;
}
void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId, uint32_t frame_type)
{
phy_timer_config_ind_t my_cpritmr;
@ -130,26 +132,14 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
my_cpritmr.runCoreId = 0;
}
if (NR_SCS_30K == scsId)
if (TDD_2500US_DOUBLE == frame_type)
{
#if 1
my_cpritmr.frameType = TDD_MODE;
my_cpritmr.frameType = TDD_2500US_DOUBLE;
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 20;
my_cpritmr.num_t_dl[0] = 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 4; // ul symbol num
my_cpritmr.num_ants[0] = 4;
#else
my_cpritmr.frameType = TDD_2500US_DOUBLE;
my_cpritmr.t_period = 2500;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 5;
my_cpritmr.num_tti_per_sfn = 20;
my_cpritmr.num_t_dl[0] = 3; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 4; // ul symbol num
@ -159,7 +149,21 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
my_cpritmr.num_t_dl_symb[1] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[1] = 4; // ul symbol num
my_cpritmr.num_ants[1] = 4;
#endif
}
else
{
if (NR_SCS_30K == scsId)
{
my_cpritmr.frameType = TDD_MODE;
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 20;
my_cpritmr.num_t_dl[0] = 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 4; // ul symbol num
my_cpritmr.num_ants[0] = 4;
}
else if (LTE_SCS_ID == scsId)
{
@ -177,6 +181,7 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
{
return;
}
}
int32_t ret = mtimer_init4phy(&my_cpritmr);
if (0 != ret)
@ -266,15 +271,14 @@ void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
uint32_t msg_buf = do_read(u32msg_addr);
uint32_t msg_type = do_read(msg_buf);
//memcpy_ucp(0x60000000, msg_buf, 32); // temp code
if (CELL_SETUP_TYPE_SIMULATION == msg_type)
{
uint32_t msg_new_del = do_read(msg_buf+12); // 0; //
uint32_t scs_id = do_read(msg_buf+16); // 1; //
uint32_t cell_id = do_read(msg_buf+20); // 0; //
uint32_t run_core = do_read(msg_buf+24);
// memcpy_ucp(0x60000000, msg_buf, 32); // temp code
uint32_t frame_type = do_read(msg_buf+28);
if (1 < msg_new_del)
{
@ -287,7 +291,7 @@ void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
if (0 == msg_new_del)
{
ecs_rfm1_build_cell(scs_id, cell_id, run_core);
ecs_rfm1_build_cell(scs_id, cell_id, run_core, frame_type);
}
else
{
@ -295,6 +299,11 @@ void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
}
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),1), 0x12345678);
}
else if (ORX_MSG_TYPE_SIMULATION == msg_type)
{
phy_sniffer_start();
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),2), ORX_MSG_TYPE_SIMULATION);
}
return;
}

3
public/pet_rfm_spu1/top/src/phy_init.s.c
View File

@ -22,6 +22,7 @@
#define RFM_TEST_MSG_SIZE (8)
#define RFM_MSG_TYPE (0)
#define CELL_SETUP_TYPE_SIMULATION (0x5a6b7c8d)
#define ORX_MSG_TYPE_SIMULATION (0xaabb7788)
static uint32_t g_u32_rfm_alloc_err = 0; //(15) 0xB7E0143C
static uint32_t g_u32_rfm_send_err = 0; //(16) 0xB7E01440
@ -89,7 +90,7 @@ int32_t cell_setup_msg_forward(char* buf, uint32_t payloadSize)
uint32_t msg_type = do_read(buf);
if (CELL_SETUP_TYPE_SIMULATION != msg_type) {
if ((CELL_SETUP_TYPE_SIMULATION != msg_type) && (ORX_MSG_TYPE_SIMULATION != msg_type)) {
return 1;
}
uint32_t u32_clock_tick = 0;

122753
public/test/testcases/case45/fronthaul/DATA/265_slot0_jesd/dl_ant_post7.dat Normal file
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File diff suppressed because it is too large Load Diff

123009
public/test/testcases/case45/fronthaul/DATA/265_slot0_jesd/dl_ant_pre7.dat Normal file
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File diff suppressed because it is too large Load Diff

17
public/test/testcases/case45/fronthaul/inc/jesd_test_case45.h Normal file
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@ -0,0 +1,17 @@
#ifndef _JESD_TEST_CASE45_H_
#define _JESD_TEST_CASE45_H_
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case45/fronthaul/note.txt Normal file
View File

@ -0,0 +1 @@
带ORX功能的7ds2u, 带收发切换，发宽带信号

152
public/test/testcases/case45/fronthaul/src/jesd_test_case45.s.c Normal file
View File

@ -0,0 +1,152 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case44.c
// Author : xinxin.li
// Created On : 2023-03-22s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case45.h"
#include "rfm1_drv.h"
extern uint32_t antDataPre7[123008];
extern uint32_t antDataPost7[122752];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stFrontHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
if (JESD_CSU_CTRL == gJesdIOMode)
{
jesd_csu_init_nr_7ds2u();
//jesd_csu_init_nr_7d2u_slot0();
}
else if (JESD_IO_CTRL == gJesdIOMode)
{
jesd_csu_init_nr_7ds2u_iomode();
}
jesd_sniffer_orx_csu_init();
return 0;
}
void fh_test_case()
{
jesd_csu_start_nr_7ds2u();
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = 4;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
// uint32_t slotSamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*13;
uint32_t f7SamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6;
uint32_t b7SamCnt = SHORTCP_SAM_CNT*7;
uint32_t cpyCnt = 0;
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
}
memset((void*)JESD_NR7DS2U_RX_SLOTS_DATA_ADDR, 0, 4*8*SHORTCP_SAM_CNT*samByteCnt);
memset((void*)JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
memset((void*)JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
}

245515
public/test/testcases/case45/fronthaul/src/jesd_test_case45_antdata_post7.s.c Normal file
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246027
public/test/testcases/case45/fronthaul/src/jesd_test_case45_antdata_pre7.s.c Normal file
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60
public/test/testcases/case45/osp/src/ape_test_case45.s.c Normal file
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@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2023-11-07
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

122880
public/test/testcases/case48/fronthaul/DATA/1cell_DLcase0_2_593_200M_slot0.dat Normal file
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File diff suppressed because it is too large Load Diff

491520
public/test/testcases/case48/fronthaul/DATA/2cell_DLcase0_2_593_100M.dat Normal file
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File diff suppressed because it is too large Load Diff

122880
public/test/testcases/case48/fronthaul/DATA/2cell_DLcase0_2_593_200M.dat Normal file
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File diff suppressed because it is too large Load Diff

122880
public/test/testcases/case48/fronthaul/DATA/2cell_DLcase0_2_593_200M_slot0.dat Normal file
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File diff suppressed because it is too large Load Diff

122880
public/test/testcases/case48/fronthaul/DATA/2cell_DLcase0_2_593_200M_slot2.dat Normal file
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File diff suppressed because it is too large Load Diff

122880
public/test/testcases/case48/fronthaul/DATA/2cell_timedata_f0_2_593.dat Normal file
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File diff suppressed because it is too large Load Diff

122880
public/test/testcases/case48/fronthaul/DATA/2cell_timedata_f0_2_593_100M.dat Normal file
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File diff suppressed because it is too large Load Diff

15
public/test/testcases/case48/fronthaul/DATA/cell_data_read.m Normal file
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@ -0,0 +1,15 @@
fd_in = fopen('D:\code\platform_v2.1_20231102_git_jesd_frameheader\public\test\testcases\case48\fronthaul\DATA\2cell_timedata.dat', 'r');
data_in = fscanf(fd_in, '%x,', Inf);
fclose(fd_in);
fd_out=fopen('D:\code\platform_v2.1_20231102_git_jesd_frameheader\public\test\testcases\case48\fronthaul\DATA\dl_ant0_preSymbol.dat', 'w+');
for i=1:1:61504
fprintf(fd_out, '0x%08x,\n', data_in(i));
end
fclose(fd_out);
fd_out=fopen('D:\code\platform_v2.1_20231102_git_jesd_frameheader\public\test\testcases\case48\fronthaul\DATA\dl_ant0_postSymbol.dat', 'w+');
for i=1:1:61376
fprintf(fd_out, '0x%08x,\n', data_in(61504+i));
end
fclose(fd_out);

61376
public/test/testcases/case48/fronthaul/DATA/dl_ant0_postSymbol.dat Normal file
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File diff suppressed because it is too large Load Diff

61504
public/test/testcases/case48/fronthaul/DATA/dl_ant0_preSymbol.dat Normal file
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File diff suppressed because it is too large Load Diff

122880
public/test/testcases/case48/fronthaul/DATA/new_2dmrs.dat Normal file
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2
public/test/testcases/case48/fronthaul/note.txt
View File

@ -1 +1 @@
7ds2u, 带收发切换，发256QAM, 245.76M 采样率
2.5ms双周期, 带收发切换，发256QAM, 245.76M 采样率，200M带宽

9
public/test/testcases/case48/fronthaul/src/jesd_test_case48.s.c
View File

@ -56,7 +56,8 @@ int32_t fh_drv_init(void)
int32_t fh_csu_test_init(void)
{
jesd_csu_init_nr_2500us_double();
//jesd_csu_init_nr_2500us_double();
jesd_csu_init_nr_2500us_double_slot0();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
@ -89,6 +90,12 @@ void jesd_tx_data_init()
uint32_t b7SamCnt = (SHORTCP_SAM_CNT*7)*2;
uint32_t cpyCnt = 0;
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
// valid data
// IQ data
samByteCnt = 4;

491008
public/test/testcases/case48/fronthaul/src/jesd_test_case48_antdata_post7.s.c
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File diff suppressed because it is too large Load Diff

492032
public/test/testcases/case48/fronthaul/src/jesd_test_case48_antdata_pre7.s.c
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File diff suppressed because it is too large Load Diff

6
public/test/testcases/case49/fronthaul/src/jesd_test_case49.s.c
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@ -90,6 +90,12 @@ void jesd_tx_data_init()
uint32_t b7SamCnt = (SHORTCP_SAM_CNT*7)*2;
uint32_t cpyCnt = 0;
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR, 0, 4*(f7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
memset_ucp((void*)JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR, 0, 4*(b7SamCnt)*samByteCnt);
// valid data
// IQ data
samByteCnt = 4;