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1.commit normalization drv version;

Browse Source 
2.add ecpri code;
3.test case: case34,case44,case21(CPRI/JESD mode)
This commit is contained in:
xinxin.li 2023-09-22 19:47:02 +08:00
parent 862b11d823
commit a9180edc85
420 changed files with 1462140 additions and 530531 deletions
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12
build.sh
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@ -1,7 +1,7 @@
set -e
usage() {
echo "usage: $0 [variants] [--debug] [--evmy] [--test caseid] [--cpri/--jesd] [--pcie] [--mask bitmap] [--diagnostic]" 1>&2
echo "usage: $0 [variants] [--debug] [--evmy] [--test caseid] [--cpri/--ecpri/--jesd] [--pcie] [--mask bitmap] [--diagnostic]" 1>&2
msg=${1:-}
if [ ! -z "${msg}" ]; then
echo "error:$1"
@ -21,10 +21,11 @@ board_option="evb"
osp_case_id=0
cpri_case_id=34
ecpri_case_id=100
jesd_case_id=43
fh_case_id=
ape_core_mask=0xf
platform_build_data=0x20230719
platform_build_data=0x20230823
while [[ "$#" > 0 ]]; do
case $1 in
@ -34,6 +35,7 @@ while [[ "$#" > 0 ]]; do
--evmy) board_option="evmy"; shift;;
--cpri) fronthaul_option="cpri"; shift;;
--ecpri) fronthaul_option="ecpri"; shift;;
--jesd) fronthaul_option="jesd"; shift;;
--pcie) backhaul_option="pcie"; shift;;
@ -60,6 +62,12 @@ while [[ "$#" > 0 ]]; do
fi
fh_case_id=${cpri_case_id};
shift;;
--testecpri) fh_test_option="yes";
if [[ ! -z "$2" ]] && [[ -n "$(echo $2 | sed -n " /^[0-9]\+$/p")" ]]; then
ecpri_case_id=$2; shift;
fi
fh_case_id=${ecpri_case_id};
shift;;
--testjesd) fh_test_option="yes";
if [[ ! -z "$2" ]] && [[ -n "$(echo $2 | sed -n " /^[0-9]\+$/p")" ]]; then
jesd_case_id=$2; shift;

45
inc/drv_ape.h
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@ -49,7 +49,7 @@ void phy_para_init(int protocol, int option);
// stc timer初始化，该接口只需八个核中的一个核调用即可
void ape_stc_init();
// pet sm初始化，该接口只需八个核中的一个核调用即可，放在main函数的最前面
// scs sm初始化，该接口只需八个核中的一个核调用即可，放在main函数的最前面
void pet_sm_init();
/***************************************************************/
// 以下接口，为帕拉丁临时验证带OSP的版本使用，最好按声明的顺序依次调用。
@ -487,6 +487,49 @@ int ape_csu_dma_2Dto2D_transfer(uint64_t addrSrc, uint16_t blockLenSrc, uint64_t
int ape_csu_dma_3Dto1D_transfer(uint64_t addrSrc, uint16_t xNumSrc, uint16_t yNumSrc, uint64_t yStepSrc, uint64_t zStepSrc,
uint64_t addrDst, uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir);
/*!
* @brief: 一维搬移到三维
* @author: xinxin.li
* @Date: 2023年8月28日
* @param: addrSrc : [源地址 ]
* @param: addrDst : [目的地址 ]
* @param: xNumDst : [目的第一维度搬移字节数 ]
* @param: yNumDst : [目的第二维度搬移个数 ]
* @param: yStepDst : [目的第二维度搬移步进字节数 ]
* @param: zStepDst : [目的第三维度搬移步进字节数 ]
* @param: dataLen : [搬移总字节数 ]
* @param: tag : [DMA Tag: 0~31用于查询是否完成 ]
* @param: isWait : [是否等DMA结束函数返回0:不等待,1:等待 ]
* @param: regGroup : [寄存器组，2：源寄存器组4，目的寄存器组5；3：源寄存器组6，目的寄存器组7 ]
* @param: dir : [0：L2G，1：G2L or G2G ]
*/
int32_t ape_csu_dma_1Dto3D_transfer(uint64_t addrSrc, uint64_t addrDst, uint16_t xNumDst, uint16_t yNumDst, uint64_t yStepDst, uint64_t zStepDst,
uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir);
/*!
* @brief: 三维搬移到三维
* @author: xinxin.li
* @Date: 2023年8月28日
* @param: addrSrc : [源地址 ]
* @param: xNumSrc : [源第一维度搬移字节数 ]
* @param: yNumSrc : [源第二维度搬移个数 ]
* @param: yStepSrc : [源第二维度搬移步进字节数 ]
* @param: zStepSrc : [源第三维度搬移步进字节数 ]
* @param: addrDst : [目的地址 ]
* @param: xNumDst : [目的第一维度搬移字节数 ]
* @param: yNumDst : [目的第二维度搬移个数 ]
* @param: yStepDst : [目的第二维度搬移步进字节数 ]
* @param: zStepDst : [目的第三维度搬移步进字节数 ]
* @param: dataLen : [搬移总字节数 ]
* @param: tag : [DMA Tag: 0~31用于查询是否完成 ]
* @param: isWait : [是否等DMA结束函数返回0:不等待,1:等待 ]
* @param: regGroup : [寄存器组，2：源寄存器组4，目的寄存器组5；3：源寄存器组6，目的寄存器组7 ]
* @param: dir : [0：L2G，1：G2L or G2G ]
*/
int32_t ape_csu_dma_3Dto3D_transfer(uint64_t addrSrc, uint16_t xNumSrc, uint16_t yNumSrc, uint64_t yStepSrc, uint64_t zStepSrc,
uint64_t addrDst, uint16_t xNumDst, uint16_t yNumDst, uint64_t yStepDst, uint64_t zStepDst,
uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir);
//pucch freq data copy from sm to dm
/*!
* @brief: 三维外部搬移到一维内部，外部地址不超过32位，寄存器组源用4目的用0

57
inc/drv_rfm.h
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@ -6,6 +6,63 @@
#define GET_STC_CNT() (LOAD_EX_V_W(STC_LOCAL_TIME_BASE))
/**************************************************/
/* 前传接口驱动初始化相关 */
/**************************************************/
// cpri option模式，决定接口速率
typedef enum _tagCpriOptionID
{
CPRI_OPTION_7 = 7,
CPRI_OPTION_8 = 8,
CPRI_OPTION_9 = 9,
CPRI_OPTION_10 = 10
}CpriOptID;
// cpri map模式
typedef enum _tagCpriMapType
{
NR4T4R_7DS2U = 0,
NR4T4R_LTE2T2R_FDD,
NR2_4T4R_7DS2U
}CpriMapType;
// ecpri option模式，决定接口速率
typedef enum _tagEcpriOptionID
{
ECPRI_OPTION_10G = 10,
ECPRI_OPTION_25G = 25
}EcpriOptID;
/*
函数名称：cpri_init
函数入参：
uint32_t option : CPRI_OPTION_7 : option7
CPRI_OPTION_8 : option8
CPRI_OPTION_9 : option9
CPRI_OPTION_10: option10
uint32_t MappingMode : NR4T4R_7DS2U : 122.88M采样率，NR模式，4T4R
NR4T4R_LTE2T2R_FDD : 122.88+30.72M采样，1NR_4T4R+1LTE_2T2R
NR2_4T4R_7DS2U : 2
函数功能：cpri驱动初始化
*/
void cpri_init(uint32_t option,uint32_t MappingMode);
/*
函数名称：jesd_init
函数入参：无
函数功能：jesd驱动初始化
*/
void jesd_init();
/*
函数名称：ecpri_init
函数入参：uint32_t nOption : ECPRI_OPTION_10G : 10g速率模式,
ECPRI_OPTION_25G : 25g速率模式
函数功能：ecpri驱动初始化
*/
void ecpri_init(uint8_t nOption);
/*
函数名称：delay_us
函数入参：num：微秒

20
inc/osp_ape.h
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@ -206,7 +206,25 @@ extern int osp_get_cfgfile(char* name, uint32_t *pbuf, int* psize);
函数返回值：无
*/
extern void osp_timer_sync(int tti); /* 使能任务定时点 */
extern void osp_timer_sync(int scsId); /* 使能任务定时点 */
/*
函数名称：osp_timer_unsync
函数功能：删小区时，用于定时点中断、任务及时隙中断
函数参数：int scsId:子载波ID号
typedef enum _tagScsID
{
LTE_SCS_ID = 0,
NR_SCS_30K,
NR_SCS_60K,
NR_SCS_120K,
SCS_NULL = 0xFFFF
}numScsID;
函数返回值：无
*/
extern void osp_timer_unsync(int scsId);
#endif

2
public/ape_spu/driver/inc/ape_cpri_timer.h
View File

@ -6,7 +6,7 @@
void set_cpri_timer_ape_int(void);
int32_t clr_cpri_timer_ape_int(void);
int32_t clr_cpri_timer_ape_int(void);
void isr_cpri_ape_slot_offset(void);

6
public/ape_spu/driver/inc/ape_ecpri_timer.h
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@ -1,11 +1,11 @@
#ifndef APEDRV_APE_INC_APE_ECPRI_TIMER_H_
#define APEDRV_APE_INC_APE_ECPRI_TIMER_H_
#include "typedef.h"
#include "typedef.h"
void set_ecpri_timer_ape_int(void);
int32_t clr_ecpri_timer_ape_int(void);
int32_t clr_ecpri_timer_ape_int(void);
void isr_ecpri_ape_slot_offset(void);

2
public/ape_spu/driver/inc/ape_jesd_timer.h
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@ -5,7 +5,7 @@
void set_jesd_timer_ape_int(int32_t nTmrId);
int32_t clr_jesd_timer_ape_int(int32_t nTmrId);
int32_t clr_jesd_timer_ape_int(int32_t nTmrId);
void isr_jesd_rx0_ape_slot(void);

6
public/ape_spu/driver/inc/ape_mtimer.h
View File

@ -3,13 +3,15 @@
#include "typedef.h"
void ape_mtimer_int_init(void);
void ape_mtimer_int_init(uint16_t nTimerId);
void ape_mtimer_int_clear(uint16_t nTimerId);
void ape_mtimer_sync(int32_t nScsId);
void ape_mtimer_unsync(int32_t nScsId);
int32_t mtimer_sfn_para_init(int32_t nTmrId);
int32_t mtimer_sfn_para_init(int32_t nTmrId, int32_t nScsId);
void ape_slot_ctw_set(uint8_t nTmrId);
int32_t mtimer_ape_slot_callback(uint8_t nTmrId);

34
public/ape_spu/driver/src/ape_cpri_timer.s.c
View File

@ -28,23 +28,23 @@ void set_cpri_timer_ape_int(void)
//int tmrId = CPRI_TMR_APE0_TXSLOT + (apeId<<1);
//UCP_PRINT_LOG("intNum = 0x%x, int set val: 0x%x. \r\n", intNum, (1<<tmrId) | (1<<(tmrId+1)));
}
int32_t clr_cpri_timer_ape_int(void)
{
int32_t apeId = get_core_id();
// tx slot
uint32_t intNum = APC_CPRI_TMR_INTR0 + MTMR_INT_APE0_SLOT + apeId;
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;
}
return 0;
}
int32_t clr_cpri_timer_ape_int(void)
{
int32_t apeId = get_core_id();
// tx slot
uint32_t intNum = APC_CPRI_TMR_INTR0 + MTMR_INT_APE0_SLOT + apeId;
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;
}
return 0;
}
void isr_cpri_ape_slot_offset(void)
{

18
public/ape_spu/driver/src/ape_drv.s.c
View File

@ -53,20 +53,30 @@ void ape_drv_int_init()
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
//spin_lock(LOCK_BUILD_CELL);
stc_timer_ctwint_init(); // stc timer ctw int
//spin_unlock(LOCK_BUILD_CELL);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
//spin_lock(LOCK_BUILD_CELL);
ctc_cal_intr_init(); // ctc int
//spin_unlock(LOCK_BUILD_CELL);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
}
void tod_int_init(void)
{
int apeId = get_core_id();
if (0 == apeId)
{
stc_timer_todint_init();
UCP_PRINT_EMPTY("stc tod int init. \r\n");
}
return;
}

44
public/ape_spu/driver/src/ape_ecpri_timer.s.c
View File

@ -29,35 +29,25 @@ void set_ecpri_timer_ape_int(void)
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
debug_write(DBG_DDR_ERR_IDX(apeId, 32), ret);
}
// int tmrId = ECPRI_TMR_APE0_TXSLOT + (apeId<<1);
// UCP_PRINT_LOG("intNum = 0x%x, int set val: 0x%x. \r\n", intNum, (1<<tmrId) | (1<<(tmrId+1)));
}
int32_t clr_ecpri_timer_ape_int(void)
{
int32_t apeId = get_core_id();
// tx slot
uint32_t intNum = APC_ECPRI_SUB_INTR2;
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;
}
return 0;
}
// temp to be deleted
//int32_t gApeSlotIntCnt2 = 0;
//int32_t gApeSlotCallCnt2 = 0;
//uint32_t lastTxStcCnt2 = 0;
//uint32_t nowTxStcCnt2 = 0;
int32_t clr_ecpri_timer_ape_int(void)
{
int32_t apeId = get_core_id();
// tx slot
uint32_t intNum = APC_ECPRI_SUB_INTR2;
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;
}
return 0;
}
void isr_ecpri_ape_slot_offset(void)
{
mtimer_ape_slot_callback(MTIMER_ECPRI_ID);

54
public/ape_spu/driver/src/ape_jesd_timer.s.c
View File

@ -43,33 +43,33 @@ void set_jesd_timer_ape_int(int32_t nTmrId)
//int tmrId = CPRI_TMR_APE0_TXSLOT + (apeId<<1);
//UCP_PRINT_LOG("intNum = 0x%x, int set val: 0x%x. \r\n", intNum, (1<<tmrId) | (1<<(tmrId+1)));
}
int32_t clr_jesd_timer_ape_int(int32_t nTmrId)
{
int32_t apeId = get_core_id();
uint32_t intNum = 0;
if (MTIMER_JESD_RX0_ID == nTmrId)
{
intNum = APC_JESD_RX0_SBU0_TMR_INTR0 + MTMR_INT_APE0_SLOT + apeId;
}
else if (MTIMER_JESD_RX1_ID == nTmrId)
{
intNum = APC_JESD_RX1_SBU0_TMR_INTR0 + MTMR_INT_APE0_SLOT + apeId;
}
else
{
return -1 ;
}
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;
}
return 0;
}
int32_t clr_jesd_timer_ape_int(int32_t nTmrId)
{
int32_t apeId = get_core_id();
uint32_t intNum = 0;
if (MTIMER_JESD_RX0_ID == nTmrId)
{
intNum = APC_JESD_RX0_SBU0_TMR_INTR0 + MTMR_INT_APE0_SLOT + apeId;
}
else if (MTIMER_JESD_RX1_ID == nTmrId)
{
intNum = APC_JESD_RX1_SBU0_TMR_INTR0 + MTMR_INT_APE0_SLOT + apeId;
}
else
{
return -1 ;
}
int32_t ret = smart_irq_free(intNum);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
// debug write
debug_write(DBG_DDR_ERR_IDX(apeId, 0), ret);
return -1;
}
return 0;
}
void isr_jesd_rx0_ape_slot(void)
{

172
public/ape_spu/driver/src/ape_mtimer.s.c
View File

@ -6,13 +6,12 @@
#include "ucp_mtimer.h"
#include "stc_timer.h"
#include "mtimer_com.h"
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
#include "ape_jesd_timer.h"
//#else
#include "ape_cpri_timer.h"
#include "ape_ecpri_timer.h"
#endif
#ifdef INTEGRATED_BS
#include "ape_jesd_timer.h"
#endif
//#endif
extern void osp_timer_call_task_spe(uint8_t u8slot, uint8_t u8taskidx); /* ¶¨Ê±µãÈÎÎñ´ÓÊ×λ¿ªÊ¼ */
//extern void osp_timer_restart(void);
@ -28,39 +27,43 @@ ddr_spinlock_t gSpinLockBuildCell;
int32_t gApeCalFlag = 0;
int32_t gApeCalCnt = 0;
void ape_mtimer_int_init(void)
void ape_mtimer_int_init(uint16_t nTimerId)
{
#ifdef DISTRIBUTED_BS
if (MTIMER_CPRI_ID == gMtimerId)
uint8_t nBsType = get_protocol_sel();
if (PROTOCOL_JESD == nBsType)
{
set_cpri_timer_ape_int();
set_jesd_timer_ape_int(nTimerId);
}
else
{
set_ecpri_timer_ape_int();
if (MTIMER_CPRI_ID == nTimerId)
{
set_cpri_timer_ape_int();
}
else
{
set_ecpri_timer_ape_int();
}
}
#endif
#ifdef INTEGRATED_BS
set_jesd_timer_ape_int(gMtimerId);
#endif
}
void ape_mtimer_int_clear(void)
void ape_mtimer_int_clear(uint16_t nTimerId)
{
#ifdef DISTRIBUTED_BS
if (MTIMER_CPRI_ID == gMtimerId)
uint8_t nBsType = get_protocol_sel();
if (PROTOCOL_JESD == nBsType)
{
clr_cpri_timer_ape_int();
clr_jesd_timer_ape_int(nTimerId);
}
else
{
clr_ecpri_timer_ape_int();
if (MTIMER_CPRI_ID == nTimerId)
{
clr_cpri_timer_ape_int();
}
else
{
clr_ecpri_timer_ape_int();
}
}
#endif
#ifdef INTEGRATED_BS
clr_jesd_timer_ape_int(gMtimerId);
#endif
}
void ape_mtimer_sync(int32_t nScsId)
@ -70,7 +73,7 @@ void ape_mtimer_sync(int32_t nScsId)
uint16_t nTimerId = do_read_volatile_short(&(phyPara[nScsId].mtimerId));
__ucps2_synch(f_SM);
gMtimerId = nTimerId;
if (-1 == mtimer_sfn_para_init(nTimerId))
if (-1 == mtimer_sfn_para_init(nTimerId, nScsId))
{
return;
}
@ -79,35 +82,35 @@ void ape_mtimer_sync(int32_t nScsId)
smart_ddr_spin_lock_init(&gSpinLockBuildCell);
smart_ddr_spinlock(&gSpinLockBuildCell);
ape_mtimer_int_init(); // mtimer int attach
ape_mtimer_int_init(nTimerId); // mtimer int attach
uint16_t runCore = do_read_volatile_short(&(phyPara[gScsId].runCoreId));
uint16_t runCore = do_read_volatile_short(&(phyPara[nScsId].runCoreId));
__ucps2_synch(f_SM);
runCore |= (1<<apeId);
do_write_short((&(phyPara[gScsId].runCoreId)), runCore);
do_write_short((&(phyPara[nScsId].runCoreId)), runCore);
smart_ddr_spinunlock(&gSpinLockBuildCell);
}
void ape_mtimer_unsync(int32_t nScsId)
{
uint16_t apeId = get_core_id();
//uint16_t nTimerId = do_read_volatile_short(&(phyPara[nScsId].mtimerId));
uint16_t nTimerId = do_read_volatile_short(&(phyPara[nScsId].mtimerId));
//gSpinLockBuildCell.lock_addr = 0xB7FD1440;
//gSpinLockBuildCell.flag_addr = 0xB7FD1444;
//smart_ddr_spin_lock_init(&gSpinLockBuildCell);
smart_ddr_spinlock(&gSpinLockBuildCell);
ape_mtimer_int_clear(); // mtimer int detach
ape_mtimer_int_clear(nTimerId); // mtimer int detach
uint16_t runCore = do_read_volatile_short(&(phyPara[gScsId].runCoreId));
uint16_t runCore = do_read_volatile_short(&(phyPara[nScsId].runCoreId));
__ucps2_synch(f_SM);
runCore &= (~(1<<apeId));
do_write_short((&(phyPara[gScsId].runCoreId)), runCore);
do_write_short((&(phyPara[nScsId].runCoreId)), runCore);
smart_ddr_spinunlock(&gSpinLockBuildCell);
}
int32_t mtimer_sfn_para_init(int32_t nTmrId)
int32_t mtimer_sfn_para_init(int32_t nTmrId, int32_t nScsId)
{
if (((int32_t)MTIMER_CPRI_ID != nTmrId)&&((int32_t)MTIMER_ECPRI_ID != nTmrId))
{
@ -115,46 +118,62 @@ int32_t mtimer_sfn_para_init(int32_t nTmrId)
return -1;
}
memset(&gCellSfnPara[nTmrId], 0, sizeof(stSfnPara));
gCellSfnPara[nTmrId].scsId = gScsId;
gCellSfnPara[nTmrId].slotPeriod = do_read_volatile_short(&(phyPara[gScsId].slotPeriod)); // 500; //
gCellSfnPara[nTmrId].tddSlotNum = do_read_volatile_short(&(phyPara[gScsId].slotNumOfTdd)); // 10; //
gCellSfnPara[nTmrId].slotMaxNum = do_read_volatile_short(&(phyPara[gScsId].slotNumOfSfn)); // 20; //
gCellSfnPara[nTmrId].scsId = nScsId;
gCellSfnPara[nTmrId].slotPeriod = do_read_volatile_short(&(phyPara[nScsId].slotPeriod)); // 500; //
gCellSfnPara[nTmrId].tddSlotNum = do_read_volatile_short(&(phyPara[nScsId].slotNumOfTdd)); // 10; //
gCellSfnPara[nTmrId].slotMaxNum = do_read_volatile_short(&(phyPara[nScsId].slotNumOfSfn)); // 20; //
__ucps2_synch(f_SMR);
gCellSfnPara[nTmrId].txSlotNum = 0; // gCellSfnPara[nTmrId].slotMaxNum - 1;
gCellSfnPara[nTmrId].txSfnNum = 0; // 1023;
gCellSfnPara[nTmrId].rxSlotNum = gCellSfnPara[nTmrId].slotMaxNum - 1;
gCellSfnPara[nTmrId].rxSfnNum = 1023;
#if 0
debug_write((DBG_DDR_IDX_DRV_BASE+48), gCellSfnPara[nTmrId].scsId); // 0xC0
debug_write((DBG_DDR_IDX_DRV_BASE+49), do_read_volatile_short(&(phyPara[gScsId].slotPeriod))); // 0xC4
debug_write((DBG_DDR_IDX_DRV_BASE+50), do_read_volatile_short(&(phyPara[gScsId].slotNumOfTdd))); // 0xC8
debug_write((DBG_DDR_IDX_DRV_BASE+51), do_read_volatile_short(&(phyPara[gScsId].slotNumOfSfn))); // 0xCC
//debug_write((DBG_DDR_IDX_DRV_BASE+52), (uint32_t)(&(phyPara[gScsId].slotNumOfTdd))); // 0xD0
#endif
return 0;
}
int32_t ape_cal_sfn(void)
int32_t ape_cal_sfn(uint8_t nTmrId)
{
int32_t apeId = get_core_id();
if (1 == gCellSfnPara[MTIMER_CPRI_ID].ctcIntFlag)
int32_t scsId = 0;
int32_t i = 0;
if (1 == gCellSfnPara[nTmrId].ctcIntFlag)
{
gCellSfnPara[MTIMER_CPRI_ID].ctcIntFlag = 0;
int32_t scsId = gCellSfnPara[MTIMER_CPRI_ID].scsId;
gCellSfnPara[MTIMER_CPRI_ID].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));
gCellSfnPara[MTIMER_CPRI_ID].rxSfnNum = do_read_volatile(&(phyPara[scsId].rxSfnNum));
gCellSfnPara[MTIMER_CPRI_ID].txSlotNum = do_read_volatile(&(phyPara[scsId].txSlotNum));
gCellSfnPara[MTIMER_CPRI_ID].rxSlotNum = do_read_volatile(&(phyPara[scsId].rxSlotNum));
for (i = 0; i < PHY_SCS_MAX_NUM; i++)
{
if (nTmrId == do_read_volatile_short(&(phyPara[i].mtimerId))) // 已建了第一个子载波小区
{
gCellSfnPara[nTmrId].scsId = i;
scsId = i;
break;
}
}
if (PHY_SCS_MAX_NUM == i)
{
return -1;
}
gCellSfnPara[nTmrId].ctcIntFlag = 0;
gCellSfnPara[nTmrId].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));
gCellSfnPara[nTmrId].rxSfnNum = do_read_volatile(&(phyPara[scsId].rxSfnNum));
gCellSfnPara[nTmrId].txSlotNum = do_read_volatile(&(phyPara[scsId].txSlotNum));
gCellSfnPara[nTmrId].rxSlotNum = do_read_volatile(&(phyPara[scsId].rxSlotNum));
gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt = 0;
gCellSfnPara[MTIMER_CPRI_ID].rxSlotIntCnt = 0;
gCellSfnPara[nTmrId].txSlotIntCnt = 0;
gCellSfnPara[nTmrId].rxSlotIntCnt = 0;
gApeCalFlag = 1;
gStcTimerPara.ctwStartFlag = 0;
gApeCalCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+544+apeId), gApeCalCnt); // 0x880
debug_write((DBG_DDR_IDX_DRV_BASE+556+apeId), GET_STC_CNT()); // 0x8b0
debug_write((DBG_DDR_IDX_DRV_BASE+536+apeId), gApeCalCnt); // 0x860
debug_write((DBG_DDR_IDX_DRV_BASE+548+apeId), GET_STC_CNT()); // 0x890
debug_write((DBG_DDR_IDX_DRV_BASE+560+apeId), gCellSfnPara[MTIMER_CPRI_ID].txSfnNum); // 0x8c0
debug_write((DBG_DDR_IDX_DRV_BASE+568+apeId), gCellSfnPara[MTIMER_CPRI_ID].rxSfnNum); // 0x8e0
#endif
}
return 0;
@ -204,28 +223,31 @@ uint32_t apeSlotInterMax = 0;
int32_t mtimer_ape_slot_callback(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = 0;
#ifdef DISTRIBUTED_BS
if (MTIMER_CPRI_ID == nTmrId)
uint8_t nBsType = get_protocol_sel();
if (PROTOCOL_JESD == nBsType)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
if (nTmrId >= MTIMER_INTEGRATED_MAX_NUM)
{
return -1;
}
tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
}
else
{
return -1;
if (MTIMER_CPRI_ID == nTmrId)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
}
else
{
return -1;
}
}
#endif
#ifdef INTEGRATED_BS
if (nTmrId >= MTIMER_MAX_NUM)
{
return -1;
}
tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
#endif
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
@ -251,9 +273,9 @@ int32_t mtimer_ape_slot_callback(uint8_t nTmrId)
uint32_t crVal = (1<<txSlotTmrId);
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), crVal);
do_write(flagAddr, crVal);
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
// sfn calibration
ape_cal_sfn();
ape_cal_sfn(nTmrId);
// update sfn and slot num
gCellSfnPara[nTmrId].txSlotNum++;
__ucps2_synch(0);
@ -310,14 +332,14 @@ uint32_t start = GET_STC_CNT();
}
lastTxStcCnt = nowTxStcCnt;
#endif
debug_write((DBG_DDR_IDX_DRV_BASE+292+(apeId<<2)), (GET_STC_CNT()-start)); // 0x490
//debug_write((DBG_DDR_IDX_DRV_BASE+292+(apeId<<2)), (GET_STC_CNT()-start)); // 0x490
}
if (tEventFlag & (1<<rxSlotTmrId)) // rx slot offset
{
uint32_t crVal = ((1<<rxSlotTmrId));
do_write(((tmrBaseAddr+MTMR_TEVENT0_REG)), crVal);
do_write(flagAddr, crVal);
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
gCellSfnPara[nTmrId].rxSlotNum++;
__ucps2_synch(0);
if (gCellSfnPara[nTmrId].rxSlotNum == gCellSfnPara[nTmrId].slotMaxNum)
@ -346,7 +368,7 @@ uint32_t start = GET_STC_CNT();
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intNum), APE_INT_RX_SLOT);
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intCnt), gCellSfnPara[nTmrId].rxSlotIntCnt);
debug_write((DBG_DDR_IDX_DRV_BASE+293+(apeId<<2)), (GET_STC_CNT()-start)); // 0x494
//debug_write((DBG_DDR_IDX_DRV_BASE+293+(apeId<<2)), (GET_STC_CNT()-start)); // 0x494
}
tEventFlag = do_read_volatile(flagAddr);
}

293
public/ape_spu/driver/src/ape_stc_timer.s.c Normal file
View File

@ -0,0 +1,293 @@
#include "ape_cnt.h"
#include "ape_csu.h"
#include "stc_timer.h"
#include "phy_para.h"
#include "ape_cpri_timer.h"
#include "ucp_drv_common.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "smartos.h"
extern void osp_timer_call_task();
extern void osp_timer_call_task_spe(uint8_t u8slot, uint8_t u8taskidx); /* ?¡§¨º¡À¦Ì?¨¨???¡ä¨®¨º¡Á???a¨º? */
stStcTimerPara gStcTimerPara;
extern stPhyScsPara* phyPara;
extern uint32_t gScsId;
void stc_timer_set_tmrpoint(stStcTimerPoint* pTmrPoint)
{
stc_timer_ctwint_disable();
gStcTimerPara.slotTddNumMax = do_read_volatile_short(&(phyPara[gScsId].slotNumOfTdd));
__ucps2_synch(f_SMR);
gStcTimerPara.slotPointNum = TDD_TMR_POINT_MAX / TDD_SLOT_NUM_MAX; // gStcTimerPara.slotTddNumMax;
gStcTimerPara.R = STC_RT;
gStcTimerPara.usR = STC_RT / 1000000;
gStcTimerPara.ctwSetFinished = 0;
gStcTimerPara.ctwStartFlag = 0;
gStcTimerPara.tmrPointTotalNum = 0;
memset(gStcTimerPara.tmrPointNum, 0, TDD_SLOT_NUM_MAX);
memset(gStcTimerPara.tmrPoint, 0, sizeof(stStcTimerPoint)*TDD_SLOT_NUM_MAX);
gStcTimerPara.curSlotNum = 0;
gStcTimerPara.curSlotTmrPointId = 0;
int32_t apeId = get_core_id();
if (NULL == pTmrPoint)
{
UCP_PRINT_ERROR("pTmrPoint NULL! \r\n");
return;
}
UCP_PRINT_LOG("stc timer set tmrpoint start. \r\n");
int32_t idx = 0;
for (int32_t i = 0; i < gStcTimerPara.slotTddNumMax; i++)
{
for (int32_t j = 0; j < gStcTimerPara.slotPointNum; j++)
{
idx = i*gStcTimerPara.slotPointNum+j;
gStcTimerPara.tmrPoint[idx].pointVal = pTmrPoint[idx].pointVal*gStcTimerPara.usR;
gStcTimerPara.tmrPoint[idx].lastFlag = pTmrPoint[idx].lastFlag;
gStcTimerPara.tmrPointNum[i]++;
gStcTimerPara.tmrPointTotalNum++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+5120+(apeId<<10) + (idx<<1)), gStcTimerPara.tmrPoint[idx].pointVal); // 0x5000
debug_write((DBG_DDR_IDX_DRV_BASE+5120+(apeId<<10) + ((idx<<1) + 1)), gStcTimerPara.tmrPoint[idx].lastFlag); // 0x5000
#endif
if (1 == pTmrPoint[idx].lastFlag)
{
break;
}
}
}
if (0 < gStcTimerPara.tmrPointTotalNum)
{
gStcTimerPara.ctwSetFinished = 1;
}
}
int32_t setCnt = 0;
void stc_timer_set_next_ctw(int32_t setFlag)
{
setCnt++;
int32_t apeId = get_core_id();
if (1 == setFlag) // set in the slot int function
{
uint32_t addr = 0;
if (apeId & 0x4)
{
addr = (uint32_t)(&LTBG1_TIME_BASE);
}
else
{
addr = (uint32_t)(&LTBG0_TIME_BASE);
}
gStcTimerPara.ctwVal = do_read_volatile(addr);
}
gStcTimerPara.curSlotTmrPointId++;
int32_t slotNum = gStcTimerPara.curSlotNum;
if (gStcTimerPara.curSlotTmrPointId >= gStcTimerPara.tmrPointNum[slotNum]) //gStcTimerPara.slotPointNum)
{
UCP_PRINT_ERROR("gStcTimerPara.curSlotTmrPointId: 0x%x error. \r\n", gStcTimerPara.curSlotTmrPointId);
}
int32_t idx = slotNum * gStcTimerPara.slotPointNum + gStcTimerPara.curSlotTmrPointId;
#if 0 //def PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+384+(apeId<<6)+(setCnt&0x3F)), idx); // 0x600
debug_write((DBG_DDR_IDX_DRV_BASE+256+(apeId<<6)+(setCnt&0x3F)), gStcTimerPara.tmrPoint[idx].lastFlag); // 0x400
#endif
gStcTimerPara.ctwVal += gStcTimerPara.tmrPoint[idx].pointVal;
if (gStcTimerPara.ctwVal >= STC_RT)
{
gStcTimerPara.ctwVal -= STC_RT;
}
do_write(((uint32_t*)(&CTW_REG_TIMER_0_0) + apeId), gStcTimerPara.ctwVal); // set ctw reg, clear ctw int
#if 0 //def PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+1024 + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId << 9)), gStcTimerPara.ctwVal); // 0x1000
// debug_write((DBG_DDR_IDX_DRV_BASE+6144 + (setCnt&0x1FF) + (apeId << 9)), gStcTimerPara.ctwVal); // 0x6000
#endif
}
void stc_timer_todint_init(void)
{
int32_t apeId = get_core_id();
#ifndef GPS_PP1S_SYNC
TOD_REG_IRQ_EN |= 0x1; // set tod int enable
#endif
uint32_t intNum = APC_STC_INTR8;
// attach interrupt func
int32_t ret = smart_irq_request(intNum, isr_stc_tod_int);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
debug_write(DBG_DDR_ERR_IDX(apeId, 8), ret);
}
}
ddr_spinlock_t gSpinLockCtwInit;
void stc_timer_ctwint_init()
{
int32_t apeId = get_core_id();
gSpinLockCtwInit.lock_addr = 0xB7FD1400;
gSpinLockCtwInit.flag_addr = 0xB7FD1404;
//gSpinLockCtwInit.spin_lock_addr = 0xB7FD1408;
//gSpinLockCtwInit.lock_w_addr = 0xB7FD140C;
//gSpinLockCtwInit.lock_loop_addr = 0xB7FD1410;
//gSpinLockCtwInit.unlock_loop_addr = 0xB7FD1410;
//gSpinLockCtwInit.unlock_addr = 0xB7FD1418;
smart_ddr_spin_lock_init(&gSpinLockCtwInit);
uint32_t intNum = APC_STC_INTR0 + apeId;
// attach interrupt func
smart_ddr_spinlock(&gSpinLockCtwInit);
int32_t ret = smart_irq_request(intNum, isr_stc_timer_int);
smart_ddr_spinunlock(&gSpinLockCtwInit);
if (0 != ret)
{
UCP_PRINT_EMPTY("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
debug_write(DBG_DDR_ERR_IDX(apeId, 9), ret);
}
}
void stc_timer_ctwint_enable()
{
int32_t apeId = get_core_id();
do_write(((uint32_t*)(&CTW_REG_IRQ_0_0) + apeId), 0x1); // set ctw irq enable
}
void stc_timer_ctwint_disable()
{
int32_t apeId = get_core_id();
do_write(((uint32_t*)(&CTW_REG_IRQ_0_0) + apeId), 0x0); // set ctw irq disable
}
//uint32_t stcCnt = 0;
//UINT32 gApe0CtwIntCnt = 0;
void isr_stc_timer_int()
{
int32_t apeId = get_core_id();
#if 0 //def PALLADIUM_TEST
gApe0CtwIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+63+apeId), gApe0CtwIntCnt); // 0xfc
#endif
stCoreInt* apeCoreIntInfo = (stCoreInt*)APE_INT_INFO_ADDR + APE_INT_MAXNUM*apeId;
int32_t status = do_read_volatile(&CTW_REG_STATUS);
__ucps2_synch(0);
if (status & (1 << apeId))
{
#if 0 //def PALLADIUM_TEST
uint32_t addr = 0;
if (apeId & 0x4)
{
addr = (uint32_t)(&LTBG1_TIME_BASE);
}
else
{
addr = (uint32_t)(&LTBG0_TIME_BASE);
}
debug_write(((DBG_DDR_IDX_DRV_BASE+2048) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(addr)); // 0x2000
#endif
gStcTimerPara.ctwIntCnt++;
int32_t idx = gStcTimerPara.curSlotNum * gStcTimerPara.slotPointNum + gStcTimerPara.curSlotTmrPointId;
uint8_t pointIdx = gStcTimerPara.curSlotTmrPointId;
if (1 != gStcTimerPara.tmrPoint[idx].lastFlag)
{
#ifdef PALLADIUM_TEST
// debug_write((DBG_DDR_IDX_DRV_BASE+192+(apeId<<6)+gStcTimerPara.curSlotNum), idx); // 0x300
#endif
stc_timer_set_next_ctw(0);
}
else
{
#ifdef PALLADIUM_TEST
// debug_write((DBG_DDR_IDX_DRV_BASE+224+(apeId<<6)+gStcTimerPara.curSlotNum), idx); // 0x380
#endif
stc_timer_ctwint_disable();
}
// debug_write(((DBG_DDR_IDX_DRV_BASE+10240) + ((gStcTimerPara.ctwIntCnt)&0x1FF) + (apeId<<9)), get_tx_nr_slot(1)); // 0xa000
//debug_write(((DBG_DDR_IDX_DRV_BASE+11264) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(&LTBG_TIME_BASE)); // 0xb000
osp_timer_call_task_spe(gStcTimerPara.curSlotNum, pointIdx);
//debug_write(((DBG_DDR_IDX_DRV_BASE+12288) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(&LTBG_TIME_BASE)); // 0xc000
#ifdef PALLADIUM_TEST
// if (1 < gStcTimerPara.ctwIntCnt)
{
// uint32_t period = GET_STC_CNT() - stcCnt;// GET_CNT_VAL(apeId)-stcCnt;//
// debug_write(((DBG_DDR_IDX_DRV_BASE+3072)+(gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), period); // 0x3000
}
// stcCnt = GET_STC_CNT();// GET_CNT_VAL(apeId); //
debug_write((DBG_DDR_IDX_DRV_BASE+101+(apeId<<1)), gStcTimerPara.ctwIntCnt); // 0x194
// write sm
do_write(&(apeCoreIntInfo[APE_INT_STC].intNum), APE_INT_STC);
do_write(&(apeCoreIntInfo[APE_INT_STC].intCnt), gStcTimerPara.ctwIntCnt);
//debug_write(((DBG_DDR_IDX_DRV_BASE+6144) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(addr)); // 0x6000
#endif
status = do_read_volatile(&CTW_REG_STATUS);
}
}
//extern UINT8 waitTodInt;
//uint32_t gApe0TodIntCnt = 0;
void isr_stc_tod_int()
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
//gApe0TodIntCnt++;
//debug_write((DBG_DDR_IDX_DRV_BASE+62), gApe0TodIntCnt); // 0xf8
#endif
int32_t status = do_read_volatile(&TOD_REG_INT_STATUS);
__ucps2_synch(0);
if (status & 0x1)
{
do_write((&TOD_REG_INT_STATUS), 0x1);
#if 0 //def PALLADIUM_TEST
uint32_t addr = 0;
if (apeId & 0x4)
{
addr = (uint32_t)(&LTBG1_TIME_BASE);
}
else
{
addr = (uint32_t)(&LTBG0_TIME_BASE);
}
debug_write(((DBG_DDR_IDX_DRV_BASE+4096) + (gStcTimerPara.todIntCnt&0x3FF)), do_read_volatile(addr)); // 0x4000
#endif
#ifndef ENABLE_SFNCAL
if (0 == gStcTimerPara.todIntCnt)
#else
if (1 == do_read_volatile(ARM_LOCK_FLAG_ADDR))
#endif
{
do_write((uint32_t*)(&TOD_REG_RT_LO), 0);
do_write((uint32_t*)(&TOD_REG_RT_HI), STC_RT);
do_write(STC_RT_ADDR, STC_RT);
}
#ifdef PALLADIUM_TEST
if (0 < gStcTimerPara.todIntCnt)
{
uint64_t temp = GET_CNT_VAL(apeId) + 0xFFFFFFFF;
uint32_t period = temp - gStcTimerPara.todLastStcCnt;
debug_write(((DBG_DDR_IDX_DRV_BASE+1088)+((gStcTimerPara.todIntCnt-1)&0x3F)), period); // 0x1000
}
gStcTimerPara.todLastStcCnt = GET_CNT_VAL(apeId);
#endif
gStcTimerPara.todIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64), gStcTimerPara.todIntCnt); // 0x100
#endif
status = do_read_volatile(&TOD_REG_INT_STATUS);
}
}

643
public/ape_spu/driver/src/stc_timer.s.c
View File

@ -1,643 +0,0 @@
#include "ucp_cpri.h"
#include "ape_cnt.h"
#include "ape_csu.h"
#include "stc_timer.h"
#include "ucp_cpri.h"
#include "ucp_js_subcrg.h"
#include "ucp_js_ctrl.h"
#include "ucp_sfr_c.h"
#include "phy_para.h"
#include "ape_cpri_timer.h"
#include "ucp_drv_common.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
#include "smartos.h"
extern void osp_timer_call_task();
extern void osp_timer_call_task_spe(uint8_t u8slot, uint8_t u8taskidx); /* ?¡§¨º¡À¦Ì?¨¨???¡ä¨®¨º¡Á???a¨º? */
stStcTimerPara gStcTimerPara;
extern stPhyScsPara* phyPara;
extern uint32_t gScsId;
void ape_stc_init()
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0x4
#endif
uint32_t pClk = stc_pclk_init();
if (0 == pClk)
{
UCP_PRINT_EMPTY("stc_init: pClk get error! \r\n");
#ifdef PALLADIUM_TEST
flag = -1;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
return;
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
stc_timer_init(pClk, STC_RT);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
do_write(&(TOD_REG_NF), (0xC0000000 | pClk)); // init finished
}
uint32_t stc_pclk_init()
{
uint32_t pClk = 0;
int32_t protoSel = get_protocol_sel();
int32_t protoOpt = get_protocol_opt();
if (PROTOCOL_CPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait cpri serdes clk init finished
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (CPRI_OPTION_7):
{
serdesTxClk = 491520000;
break;
}
case (CPRI_OPTION_8):
{
serdesTxClk = 316800000;
break;
}
case (CPRI_OPTION_9):
{
serdesTxClk = 380160000;
break;
}
case (CPRI_OPTION_10):
{
serdesTxClk = 760320000;
break;
}
default:
{
serdesTxClk = 316800000;
break;
}
}
JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
JECS_CTRL_PROTOCOL_SEL &= (~0x1); // jecs_protocol_sel = 0, sel cpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_ECPRI == protoSel)
{
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (ECPRI_OPTION_10G):
{
serdesTxClk = 156250000;
break;
}
case (ECPRI_OPTION_25G):
{
serdesTxClk = 390625000;
break;
}
default:
{
serdesTxClk = 156250000;
break;
}
}
// JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
JECS_CTRL_PROTOCOL_SEL |= 0x1; // jecs_protocol_sel = 1, sel ecpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_JESD == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait jesd serdes clk init finished
JECS_CRG_PLLSEL |= (0x6 << 7); // stc_src_clk_sel[2:0]=0x6
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
// laneRate = IQ_sample_rate * M * N' * (10/8)/L // max_laneRate = 12.5Gbps
// serdesTxClk = laneRate/40;
// pClk = serdesTxClk;
uint32_t samClk = do_read_volatile(JESD_TX_SAMPLE_RATE);
uint32_t jesdPara = do_read_volatile(JESD_TX_CH_PARA);
uint8_t paraL = jesdPara & 0xFF;
uint8_t paraM = (jesdPara >> 8) & 0xFF;
uint8_t paraN = (jesdPara >> 16) & 0xFF;
pClk = (uint64_t)(samClk/paraL/40)*paraM*paraN*10/8; // (uint64_t)(122880000/4/40)*8*16*10/8;
}
else
{
PETP_CLK_CFG_REG = 0x523000; // ECS_PCLK=1G/4=250M
JECS_CRG_CLK_CTRL3 = 0x520000; // STC_PCLK=ECS_PCLK/1=250M
// JECS_CRG_PLLSEL &= (~(1 << 9)); // stc_src_clk_sel2=0
pClk = 250000000; // 100000000;
UCP_PRINT_EMPTY("stc_pclk_init: use soc_crg to generate pclk, 250M. \r\n");
}
return pClk;
}
int32_t gcd_stein(uint32_t x, uint32_t y)
{
if (x < y)
{
int32_t tmp = x;
x = y;
y = tmp;
}
if (0 == (x%y))
{
return y;
}
if ((0 == (x%2)) && (0 == (y%2)))
{
return (2*gcd_stein(x>>1, y>>1));
}
else if ((0 == (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x>>1, y));
}
else if ((0 != (x%2)) && (0 == (y%2)))
{
return (gcd_stein(x, y>>1));
}
else if ((0 != (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x, ((x-y)>>1)));
}
else
{
return 0;
}
}
void stc_timer_init(uint32_t pClk, uint32_t valR)
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0x8
#endif
stc_timer_tod_init(pClk);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
#if 0
stc_pp1s_src_init(STC_PP1S_SRC_GPS); // select gps pp1s as stc ppls input
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(apeId<<2)), flag);
#endif
#endif
stc_timer_para_init(pClk, valR);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer_local_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer0_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer1_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
}
void stc_timer_para_init(uint32_t pClk, uint32_t valR)
{
//int apeId = get_core_id();
uint32_t remain = 0;
uint32_t gcd = 0;
memset(&gStcTimerPara, 0, sizeof(stStcTimerPara));
gStcTimerPara.pClk = pClk;
gStcTimerPara.R = valR;
gStcTimerPara.usR = valR / 1000000;
gStcTimerPara.N1 = valR/pClk;
if (gStcTimerPara.N1 * pClk == valR)
{
gStcTimerPara.N1 -= 1;
}
gStcTimerPara.N = gStcTimerPara.N1 + 1;
remain = valR-gStcTimerPara.N1*pClk;
gcd = gcd_stein(pClk, remain);
if (0 == gcd)
{
UCP_PRINT_EMPTY("gcd error! \r\n");
return;
}
gStcTimerPara.A = remain / gcd;
gStcTimerPara.C = pClk / gcd;
UCP_PRINT_EMPTY("pclk = 0x%x. \r\n", gStcTimerPara.pClk);
UCP_PRINT_EMPTY("R = 0x%x. \r\n", gStcTimerPara.R);
UCP_PRINT_EMPTY("N = 0x%x. \r\n", gStcTimerPara.N);
UCP_PRINT_EMPTY("N1 = 0x%x. \r\n", gStcTimerPara.N1);
UCP_PRINT_EMPTY("A = 0x%x. \r\n", gStcTimerPara.A);
UCP_PRINT_EMPTY("C = 0x%x. \r\n", gStcTimerPara.C);
#if 0 // def PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+24), gStcTimerPara.pClk); // 0x60
debug_write((DBG_DDR_IDX_DRV_BASE+25), gStcTimerPara.N); // 0x64
debug_write((DBG_DDR_IDX_DRV_BASE+26), gStcTimerPara.A); // 0x68
debug_write((DBG_DDR_IDX_DRV_BASE+27), gStcTimerPara.C); // 0x6c
#endif
}
void stc_timer_tod_init(uint32_t pClk)
{
JECS_CRG_STC_RST_CTRL |= BIT24;
stc_tod_para_init(pClk);
//stc_timer_todint_init();
//do_write(STC_TOD_INT_ADDR, 0); // clear tod int flag
}
void stc_pp1s_src_init(uint8_t srcId)
{
// gnss_sel stc_sel cpri_sel
//JECS_CTRL_CPRI_GMAC_PHY_INT = (0x0 << 4) | (0x5 << 7) | (0x6<<10);
JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 7);
JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 7); // select gps pp1s as stc ppls input
}
void stc_timer_local_init()
{
LTBG_REG_R = gStcTimerPara.R;
LTBG_TIME_SET = 0;
LTBG_REG_A = gStcTimerPara.A;
LTBG_REG_C = gStcTimerPara.C;
LTBG_REG_N = gStcTimerPara.N;
LTBG_REG_N1 = gStcTimerPara.N1;
}
void stc_timer0_para_init()
{
LTBG0_REG_R = gStcTimerPara.R;
LTBG0_TIME_SET = 0;
LTBG0_REG_A = gStcTimerPara.A;
LTBG0_REG_C = gStcTimerPara.C;
LTBG0_REG_N = gStcTimerPara.N;
LTBG0_REG_N1 = gStcTimerPara.N1;
}
void stc_timer1_para_init()
{
LTBG1_REG_R = gStcTimerPara.R;
LTBG1_TIME_SET = 0;
LTBG1_REG_A = gStcTimerPara.A;
LTBG1_REG_C = gStcTimerPara.C;
LTBG1_REG_N = gStcTimerPara.N;
LTBG1_REG_N1 = gStcTimerPara.N1;
}
void stc_tod_para_init(uint32_t pClk)
{
//TOD_REG_FT_LO = 0; // 0xB0AAAAAA; // 0x11AAAAAA; //
//TOD_REG_FT_HI = 40; // 40; //4; //
double nsOfClk = 1000000000.0 / pClk;
uint32_t hiOfFt = 1000000000 / pClk;
uint64_t coff = (1ULL<<32);
uint32_t loOfFt = (uint32_t)((double)(nsOfClk - hiOfFt) * coff); // ???
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+5), loOfFt); // 0x8
debug_write((DBG_DDR_IDX_DRV_BASE+6), hiOfFt); // 0xc
#endif
do_write((&TOD_REG_FT_LO), loOfFt);
do_write((&TOD_REG_FT_HI), hiOfFt);
uint32_t loOfRt = 0;
uint32_t hiOfRt = 0;
//#ifdef PALLADIUM_TEST
// hiOfRt = STC_RT_PALLADIUM; // one tod period: 100ms
// do_write(STC_RT_ADDR, STC_RT_PALLADIUM);
//#else
hiOfRt = STC_RT;
do_write(STC_RT_ADDR, STC_RT);
//#endif
UCP_PRINT_EMPTY("RT LO = 0x%x. \r\n", loOfRt);
UCP_PRINT_EMPTY("RT HI = 0x%x. \r\n", hiOfRt);
do_write((&TOD_REG_RT_LO), loOfRt);
do_write((&TOD_REG_RT_HI), hiOfRt);
TOD_REG_CONFIG |= (1<<3); // onepps_output_enable
do_write(STC_ONEPPS_OUT_ADDR, 1);
}
void stc_timer_sync(int32_t nScsId)
{
gStcTimerPara.slotTddNumMax = do_read_volatile_short(&(phyPara[nScsId].slotNumOfTdd));
__ucps2_synch(f_SMR);
gStcTimerPara.slotPointNum = TDD_TMR_POINT_MAX / TDD_SLOT_NUM_MAX; // 500/10=50 // gStcTimerPara.slotTddNumMax;
}
void stc_timer_set_tmrpoint(stStcTimerPoint* pTmrPoint)
{
stc_timer_ctwint_disable();
gStcTimerPara.slotTddNumMax = do_read_volatile_short(&(phyPara[gScsId].slotNumOfTdd));
__ucps2_synch(f_SMR);
gStcTimerPara.slotPointNum = TDD_TMR_POINT_MAX / TDD_SLOT_NUM_MAX; // 500/10=50 // gStcTimerPara.slotTddNumMax;
gStcTimerPara.R = STC_RT;
gStcTimerPara.usR = STC_RT / 1000000;
gStcTimerPara.ctwSetFinished = 0;
gStcTimerPara.ctwStartFlag = 0;
gStcTimerPara.tmrPointTotalNum = 0;
memset(gStcTimerPara.tmrPointNum, 0, TDD_SLOT_NUM_MAX);
memset(gStcTimerPara.tmrPoint, 0, sizeof(stStcTimerPoint)*TDD_SLOT_NUM_MAX);
gStcTimerPara.curSlotNum = 0;
gStcTimerPara.curSlotTmrPointId = 0;
int32_t apeId = get_core_id();
if (NULL == pTmrPoint)
{
UCP_PRINT_ERROR("pTmrPoint NULL! \r\n");
return;
}
UCP_PRINT_LOG("stc timer set tmrpoint start. \r\n");
int32_t idx = 0;
for (int32_t i = 0; i < gStcTimerPara.slotTddNumMax; i++)
{
for (int32_t j = 0; j < gStcTimerPara.slotPointNum; j++)
{
idx = i*gStcTimerPara.slotPointNum+j;
gStcTimerPara.tmrPoint[idx].pointVal = pTmrPoint[idx].pointVal*gStcTimerPara.usR;
gStcTimerPara.tmrPoint[idx].lastFlag = pTmrPoint[idx].lastFlag;
gStcTimerPara.tmrPointNum[i]++;
gStcTimerPara.tmrPointTotalNum++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+5120+(apeId<<10) + (idx<<1)), gStcTimerPara.tmrPoint[idx].pointVal); // 0x5000
debug_write((DBG_DDR_IDX_DRV_BASE+5120+(apeId<<10) + ((idx<<1) + 1)), gStcTimerPara.tmrPoint[idx].lastFlag); // 0x5000
#endif
if (1 == pTmrPoint[idx].lastFlag)
{
break;
}
}
}
if (0 < gStcTimerPara.tmrPointTotalNum)
{
gStcTimerPara.ctwSetFinished = 1;
}
}
int32_t setCnt = 0;
void stc_timer_set_next_ctw(int32_t setFlag)
{
setCnt++;
int32_t apeId = get_core_id();
if (1 == setFlag) // set in the slot int function
{
uint32_t addr = 0;
if (apeId & 0x4)
{
addr = (uint32_t)(&LTBG1_TIME_BASE);
}
else
{
addr = (uint32_t)(&LTBG0_TIME_BASE);
}
gStcTimerPara.ctwVal = do_read_volatile(addr);
}
gStcTimerPara.curSlotTmrPointId++;
int32_t slotNum = gStcTimerPara.curSlotNum;
if (gStcTimerPara.curSlotTmrPointId >= gStcTimerPara.tmrPointNum[slotNum]) //gStcTimerPara.slotPointNum)
{
UCP_PRINT_ERROR("gStcTimerPara.curSlotTmrPointId: 0x%x error. \r\n", gStcTimerPara.curSlotTmrPointId);
}
int32_t idx = slotNum * gStcTimerPara.slotPointNum + gStcTimerPara.curSlotTmrPointId;
#if 0 //def PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+384+(apeId<<6)+(setCnt&0x3F)), idx); // 0x600
debug_write((DBG_DDR_IDX_DRV_BASE+256+(apeId<<6)+(setCnt&0x3F)), gStcTimerPara.tmrPoint[idx].lastFlag); // 0x400
#endif
gStcTimerPara.ctwVal += gStcTimerPara.tmrPoint[idx].pointVal;
if (gStcTimerPara.ctwVal >= STC_RT)
{
gStcTimerPara.ctwVal -= STC_RT;
}
do_write(((uint32_t*)(&CTW_REG_TIMER_0_0) + apeId), gStcTimerPara.ctwVal); // set ctw reg, clear ctw int
#if 0 //def PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+1024 + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId << 9)), gStcTimerPara.ctwVal); // 0x1000
// debug_write((DBG_DDR_IDX_DRV_BASE+6144 + (setCnt&0x1FF) + (apeId << 9)), gStcTimerPara.ctwVal); // 0x6000
#endif
}
void stc_timer_todint_init(void)
{
int32_t apeId = get_core_id();
#ifndef GPS_PP1S_SYNC
TOD_REG_IRQ_EN |= 0x1; // set tod int enable
#endif
uint32_t intNum = APC_STC_INTR8;
// attach interrupt func
int32_t ret = smart_irq_request(intNum, isr_stc_tod_int);
if (0 != ret)
{
UCP_PRINT_ERROR("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
debug_write(DBG_DDR_ERR_IDX(apeId, 8), ret);
}
}
ddr_spinlock_t gSpinLockCtwInit;
void stc_timer_ctwint_init()
{
int32_t apeId = get_core_id();
gSpinLockCtwInit.lock_addr = 0xB7FD1400;
gSpinLockCtwInit.flag_addr = 0xB7FD1404;
//gSpinLockCtwInit.spin_lock_addr = 0xB7FD1408;
//gSpinLockCtwInit.lock_w_addr = 0xB7FD140C;
//gSpinLockCtwInit.lock_loop_addr = 0xB7FD1410;
//gSpinLockCtwInit.unlock_loop_addr = 0xB7FD1410;
//gSpinLockCtwInit.unlock_addr = 0xB7FD1418;
smart_ddr_spin_lock_init(&gSpinLockCtwInit);
uint32_t intNum = APC_STC_INTR0 + apeId;
// attach interrupt func
smart_ddr_spinlock(&gSpinLockCtwInit);
int32_t ret = smart_irq_request(intNum, isr_stc_timer_int);
smart_ddr_spinunlock(&gSpinLockCtwInit);
if (0 != ret)
{
UCP_PRINT_EMPTY("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
debug_write(DBG_DDR_ERR_IDX(apeId, 9), ret);
}
}
void stc_timer_ctwint_enable()
{
int32_t apeId = get_core_id();
do_write(((uint32_t*)(&CTW_REG_IRQ_0_0) + apeId), 0x1); // set ctw irq enable
}
void stc_timer_ctwint_disable()
{
int32_t apeId = get_core_id();
do_write(((uint32_t*)(&CTW_REG_IRQ_0_0) + apeId), 0x0); // set ctw irq disable
}
//uint32_t stcCnt = 0;
//UINT32 gApe0CtwIntCnt = 0;
void isr_stc_timer_int()
{
int32_t apeId = get_core_id();
#if 0 //def PALLADIUM_TEST
gApe0CtwIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+63+apeId), gApe0CtwIntCnt); // 0xfc
#endif
stCoreInt* apeCoreIntInfo = (stCoreInt*)APE_INT_INFO_ADDR + APE_INT_MAXNUM*apeId;
int32_t status = do_read_volatile(&CTW_REG_STATUS);
__ucps2_synch(0);
if (status & (1 << apeId))
{
#if 0 //def PALLADIUM_TEST
uint32_t addr = 0;
if (apeId & 0x4)
{
addr = (uint32_t)(&LTBG1_TIME_BASE);
}
else
{
addr = (uint32_t)(&LTBG0_TIME_BASE);
}
debug_write(((DBG_DDR_IDX_DRV_BASE+2048) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(addr)); // 0x2000
#endif
gStcTimerPara.ctwIntCnt++;
int32_t idx = gStcTimerPara.curSlotNum * gStcTimerPara.slotPointNum + gStcTimerPara.curSlotTmrPointId;
if (1 != gStcTimerPara.tmrPoint[idx].lastFlag)
{
#ifdef PALLADIUM_TEST
// debug_write((DBG_DDR_IDX_DRV_BASE+192+(apeId<<6)+gStcTimerPara.curSlotNum), idx); // 0x300
#endif
stc_timer_set_next_ctw(0);
}
else
{
#ifdef PALLADIUM_TEST
// debug_write((DBG_DDR_IDX_DRV_BASE+224+(apeId<<6)+gStcTimerPara.curSlotNum), idx); // 0x380
#endif
stc_timer_ctwint_disable();
}
// debug_write(((DBG_DDR_IDX_DRV_BASE+10240) + ((gStcTimerPara.ctwIntCnt)&0x1FF) + (apeId<<9)), get_tx_nr_slot(1)); // 0xa000
// debug_write(((DBG_DDR_IDX_DRV_BASE+11264) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(&LTBG_TIME_BASE)); // 0xb000
//osp_timer_call_task(); // start task
osp_timer_call_task_spe(gStcTimerPara.curSlotNum, gStcTimerPara.curSlotTmrPointId);
//debug_write(((DBG_DDR_IDX_DRV_BASE+12288) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(&LTBG_TIME_BASE)); // 0xc000
#ifdef PALLADIUM_TEST
// if (1 < gStcTimerPara.ctwIntCnt)
{
// uint32_t period = GET_STC_CNT() - stcCnt;// GET_CNT_VAL(apeId)-stcCnt;//
// debug_write(((DBG_DDR_IDX_DRV_BASE+3072)+(gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), period); // 0x3000
}
// stcCnt = GET_STC_CNT();// GET_CNT_VAL(apeId); //
debug_write((DBG_DDR_IDX_DRV_BASE+101+(apeId<<1)), gStcTimerPara.ctwIntCnt); // 0x194
// write sm
do_write(&(apeCoreIntInfo[APE_INT_STC].intNum), APE_INT_STC);
do_write(&(apeCoreIntInfo[APE_INT_STC].intCnt), gStcTimerPara.ctwIntCnt);
//debug_write(((DBG_DDR_IDX_DRV_BASE+6144) + (gStcTimerPara.ctwIntCnt&0x1FF) + (apeId<<9)), do_read_volatile(addr)); // 0x6000
#endif
status = do_read_volatile(&CTW_REG_STATUS);
}
}
//extern UINT8 waitTodInt;
//uint32_t gApe0TodIntCnt = 0;
void isr_stc_tod_int()
{
//int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
//gApe0TodIntCnt++;
//debug_write((DBG_DDR_IDX_DRV_BASE+62), gApe0TodIntCnt); // 0xf8
#endif
int32_t status = do_read_volatile(&TOD_REG_INT_STATUS);
__ucps2_synch(0);
if (status & 0x1)
{
do_write((&TOD_REG_INT_STATUS), 0x1);
#if 0 //def PALLADIUM_TEST
uint32_t addr = 0;
if (apeId & 0x4)
{
addr = (uint32_t)(&LTBG1_TIME_BASE);
}
else
{
addr = (uint32_t)(&LTBG0_TIME_BASE);
}
debug_write(((DBG_DDR_IDX_DRV_BASE+4096) + (gStcTimerPara.todIntCnt&0x3FF)), do_read_volatile(addr)); // 0x4000
#endif
#ifndef ENABLE_SFNCAL
if (0 == gStcTimerPara.todIntCnt)
#else
if (1 == do_read_volatile(ARM_LOCK_FLAG_ADDR))
#endif
{
do_write((uint32_t*)(&TOD_REG_RT_LO), 0);
do_write((uint32_t*)(&TOD_REG_RT_HI), STC_RT);
do_write(STC_RT_ADDR, STC_RT);
}
#if 0 //def PALLADIUM_TEST
if (0 < gStcTimerPara.todIntCnt)
{
uint64_t temp = GET_CNT_VAL(apeId) + 0xFFFFFFFF;
uint32_t period = temp - gStcTimerPara.todLastStcCnt;
debug_write(((DBG_DDR_IDX_DRV_BASE+128)+((gStcTimerPara.todIntCnt-1)&0x3F)), period); // 0x200
}
gStcTimerPara.todLastStcCnt = GET_CNT_VAL(apeId);
#endif
gStcTimerPara.todIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64), gStcTimerPara.todIntCnt); // 0x100
#endif
status = do_read_volatile(&TOD_REG_INT_STATUS);
}
}

2
public/ape_spu/top/inc/ape_top.h
View File

@ -20,7 +20,7 @@
ALWAYS_INLINE int32_t get_core_id(void);
void set_core_id(void);
void soc_drv_init(void);
int32_t soc_drv_init(void);
void spu_drv_init(void);
void spu_msg_transfer_init(void);

16
public/ape_spu/top/src/ape_top.s.c
View File

@ -21,6 +21,7 @@
#include "msg_transfer_mem.h"
#include "msg_transfer_queue.h"
#include "pet_sm_mgt.h"
#include "osp_init.h"
static int32_t gCoreId = 0;
ALWAYS_INLINE int32_t get_core_id(void)
@ -44,6 +45,21 @@ void set_core_id(void)
return;
}
int32_t soc_drv_init()
{
int apeId = get_core_id();
if (0 == apeId)
{
pet_sm_init();
osp_var_init();
}
return 0;
}
void spu_drv_init(void)
{
pet_sm_alloc();

42
public/ape_spu/top/src/phy_init.s.c
View File

@ -14,52 +14,10 @@
#include <typedef.h>
#include "ucp_printf.h"
#include "stc_timer.h"
#include "phy_para.h"
#include "ucp_utility.h"
#include "pet_sm_mgt.h"
#include "osp_init.h"
void soc_drv_init(void)
{
int apeId = get_core_id();
if (0 == apeId)
{
pet_sm_init();
osp_var_init();
SET_CLK_CFG_EMU();
UCP_PRINT_EMPTY("sys clock init.\r\n");
//phy_para_init(PROTOCOL_NULL, PROTO_OPTION_NULL);
#ifdef DISTRIBUTED_BS
phy_para_init(PROTOCOL_CPRI, CPRI_OPTION_8);
#endif
#ifdef INTEGRATED_BS
phy_para_init(PROTOCOL_JESD, PROTO_OPTION_NULL);
#endif
UCP_PRINT_EMPTY("phy para init.\r\n");
ape_stc_init();
UCP_PRINT_EMPTY("stc timer init. \r\n");
}
}
void tod_int_init(void)
{
int apeId = get_core_id();
if (0 == apeId)
{
stc_timer_todint_init();
UCP_PRINT_EMPTY("stc tod int init. \r\n");
}
return;
}
#ifdef TEST_ENABLE
void ape_test_task_reg(void);
#endif

43
public/common/driver/inc/ape_csu.h
View File

@ -330,6 +330,49 @@ int32_t ape_csu_dma_2Dto2D_transfer(uint64_t addrSrc, uint16_t blockLenSrc, uint
int32_t ape_csu_dma_3Dto1D_transfer(uint64_t addrSrc, uint16_t xNumSrc, uint16_t yNumSrc, uint64_t yStepSrc, uint64_t zStepSrc,
uint64_t addrDst, uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir);
/*!
* @brief: 一维搬移到三维
* @author: xinxin.li
* @Date: 2023年8月28日
* @param: addrSrc : [源地址 ]
* @param: addrDst : [目的地址 ]
* @param: xNumDst : [目的第一维度搬移字节数 ]
* @param: yNumDst : [目的第二维度搬移个数 ]
* @param: yStepDst : [目的第二维度搬移步进字节数 ]
* @param: zStepDst : [目的第三维度搬移步进字节数 ]
* @param: dataLen : [搬移总字节数 ]
* @param: tag : [DMA Tag: 0~31用于查询是否完成 ]
* @param: isWait : [是否等DMA结束函数返回0:不等待,1:等待 ]
* @param: regGroup : [寄存器组，2：源寄存器组4，目的寄存器组5；3：源寄存器组6，目的寄存器组7 ]
* @param: dir : [0：L2G，1：G2L or G2G ]
*/
int32_t ape_csu_dma_1Dto3D_transfer(uint64_t addrSrc, uint64_t addrDst, uint16_t xNumDst, uint16_t yNumDst, uint64_t yStepDst, uint64_t zStepDst,
uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir);
/*!
* @brief: 三维搬移到三维
* @author: xinxin.li
* @Date: 2023年8月28日
* @param: addrSrc : [源地址 ]
* @param: xNumSrc : [源第一维度搬移字节数 ]
* @param: yNumSrc : [源第二维度搬移个数 ]
* @param: yStepSrc : [源第二维度搬移步进字节数 ]
* @param: zStepSrc : [源第三维度搬移步进字节数 ]
* @param: addrDst : [目的地址 ]
* @param: xNumDst : [目的第一维度搬移字节数 ]
* @param: yNumDst : [目的第二维度搬移个数 ]
* @param: yStepDst : [目的第二维度搬移步进字节数 ]
* @param: zStepDst : [目的第三维度搬移步进字节数 ]
* @param: dataLen : [搬移总字节数 ]
* @param: tag : [DMA Tag: 0~31用于查询是否完成 ]
* @param: isWait : [是否等DMA结束函数返回0:不等待,1:等待 ]
* @param: regGroup : [寄存器组，2：源寄存器组4，目的寄存器组5；3：源寄存器组6，目的寄存器组7 ]
* @param: dir : [0：L2G，1：G2L or G2G ]
*/
int32_t ape_csu_dma_3Dto3D_transfer(uint64_t addrSrc, uint16_t xNumSrc, uint16_t yNumSrc, uint64_t yStepSrc, uint64_t zStepSrc,
uint64_t addrDst, uint16_t xNumDst, uint16_t yNumDst, uint64_t yStepDst, uint64_t zStepDst,
uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir);
void ape_csu_dma_3Dto1D_G2L_ch4ch0_simp_transfer(uint32_t addrSrc, uint16_t xNumSrc, uint16_t yNumSrc, uint32_t yStepSrc, uint32_t zStepSrc,
uint32_t addrDst, uint32_t dataLen, uint8_t tag, uint8_t isWait);

33
public/common/driver/inc/mtimer_com.h
View File

@ -15,7 +15,6 @@
#define CPRI_RX_SERDES_DELAY 74 // serdes datasheet, table5-3
typedef enum _tagMTmrIntID
{
MTMR_INT_SLOT_OFFSET = 0,
@ -60,17 +59,28 @@ typedef enum _tagMTmrTID
MTMR_CSU_INSERT = 24,
MTMR_TDD_OFFSET_10000 = 25,
#ifdef DISTRIBUTED_BS
MTMR_TDD_OFFSET_2500 = 26,
MTMR_TDD_OFFSET_7500 = 27,
#endif
#ifdef INTEGRATED_BS
MTMR_JESD_RXON = 26,
MTMR_JESD_RXOFF = 27,
#endif
MTMR_TDD_OFFSET_2500 = 26, // also as MTMR_JESD_RXON = 26,
MTMR_TDD_OFFSET_7500 = 27, // also as MTMR_JESD_RXOFF = 27,
MTMR_JESD_TXOFF = 28,
MTMR_JESD_TXON = 29,
MTMR_LTE_FAPI = 30,
MTMR_ECPRI_TX_SYMBOL0 = 32,
MTMR_ECPRI_TX_SYMBOL1 = 33,
MTMR_ECPRI_TX_SYMBOL2 = 34,
MTMR_ECPRI_TX_SYMBOL3 = 35,
MTMR_ECPRI_TX_SYMBOL4 = 36,
MTMR_ECPRI_TX_SYMBOL5 = 37,
MTMR_ECPRI_TX_SYMBOL6 = 38,
MTMR_ECPRI_TX_SYMBOL7 = 39,
MTMR_ECPRI_TX_SYMBOL8 = 40,
MTMR_ECPRI_TX_SYMBOL9 = 41,
MTMR_ECPRI_TX_SYMBOL10 = 42,
MTMR_ECPRI_TX_SYMBOL11 = 43,
MTMR_ECPRI_TX_SYMBOL12 = 44,
MTMR_ECPRI_TX_SYMBOL13 = 45
}MTmrTID;
typedef enum _tagMTmrCID
@ -122,6 +132,7 @@ typedef struct _tagMtimerPara{
uint32_t tddPeriod; // tdd period, us as unit
uint32_t tddSlotNum; // slot num of every tdd period
uint32_t slotMaxNum;
uint32_t symbolMaxNum;
}stMtimerPara;
typedef struct _tagMtimerIntStat{
@ -138,11 +149,15 @@ typedef struct _tagMtimerIntStat{
uint32_t csuEnCnt;
uint32_t txSlotIntCnt;
uint32_t rxSlotIntCnt;
uint32_t txSymbolIntCnt;
// int flag
uint32_t sfnOffsetIntFlag;
}stMtimerIntStat;
typedef struct _tagMtimerPhyPara{
// symbolÏà¹Ø
uint32_t symbolMaxNum;
uint32_t txSymbolNum;
// ÎïÀí²ãʱ϶Ïà¹Ø
uint32_t slotMaxNum;
uint32_t slotNumPP1s;

77
public/common/driver/inc/phy_para.h
View File

@ -5,6 +5,7 @@
#define PHY_SCS_MAX_NUM 4
#define SFN_PERIOD 10000 // 10ms
#define SLOT_SYMBOL_NUM 14
#define SPU_DRV_SM_ADDR (0x0A4D7000)
@ -73,19 +74,15 @@
//#define INTEGRATION_BS
//#define GPS_PP1S_SYNC
#define GPS_LTE_OFFSET 0 //700 // us
#define GPS_NR_OFFSET 0 //2700 // us
#define LTE_NR_OFFSET 0 //2000 // us
#define GPS_LTE_OFFSET 0 // 700 // us
#define GPS_NR_OFFSET 0 // 2700 // us
#define LTE_NR_OFFSET 0 // 2000 // us
#define SCS_MAX_NUM 2
#ifdef DISTRIBUTED_BS
#define MTIMER_MAX_NUM 2
#endif
#ifdef INTEGRATED_BS
#define MTIMER_MAX_NUM 4
#endif
#define MTIMER_INTEGRATED_MAX_NUM 4
#define MTIMER_DISTRIBUTED_MAX_NUM 2
typedef enum _tagScsId
{
SCS_1st_MTIMER_ID = 0,
@ -119,7 +116,8 @@ typedef enum _tagAPEIntInfoId
typedef enum _tagCtcIntType
{
CTC_INT_TYPE_NULL = 0,
CTC_INT_TYPE_CAL = 1
CTC_INT_TYPE_CAL_SCS0 = 1,
CTC_INT_TYPE_CAL_SCS1 = 2,
}numCtcIntType;
typedef enum _tagProtocolID
@ -137,13 +135,13 @@ typedef enum _tagCpriOptionID
CPRI_OPTION_8 = 8,
CPRI_OPTION_9 = 9,
CPRI_OPTION_10 = 10
}cpriOptID;
}CpriOptID;
typedef enum _tagEcpriOptionID
{
ECPRI_OPTION_10G = 1,
ECPRI_OPTION_25G = 2
}ecpriOptID;
ECPRI_OPTION_10G = 10,
ECPRI_OPTION_25G = 25
}EcpriOptID;
typedef enum _tagScsID
{
@ -189,24 +187,7 @@ typedef struct _tagPhyScsPara
// UINT64 rxSlotStcCnt;
// UINT64 txSlotStcCnt;
}stPhyScsPara;
#if 0
typedef struct phy_timer_config_ind_t
{
uint32_t scsId;
uint32_t runCoreId; // 此次需要建小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。
uint16_t bandWidth; //带宽:5M,10M,15M,20M,25M,30M,40M,50M,60M,80M,100M
uint16_t t_period; //timer周期=t_us*num_t, 500us, 625us, 1000us, 1250us, 2500us, 5000us, 10000us, 20000us
uint16_t t_us; //物理层时隙定时长度, 125us, 250us, 500us, 1000us
uint8_t num_t; //timer周期内时隙的个数5,10,20,40,80
uint8_t num_t_per_sfn; //一个SFN内的时隙个数
uint8_t num_t_dl; //下行时隙个数
uint8_t num_t_dl_symb; //时隙内下行符号个数
uint8_t num_t_ul_symb; //时隙内上行符号个数
uint8_t num_ants; //天线个数
}phy_timer_config_ind_t;
#else
typedef struct phy_timer_config_ind_t
{
uint32_t frameType; //0:FDD, 1:TDD, 2:TDD(双周期DDDSUDDSUU)
@ -226,7 +207,6 @@ typedef struct phy_timer_config_ind_t
uint8_t num_t_ul_symb[2]; //S时隙内上行符号个数
uint8_t num_ants[2]; //天线个数
}phy_timer_config_ind_t;
#endif
typedef struct _tagPhyDelCell
{
@ -249,14 +229,31 @@ typedef struct _tagSfnPara
uint32_t slotMaxNum;
uint32_t ctcIntFlag;
uint32_t txSlotNum;
uint32_t rxSlotNum;
uint32_t txSfnNum;
uint32_t rxSfnNum;
uint32_t txSlotIntCnt;
uint32_t rxSlotIntCnt;
uint64_t txSlotTiming;
uint64_t rxSlotTiming;
uint32_t rxSlotNum;
uint32_t txSfnNum;
uint32_t rxSfnNum;
uint32_t symbolMaxNum;
uint32_t txSymbolNum;
uint32_t txSlotIntCnt;
uint32_t rxSlotIntCnt;
uint32_t txSymbolIntCnt;
uint64_t txSlotTiming;
uint64_t rxSlotTiming;
}stSfnPara;
typedef enum _tagCpriMapType
{
NR4T4R_7DS2U = 0,
NR4T4R_LTE2T2R_FDD,
NR2_4T4R_7DS2U
}CpriMapType;
typedef enum _tagCpriMode
{
NR_MODE = 0,
LTE_MODE
}CpriMode;
void sfn_para_init(void);

2
public/ape_spu/driver/inc/stc_timer.h → public/common/driver/inc/stc_timer.h
View File

@ -56,7 +56,7 @@ typedef enum _tagStcPP1sSrc{
STC_PP1S_SRC_GPS = 5
}numStcPP1sSrc;
void ape_stc_init();
void rfm_stc_init();
uint32_t stc_pclk_init();

170
public/common/driver/src/ape_csu.s.c
View File

@ -447,6 +447,176 @@ int32_t ape_csu_dma_3Dto1D_transfer(uint64_t addrSrc, uint16_t xNumSrc, uint16_t
return 0;
}
/*!
* @brief: 一维搬移到三维
* @author: xinxin.li
* @Date: 2023年8月28日
* @param: addrSrc : [源地址 ]
* @param: addrDst : [目的地址 ]
* @param: xNumDst : [目的第一维度搬移字节数 ]
* @param: yNumDst : [目的第二维度搬移个数 ]
* @param: yStepDst : [目的第二维度搬移步进字节数 ]
* @param: zStepDst : [目的第三维度搬移步进字节数 ]
* @param: dataLen : [搬移总字节数 ]
* @param: tag : [DMA Tag: 0~31用于查询是否完成 ]
* @param: isWait : [是否等DMA结束函数返回0:不等待,1:等待 ]
* @param: regGroup : [寄存器组，2：源寄存器组4，目的寄存器组5；3：源寄存器组6，目的寄存器组7 ]
* @param: dir : [0：L2G，1：G2L or G2G ]
*/
int32_t ape_csu_dma_1Dto3D_transfer(uint64_t addrSrc, uint64_t addrDst, uint16_t xNumDst, uint16_t yNumDst, uint64_t yStepDst, uint64_t zStepDst,
uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir)
{
if ((DMA_REG_GROUP2 > regGroup) || (DMA_REG_GROUP3 < regGroup))
{
return -1;
}
if ((0 != dir) && (1 != dir))
{
return -1;
}
uint8_t apeId = get_core_id();
uint8_t fifoId = (8 <= apeId) ? (0) : (apeId & 0x1);
apeId = apeId & 0x1;
// src
uint32_t offset_w = (apeId<<3) + (regGroup<<1);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRL0) + offset_w), addrSrc & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRH0) + offset_w), (uint32_t)(addrSrc >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPL0) + offset_w), 256);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPH0) + offset_w), 0);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPL0) + offset_w), 1024);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPH0) + offset_w), 0);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYNUMXNUM0) + offset_w), (4<<16)|256);
if (0 == dir) // L2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), (0xE<<24) | dataLen);
}
else // G2L or G2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), (0xF<<28) | dataLen);
}
// dst
offset_w = (apeId<<3) + (regGroup<<1) + 1;
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRL0) + offset_w), addrDst & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRH0) + offset_w), (uint32_t)(addrDst >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPL0) + offset_w), yStepDst & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPH0) + offset_w), (uint32_t)(yStepDst >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPL0) + offset_w), zStepDst & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPH0) + offset_w), (uint32_t)(zStepDst >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYNUMXNUM0) + offset_w), (yNumDst<<16)|xNumDst);
if (0 == dir) // L2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), dataLen);
}
else // G2L or G2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), (0xE<<24) | dataLen);
}
stCsuDmaCmdL dmaCmdL;
*((uint32_t *)(&dmaCmdL)) = 0;
dmaCmdL.dmaType = 1;
dmaCmdL.idSrc = (regGroup<<1) + (apeId<<3);
dmaCmdL.idDst = (regGroup<<1)+1 + (apeId<<3);
dmaCmdL.dmaTag = tag;
do_write(((stCsuDmaCmdL*)(&APC_CSU_CMDFIFO0) + (fifoId<<1) + dir), (*(uint32_t*)(&dmaCmdL)));
if(1 == isWait)
{
while (0 == (do_read_volatile((uint32_t*)(&APC_CSU_DMASTATUS)) & (1 << tag)));
}
return 0;
}
/*!
* @brief: 三维搬移到三维
* @author: xinxin.li
* @Date: 2023年8月28日
* @param: addrSrc : [源地址 ]
* @param: xNumSrc : [源第一维度搬移字节数 ]
* @param: yNumSrc : [源第二维度搬移个数 ]
* @param: yStepSrc : [源第二维度搬移步进字节数 ]
* @param: zStepSrc : [源第三维度搬移步进字节数 ]
* @param: addrDst : [目的地址 ]
* @param: xNumDst : [目的第一维度搬移字节数 ]
* @param: yNumDst : [目的第二维度搬移个数 ]
* @param: yStepDst : [目的第二维度搬移步进字节数 ]
* @param: zStepDst : [目的第三维度搬移步进字节数 ]
* @param: dataLen : [搬移总字节数 ]
* @param: tag : [DMA Tag: 0~31用于查询是否完成 ]
* @param: isWait : [是否等DMA结束函数返回0:不等待,1:等待 ]
* @param: regGroup : [寄存器组，2：源寄存器组4，目的寄存器组5；3：源寄存器组6，目的寄存器组7 ]
* @param: dir : [0：L2G，1：G2L or G2G ]
*/
int32_t ape_csu_dma_3Dto3D_transfer(uint64_t addrSrc, uint16_t xNumSrc, uint16_t yNumSrc, uint64_t yStepSrc, uint64_t zStepSrc,
uint64_t addrDst, uint16_t xNumDst, uint16_t yNumDst, uint64_t yStepDst, uint64_t zStepDst,
uint32_t dataLen, uint8_t tag, uint8_t isWait, uint8_t regGroup, uint8_t dir)
{
if ((DMA_REG_GROUP2 > regGroup) || (DMA_REG_GROUP3 < regGroup))
{
return -1;
}
if ((0 != dir) && (1 != dir))
{
return -1;
}
uint8_t apeId = get_core_id();
uint8_t fifoId = (8 <= apeId) ? (0) : (apeId & 0x1);
apeId = apeId & 0x1;
// src
uint32_t offset_w = (apeId<<3) + (regGroup<<1);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRL0) + offset_w), addrSrc & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRH0) + offset_w), (uint32_t)(addrSrc >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPL0) + offset_w), yStepSrc & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPH0) + offset_w), (uint32_t)(yStepSrc >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPL0) + offset_w), zStepSrc & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPH0) + offset_w), (uint32_t)(zStepSrc >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYNUMXNUM0) + offset_w), (yNumSrc<<16)|xNumSrc);
if (0 == dir) // L2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), (0xE<<24) | dataLen);
}
else // G2L or G2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), (0xF<<28) | dataLen);
}
// dst
offset_w = (apeId<<3) + (regGroup<<1) + 1;
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRL0) + offset_w), addrDst & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAADDRH0) + offset_w), (uint32_t)(addrDst >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPL0) + offset_w), yStepDst & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYSTEPH0) + offset_w), (uint32_t)(yStepDst >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPL0) + offset_w), zStepDst & 0xFFFFFFFF);
do_write(((stCsuDmaReg*)(&APC_CSU_DMAZSTEPH0) + offset_w), (uint32_t)(zStepDst >> 32));
do_write(((stCsuDmaReg*)(&APC_CSU_DMAYNUMXNUM0) + offset_w), (yNumDst<<16)|xNumDst);
if (0 == dir) // L2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), dataLen);
}
else // G2L or G2G
{
do_write(((stCsuDmaReg*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), (0xE<<24) | dataLen);
}
stCsuDmaCmdL dmaCmdL;
*((uint32_t *)(&dmaCmdL)) = 0;
dmaCmdL.dmaType = 1;
dmaCmdL.idSrc = (regGroup<<1) + (apeId<<3);
dmaCmdL.idDst = (regGroup<<1)+1 + (apeId<<3);
dmaCmdL.dmaTag = tag;
do_write(((stCsuDmaCmdL*)(&APC_CSU_CMDFIFO0) + (fifoId<<1) + dir), (*(uint32_t*)(&dmaCmdL)));
if(1 == isWait)
{
while (0 == (do_read_volatile((uint32_t*)(&APC_CSU_DMASTATUS)) & (1 << tag)));
}
return 0;
}
//pucch freq data copy from sm to dm
/*!
* @brief: 三维外部搬移到一维内部，外部地址不超过32位，寄存器组源用4目的用0

6
public/common/driver/src/ctc_intr.s.c
View File

@ -28,7 +28,7 @@ int32_t ctc_cal_intr_init(void)
{
do_write(CTC_INT_TYPE_ADDR, CTC_INT_TYPE_NULL);
}
else if ((0 <= apeId) && (7 >= apeId))
else if (((0 <= apeId) && (7 >= apeId)) || (10 == apeId))
{
gSpinLockCtcInit.lock_addr = 0xB7FD1420;
gSpinLockCtcInit.flag_addr = 0xB7FD1424;
@ -71,10 +71,10 @@ void isr_ctc_cal(void)
debug_write((DBG_DDR_IDX_DRV_BASE+524+apeId), GET_STC_CNT()); // 0x830
int32_t type = do_read_volatile(CTC_INT_TYPE_ADDR);
if (CTC_INT_TYPE_CAL == type)
if ((CTC_INT_TYPE_CAL_SCS0 == type) || (CTC_INT_TYPE_CAL_SCS1 == type))
{
do_write(((uint32_t*)(&SYSC_CTC28_REG)+apeId), 0); // clear int
gCellSfnPara[gMtimerId].ctcIntFlag = 1;
gCellSfnPara[type-1].ctcIntFlag = 1;
#if 0
int32_t scsId = gCellSfnPara[gMtimerId].scsId;
gCellSfnPara[gMtimerId].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));

26
public/common/driver/src/phy_para.s.c
View File

@ -9,24 +9,18 @@ uint32_t* pProtoSel = (uint32_t*)PROTO_SEL_ADDR;
uint32_t* pProtoOpt = (uint32_t*)PROTO_OPT_ADDR;
stPhyScsPara* phyPara = (stPhyScsPara*)PHY_PARA_ADDR;
stSfnPara gCellSfnPara[2]; // cell para
uint32_t gScsId = 0;
uint32_t gMtimerId = 0;
uint32_t* gCpriCsuStopCmd = (uint32_t*)CSU_STOP_CMD_ADDR;
uint32_t gScsId = 0;
uint32_t gMtimerId = 0;
uint32_t* gCpriCsuStopCmd = (uint32_t*)CSU_STOP_CMD_ADDR;
void sfn_para_init(void)
{
gScsId = SCS_NULL;
memset(&gCellSfnPara[0], 0, sizeof(stSfnPara) * 2);
#ifdef DISTRIBUTED_BS
gMtimerId = MTIMER_CPRI_ID; // protecting overflow
gCellSfnPara[MTIMER_CPRI_ID].scsId = SCS_NULL;
gCellSfnPara[MTIMER_ECPRI_ID].scsId = SCS_NULL;
#endif
#ifdef INTEGRATED_BS
gMtimerId = MTIMER_JESD_RX0_ID; // protecting overflow
gCellSfnPara[MTIMER_JESD_RX0_ID].scsId = SCS_NULL;
gCellSfnPara[MTIMER_JESD_RX1_ID].scsId = SCS_NULL;
#endif
//gScsId = SCS_NULL;
memset(&gCellSfnPara[0], 0, sizeof(stSfnPara) * SCS_MAX_NUM);
//gMtimerId = SCS_1st_MTIMER_ID; // protecting overflow
gCellSfnPara[SCS_1st_MTIMER_ID].scsId = SCS_NULL;
gCellSfnPara[SCS_2nd_MTIMER_ID].scsId = SCS_NULL;
}
void phy_para_init(int32_t protocol, int32_t option)
@ -34,7 +28,7 @@ void phy_para_init(int32_t protocol, int32_t option)
int32_t i = 0;
memset_ext((void*)PROTO_SEL_ADDR, 0, 0x1000); // init sm for drv, 0x0a4d7000~0x0a4d7FFF
__ucps2_synch(0);
__ucps2_synch(0);
do_write(PROTO_SEL_ADDR, protocol);
do_write(PROTO_OPT_ADDR, option);

11
public/common/ecs_dm/inc/cpri_delay.h
View File

@ -132,15 +132,14 @@ typedef struct _tagCpriSetDelayRsp
uint8_t u8rsv[2];
}stCpriSetDelayRsp;
typedef struct _tagOamMsgTransferHeader {
uint8_t numMsg;
typedef struct _tagOamMsgTransferHeader {
uint8_t numMsg;
uint8_t cellIndex;
uint16_t rsv;
uint32_t msgType;
uint32_t msgType;
uint32_t msgLen;
uint32_t msgData[0];
} stOamMsgTransferHeader;
uint32_t msgData[0];
} stOamMsgTransferHeader;
void cpri_delay_init();

15
public/common/ecs_dm/inc/ecs_rfm_dm_mgt.h
View File

@ -23,18 +23,15 @@
#include "gpio_drv.h"
typedef struct tEcsRfmDmLocalMgt {
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
stCpriPara* pCpriPara;
stCpriDelayMeasure* pCpriDelay;
#endif
#ifdef INTEGRATED_BS
#endif
//#endif
stGpioOnBoard* pGpioInfo;
stFhAlarmStat* pAlarmStatus;
stMtimerPara* pMtimerPara[MTIMER_MAX_NUM];
stMtimerPara* pMtimerPara[MTIMER_INTEGRATED_MAX_NUM];
stOamMsgTransferHeader* pOamMsgPtr;
stCpriSetLinkDelay* pOamBaseDelaySetRspPtr ;
stCpriGetLinkDelay* pOamBaseDelayQryRspPtr ;
@ -43,7 +40,7 @@ typedef struct tEcsRfmDmLocalMgt {
EcsRfmDmLocalMgt_t* get_ecs_rfm_dm_local_mgt(void);
void ecs_rfm_dm_alloc(void);
int32_t ecs_rfm_dm_alloc(void);
#endif

13
public/common/ecs_dm/inc/hw_cpri.h
View File

@ -18,13 +18,6 @@
#include "typedef.h"
//#define CPRI_NOTIMING_TEST
//#define CPRI_TIMING_TEST
#define CPRI_TIMING_7D2U_TEST
//#define CPRI_TIMING_LTE_FDD_TEST
#define CPRI_10G_TEST
//#define CPRI_24G_TEST
typedef struct _tagCpriPara
{
uint32_t option_num;
@ -68,7 +61,9 @@ typedef struct _tagCpriIntStat
//uint32_t gScrRxRfpValH;
}stCpriIntStat;
void cpri_init(uint32_t option);
void cpri_init(uint32_t option,uint32_t MappingMode);
void cpri_ecprimode_init();
// cpri参数初始化
void cpri_para_init(uint32_t option);
@ -78,6 +73,8 @@ void cpri_int_init(void);
void isr_cpri_int(void);
void isr_gmac_int(void);
void HeaderTxRam_init();
#endif

86
public/common/ecs_dm/src/ecs_rfm_dm_mgt.s.c
View File

@ -22,35 +22,71 @@ EcsRfmDmLocalMgt_t* get_ecs_rfm_dm_local_mgt(void)
return (EcsRfmDmLocalMgt_t *)&gEcsRfmDmLocalMgt;
}
void ecs_rfm_dm_alloc(void)
int32_t ecs_rfm_dm_alloc(void)
{
//int32_t core_id = get_core_id();
//UCP_PRINT_LOG("ecs_rfm_spu[%d] start allocating dm.",core_id);
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
MEM_SECTION_INFO* pMemSection = GetRfmDm1Section();
#ifdef DISTRIBUTED_BS
pEcsDmLocalMgt->pCpriPara = (stCpriPara*)memSectionAlloc(pMemSection, sizeof(stCpriPara), MEM_ALIGNED_4BYTES, "pCpriPara");
pEcsDmLocalMgt->pCpriDelay = (stCpriDelayMeasure*)memSectionAlloc(pMemSection, sizeof(stCpriDelayMeasure), MEM_ALIGNED_4BYTES, "pCpriDelay");
#endif
#ifdef INTEGRATED_BS
//pEcsDmLocalMgt->pJesdGpioInfo = (stGpioJesd*)memSectionAlloc();
#endif
//stGpioOnBoard* pGpioInfo = (stGpioOnBoard*)0x0A4D7400;
pEcsDmLocalMgt->pGpioInfo = (stGpioOnBoard*)memSectionAlloc(pMemSection, sizeof(stGpioOnBoard), MEM_ALIGNED_4BYTES, "pGpioInfo"); // (stGpioOnBoard*)0x0A4D7400;
pEcsDmLocalMgt->pAlarmStatus = (stFhAlarmStat*)memSectionAlloc(pMemSection, sizeof(stFhAlarmStat), MEM_ALIGNED_4BYTES, "pAlarmStatus");
pEcsDmLocalMgt->pOamMsgPtr = (stOamMsgTransferHeader*)memSectionAlloc(pMemSection, sizeof(stOamMsgTransferHeader), MEM_ALIGNED_4BYTES, "pOamMsg");
pEcsDmLocalMgt->pOamBaseDelaySetRspPtr = (stCpriSetLinkDelay*)memSectionAlloc(pMemSection, sizeof(stCpriSetLinkDelay), MEM_ALIGNED_4BYTES, "pOamBaseDelaySetRsp");
pEcsDmLocalMgt->pOamBaseDelayQryRspPtr = (stCpriGetLinkDelay*)memSectionAlloc(pMemSection, sizeof(stCpriGetLinkDelay), MEM_ALIGNED_4BYTES, "pOamBaseDelayQryRsp");
pEcsDmLocalMgt->pOamFiberDelayQryRspPtr = (stCpriGetRndDelay*)memSectionAlloc(pMemSection, sizeof(stCpriGetRndDelay), MEM_ALIGNED_4BYTES, "OamFiberDelayQryRsp");
for (int i = 0; i < MTIMER_MAX_NUM; i++)
if (NULL == pEcsDmLocalMgt)
{
pEcsDmLocalMgt->pMtimerPara[i] = (stMtimerPara*)memSectionAlloc(pMemSection, sizeof(stMtimerPara), MEM_ALIGNED_4BYTES, "pMtimerPara[i]");
return -1;
}
MEM_SECTION_INFO* pMemSection = GetRfmDm1Section();
if (NULL == pMemSection)
{
return -1;
}
return;
pEcsDmLocalMgt->pCpriPara = (stCpriPara*)memSectionAlloc(pMemSection, sizeof(stCpriPara), MEM_ALIGNED_4BYTES, "pCpriPara");
if (NULL == pEcsDmLocalMgt->pCpriPara)
{
return -1;
}
pEcsDmLocalMgt->pCpriDelay = (stCpriDelayMeasure*)memSectionAlloc(pMemSection, sizeof(stCpriDelayMeasure), MEM_ALIGNED_4BYTES, "pCpriDelay");
if (NULL == pEcsDmLocalMgt->pCpriDelay)
{
return -1;
}
//stGpioOnBoard* pGpioInfo = (stGpioOnBoard*)0x0A4D7400;
pEcsDmLocalMgt->pGpioInfo = (stGpioOnBoard*)memSectionAlloc(pMemSection, sizeof(stGpioOnBoard), MEM_ALIGNED_4BYTES, "pGpioInfo"); // (stGpioOnBoard*)0x0A4D7400;
if (NULL == pEcsDmLocalMgt->pGpioInfo)
{
return -1;
}
pEcsDmLocalMgt->pAlarmStatus = (stFhAlarmStat*)memSectionAlloc(pMemSection, sizeof(stFhAlarmStat), MEM_ALIGNED_4BYTES, "pAlarmStatus");
if (NULL == pEcsDmLocalMgt->pAlarmStatus)
{
return -1;
}
pEcsDmLocalMgt->pOamMsgPtr = (stOamMsgTransferHeader*)memSectionAlloc(pMemSection, sizeof(stOamMsgTransferHeader), MEM_ALIGNED_4BYTES, "pOamMsg");
if (NULL == pEcsDmLocalMgt->pOamMsgPtr)
{
return -1;
}
pEcsDmLocalMgt->pOamBaseDelaySetRspPtr = (stCpriSetLinkDelay*)memSectionAlloc(pMemSection, sizeof(stCpriSetLinkDelay), MEM_ALIGNED_4BYTES, "pOamBaseDelaySetRsp");
if (NULL == pEcsDmLocalMgt->pOamBaseDelaySetRspPtr)
{
return -1;
}
pEcsDmLocalMgt->pOamBaseDelayQryRspPtr = (stCpriGetLinkDelay*)memSectionAlloc(pMemSection, sizeof(stCpriGetLinkDelay), MEM_ALIGNED_4BYTES, "pOamBaseDelayQryRsp");
if (NULL == pEcsDmLocalMgt->pOamBaseDelayQryRspPtr)
{
return -1;
}
pEcsDmLocalMgt->pOamFiberDelayQryRspPtr = (stCpriGetRndDelay*)memSectionAlloc(pMemSection, sizeof(stCpriGetRndDelay), MEM_ALIGNED_4BYTES, "OamFiberDelayQryRsp");
if (NULL == pEcsDmLocalMgt->pOamFiberDelayQryRspPtr)
{
return -1;
}
for (int i = 0; i < MTIMER_INTEGRATED_MAX_NUM; i++)
{
pEcsDmLocalMgt->pMtimerPara[i] = (stMtimerPara*)memSectionAlloc(pMemSection, sizeof(stMtimerPara), MEM_ALIGNED_4BYTES, "pMtimerPara[i]");
if (NULL == pEcsDmLocalMgt->pMtimerPara[i])
{
return -1;
}
}
return 0;
}

25
public/common/handshake/src/ucp_handshake.s.c
View File

@ -68,8 +68,29 @@ void handshake_response_to_host(int32_t core_id)
UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x],value[0x%08x].",core_id,response);
return;
}
//msgagent is the core which agented msg_transfer_init,PET_RFM_SPU1_CORE_ID
void handshake_response_to_msgagent(int32_t core_id)
{
volatile uint32_t request = 0;
volatile uint32_t response = core_id + HANDSHKAE_RESP_VALUE;
UcpHandshake_t* pHandshake = (UcpHandshake_t *)get_handshake_info();
while(1) {
request = do_read_volatile(&pHandshake->request[core_id]);
if (request == (core_id + HANDSHKAE_REQ_VALUE)) {
UCP_PRINT_EMPTY("Recieved handshake request message from core[0x%08x],value[0x%08x].",core_id,request);
do_write(&pHandshake->response[core_id], response);
UCP_PRINT_EMPTY("Sent handshake response message to core[0x%08x],value[0x%08x].",core_id,response);
break;
}
}
return;
}
//master is the core which controlled the handshake flow
#if 0
void handshake_with_host(void)
@ -96,6 +117,9 @@ void handshake_master_with_slave(void)
coreReadyBitMap = 1 << core_id;
debug_write(DBG_DDR_COMMON_IDX(core_id,90), handshake_coremask);
//msgagent need to run before other cores.
handshake_response_to_msgagent(PET_RFM_SPU1_CORE_ID);
while(1) {
for(uint32_t i = 0; i < MAX_NUM_SPU; i++) {
coreMask = (handshake_coremask >> i) & 0x1;
@ -144,4 +168,3 @@ void handshake_slave_with_master(void)
}

16
public/common/msg/src/msg_transfer_layer.s.c
View File

@ -150,10 +150,10 @@ int32_t msg_transfer_alloc_msg(int32_t handle_id, uint16_t cu_flag, uint32_t buf
UCP_PRINT_LOG("msg_transfer_alloc_msg,buf:0x%08x,availableSize:0x%08x,offset:0x%08x", *(uint32_t *)buf, ch->availableSize, ch->offset);
#else
int32_t availableLength = ch->bufSize - MSG_MBUF_HEAD_SIZE;
if(0 >= availableLength) {
return UNINITIALIZED_QUEUE;
}
if(0 >= availableLength) {
return UNINITIALIZED_QUEUE;
}
*availableSize = availableLength;
if (bufSize > availableLength) {
UCP_PRINT_ERROR("msg_transfer_alloc_msg,OUT_OF_BLOCK_MEMORY");
@ -161,9 +161,9 @@ int32_t msg_transfer_alloc_msg(int32_t handle_id, uint16_t cu_flag, uint32_t buf
}
msg_buf = msg_queue_ul_alloc_buf(inst_id,que_id,&buf_id);
if(NULL == msg_buf){
return UNINITIALIZED_QUEUE;
}
if(NULL == msg_buf){
return UNINITIALIZED_QUEUE;
}
*(uint32_t *)buf = (uint32_t)msg_buf;
*offset = buf_id;//redefine offset to buf_id
#endif
@ -208,7 +208,7 @@ int32_t msg_transfer_send_msg(int32_t handle_id, uint16_t cu_flag, uint8_t* msg_
MsgMemBufAttr_t *mbuf = (MsgMemBufAttr_t *)get_mbuf_ptr(ch->bufBase, ch->bufSize, idx);
do_write(&mbuf->msgSize, msg_len);
__ucps2_synch(0);
uint32_t value = (inst_id << 24) + (que_id << 16) + idx;
int32_t ret = ecs_hw_que_send(ECS_RFM_SPU0_HW_QUEUE, value);
#endif

100
public/common/platform/inc/spu_hw_queue.h
View File

@ -1,63 +1,63 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : spu_hw_queue.h
// Author : lishuang.xie
// Created On : 2023-02-06
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : spu_hw_queue.h
// Author : lishuang.xie
// Created On : 2023-02-06
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#ifndef __SPU_HW_QUEUE_H__
#ifndef __SPU_HW_QUEUE_H__
#define __SPU_HW_QUEUE_H__
#include "typedef.h"
#include "ucp_utility.h"
#define ECS_RFM_SPU0_HW_QUEUE (14)//(6)
#define ECS_RFM_SPU0_HW_QUEUE (14)//(6)
#define ECS_RFM_SPU1_HW_QUEUE (15)//(7)
/* message head */
typedef struct ECS_MSG_HEAD
{
uint32_t msg_size; /* message size */
uint8_t msg_type; /* message type */
uint8_t msg_type_oam;/* padding */
uint8_t msg_padding[2];
uint8_t src_core_id; /* src core ID */
uint8_t dst_core_id; /* dst core ID */
uint8_t src_task_id; /* src task ID */
uint8_t dst_task_id; /* dst task ID */
uint8_t data[0];
}ecs_msg_head;
#define ECS_MSG_HEAD_LEN sizeof(ecs_msg_head)
/* calback function type */
typedef void(*ECS_HWQUE_IRQ_FUNC)();
typedef struct ECS_HW_QUE_INFO_withirq
{
int32_t ecs_hq_id;
int32_t ecs_hq_vector;
ECS_HWQUE_IRQ_FUNC irq_entry;
}ecs_hw_que_info_withirq_t;
typedef struct ECS_HW_QUE_INFO_NOIRQ
{
int32_t ecs_hq_id;
int32_t ecs_hq_vector;
}ecs_hw_que_info_noirq_t;
/* message head */
typedef struct ECS_MSG_HEAD
{
uint32_t msg_size; /* message size */
uint8_t msg_type; /* message type */
uint8_t msg_type_oam;/* padding */
uint8_t msg_padding[2];
uint8_t src_core_id; /* src core ID */
uint8_t dst_core_id; /* dst core ID */
uint8_t src_task_id; /* src task ID */
uint8_t dst_task_id; /* dst task ID */
uint8_t data[0];
}ecs_msg_head;
#define ECS_MSG_HEAD_LEN sizeof(ecs_msg_head)
/* calback function type */
typedef void(*ECS_HWQUE_IRQ_FUNC)();
typedef struct ECS_HW_QUE_INFO_withirq
{
int32_t ecs_hq_id;
int32_t ecs_hq_vector;
ECS_HWQUE_IRQ_FUNC irq_entry;
}ecs_hw_que_info_withirq_t;
typedef struct ECS_HW_QUE_INFO_NOIRQ
{
int32_t ecs_hq_id;
int32_t ecs_hq_vector;
}ecs_hw_que_info_noirq_t;
void ecs_hw_que_init(uint8_t core_id);
void ecs_hw_que_init_withirq(uint8_t core_id, uint8_t que_id);
void ecs_hw_que_init_noirq(uint8_t core_id, uint8_t que_id);
void ecs_hw_que_init_withirq(uint8_t core_id, uint8_t que_id);
void ecs_hw_que_init_noirq(uint8_t core_id, uint8_t que_id);
ALWAYS_INLINE int32_t ecs_hw_que_send(uint8_t u8dst_que_id, uint32_t u32value);
ALWAYS_INLINE int32_t ecs_hw_que_recv(uint8_t u8dst_que_id, uint32_t *pu32value);

146
public/common/utility/inc/ucp_printf.h
View File

@ -1,73 +1,73 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ucp_printf.h
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#ifndef __UCP_PRINTF_H__
#define __UCP_PRINTF_H__
#include <stdio.h>
#include "spu_log.h"
#define PRINT_OFF 0x00000000 // close all PRINT
#define PRINT_ERROR 0x00000001
#define PRINT_WARN 0x00000002
#define PRINT_LOG 0x00000004
#define PRINT_DEBUG 0x00000008
#define PRINT_TICK 0x00000010
//#define UCP_PRINT_LEVEL (PRINT_OFF)
//#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_WARN |PRINT_LOG | PRINT_DEBUG | PRINT_TICK)
//#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_DEBUG)
#define UCP_PRINT_LEVEL (PRINT_ERROR)
#if (UCP_PRINT_LEVEL & PRINT_ERROR)
//#define UCP_PRINT_ERROR(fmt, args...) printf(__FILE__ ": [ERROR]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_ERROR(fmt, args...) spu_log_output(LOG_ERROR, "[ERROR]:" fmt "\n", ##args)
#else
#define UCP_PRINT_ERROR(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_WARN)
//#define UCP_PRINT_WARN(fmt, args...) printf(__FILE__ ": [WARN]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_WARN(fmt, args...) spu_log_output(LOG_WARN, "[WARN]:" fmt "\n", ##args)
#else
#define UCP_PRINT_WARN(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_LOG)
//#define UCP_PRINT_LOG(fmt, args...) printf(__FILE__ ": [LOG]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_LOG(fmt, args...) spu_log_output(LOG_INFO, "[LOG]:" fmt "\n", ##args)
#else
#define UCP_PRINT_LOG(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_DEBUG)
//#define UCP_PRINT_LOG(fmt, args...) printf(__FILE__ ": [LOG]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_DEBUG(fmt, args...) spu_log_output(LOG_DEBUG, "[DEBUG]:" fmt "\n", ##args)
#else
#define UCP_PRINT_DEBUG(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_TICK)
//#define UCP_PRINT_TICK(fmt, args...) printf(__FILE__ ": [TICK]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_TICK(fmt, args...) spu_log_output(LOG_TICK, "[TICK]:" fmt "\n", ##args)
#else
#define UCP_PRINT_TICK(fmt, args...)
#endif
#define UCP_PRINT_EMPTY(fmt, args...)
#endif
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ucp_printf.h
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#ifndef __UCP_PRINTF_H__
#define __UCP_PRINTF_H__
#include <stdio.h>
#include "spu_log.h"
#define PRINT_OFF 0x00000000 // close all PRINT
#define PRINT_ERROR 0x00000001
#define PRINT_WARN 0x00000002
#define PRINT_LOG 0x00000004
#define PRINT_DEBUG 0x00000008
#define PRINT_TICK 0x00000010
//#define UCP_PRINT_LEVEL (PRINT_OFF)
//#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_WARN |PRINT_LOG | PRINT_DEBUG | PRINT_TICK)
//#define UCP_PRINT_LEVEL (PRINT_ERROR | PRINT_DEBUG)
#define UCP_PRINT_LEVEL (PRINT_ERROR)
#if (UCP_PRINT_LEVEL & PRINT_ERROR)
//#define UCP_PRINT_ERROR(fmt, args...) printf(__FILE__ ": [ERROR]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_ERROR(fmt, args...) spu_log_output(LOG_ERROR, "[ERROR]:" fmt "\n", ##args)
#else
#define UCP_PRINT_ERROR(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_WARN)
//#define UCP_PRINT_WARN(fmt, args...) printf(__FILE__ ": [WARN]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_WARN(fmt, args...) spu_log_output(LOG_WARN, "[WARN]:" fmt "\n", ##args)
#else
#define UCP_PRINT_WARN(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_LOG)
//#define UCP_PRINT_LOG(fmt, args...) printf(__FILE__ ": [LOG]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_LOG(fmt, args...) spu_log_output(LOG_INFO, "[LOG]:" fmt "\n", ##args)
#else
#define UCP_PRINT_LOG(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_DEBUG)
//#define UCP_PRINT_LOG(fmt, args...) printf(__FILE__ ": [LOG]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_DEBUG(fmt, args...) spu_log_output(LOG_DEBUG, "[DEBUG]:" fmt "\n", ##args)
#else
#define UCP_PRINT_DEBUG(fmt, args...)
#endif
#if (UCP_PRINT_LEVEL & PRINT_TICK)
//#define UCP_PRINT_TICK(fmt, args...) printf(__FILE__ ": [TICK]: %d: %s():" fmt "\n", __LINE__, __func__, ##args)
#define UCP_PRINT_TICK(fmt, args...) spu_log_output(LOG_TICK, "[TICK]:" fmt "\n", ##args)
#else
#define UCP_PRINT_TICK(fmt, args...)
#endif
#define UCP_PRINT_EMPTY(fmt, args...)
#endif

2
public/common/utility/inc/ucp_utility.h
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@ -70,6 +70,7 @@ void ucp_nop(uint32_t cycleCnt);
#define DBG_DDR_IDX_OSP2_BASE (2048*11) // 0xB7E16000
#define DBG_DDR_IDX_ERR_BASE (2048*18)
#define DBG_DDR_IDX_CPRI_BASE (2048*20)
#define DBG_DDR_IDX_ECPRI_BASE (2048*24)
#define DBG_DDR_IRQ_ADDR_BASE (0xB7FC0000)
#define DBG_DDR_IRQ_LEN (0x1000)
#define DBG_DDR_OS_ADDR_BASE (0xB7FCD000)
@ -84,6 +85,7 @@ void ucp_nop(uint32_t cycleCnt);
#define DBG_DDR_COMMON_IDX(core_id,x) (DBG_DDR_IDX_COMMON_BASE + (core_id) * 128 + (x))
#define DBG_DDR_MSG_IDX(queue_no,x) (DBG_DDR_IDX_MSG_BASE + (queue_no) * 192 + (x))
#define DBG_DDR_ERR_IDX(core_id,x) (DBG_DDR_IDX_ERR_BASE + (core_id)*128 + (x))
#define DBG_DDR_ECPRI_IDX(ape_id,x) (DBG_DDR_IDX_ECPRI_BASE + (ape_id)*1024 + (x))
#define OSP_DEBUG_HW_POT(core_id, idx) (DBG_DDR_OSP_HW_BASE + ((core_id)*DBG_DDR_OSP_HW_LEN) + idx)
#define UCP_OSP_DBG_HW_CNT_ENABLE

54
public/ecs_rfm_spu0/driver/inc/ecpri_csu.h Normal file
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@ -0,0 +1,54 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_csu.h
* Create Date: 23/07/31
* Description: eCPRI CSU Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. LiX 23/07/31 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_CSU_H_
#define _ECPRI_CSU_H_
#include "typedef.h"
#include "ucp_csu.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "ecpri_queue_proc.h"
#ifndef NULL
#define NULL ((void *)0)
#endif
#define ECPRI_CSU_REG_NUM 32
#define ECPRI_CSU_RFM_REG_START 0
#define ECPRI_CSU_RFM_REG_END 11
#define ECPRI_CSU_DATA_BUF_ADDR (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE) // (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)
#define ECPRI_CSU_DBG_BUF_ADDR (ECPRI_DBG_BUF_ADDR + 0x00080000ul) // (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)
//#define SERDES_INIT_FLAG_ADDR (0x0A4D7240) // cpri or jesd clk init finished
typedef enum _tagEcpriChId
{
ECPRI_U_PLANE = 0,
ECPRI_C_PLANE
} EcpriChId;
int32_t ecpri_csu_init(void);
uint32_t ecpri_csu_get_free_channel(void);
uint32_t ecpri_csu_send(uint64_t dataAddr, uint32_t dataLen, uint8_t isWait);
int32_t ecpri_csu_task_lookup(uint8_t task_tag, uint8_t isWait);
void ecpri_csu_send_test(void);
#endif

127
public/ecs_rfm_spu0/driver/inc/ecpri_queue_proc.h Normal file
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@ -0,0 +1,127 @@
//******************** (C) COPYRIGHT 2020 SmartLogic*******************************
// FileName : ecpri_queue_proc.h
// Author : shanghuihui, huihui.shang@smartlogictech.com
// Date First Issued : 2023-05-15 11:16:39 AM
// Last Modified : 2023-05-15 11:16:39 AM
// Description :
// ------------------------------------------------------------
// Modification History:
// Version Date Author Modification Description
//
//**********************************************************************************
#ifndef _ECPRI_QUEUE_PROC_H_
#define _ECPRI_QUEUE_PROC_H_
//#include <netinet/in.h>
//#include "typedef.h"
#include "ucp_ecpri.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "app_interface.h"
#include "ucp_handshake.h"
#include "ucp_tick.h"
#include "ape_csu.h"
#include "hwque.h"
#ifndef NULL
#define NULL ((void *)0)
#endif
/* eCPRI数据缓冲区地址 */
#define ECPRI_DATA_BUF_ADDR 0xAEE00000ul
/* eCPRI数据缓冲区大小（63MB） */
#define ECPRI_DATA_BUF_SIZE 0x01E00000ul // 0x03F00000ul
/* eCPRI调试缓冲区地址 */
#define ECPRI_DBG_BUF_ADDR (ECPRI_DATA_BUF_ADDR + 0x03F00000ul) // (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)
/* eCPRI调试缓冲区大小（1MB） */
#define ECPRI_DBG_BUF_SIZE 0x00100000ul
/* eCPRI数据包大小（16KB） */
#define ECPRI_DATA_PKT_SIZE 0x00004000ul
/* eCPRI数据包最大数量 */
#define ECPRI_DATA_PKT_MAX (ECPRI_DATA_BUF_SIZE / ECPRI_DATA_PKT_SIZE)
/* eCPRI ROEC DESC地址单位（1:32B） */
#define ECPRI_DESC_ADDR_UNIT 32
/* 数据包类型-eCPRI */
#define ECPRI_PKT_TYPE_ECPRI 0xAEFE
/* 数据包类型-1588 */
#define ECPRI_PKT_TYPE_1588 0x88F7
/* APE测试任务ID */
#define ECPRI_APE_TEST_TASK_ID 40 // 63
/* STC统计最大cycle值 */
#define STC_CYCLE_MAX 1000000000ul
/* 循环队列结构体 */
typedef struct Stru_Ring_Buf
{
uint32_t u32WrIdx; /* 写索引 */
uint32_t u32RdIdx; /* 读索引 */
uint32_t u32BufSize; /* 缓冲区大小 */
uint8_t *pu8Buf; /* 缓冲区指针 */
} STRU_RING_BUF;
/* 通知消息结构体 */
typedef struct Stru_Inform_Msg
{
uint32_t u32PktAddr; /* 数据包地址 */
uint32_t u32PktLen; /* 数据包长度 */
} STRU_INFORM_MSG;
/* 消息类型枚举 */
typedef enum Enum_Msg_Type
{
E_MSG_TYPE_APE = 0x55, /* APE消息类型 */
E_MSG_TYPE_ARM = 0xaa /* ARM消息类型 */
} ENUM_MSG_TYPE;
/* 核ID */
typedef enum Enum_Core_Id
{
E_CORE_ID_APE0 = 0, /* APE0核ID */
E_CORE_ID_APE1, /* APE1核ID */
E_CORE_ID_APE2, /* APE2核ID */
E_CORE_ID_APE3, /* APE3核ID */
E_CORE_ID_APE4, /* APE4核ID */
E_CORE_ID_APE5, /* APE5核ID */
E_CORE_ID_APE6, /* APE6核ID */
E_CORE_ID_APE7, /* APE7核ID */
E_CORE_ID_PET0, /* PET RFM SPU0核ID */
E_CORE_ID_PET1, /* PET RFM SPU1核ID */
E_CORE_ID_ECS0, /* ECS RFM SPU0核ID */
E_CORE_ID_ECS1, /* PET RFM SPU1核ID */
E_CORE_ID_ARM0 /* ARM0核ID */
} ENUM_APE_CORE_ID;
/* ecpri循环队列初始化 */
void ecpri_queue_init(void);
/* ecpri循环队列轮询 */
void ecpri_queue_proc(void);
/* ecpri数据包处理 */
void ecpri_packet_proc(uint32_t u32PktAddr);
/* ecpri通知ape */
int32_t ecpri_inform_ape(uint32_t u32PktAddr, uint32_t u32PktLen);
/* ecpri通知arm */
int32_t ecpri_inform_arm(uint32_t u32PktAddr, uint32_t u32PktLen);
/* ecpri通知arm扩展接口 */
int32_t ecpri_inform_arm_ex(uint32_t u32PktAddr);
/* ecpri内存拷贝测试 */
void ecpri_memcpy_test(void);
/* ecpri csu_dma搬数测试 */
void ecpri_csu_dma_test(void);
#endif /* _ECPRI_QUEUE_PROC_H_ */

2
public/ecs_rfm_spu0/driver/inc/rfm0_cpri_timer.h
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@ -6,6 +6,6 @@
void set_cpri_timer_rfm0_int(void);
void isr_cpri_rfm0_slot_offset(void);
void isr_cpri_rfm0_symbol(void);
#endif /* APEDRV_APE_INC_APE_CPRI_TIMER_H_ */

2
public/ecs_rfm_spu0/driver/inc/rfm0_ecpri_timer.h
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@ -3,6 +3,6 @@
void set_ecpri_timer_rfm0_int(void);
void isr_ecpri_rfm0_slot_offset(void);
void isr_ecpri_rfm0_symbol(void);
#endif /* APEDRV_APE_INC_APE_ECPRI_TIMER_H_ */

7
public/ecs_rfm_spu0/driver/inc/rfm0_mtimer.h
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@ -1,12 +1,15 @@
#ifndef _RFM0_MTIMER_H_
#define _RFM0_MTIMER_H_
#include "typedef.h"
void rfm0_mtimer_int_init(void);
int32_t rfm0_mtimer_int_init(void);
//int mtimer_sfn_para_init(int nTmrId);
void phy_cell_para_init();
//void phy_cell_para_init();
int32_t mtimer_rfm0_symbol_callback(uint8_t nTmrId);
#endif

252
public/ecs_rfm_spu0/driver/src/ecpri_csu.s.c Normal file
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@ -0,0 +1,252 @@
#include "ecpri_csu.h"
#if 0
char g_acEcpriCsuSendBuf[16384] = {
0X00, 0X1B, 0X21, 0X89, 0X67, 0X5C,
0X00, 0X0A, 0X09, 0X08, 0X07, 0X16,
0X81, 0X00, 0X00, 0X01, 0XAE, 0XFE,
0X45, 0X00, 0X00, 0XBE, 0X12, 0X34,
0X40, 0X00, 0XFF, 0X11, 0X40, 0XC9
};
#endif
char g_acEcpriDataHeaderBuf[30] = {
0X00, 0X1B, 0X21, 0X89, 0X67, 0X5C,
0XFF, 0XFA, 0XF9, 0XF8, 0XF7, 0XF6, //MAC地址不能重复 0X00, 0X0A, 0X09, 0X08, 0X07, 0X16
0X81, 0X00, 0X00, 0X01, 0XAE, 0XFE,
0X45, 0X00, 0X00, 0XBE, 0X12, 0X34,
0X40, 0X00, 0XFF, 0X11, 0X40, 0XC9
};
void ecpri_csu_send_data_init(void)
{
uint32_t i = 0;
for (i = 0; i < 30; i++)
{
do_write_byte(ECPRI_CSU_DATA_BUF_ADDR + i, g_acEcpriDataHeaderBuf[i]);
}
memset_ucp(ECPRI_CSU_DATA_BUF_ADDR + 30, 0x5A, (11264 - 30));
}
int32_t ecpri_csu_init(void)
{
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x55555555);
#if 0
memset_ucp((char *)&g_acEcpriCsuSendBuf[30], 0x5A, 11264);
#else
ecpri_csu_send_data_init();
#endif
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x11111111);
do_write(&JECS_CSU_EM_BS_SMSEL_PREDATANUM, ((0x1<<25) | (0x1<<14) | (0x5<<5) | 0x8)); // bit25: ecpri mode， bit14: FIFO1
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x10, do_read_volatile(&JECS_CSU_EM_BS_SMSEL_PREDATANUM));
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x22222222);
do_write(&JECS_CSU_FINDDMATAG, 0x60); // DMA搬移完成才能查到结束状态
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x14, do_read_volatile(&JECS_CSU_FINDDMATAG));
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x33333333);
do_write(&JECS_CSU_TAGMASK0, 0xFFFFFFFF);
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x18, do_read_volatile(&JECS_CSU_TAGMASK0));
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0x44444444);
for (uint8_t i = 0; i < ECPRI_CSU_REG_NUM; i++)
{
uint8_t offset = (i<<3);
do_write(((uint32_t*)(&JECS_CSU_DMAADDRL0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x00, do_read_volatile(&JECS_CSU_DMAADDRL0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAADDRH0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x04, do_read_volatile(&JECS_CSU_DMAADDRH0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAYNUMXNUM0) + offset), ((4 << 16) | 1024));
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x08, do_read_volatile(&JECS_CSU_DMAYNUMXNUM0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAYSTEPL0) + offset), 1024);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x0C, do_read_volatile(&JECS_CSU_DMAYSTEPL0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAYSTEPH0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x10, do_read_volatile(&JECS_CSU_DMAYSTEPH0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAZSTEPL0) + offset), 4096);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x14, do_read_volatile(&JECS_CSU_DMAZSTEPL0 + offset));
do_write(((uint32_t*)(&JECS_CSU_DMAZSTEPH0) + offset), 0);
do_write(ECPRI_CSU_DBG_BUF_ADDR + (i + 1) * 0x20 + 0x18, do_read_volatile(&JECS_CSU_DMAZSTEPH0 + offset));
}
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x00, 0xaaaaaaaa);
return 0;
}
/*!
* @brief: 设置ecpri的PreDataNum参数，只能设置FIFO1
* @author: xinxin.li
* @Date: 2023年6月1日
* @param: preData0 : [bit[4:0]: Global端未收到读响应的读请求个数未超过PREDATANUM[4:0]，CSU开始向总线发起读请求，直到Global端未收到读响应的读请求个数超过PREDATANUM[4:0]，CSU暂停向总线发起读请求]
* @param: preData1 : [bit[9:5]: 未收到读响应的读请求个数不超过PREDATANUM[9:5]的值时，CSU再次向总线发起读请求 ]
* @return: -1：参数错误，0：配置成功
*/
int32_t ecpri_csu_set_predatanum(uint8_t preData0, uint8_t preData1)
{
do_write(&JECS_CSU_EM_BS_SMSEL_PREDATANUM, ((0x1<<25) | (0x1<<14) | (preData1<<5) | preData0)); // bit25: ecpri mode， bit14: FIFO1
return 0;
}
//tag 0 reg_group = 0(0->1) CmdFIFO = 1 rfm
//tag 1 1(2->3) 1
//tag 2 2(4->5) 1
//tag 3 3(6->7) 1
//tag 4 4(8->9) 1
//tag 5 5(10->11) 1
//tag 6 6(12->13) 1
//tag 7 7(14->15) 1
//tag 8 8(16->17) 1
//tag 9 9(18->19) 1
//tag 10 10(20->21) 1
//tag 11 11(22->23) 1
//tag 12 reg_group = 12(24->25) CmdFIFO = 1 arm
//tag 13 13(26->27) 1
//tag 14 14(28->29) 1
//tag 15 15(30->31) 1
// get unused register group according to tag number
int32_t ecpri_csu_get_free_reg_group(uint8_t tag)
{
if (ECPRI_CSU_RFM_REG_END < tag)
{
return -1;
}
uint8_t regGroup = tag; //0~11
uint32_t bitMap = (0x1<<regGroup);
uint32_t dmaStatus = do_read_volatile(&JECS_CSU_DMASTATUS);
if (bitMap != (dmaStatus & bitMap))
{
return -1;
}
return regGroup; // reg group(0~11)
}
uint32_t ecpri_csu_get_free_channel(void)
{
while (1)
{
for (int tag = ECPRI_CSU_RFM_REG_START; tag <= ECPRI_CSU_RFM_REG_END; tag++)
{
if (0 == (do_read_volatile(&JECS_CSU_DMASTATUS) & (1<<tag)))
{
continue;
}
else
{
int32_t temp = ecpri_csu_get_free_reg_group(tag);
if (-1 == temp)
{
continue;
}
else
{
uint8_t regGroup = temp & 0xFF;
uint32_t ret = regGroup | (tag<<8);
return ret;
}
}
}
}
}
/* ecpri内存拷贝测试DDR--->DDR */
uint32_t ecpri_csu_send(uint64_t dataAddr, uint32_t dataLen, uint8_t isWait)
{
uint8_t regGroup = 0;
uint8_t tag = 0;
uint32_t temp = ecpri_csu_get_free_channel();
regGroup = temp & 0xFF;
tag = (temp>>8) & 0xFF;
uint16_t offset_w = regGroup << 4;
// src reg
do_write(((uint32_t*)(&JECS_CSU_DMAADDRL0) + offset_w), (dataAddr & 0xFFFFFFFF));
do_write(((uint32_t*)(&JECS_CSU_DMAADDRH0) + offset_w), (uint32_t)(dataAddr >> 32));
do_write(((uint32_t*)(&JECS_CSU_DMASIZEGRANALLNUM0) + offset_w), ((0xF<<28) | (0xE<<24) | dataLen)); // DM,CGran=1,Gran=6;size=0xF
// dst reg
//do_write(((uint32_t*)(&JECS_CSU_DMAADDRL1) + offset_w), 0);
//do_write(((uint32_t*)(&JECS_CSU_DMAADDRH1) + offset_w), 0);
//do_write(((uint32_t*)(&JECS_CSU_DMASIZEGRANALLNUM1) + offset_w), ((0x8<<28) | (0x0<<24) | dataLen)); // 1<<{GRAN[3],SIZE[3]}
do_write(((uint32_t*)(&JECS_CSU_DMASIZEGRANALLNUM1) + offset_w), ((0x9<<28) | (0x0<<24) | dataLen)); // 1<<{GRAN[3],SIZE[3]}, SIZE[2:0]->packet_end, GRAN[2:0]->section_end
stCsuDmaCmdL dmaCmdL;
*(uint32_t *)(&dmaCmdL) = 0;
dmaCmdL.dmaType = 1;
dmaCmdL.idSrc = 0 + (regGroup<<1);
dmaCmdL.idDst = 1 + (regGroup<<1);
dmaCmdL.dmaTag = tag;
dmaCmdL.ecpriEnd = 1; // packet end
do_write(((stCsuDmaCmdL*)(&JECS_CSU_CMDFIFO1)), (*(uint32_t*)(&dmaCmdL)));
if (1 == isWait)
{
while (0 == (do_read_volatile((uint32_t*)(&JECS_CSU_DMASTATUS)) & (1 << tag)));
}
return tag;
}
/*!
* @brief: 查看tag号对应的dma任务是否完成，未完成返回0，完成返回1
* 如果isWait==1，则等待该tag对应的任务完成，再返回，返回1
* @author: xinxin.li
* @Date: 2023年6月1日
* @param: task_tag : [DMA Tag: 0~31用于查询是否完成 ]
* @param: isWait : [是否等DMA结束函数返回0:不等待,1:等待 ]
* @return: 1：已完成，0：未完成
*/
int32_t ecpri_csu_task_lookup(uint8_t task_tag, uint8_t isWait)
{
if (0 == isWait)
{
return (do_read_volatile((uint32_t*)(&JECS_CSU_DMASTATUS)) & (1 << task_tag));
}
else
{
while (0 == (do_read_volatile((uint32_t*)(&JECS_CSU_DMASTATUS)) & (1 << task_tag)))
{
ucp_nop(1);
}
return 1;
}
}
uint32_t g_u32CsuSendCnt = 0;
void ecpri_csu_send_test(void)
{
uint32_t tag = 0xFFFFFFFF;
//tag = ecpri_csu_send((uint64_t)ECPRI_CSU_DATA_BUF_ADDR, 0x2C00, 1); //发送11KB
//tag = ecpri_csu_send((uint64_t)ECPRI_CSU_DATA_BUF_ADDR, 0x200, 1); //发送512B
tag = ecpri_csu_send((uint64_t)ECPRI_CSU_DATA_BUF_ADDR, 0x2580, 1); //发送512B
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x8000 + 0x10 + g_u32CsuSendCnt * 0x4, tag);
g_u32CsuSendCnt++;
do_write(ECPRI_CSU_DBG_BUF_ADDR + 0x8000 + 0x00, g_u32CsuSendCnt);
}

603
public/ecs_rfm_spu0/driver/src/ecpri_queue_proc.s.c Normal file
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@ -0,0 +1,603 @@
#include "ecpri_queue_proc.h"
/* 循环队列结构 */
STRU_RING_BUF g_struRingBuf = {0};
/* 读取数据包总数 */
uint64_t g_u64RdPktTotal = 0;
/* 读取数据包循环计数 */
uint32_t g_u32RdPktCnt = 0;
/* ecpri循环队列初始化 */
void ecpri_queue_init(void)
{
/* 数据包存放位置，单位：32Byte */
uint32_t u32DescPtr = 0;
/* 数据包内存地址，单位：Byte */
uint32_t u32MemAddr = 0;
/* 初始化循环缓冲区管理结构 */
g_struRingBuf.u32WrIdx = 0;
g_struRingBuf.u32RdIdx = 0;
g_struRingBuf.pu8Buf= (uint8_t *)ECPRI_DATA_BUF_ADDR;
g_struRingBuf.u32BufSize = ECPRI_DATA_BUF_SIZE;
/* 初始化读取数据包总数 */
g_u64RdPktTotal = 0;
/* 获取数据包存放位置 */
u32DescPtr = do_read_volatile(&DESC_PTR_2);
/* 计算数据包内存地址并进行校验 */
u32MemAddr = u32DescPtr * ECPRI_DESC_ADDR_UNIT;
if ((u32MemAddr < ECPRI_DATA_BUF_ADDR) ||
(u32MemAddr >= (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)) ||
(((u32MemAddr - ECPRI_DATA_BUF_ADDR) % ECPRI_DATA_PKT_SIZE) != 0))
{
do_write(ECPRI_DBG_BUF_ADDR + 0x10, 0x11111111);
do_write(ECPRI_DBG_BUF_ADDR + 0x20, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x24, u32MemAddr);
return;
}
/* 更新描述符下一个地址和当前接收数据包存放位置相同 */
do_write(&DESC_TAIL_ADDR_2, u32DescPtr);
/* 更新读/写索引 */
g_struRingBuf.u32WrIdx = (u32MemAddr - ECPRI_DATA_BUF_ADDR) / ECPRI_DATA_PKT_SIZE;
g_struRingBuf.u32RdIdx = g_struRingBuf.u32WrIdx;
/* 清空eCPRI数据和调试缓冲区 */
memset_ucp(ECPRI_DATA_BUF_ADDR, 0x00, ECPRI_DATA_BUF_SIZE);
memset_ucp(ECPRI_DBG_BUF_ADDR, 0x00, ECPRI_DBG_BUF_SIZE);
do_write(ECPRI_DBG_BUF_ADDR + 0x10, 0x00000000);
do_write(ECPRI_DBG_BUF_ADDR + 0x20, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x24, u32MemAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x28, g_struRingBuf.u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x2C, g_struRingBuf.u32RdIdx);
}
/* ecpri循环队列轮询处理 */
void ecpri_queue_proc(void)
{
/* 数据包存放位置，单位：32Byte */
uint32_t u32DescPtr = 0;
/* 数据包内存地址，单位：Byte */
uint32_t u32MemAddr = 0;
/* 读取包数 */
uint32_t u32RdPktNum = 0;
/* 数据包地址 */
uint32_t u32PktAddr = 0;
/* 计数索引 */
uint32_t i = 0;
/* 获取数据包存放位置 */
u32DescPtr = do_read_volatile(&DESC_PTR_2);
/* 计算数据包内存地址并进行校验 */
u32MemAddr = u32DescPtr * ECPRI_DESC_ADDR_UNIT;
if ((u32MemAddr < ECPRI_DATA_BUF_ADDR) ||
(u32MemAddr >= (ECPRI_DATA_BUF_ADDR + ECPRI_DATA_BUF_SIZE)) ||
(((u32MemAddr - ECPRI_DATA_BUF_ADDR) % ECPRI_DATA_PKT_SIZE) != 0))
{
do_write(ECPRI_DBG_BUF_ADDR + 0x30, 0x11111111);
do_write(ECPRI_DBG_BUF_ADDR + 0x40, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x44, u32MemAddr);
return;
}
/* 计算写索引 */
g_struRingBuf.u32WrIdx = (u32MemAddr - ECPRI_DATA_BUF_ADDR) / ECPRI_DATA_PKT_SIZE;
/* 读/写索引相同，没有数据包要读 */
if (g_struRingBuf.u32WrIdx == g_struRingBuf.u32RdIdx)
{
do_write(ECPRI_DBG_BUF_ADDR + 0x30, 0x22222222);
do_write(ECPRI_DBG_BUF_ADDR + 0x40, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x44, u32MemAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x48, g_struRingBuf.u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x4C, g_struRingBuf.u32RdIdx);
return;
}
/* 计算所要读取的包数 */
u32RdPktNum = (g_struRingBuf.u32WrIdx + ECPRI_DATA_PKT_MAX - g_struRingBuf.u32RdIdx) % ECPRI_DATA_PKT_MAX;
for (i = 0; i < u32RdPktNum; i++)
{
/* 计算数据包地址 */
u32PktAddr = ECPRI_DATA_BUF_ADDR + g_struRingBuf.u32RdIdx * ECPRI_DATA_PKT_SIZE;
/* ecpri数据包处理 */
ecpri_packet_proc(u32PktAddr);
/* 更新描述符下一个地址 */
do_write(&DESC_TAIL_ADDR_2, ((u32PktAddr + ECPRI_DATA_PKT_SIZE) / ECPRI_DESC_ADDR_UNIT));
//printf("[ecpri_queue_proc] u32PktAddr[0x%08x], u32PktLen[0x%08x].\n", u32PktAddr, u32PktLen);
//printf("[ecpri_queue_proc] u32RdIdx[0x%08x], u32WrIdx[0x%08x].\n", u32RdIdx, u32WrIdx);
//UCP_PRINT_ERROR("[ecpri_queue_proc] u32PktAddr[0x%08x], u32PktLen[0x%08x].\n", u32PktAddr, u32PktLen);
//UCP_PRINT_ERROR("[ecpri_queue_proc] u32RdIdx[0x%08x], u32WrIdx[0x%08x].\n", u32RdIdx, u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x00, g_struRingBuf.u32WrIdx);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x04, g_struRingBuf.u32RdIdx);
/* 更新读索引 */
g_struRingBuf.u32RdIdx++;
g_struRingBuf.u32RdIdx %= ECPRI_DATA_PKT_MAX;
/* 更新读取数据包循环计数 */
g_u32RdPktCnt++;
g_u32RdPktCnt %= ECPRI_DATA_PKT_MAX;
}
/* 更新读取数据包总数 */
g_u64RdPktTotal += u32RdPktNum;
do_write(ECPRI_DBG_BUF_ADDR + 0x30, 0x00000000);
do_write(ECPRI_DBG_BUF_ADDR + 0x34, ((g_u64RdPktTotal & 0xFFFFFFFF00000000) >> 8));
do_write(ECPRI_DBG_BUF_ADDR + 0x38, (g_u64RdPktTotal & 0xFFFFFFFF));
do_write(ECPRI_DBG_BUF_ADDR + 0x3C, u32RdPktNum);
do_write(ECPRI_DBG_BUF_ADDR + 0x40, u32DescPtr);
do_write(ECPRI_DBG_BUF_ADDR + 0x44, u32MemAddr);
}
/* ecpri数据包处理 */
void ecpri_packet_proc(uint32_t u32PktAddr)
{
/* eCPRI包类型字段偏移 */
uint32_t u32TypeOffset = 16;
/* eCPRI包长字段偏移 */
uint32_t u32LenOffset = 20;
/* 数据包类型 */
uint16_t u16PktType = 0;
/* 数据包长度 */
uint16_t u16PktLen = 0;
#if 0
/* 净荷地址 */
uint32_t u32PayloadAddr = 0;
#endif
/* 判断包类型是否是eCPRI报文 */
u16PktType = do_read_short(u32PktAddr + u32TypeOffset);
u16PktType = ((u16PktType & 0xFF) << 8) | ((u16PktType & 0xFF00) >> 8);
if (ECPRI_PKT_TYPE_ECPRI == u16PktType)
{
/* 获取eCPRI数据包净荷长度，单位：Byte */
u16PktLen = do_read_short(u32PktAddr + u32LenOffset);
u16PktLen = ((u16PktLen & 0xFF) << 8) | ((u16PktLen & 0xFF00) >> 8);
#if 1
/* 计数eCPRI数据包总长度 */
u16PktLen += 18;
//TODO:
/* 将eCPRI数据包净荷地址和净荷长度发送给APE */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x08, u32PktAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x0C, u16PktLen);
(void)ecpri_inform_ape(u32PktAddr, u16PktLen);
#else
/* 计数eCPRI数据包净荷地址 */
u32PayloadAddr = u32PktAddr + 18;
//TODO:
/* 将eCPRI数据包净荷地址和净荷长度发送给APE */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x08, u32PayloadAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x0C, u16PktLen);
(void)ecpri_inform_ape(u32PayloadAddr, u16PktLen);
#endif
}
else
{
/* 获取非eCPRI数据包（如1588等）总长度，单位：Byte */
u32LenOffset = ECPRI_DATA_PKT_SIZE - 0x1C;
u16PktLen = do_read_short(u32PktAddr + u32LenOffset);
//TODO:
/* 将非eCPRI数据包地址和总长度发送给ARM */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x08, u32PktAddr);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x0C, u16PktLen);
#if 0
(void)ecpri_inform_arm(u32PktAddr, u16PktLen);
#else
(void)ecpri_inform_arm_ex(u32PktAddr);
#endif
}
}
/* ecpri通知ape */
int32_t ecpri_inform_ape(uint32_t u32PktAddr, uint32_t u32PktLen)
{
/* 返回值 */
int32_t s32Ret = 0;
/* 消息长度 */
int32_t s32MsgSize = 8;
/* 消息地址 */
char *pcMsgAddr = NULL;
/* 通知消息 */
STRU_INFORM_MSG struInformMsg = {0};
/* 申请消息 */
pcMsgAddr = osp_alloc_msg(s32MsgSize);
if (NULL == pcMsgAddr)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-1));
return -1;
}
/* 组装通知消息 */
#if 1
struInformMsg.u32PktAddr = u32PktAddr;
struInformMsg.u32PktLen = u32PktLen;
memcpy_ucp(pcMsgAddr, &struInformMsg, sizeof(STRU_INFORM_MSG));
#else
do_write(pcMsgAddr, u32PktAddr);
do_write(pcMsgAddr + 4, u32PktLen);
#endif
s32Ret = osp_send_msg((uint32_t)pcMsgAddr,
(uint32_t)sizeof(STRU_INFORM_MSG),
(uint8_t)E_MSG_TYPE_APE,
(uint8_t)ECS_RFM_SPU0_CORE_ID,
(uint8_t)E_CORE_ID_APE0,
(uint8_t)0, // 40 //0
(uint8_t)61); // 40 //ECPRI_APE_TEST_TASK_ID
if (0 != s32Ret)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-2));
return -2;
}
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, 0);
/* 数据包类型-eCPRI */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x14, ECPRI_PKT_TYPE_ECPRI);
return 0;
}
/* ecpri通知arm */
int32_t ecpri_inform_arm(uint32_t u32PktAddr, uint32_t u32PktLen)
{
/* 返回值 */
int32_t s32Ret = 0;
/* 消息长度 */
int32_t s32MsgSize = 8;
/* 消息地址 */
char *pcMsgAddr = NULL;
/* 通知消息 */
STRU_INFORM_MSG struInformMsg = {0};
/* 申请消息 */
pcMsgAddr = osp_alloc_msg(s32MsgSize);
if (NULL == pcMsgAddr)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-1));
return -1;
}
/* 组装通知消息 */
#if 1
struInformMsg.u32PktAddr = u32PktAddr;
struInformMsg.u32PktLen = u32PktLen;
memcpy_ucp(pcMsgAddr, &struInformMsg, sizeof(STRU_INFORM_MSG));
#else
do_write(pcMsgAddr, u32PktAddr);
do_write(pcMsgAddr + 4, u32PktLen);
#endif
s32Ret = osp_send_msg((uint32_t)pcMsgAddr,
(uint32_t)sizeof(STRU_INFORM_MSG),
(uint8_t)E_MSG_TYPE_ARM,
(uint8_t)ECS_RFM_SPU0_CORE_ID,
(uint8_t)E_CORE_ID_ARM0,
(uint8_t)0, // 0
(uint8_t)0); // 61
if (0 != s32Ret)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-2));
return -2;
}
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, 0);
/* 数据包类型-Other */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x14, ECPRI_PKT_TYPE_1588);
return 0;
}
/* ecpri通知arm扩展接口 */
int32_t ecpri_inform_arm_ex(uint32_t u32PktAddr)
{
/* 返回值 */
int32_t s32Ret = 0;
/* 硬件队列入队 */
s32Ret = smart_in_que((int)E_CORE_ID_ARM0, u32PktAddr);
if (0 != s32Ret)
{
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, (uint32_t)(-2));
return -2;
}
/* 返回值 */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x10, 0);
/* 数据包类型-Other */
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + g_u32RdPktCnt * 0x20 + 0x14, ECPRI_PKT_TYPE_1588);
return 0;
}
/* ecpri内存拷贝测试DDR--->DDR */
void ecpri_memcpy_test(void)
{
/* 计数索引 */
uint32_t i = 0;
/* 计数索引 */
uint32_t j = 0;
/* 开始Cycle */
uint32_t u32StartCycle = 0;
/* 结束Cycle */
uint32_t u32EndCycle = 0;
/* Cycle计数 */
uint32_t u32CycleNum = 0;
/* 填充内存 */
for (i = 0; i < 0x4000; i++)
{
do_write_byte((ECPRI_DATA_BUF_ADDR + i), (i % 256));
}
/* 64Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 64);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x04, 64);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x08, u32CycleNum);
}
/* 128Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 128);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x04, 128);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x08, u32CycleNum);
}
/* 256Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 256);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x04, 256);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x08, u32CycleNum);
}
/* 512Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 512);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x04, 512);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x08, u32CycleNum);
}
/* 1024Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 1024);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x04, 1024);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x08, u32CycleNum);
}
/* 1514Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 1514);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x04, 1514);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x08, u32CycleNum);
}
/* 11264Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
memcpy_ucp((char *)(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000), (char *)ECPRI_DATA_BUF_ADDR, 11264);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x04, 11264);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x08, u32CycleNum);
}
}
/* ecpri csu_dma搬数测试 */
void ecpri_csu_dma_test(void)
{
/* 计数索引 */
uint32_t i = 0;
/* 计数索引 */
uint32_t j = 0;
/* 开始Cycle */
uint32_t u32StartCycle = 0;
/* 结束Cycle */
uint32_t u32EndCycle = 0;
/* Cycle计数 */
uint32_t u32CycleNum = 0;
/* 填充内存 */
for (i = 0; i < 0x4000; i++)
{
do_write_byte((ECPRI_DATA_BUF_ADDR + i), (i % 256));
}
/* 64Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000),
64, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 1) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x04, 64);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 1) * 0x10 + 0x08, u32CycleNum);
}
/* 128Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000),
128, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 101) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x04, 128);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 101) * 0x10 + 0x08, u32CycleNum);
}
/* 256Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000),
256, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 201) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x04, 256);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 201) * 0x10 + 0x08, u32CycleNum);
}
/* 512Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000),
512, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 301) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x04, 512);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 301) * 0x10 + 0x08, u32CycleNum);
}
/* 1024Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000),
1024, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 401) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x04, 1024);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 401) * 0x10 + 0x08, u32CycleNum);
}
/* 1514Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000),
1514, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 501) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x04, 1514);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 501) * 0x10 + 0x08, u32CycleNum);
}
/* 11264Byte拷贝测试 */
for (j = 0; j < 100; j++)
{
rdmcycle(&u32StartCycle);
ape_csu_dma_1D_G2L_ch2ch3_transfer(ECPRI_DATA_BUF_ADDR,
(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000),
11264, 1, 1);
rdmcycle(&u32EndCycle);
u32CycleNum = (u32EndCycle + STC_CYCLE_MAX - u32StartCycle) % STC_CYCLE_MAX + 1;
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x00, (uint32_t)(ECPRI_DATA_BUF_ADDR + (j + 601) * 0x4000));
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x04, 11264);
do_write(ECPRI_DBG_BUF_ADDR + 0x100 + (j + 601) * 0x10 + 0x08, u32CycleNum);
}
}

128
public/ecs_rfm_spu0/driver/src/rfm0_cpri_timer.s.c
View File

@ -6,21 +6,19 @@
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "rfm0_mtimer.h"
#include "inter_vector.h"
// int cnt
//UINT32 gRfm0TxSlotIntCnt = 0;
//UINT32 gRfm0RxSlotIntCnt = 0;
extern stPhyScsPara* phyPara;
extern stSfnPara gCellSfnPara[2];
#if 0
void set_cpri_timer_rfm0_int(void)
{
int32_t apeId = get_core_id();
// tx slot
uint32_t intNum = APC_CPRI_TMR_INTR0 + MTMR_INT_RFM0_SLOT;
int32_t ret = smart_irq_request(intNum, isr_cpri_rfm0_slot_offset);
int32_t ret = smart_irq_request(intNum, isr_cpri_rfm0_symbol);
if (0 != ret)
{
UCP_PRINT_EMPTY("attach int num: 0x%x error. errno = 0x%x. \r\n", intNum, ret);
@ -28,125 +26,9 @@ void set_cpri_timer_rfm0_int(void)
}
}
int32_t gRfm0CalFlag = 0;
int32_t gRfm0CalCnt = 0;
int ecs_rfm0_cal_sfn(void)
void isr_cpri_rfm0_symbol(void)
{
if (1 == gCellSfnPara[MTIMER_CPRI_ID].ctcIntFlag)
{
gCellSfnPara[MTIMER_CPRI_ID].ctcIntFlag = 0;
int scsId = gCellSfnPara[MTIMER_CPRI_ID].scsId;
gCellSfnPara[MTIMER_CPRI_ID].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));
gCellSfnPara[MTIMER_CPRI_ID].rxSfnNum = do_read_volatile(&(phyPara[scsId].rxSfnNum));
gCellSfnPara[MTIMER_CPRI_ID].txSlotNum = do_read_volatile(&(phyPara[scsId].txSlotNum));
gCellSfnPara[MTIMER_CPRI_ID].rxSlotNum = do_read_volatile(&(phyPara[scsId].rxSlotNum));
gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt = 0;
gCellSfnPara[MTIMER_CPRI_ID].rxSlotIntCnt = 0;
gRfm0CalFlag = 1;
gRfm0CalCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+556+10), GET_STC_CNT()); // 0x8b0, 10:apeId
}
return 0;
mtimer_rfm0_symbol_callback(MTIMER_CPRI_ID);
}
// temp to be deleted
int32_t gRfm0IntCnt = 0;
uint32_t gRfm0LastTxTiming = 0;
uint32_t gRfm0LastRxTiming = 0;
void isr_cpri_rfm0_slot_offset(void)
{
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
int32_t eventId = MTMR_INT_RFM0_SLOT;
int32_t apeId = get_core_id();
stCoreInt* apeCoreIntInfo = (stCoreInt*)APE_INT_INFO_ADDR + APE_INT_MAXNUM*apeId;
tmrIntcFlag = do_read_volatile(&CPRI_TMR_INTC_REG);
if (tmrIntcFlag & (1 << eventId)) /* tmr int */
{
uint32_t flagAddr = (uint32_t)((uint32_t*)(&CPRI_TMR_TINTF00_REG) + 6*MTMR_INT_RFM0_SLOT);
int32_t txSlotTmrId = MTMR_RFM0_TXSLOT;
int32_t rxSlotTmrId = MTMR_RFM0_RXSLOT;
tEventFlag = do_read_volatile(flagAddr);
if (tEventFlag & ((1<<txSlotTmrId) | (1<<rxSlotTmrId)))
{
if (tEventFlag & (1<<txSlotTmrId)) // tx slot offset
{
uint32_t crVal = (1<<txSlotTmrId);
do_write(((uint32_t*)(&CPRI_TMR_TEVENT0_REG)), crVal);
do_write(flagAddr, crVal);
// sfn calibration
ecs_rfm0_cal_sfn();
gCellSfnPara[MTIMER_CPRI_ID].txSlotNum++;
__ucps2_synch(0);
if (gCellSfnPara[MTIMER_CPRI_ID].txSlotNum == gCellSfnPara[MTIMER_CPRI_ID].slotMaxNum)
{
gCellSfnPara[MTIMER_CPRI_ID].txSfnNum++;
gCellSfnPara[MTIMER_CPRI_ID].txSfnNum &= 0x3FF;
gCellSfnPara[MTIMER_CPRI_ID].txSlotNum = 0;
}
gCellSfnPara[MTIMER_CPRI_ID].txSlotTiming = GET_STC_CNT();
do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2), gCellSfnPara[MTIMER_CPRI_ID].txSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((1+(apeId<<2))<<2), gCellSfnPara[MTIMER_CPRI_ID].txSlotNum);
#if 1
if (8 > gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt)
{
debug_write((DBG_DDR_IDX_DRV_BASE+576+(4<<3)+gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt), (GET_STC_CNT())); // -gRfm0LastTxTiming)); // 0x900
gRfm0LastTxTiming = GET_STC_CNT();
}
#endif
gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+82), gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt); // 0x148
// write sm
do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intNum), APE_INT_TX_SLOT);
do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intCnt), gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt);
#if 0 //def PALLADIUM_TEST
debug_write(((DBG_DDR_IDX_DRV_BASE+448)+(gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt&0x3F)), get_tx_nr_slot(1)); // 0x700
debug_write(((DBG_DDR_IDX_DRV_BASE+512)+(gCellSfnPara[MTIMER_CPRI_ID].txSlotIntCnt&0x3F)), get_tx_nr_sfn(1)); // 0x800
#endif
}
if (tEventFlag & (1<<rxSlotTmrId)) // rx slot offset
{
uint32_t crVal = ((1<<rxSlotTmrId));
do_write(((uint32_t*)(&CPRI_TMR_TEVENT0_REG)), crVal);
do_write(flagAddr, crVal);
// update sfn and slot num
gCellSfnPara[MTIMER_CPRI_ID].rxSlotNum++;
__ucps2_synch(0);
if (gCellSfnPara[MTIMER_CPRI_ID].rxSlotNum == gCellSfnPara[MTIMER_CPRI_ID].slotMaxNum)
{
gCellSfnPara[MTIMER_CPRI_ID].rxSfnNum++;
gCellSfnPara[MTIMER_CPRI_ID].rxSfnNum &= 0x3FF;
gCellSfnPara[MTIMER_CPRI_ID].rxSlotNum = 0;
}
gCellSfnPara[MTIMER_CPRI_ID].rxSlotTiming = GET_STC_CNT();
do_write(SLOT_NUM_DEBUG_ADDR+((2+(apeId<<2))<<2), gCellSfnPara[MTIMER_CPRI_ID].rxSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((3+(apeId<<2))<<2), gCellSfnPara[MTIMER_CPRI_ID].rxSlotNum);
#if 1 //def PALLADIUM_TEST
if (8 > gCellSfnPara[MTIMER_CPRI_ID].rxSlotIntCnt)
{
debug_write((DBG_DDR_IDX_DRV_BASE+624+(4<<3)+gCellSfnPara[MTIMER_CPRI_ID].rxSlotIntCnt), (GET_STC_CNT())); // -gRfm0LastTxTiming)); // 0x900
gRfm0LastRxTiming = GET_STC_CNT();
}
#endif
gCellSfnPara[MTIMER_CPRI_ID].rxSlotIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+83), gCellSfnPara[MTIMER_CPRI_ID].rxSlotIntCnt); // 0x14c
// write sm
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intNum), APE_INT_RX_SLOT);
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intCnt), gCellSfnPara[MTIMER_CPRI_ID].rxSlotIntCnt);
}
tEventFlag = do_read_volatile(flagAddr);
}
do_write((&CPRI_TMR_INTC_REG), (1 << eventId)); // clear int
}
}
#endif

178
public/ecs_rfm_spu0/driver/src/rfm0_drv.s.c
View File

@ -1,84 +1,102 @@
#include "inter_vector.h"
#include "ucp_printf.h"
#include "rfm0_drv.h"
#include "inter_vector.h"
#include "ucp_printf.h"
#include "rfm0_drv.h"
#include "spu_hw_queue.h"
#include "phy_para.h"
#include "rfm0_mtimer.h"
#include "ape_csu.h"
#include "hwque.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ctc_intr.h"
#include "spu_log.h"
#include "phy_para.h"
#include "rfm0_mtimer.h"
#include "ape_csu.h"
#include "hwque.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ctc_intr.h"
#include "spu_log.h"
#include "app_interface.h"
/*****************************************************/
void ecs_rfm0_drv_init(void)
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
int32_t ret = 0;
#if 1
ret = smart_irq_debug_init(DBG_DDR_IRQ_ADDR_BASE+apeId*DBG_DDR_IRQ_LEN, DBG_DDR_IRQ_LEN);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 11), ret);
}
#endif
ret = smart_irq_init(apeId);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 14), ret);
}
UCP_PRINT_EMPTY("smart inter init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
ape_csu_init();
UCP_PRINT_EMPTY("ape csu init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
sfn_para_init();
UCP_PRINT_EMPTY("sfn para init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#if 0
ctc_cal_intr_init();
UCP_PRINT_EMPTY("ctc cal intr init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
rfm0_mtimer_int_init();
UCP_PRINT_EMPTY("set mtimer rfm0 int.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#endif
//ecs_hw_que_init(apeId);
//ecs_hw_que_init_withirq(apeId, apeId);
//ecs_msg_que_init(apeId);
//#ifdef ECPRI_DISTRIBUTED_BS
#include "ecpri_queue_proc.h"
#include "ecpri_csu.h"
//#endif
/*****************************************************/
void ecs_rfm0_drv_init(void)
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
int32_t ret = 0;
#if 1
ret = smart_irq_debug_init(DBG_DDR_IRQ_ADDR_BASE+apeId*DBG_DDR_IRQ_LEN, DBG_DDR_IRQ_LEN);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 11), ret);
}
#endif
ret = smart_irq_init(apeId);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 14), ret);
}
UCP_PRINT_EMPTY("smart inter init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
ape_csu_init();
UCP_PRINT_EMPTY("ape csu init. \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
sfn_para_init();
UCP_PRINT_EMPTY("sfn para init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#if 1
ctc_cal_intr_init();
UCP_PRINT_EMPTY("ctc cal intr init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
rfm0_mtimer_int_init();
UCP_PRINT_EMPTY("set mtimer rfm0 int.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
#endif
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* wait ecpri serdes clk init finished */
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR)));
/* eCPRIÑ­»·¶ÓÁгõʼ»¯ */
ecpri_queue_init();
/* eCPRI CSU³õʼ»¯ */
ecpri_csu_init();
}
ecs_hw_que_init(apeId);
//ecs_hw_que_init_withirq(apeId, apeId);
//ecs_msg_que_init(apeId);
//ecs_hw_que_init_noirq(apeId, ECS_RFM_SPU0_HW_QUEUE);
spu_log_init(LOG_ERROR);
UCP_PRINT_EMPTY("[rfm0_drv_init]: OK \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
}
UCP_PRINT_EMPTY("[rfm0_drv_init]: OK \r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(apeId<<2)), flag); // 0xA0
#endif
}

83
public/ecs_rfm_spu0/driver/src/rfm0_ecpri_timer.s.c
View File

@ -2,24 +2,21 @@
#include "ucp_drv_common.h"
#include "ucp_ecpri.h"
#include "ucp_param.h"
#include "mtimer_com.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "phy_para.h"
#include "smartos.h"
#include "rfm0_mtimer.h"
#include "inter_vector.h"
// int cnt
//UINT32 gRfm0TxSlotIntCnt = 0;
//UINT32 gRfm0RxSlotIntCnt = 0;
extern stSfnPara gCellSfnPara[2];
#if 0
void set_ecpri_timer_rfm0_int(void)
{
int32_t apeId = get_core_id();
// tx slot
uint32_t intNum = APC_ECPRI_SUB_INTR2;
int32_t ret = smart_irq_request(intNum, isr_ecpri_rfm0_slot_offset);
int32_t ret = smart_irq_request(intNum, isr_ecpri_rfm0_symbol);
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(apeId, 33), ret);
@ -27,75 +24,9 @@ void set_ecpri_timer_rfm0_int(void)
}
}
// temp to be deleted
int32_t gRfm0IntCnt2 = 0;
void isr_ecpri_rfm0_slot_offset(void)
void isr_ecpri_rfm0_symbol(void)
{
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
int32_t eventId = ECPRI_TMR_INT_RFM0_SLOT;
#ifdef PALLADIUM_TEST
// temp
gRfm0IntCnt2++;
debug_write((DBG_DDR_IDX_DRV_BASE+121), gRfm0IntCnt2); // 0x1e4
#endif
tmrIntcFlag = do_read_volatile(&ECPRI_TMR_INTC_REG);
if (tmrIntcFlag & (1 << eventId)) /* tmr int */
{
uint32_t flagAddr = (uint32_t)((uint32_t*)(&ECPRI_TMR_TINTF00_REG) + 6*ECPRI_TMR_INT_RFM0_SLOT);
int32_t txSlotTmrId = ECPRI_TMR_RFM0_TXSLOT;
int32_t rxSlotTmrId = ECPRI_TMR_RFM0_RXSLOT;
tEventFlag = do_read_volatile(flagAddr);
if (tEventFlag & ((1<<txSlotTmrId) | (1<<rxSlotTmrId)))
{
if (tEventFlag & (1<<txSlotTmrId)) // tx slot offset
{
uint32_t crVal = (1<<txSlotTmrId);
do_write(((uint32_t*)(&ECPRI_TMR_TEVENT0_REG)), crVal);
do_write(flagAddr, crVal);
gCellSfnPara[MTIMER_ECPRI_ID].txSlotNum++;
__ucps2_synch(0);
if (gCellSfnPara[MTIMER_ECPRI_ID].txSlotNum == gCellSfnPara[MTIMER_ECPRI_ID].slotMaxNum)
{
gCellSfnPara[MTIMER_ECPRI_ID].txSfnNum++;
gCellSfnPara[MTIMER_ECPRI_ID].txSfnNum &= 0x3FF;
gCellSfnPara[MTIMER_ECPRI_ID].txSlotNum = 0;
}
#ifdef PALLADIUM_TEST
gCellSfnPara[MTIMER_ECPRI_ID].txSlotIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+98), gCellSfnPara[MTIMER_ECPRI_ID].txSlotIntCnt); // 0x190
debug_write(((DBG_DDR_IDX_DRV_BASE+448)+(gCellSfnPara[MTIMER_ECPRI_ID].txSlotIntCnt&0x3F)), GET_STC_CNT()); // 0x700
#endif
}
if (tEventFlag & (1<<rxSlotTmrId)) // rx slot offset
{
uint32_t crVal = ((1<<rxSlotTmrId));
do_write(((uint32_t*)(&ECPRI_TMR_TEVENT0_REG)), crVal);
do_write(flagAddr, crVal);
gCellSfnPara[MTIMER_ECPRI_ID].rxSlotNum++;
__ucps2_synch(0);
if (gCellSfnPara[MTIMER_ECPRI_ID].rxSlotNum == gCellSfnPara[MTIMER_ECPRI_ID].slotMaxNum)
{
gCellSfnPara[MTIMER_ECPRI_ID].rxSfnNum++;
gCellSfnPara[MTIMER_ECPRI_ID].rxSfnNum &= 0x3FF;
gCellSfnPara[MTIMER_ECPRI_ID].rxSlotNum = 0;
}
#ifdef PALLADIUM_TEST
gCellSfnPara[MTIMER_ECPRI_ID].rxSlotIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+99), gCellSfnPara[MTIMER_ECPRI_ID].rxSlotIntCnt); // 0x194
debug_write(((DBG_DDR_IDX_DRV_BASE+512)+(gCellSfnPara[MTIMER_ECPRI_ID].rxSlotIntCnt&0x3F)), GET_STC_CNT()); // 0x800
#endif
}
tEventFlag = do_read_volatile(flagAddr);
}
}
do_write((&ECPRI_TMR_INTC_REG), (1 << eventId)); // clear int
mtimer_rfm0_symbol_callback(MTIMER_ECPRI_ID);
}
#endif

188
public/ecs_rfm_spu0/driver/src/rfm0_mtimer.s.c
View File

@ -4,37 +4,31 @@
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "phy_para.h"
#ifdef DISTRIBUTED_BS
#include "ucp_mtimer.h"
#include "mtimer_com.h"
//#ifdef DISTRIBUTED_BS
#include "rfm0_cpri_timer.h"
#include "rfm0_ecpri_timer.h"
#endif
#ifdef INTEGRATED_BS
#include "rfm0_jesd_timer.h"
#endif
//#endif
stPhyCellPara* pPhyCellPara = (stPhyCellPara*)PHY_CELL_ADDR;
extern stPhyScsPara* phyPara;
extern uint32_t gScsId;
extern uint32_t gMtimerId;
//extern uint32_t gScsId;
//extern uint32_t gMtimerId;
extern stSfnPara gCellSfnPara[2];
void rfm0_mtimer_int_init(void)
int32_t rfm0_mtimer_int_init(void)
{
#ifdef DISTRIBUTED_BS
if (MTIMER_CPRI_ID == gMtimerId)
{
set_cpri_timer_rfm0_int();
}
else
{
set_ecpri_timer_rfm0_int();
}
#endif
#ifdef INTEGRATED_BS
set_jesd_timer_rfm0_int(gMtimerId);
#endif
if (PROTOCOL_ECPRI == get_protocol_sel())
{
set_cpri_timer_rfm0_int();
set_ecpri_timer_rfm0_int();
}
return 0;
}
#if 0
void phy_cell_para_init(int32_t nScsId)
{
memset_ext((void*)pPhyCellPara, 0, sizeof(stPhyCellPara));
@ -52,4 +46,154 @@ void phy_cell_para_init(int32_t nScsId)
gCellSfnPara[gMtimerId].rxSlotNum = gCellSfnPara[gMtimerId].slotMaxNum - 1;
gCellSfnPara[gMtimerId].rxSfnNum = 1023;
}
#endif
int32_t gRfm0CalFlag = 0;
int32_t gRfm0CalCnt = 0;
int32_t ecs_rfm0_cal_sfn(uint8_t nTmrId)
{
int32_t apeId = get_core_id();
int32_t scsId = 0;
int32_t i = 0;
if (1 == gCellSfnPara[nTmrId].ctcIntFlag)
{
for (i = 0; i < PHY_SCS_MAX_NUM; i++)
{
if (nTmrId == do_read_volatile_short(&(phyPara[i].mtimerId))) // 已建了第一个子载波小区
{
gCellSfnPara[nTmrId].scsId = i;
scsId = i;
break;
}
}
if (PHY_SCS_MAX_NUM == i)
{
return -1;
}
gCellSfnPara[nTmrId].ctcIntFlag = 0;
gCellSfnPara[nTmrId].slotPeriod = do_read_volatile_short(&(phyPara[scsId].slotPeriod)); // 500; //
gCellSfnPara[nTmrId].tddSlotNum = do_read_volatile_short(&(phyPara[scsId].slotNumOfTdd)); // 10; //
gCellSfnPara[nTmrId].slotMaxNum = do_read_volatile_short(&(phyPara[scsId].slotNumOfSfn)); // 20; //
gCellSfnPara[nTmrId].txSfnNum = do_read_volatile(&(phyPara[scsId].txSfnNum));
gCellSfnPara[nTmrId].rxSfnNum = do_read_volatile(&(phyPara[scsId].rxSfnNum));
gCellSfnPara[nTmrId].txSlotNum = do_read_volatile(&(phyPara[scsId].txSlotNum));
gCellSfnPara[nTmrId].rxSlotNum = do_read_volatile(&(phyPara[scsId].rxSlotNum));
gCellSfnPara[nTmrId].txSymbolNum = 0;
gCellSfnPara[nTmrId].txSymbolIntCnt = 0;
gCellSfnPara[nTmrId].txSlotIntCnt = 0;
gCellSfnPara[nTmrId].rxSlotIntCnt = 0;
gRfm0CalFlag = 1;
gRfm0CalCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+544+apeId), gRfm0CalCnt); // 0x880
debug_write((DBG_DDR_IDX_DRV_BASE+556+apeId), GET_STC_CNT()); // 0x8b0
#endif
}
return 0;
}
uint32_t lastTxStcCnt = 0;
uint32_t nowTxStcCnt = 0;
uint32_t rfm0SymbolErrCnt = 0;
uint32_t rfm0SymbolInterMax = 0;
int32_t mtimer_rfm0_symbol_callback(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = 0;
if (MTIMER_CPRI_ID == nTmrId)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
}
else
{
return -1;
}
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
uint32_t tEventAddr = 0;
uint32_t tFlagAddr = 0;
stSfnPara* pSfnPara = &gCellSfnPara[nTmrId];
int32_t apeId = get_core_id();
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG);
if ((tmrIntcFlag & (1 << MTMR_INT_RFM0_SLOT))) /* symbol int */
{
tFlagAddr = tmrBaseAddr + MTMR_TINTF00_REG + 6*(MTMR_INT_RFM0_SLOT<<2) + 2*((MTMR_ECPRI_TX_SYMBOL0>>5)<<2); // MTMR_TINTF01_REG
tEventAddr = tmrBaseAddr+MTMR_TEVENT0_REG + ((MTMR_ECPRI_TX_SYMBOL0>>5)<<2);
tEventFlag = do_read_volatile(tFlagAddr);
if (tEventFlag & 0x3FFF) // 14symbols // tx symbol offset int
{
do_write(tEventAddr, tEventFlag);
do_write(tFlagAddr, tEventFlag); // clear int flag
pSfnPara->txSymbolIntCnt++;
//uint32_t addr = 0;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+2048+32+nTmrId), pSfnPara->txSymbolIntCnt); // 0xb7e08080
#endif
ecs_rfm0_cal_sfn(nTmrId);
pSfnPara->txSymbolNum++;
__ucps2_synch(0);
if (pSfnPara->txSymbolNum == SLOT_SYMBOL_NUM)
{
pSfnPara->txSlotNum++;
if (pSfnPara->txSlotNum == pSfnPara->slotMaxNum)
{
pSfnPara->txSfnNum++;
pSfnPara->txSfnNum &= 0x3FF;
pSfnPara->txSlotNum = 0;
}
pSfnPara->txSymbolNum = 0;
}
__ucps2_synch(0);
if (MTIMER_CPRI_ID == nTmrId)
{
do_write(SLOT_NUM_DEBUG_ADDR+(((apeId-1)<<2)<<2), pSfnPara->txSymbolNum);
do_write(SLOT_NUM_DEBUG_ADDR+((apeId<<2)<<2), pSfnPara->txSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((1+(apeId<<2))<<2), pSfnPara->txSlotNum);
do_write(SLOT_NUM_DEBUG_ADDR+((2+(apeId<<2))<<2), pSfnPara->rxSfnNum);
do_write(SLOT_NUM_DEBUG_ADDR+((3+(apeId<<2))<<2), pSfnPara->rxSlotNum);
}
#if 1
nowTxStcCnt = GET_STC_CNT();
debug_write(((DBG_DDR_IDX_DRV_BASE+2048+128) + (gCellSfnPara[nTmrId].txSymbolIntCnt&0x3F)), nowTxStcCnt); // 0xb7e08200
//debug_write(((DBG_DDR_IDX_DRV_BASE+2048+192) + (gCellSfnPara[nTmrId].txSymbolIntCnt&0x3F)), get_tx_nr_slot(NR_SCS_30K)); // 0x800
if ((nowTxStcCnt > lastTxStcCnt) && (2 < gCellSfnPara[nTmrId].txSlotIntCnt))
{
uint32_t cost = nowTxStcCnt - lastTxStcCnt;
//debug_write(((DBG_DDR_IDX_DRV_BASE+576) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), nowTxStcCnt); // 0x900
//debug_write(((DBG_DDR_IDX_DRV_BASE+640) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), cost); // 0xa00
if (((gCellSfnPara[nTmrId].slotPeriod*1000+5000) < cost) || ((gCellSfnPara[nTmrId].slotPeriod*1000-5000) > cost))
{
rfm0SymbolErrCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+64+(nTmrId<<2)), rfm0SymbolErrCnt); // 0xb7e08100
}
if (rfm0SymbolInterMax < cost)
{
rfm0SymbolInterMax = cost;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+65+(nTmrId<<2)), rfm0SymbolInterMax); // 0xb7e08104
}
}
lastTxStcCnt = nowTxStcCnt;
#endif
tEventFlag = do_read_volatile(tFlagAddr);
}
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_RFM0_SLOT)); // clear int
}
return 0;
}

22
public/ecs_rfm_spu0/top/src/main.s.c
View File

@ -19,6 +19,9 @@
#include "ucp_utility.h"
#include "spu_shell.h"
#include "hwque.h"
#include "phy_para.h"
#include "ecpri_queue_proc.h"
#include "ecpri_csu.h"
int32_t main(int32_t argc, char* argv[])
{
@ -28,7 +31,7 @@ int32_t main(int32_t argc, char* argv[])
/* hw_debug_init */
int32_t core_id = get_core_id();
int ret = 0;
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // 推荐384，实际512
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // 鎺ㄨ崘384锛屽疄闄?512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);
@ -42,8 +45,21 @@ int32_t main(int32_t argc, char* argv[])
spu_shell_init();
while(1) {
//
while (1)
{
if (PROTOCOL_ECPRI == get_protocol_sel())
{
/* eCPRI循环队列轮询处理 */
ecpri_queue_proc();
/* 手动触发eCPRI CSU发送数据测试 */
if (1 == do_read_volatile(ECPRI_DBG_BUF_ADDR + 0x0C))
{
ecpri_csu_send_test();
do_write(ECPRI_DBG_BUF_ADDR + 0x0C, 0x00);
}
}
}
return 0;

3
public/ecs_rfm_spu1/driver/inc/HeaderRam.h
View File

@ -1,4 +1,6 @@
#ifndef __HEADERRAM_H__
#define __HEADERRAM_H__
#include "cpri_csu.h"
@ -16,3 +18,4 @@
void Cpri_Header_Tx(void);
#endif

2
public/ecs_rfm_spu1/driver/inc/cpri_csu.h
View File

@ -38,6 +38,7 @@
//#define CSU_TX_DUMMY_ADDR 0x90000000
//#define CSU_RX_DUMMY_ADDR 0x98000000
#if 0
#ifdef CPRI_TIMING_7D2U_TEST
#ifdef CPRI_10G_TEST//option8
#define ID_NUM 6
@ -106,6 +107,7 @@
#define ID_NUM_TIMING 9
#define HYPER_FRAME_NUM 150 // 10 //15
#endif
#endif
#define ID_DATA_STEP 0x12C000 // 0x258000 // 0x3C000

6
public/ecs_rfm_spu1/driver/inc/cpri_driver.h
View File

@ -30,7 +30,8 @@ void jecspma_recrx_eq();
void jecspma_recrx_reset();
void config_cpri_map_directed(uint32_t cpri_speed_sel);
//void config_cpri_map_directed(uint32_t cpri_speed_sel);
void config_cpri_map_directed(uint32_t option,uint32_t MappingMode);
void start_cpri_map(void);
void stop_cpri_map(void);
@ -61,6 +62,3 @@ uint32_t UCP_API_CPRI_GetTxXCnt();
uint32_t UCP_API_CPRI_GetRxHfnCnt();

4
public/ecs_rfm_spu1/driver/inc/cpri_timer.h
View File

@ -41,6 +41,8 @@ typedef enum _tagCpriPP1sSrc{
CPRI_PP1S_SRC_STC = 6
}numCpriPP1sSrc;
void cpri_timer_ecprimode_clk_init();
void cpri_mtimer_init(int32_t nScsId, int32_t nTddSlotNum);
void cpri_timer_init(void);
@ -82,6 +84,8 @@ void clear_cpri_lte_fapi_offset(void);
int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId);
int32_t clear_cpri_ape_slot_offset(uint32_t apeCoreId);
int32_t set_cpri_tx_symbol_offset(uint8_t symbolId);
void set_cpri_timer_int(void);

47
public/ecs_rfm_spu1/driver/inc/ecpri_driver.h Normal file
View File

@ -0,0 +1,47 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_driver.h
* Create Date: 23/08/18
* Description: eCPRI Driver Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_DRIVER_H_
#define _ECPRI_DRIVER_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ucp_js_subcrg.h"
#include "ucp_param.h"
#include "ecpri_pma.h"
#include "ecpri_roec.h"
#include "ecpri_switch.h"
#include "phy_para.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
void ecpri_init(uint8_t nOption);
void ecpri_cprimode_init();
extern void ecpri_init_ex(uint32_t ecpri_speed_sel);
#endif /* _ECPRI_DRIVER_H_ */

50
public/ecs_rfm_spu1/driver/inc/ecpri_pma.h Normal file
View File

@ -0,0 +1,50 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_pma.h
* Create Date: 23/08/18
* Description: eCPRI PMA Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_PMA_H_
#define _ECPRI_PMA_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ucp_js_subcrg.h"
#include "ucp_pma.h"
#include "ucp_js_ctrl.h"
#include "ucp_utility.h"
#include "ucp_drv_common.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
extern DDR0 uint32_t pma_fw[16384*2];
/* eCPRI ROEC init */
extern void ecpri_pcs_rst_ctrl_ex(void);
extern void init_ecpri_pma_rst_ex(void);
extern void init_pma_commonconfig_ex(uint32_t ecpri_speed_sel);
extern void init_jecspma(uint32_t ecpri_speed_sel);
extern void init_jecspma_rxtx(void);
extern void ecpri_pma_rx_adapt(void);
#endif /* _ECPRI_PMA_H_ */

50
public/ecs_rfm_spu1/driver/inc/ecpri_roec.h Normal file
View File

@ -0,0 +1,50 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_roec.h
* Create Date: 23/08/18
* Description: eCPRI ROEC Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_ROEC_H_
#define _ECPRI_ROEC_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ucp_ecpri.h"
#include "ucp_param.h"
#include "ucp_utility.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* eCPRI buffer physical address */
#define ECPRI_BUF_PHY_ADDR 0xAEE00000
/* eCPRI buffer length */
#define ECPRI_BUF_LEN 0x04000000
/* 502 verify case define data */
#define OTHER_DES_ADDR 0xAEE00000ul // 0xAEE00000ul // 0x09d00000ul
#define OTHER_DES_SIZE 0x03E00000ul // 0x03F00000ul // 0x00100000ul
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI ROEC init */
extern void ecpri_roec_init(void);
#endif /* _ECPRI_ROEC_H_ */

46
public/ecs_rfm_spu1/driver/inc/ecpri_switch.h Normal file
View File

@ -0,0 +1,46 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_switch.h
* Create Date: 23/08/18
* Description: eCPRI SWITCH Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_SWITCH_H_
#define _ECPRI_SWITCH_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include <stdbool.h>
#include "ucp_ecpri.h"
#include "ucp_param.h"
#include "ucp_utility.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
/* operation result */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef ERROR
#define ERROR (-1)
#endif
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI ROEC init */
extern void ecpri_pcs_init(uint32_t ecpri_speed_sel);
extern void ecpri_mac_init(uint32_t ecpri_speed_sel);
extern void ecpri_switch_init(uint32_t ecpri_speed_sel);
/* eCPRI PCS link status get */
extern bool ecpri_pcs_link_status_get(void);
#endif /* _ECPRI_SWITCH_H_ */

19
public/ecs_rfm_spu1/driver/inc/ecpri_timer.h
View File

@ -4,11 +4,8 @@
#include "typedef.h"
#include "phy_para.h"
//extern stPhyScsPara* phyPara;
//stEcpriTimerPara gEcpriTmrPara;
//stCpriDelayMeasure cpriDelay;
#define ECPRI_SYMBOL_LONGCP 4448
#define ECPRI_SYMBOL_SHORTCP 4384
/*
ecpri的pp1s选择信号;
3’b000:表示选择gmac_pps;
@ -27,19 +24,12 @@ typedef enum _tagEcpriPP1sSrc{
ECPRI_PP1S_SRC_STC = 6
}numEcpriPP1sSrc;
void ecpri_init();
void init_ecpri_clk(void);
void init_ecpri_pma_rst(void);
void ecpri_pcs_rst_ctrl();
void ecpri_mtimer_init(int32_t nScsId, int32_t nTddSlotNum);
void ecpri_timer_init(int32_t nScsId, int32_t nTddSlotNum);
void ecpri_timer_cprimode_clk_init();
void ecpri_timer_clear_all_event();
void ecpri_1pps_src_init(uint8_t srcId);
@ -72,6 +62,7 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId);
int32_t clear_ecpri_ape_slot_offset(uint32_t apeCoreId);
int32_t set_ecpri_tx_symbol_offset(uint8_t symbolId);
void start_ecpri_timer(void);

1
public/ecs_rfm_spu1/driver/inc/jesd_timer.h
View File

@ -3,7 +3,6 @@
#include "typedef.h"
#include "phy_para.h"
//#include "dw_apb_gpio.h"
#define JESD_TXRX_CHANGE_GAP 13
#define JESD_RF_ON_GAP 8

3
public/ecs_rfm_spu1/driver/inc/mtimer_cell.h
View File

@ -5,7 +5,7 @@
#include "ucp_drv_common.h"
#include "phy_para.h"
void phy_cell_para_init(int32_t nScsId);
//void phy_cell_para_init(int32_t nScsId);
void mtimer_init4phy(phy_timer_config_ind_t *mtmr);
@ -15,5 +15,4 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr);
// 删小区，先通知APE删除任务和定时点，再走ecs rfm1的删小区流程
int32_t mtimer_del_cell_cfg(stPhyDelCell* delCell);
#endif /* CPRI_CELL_H_ */

1
public/ecs_rfm_spu1/driver/inc/rfm1_drv.h
View File

@ -9,6 +9,5 @@ void check_phy_cell(void);
void check_10ms_offset(void);
void HeaderTxRam_init();
#endif

7
public/ecs_rfm_spu1/driver/src/HeaderRam.s.c
View File

@ -11,13 +11,12 @@
#include "cpri_timer.h"
#include "HeaderRam.h"
#ifdef DISTRIBUTED_BS
#ifdef TEST_ENABLE
#include "cpri_test.h"
#endif
#endif
uint32_t HeaderTxtimes = 0;
volatile uint32_t gVendorFlag;
void Cpri_Header_Tx(void)
@ -27,7 +26,8 @@ void Cpri_Header_Tx(void)
uint32_t j= 0;
uint32_t CurrentHfnCnt =0;
if(NR4T4R_7DS2U == gVendorFlag)
{
CurrentHfnCnt = UCP_API_CPRI_GetTxHfnCnt();
HeaderTxtimes++;
@ -70,6 +70,7 @@ void Cpri_Header_Tx(void)
debug_write((DBG_DDR_IDX_CPRI_BASE+141), do_read_volatile(&AUX_CNT0));
}
debug_write((DBG_DDR_IDX_CPRI_BASE+144), CurrentHfnCnt);
}
}

5
public/ecs_rfm_spu1/driver/src/cpri_csu.s.c
View File

@ -25,7 +25,7 @@ int32_t cpri_csu_task_lookup(uint8_t task_tag)
{
return (do_read_volatile((uint32_t*)(&JECS_CSU_DMASTATUS)) & (task_tag));
}
#if 0
void cpri_csu_axc_init_notiming(void)
{
uint32_t basic_frame_byte = 0;
@ -664,6 +664,7 @@ void cpri_csu_axc_link_init_timing()
memcpy_ext(pLinkDesc, &stLinkDesc, sizeof(stCsuLinkDesc1L3D));
}
}
#endif
void cpri_csu_axcctrl_init_timing()
{
@ -820,6 +821,7 @@ void cpri_csu_start_timing(void)
#endif
}
#if 0
void cpri_csu_axc_init_7d2u(void)
{
uint32_t basic_frame_byte = 0;
@ -1710,5 +1712,6 @@ void cpri_csu_start_timing_7d2u(void)
JECS_CSU_CMDHIGHDATA = 0;
JECS_CSU_CMDFIFO3 = (1<<4)+(1<<5)+(22<<8)+(23<<13)+(2<<18); // 普通DMA，多维传输，cache模式，sbuffid=22,dbuffid=23,tag=2
}
#endif

26
public/ecs_rfm_spu1/driver/src/cpri_delay.s.c
View File

@ -19,15 +19,15 @@ uint32_t gCpriDelayOamSetFlag = 0;
void cpri_delay_init()
{
stCpriDelayMeasure* pCpriDelay = NULL; // pEcsDmLocalMgt->pCpriDelay;
uint16_t gpsOffset = 0;
#ifdef DISTRIBUTED_BS
uint16_t gpsOffset = 0;
//#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
uint32_t addr = (uint32_t)&(phyPara[pMtimerPara->scsId].gpsOffset);
gpsOffset = do_read_volatile_short(addr);
#endif
//#endif
if (NULL == pCpriDelay)
{
return;
@ -71,10 +71,10 @@ void cpri_delay_measurement()
stCpriDelayMeasure* pCpriDelay = NULL; // pEcsDmLocalMgt->pCpriDelay;
stFhAlarmStat* pAlarmStat = pEcsDmLocalMgt->pAlarmStatus;
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
pCpriPara = pEcsDmLocalMgt->pCpriPara;
pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
#endif
//#endif
if (NULL == pCpriPara || NULL == pCpriDelay)
{
return;
@ -356,11 +356,11 @@ void cpri_delay_measurement_ck()
stCpriPara* pCpriPara = NULL; // pEcsDmLocalMgt->pCpriPara;
stCpriDelayMeasure* pCpriDelay = NULL; // pEcsDmLocalMgt->pCpriDelay;
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
pCpriPara = pEcsDmLocalMgt->pCpriPara;
pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
#endif
//#endif
if (NULL == pCpriPara || NULL == pCpriDelay)
{
return;
@ -408,10 +408,10 @@ stCpriSetDelayRsp* set_cpri_link_delay(stCpriSetLinkDelay* pCpriSetDelay)
memset(&gCpriSetDelayRep, 0, sizeof(stCpriSetDelayRsp));
gCpriSetDelayRep.u8fiber_port = pCpriSetDelay->u8fiber_port;
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
#endif
//#endif
if (NULL == pCpriDelay)
{
gCpriSetDelayRep.u8result = 0;
@ -438,10 +438,10 @@ void get_cpri_link_delay(uint8_t u8fiber_port, stCpriGetLinkDelay* pCpriGetDelay
}
stCpriDelayMeasure* pCpriDelay = NULL; // pEcsDmLocalMgt->pCpriDelay;
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
#endif
//#endif
if (NULL == pCpriDelay)
{
pCpriGetDelay->u8result = 0; // fail
@ -464,10 +464,10 @@ void get_cpri_rndtrip_delay(uint8_t u8fiber_port, stCpriGetRndDelay* pCpriRndDea
}
stCpriDelayMeasure* pCpriDelay = NULL; // pEcsDmLocalMgt->pCpriDelay;
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
#endif
//#endif
if (NULL == pCpriDelay)
{
pCpriRndDealy->u8result = 0; // fail

727
public/ecs_rfm_spu1/driver/src/cpri_driver.s.c
View File

@ -2304,7 +2304,7 @@ void jecspma_recrx_eq()
uint32_t j=0;
init_jecspma_recrx();
//for(uint32_t i = 0;i<10 ; i++)
while(1)
// while(1)
{
i++;
//rx adapt eq
@ -2380,7 +2380,7 @@ void jecspma_recrx_eq()
#endif
debug_write((DBG_DDR_IDX_CPRI_BASE+1), i);
debug_write((DBG_DDR_IDX_CPRI_BASE+2), j);
#if 1
#if 0
//ucp_nop(400);
//if(0xA0 < (((do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK))>>8) & 0xFF))
@ -2506,13 +2506,48 @@ void jecspma_recrx_reset()
}
#if 0
uint32_t resynctimes = 0;
delay_us(10000);
for(uint32_t i=0;i<500;i++)
{
if(do_read_volatile(&CPRI_FRAME_RX_STAT) != 0x1E)
{
resynctimes++;
jecspma_recrx_eq();
debug_write((DBG_DDR_IDX_CPRI_BASE+3), i);
debug_write((DBG_DDR_IDX_CPRI_BASE+7), resynctimes);
}
else
{
delay_us(1000);
}
}
#endif
}
void init_cpri(uint32_t cpri_speed_sel)
{
uint32_t resynctimes = 0;
// uint32_t resynctimes = 0;
//JECS_CTRL_PROTOCOL_SEL = JECS_CTRL_PROTOCOL_SEL | BIT4;//cpri tx pma sel jecs
do_write(&JECS_CTRL_PROTOCOL_SEL, do_read_volatile(&JECS_CTRL_PROTOCOL_SEL) | BIT4);
#if 0
/************************************
配置光模块使能：PD16/AP_GPIO0B29
低：光模块发射打开
高：光模块发射关闭
*****************************************/
// do_write((GPIO0_A29_PINMUX_REG_ADDR+0xc), (do_read_volatile((GPIO0_A29_PINMUX_REG_ADDR+0xc))|0x3));
do_write((0x0445818c), (do_read_volatile(0x0445818c)|0x3));//pinmux
__ucps2_synch(f_SM);
do_write((0x04450010), (do_read_volatile(0x04450010)|(BIT29))); //dir:1:out;0:in
__ucps2_synch(f_SM);
do_write((0x0445000c), (do_read_volatile(0x0445000c)&(~(BIT29)))); // data:0
__ucps2_synch(f_SM);
delay_us(1000);
#endif
init_cpri_pma_rst();
Init_cpri_clk(cpri_speed_sel);
@ -2601,8 +2636,11 @@ void init_cpri(uint32_t cpri_speed_sel)
else
{
}
jecspma_recrx_eq();
#if 1
#if 0
delay_us(10000);
for(uint32_t i=0;i<3000;i++)
{
@ -2621,359 +2659,270 @@ void init_cpri(uint32_t cpri_speed_sel)
#endif
do_write(&ALARM_FLAG,0x0);
}
void config_cpri_map_directed(uint32_t cpri_speed_sel)
DDR0 uint32_t ID_SIZE_buf[3][16] = {
{1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0},
{1,1,8,8,8,8,2,2,1,0,0,0,0,0,0,0},
{1,1,8,8,8,8,8,8,8,8,1,0,0,0,0,0}
};
uint32_t ID_SIZE[16]={0};
void config_cpri_map_directed(uint32_t option,uint32_t MappingMode)
{
uint64_t addr;
#if 0
if(8 == cpri_speed_sel)
{
#ifdef CPRI_TIMING_7D2U_TEST
ID_SIZE[16] = {1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0};
#endif
uint64_t addr;
#ifdef CPRI_TIMING_LTE_FDD_TEST
ID_SIZE[16] = {1,1,8,8,8,8,2,2,1,0,0,0,0,0,0,0};
#endif
}
// if(SIZE_SUM > MAX_SIZE){
// printf("CONFIGURATION ERR:SIZE SUM EXCEED MAX SIZE IN ONE BASIC FRAME!");
else if(10 == cpri_speed_sel)
if(8 == option)
{
ID_SIZE[16] = {1,1,8,8,8,8,8,8,8,8,1,0,0,0,0,0};
// ERR();
}
#endif
// printf("START TO INIT CPRI MAP DIRECTED,SIZE_SUM=",SIZE_SUM);
// printf("MAP_START_ID=",MAP_START_ID);
//axc rx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< ID0_SIZE*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+0; //id 0
}
else if(addr< (ID0_SIZE+ID1_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+1; //id 1
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+2; //id 2
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+3; //id 3
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+4; //id 4
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+5; //id 5
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+6; //id 6
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+7; //id 7
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+8; //id 8
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+9; //id 9
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+10; //id 10
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+11; //id 11
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+12; //id 12
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE+ID13_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+13; //id 13
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE+ID13_SIZE+ID14_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+14; //id 14
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE+ID13_SIZE+ID14_SIZE+ID15_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+15; //id 15
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = 0;
}
}
//axc tx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< ID0_SIZE*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID0_SIZE<<16) + ((addr/4)<<8) + BIT7+0; //id 0
}
else if(addr< (ID0_SIZE+ID1_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID1_SIZE<<16) + ((addr/4)<<8) + BIT7+1; //id 1
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID2_SIZE<<16) + ((addr/4)<<8) + BIT7+2; //id 2
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID3_SIZE<<16) + ((addr/4)<<8) + BIT7+3; //id 3
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID4_SIZE<<16) + ((addr/4)<<8) + BIT7+4; //id 4
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID5_SIZE<<16) + ((addr/4)<<8) + BIT7+5; //id 5
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID6_SIZE<<16) + ((addr/4)<<8) + BIT7+6; //id 6
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID7_SIZE<<16) + ((addr/4)<<8) + BIT7+7; //id 7
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID8_SIZE<<16) + ((addr/4)<<8) + BIT7+8; //id 8
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID9_SIZE<<16) + ((addr/4)<<8) + BIT7+9; //id 9
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID10_SIZE<<16) + ((addr/4)<<8) + BIT7+10; //id 10
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID11_SIZE<<16) + ((addr/4)<<8) + BIT7+11; //id 11
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID12_SIZE<<16) + ((addr/4)<<8) + BIT7+12; //id 12
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE+ID13_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID13_SIZE<<16) + ((addr/4)<<8) + BIT7+13; //id 13
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE+ID13_SIZE+ID14_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID14_SIZE<<16) + ((addr/4)<<8) + BIT7+14; //id 14
}
else if(addr< (ID0_SIZE+ID1_SIZE+ID2_SIZE+ID3_SIZE+ID4_SIZE+ID5_SIZE+ID6_SIZE+ID7_SIZE+ID8_SIZE+ID9_SIZE+ID10_SIZE+ID11_SIZE+ID12_SIZE+ID13_SIZE+ID14_SIZE+ID15_SIZE)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID15_SIZE<<16) + ((addr/4)<<8) + BIT7+15; //id 15
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = 0;
}
}
#ifdef CPRI_TIMING_7D2U_TEST
//map tx cfg
// printf("START TO INIT MAP TX AXC CFG!");
if(8 == cpri_speed_sel)
{
for(addr = 0; addr<0x400;addr = addr +4)
if(NR4T4R_7DS2U == MappingMode)
{
if(addr< 5*4)
{
// op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8+1)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
//(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0;
}
//ID_SIZE[16] = {1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0};
memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64);
}
//map rx cfg
// printf("START TO INIT MAP RX AXC CFG!");
else if(NR4T4R_LTE2T2R_FDD == MappingMode)
{
memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[1], 64);
// ID_SIZE[16] = {1,1,8,8,8,8,2,2,1,0,0,0,0,0,0,0};
}
}
else if(10 == option)
{
if(NR2_4T4R_7DS2U == MappingMode)
{
memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[2], 64);
// ID_SIZE[16] = {1,1,8,8,8,8,8,8,8,8,1,0,0,0,0,0};
}
}
else
{
//ID_SIZE[16] = {1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0};//默认NR4T4R_7DS2U option8
memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64);
}
//axc rx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 5*4)
if(addr< ID_SIZE[0]*4)
{
// op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2)*4)
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+0; //id 0
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64)*4)
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+1; //id 1
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8)*4)
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+2; //id 2
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8+1)*4)
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+3; //id 3
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
//(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0;
}
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+4; //id 4
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+5; //id 5
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+6; //id 6
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+7; //id 7
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+8; //id 8
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+9; //id 9
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+10; //id 10
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+11; //id 11
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+12; //id 12
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+13; //id 13
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+14; //id 14
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14]+ID_SIZE[15])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = ((addr/4)<<8) + BIT7+15; //id 15
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0xC00)) = 0;
}
}
}
if( 10== cpri_speed_sel)
//axc tx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< ID_SIZE[0]*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[0]<<16) + ((addr/4)<<8) + BIT7+0; //id 0
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[1]<<16) + ((addr/4)<<8) + BIT7+1; //id 1
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[2]<<16) + ((addr/4)<<8) + BIT7+2; //id 2
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[3]<<16) + ((addr/4)<<8) + BIT7+3; //id 3
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[4]<<16) + ((addr/4)<<8) + BIT7+4; //id 4
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[5]<<16) + ((addr/4)<<8) + BIT7+5; //id 5
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[6]<<16) + ((addr/4)<<8) + BIT7+6; //id 6
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[7]<<16) + ((addr/4)<<8) + BIT7+7; //id 7
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[8]<<16) + ((addr/4)<<8) + BIT7+8; //id 8
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[9]<<16) + ((addr/4)<<8) + BIT7+9; //id 9
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[10]<<16) + ((addr/4)<<8) + BIT7+10; //id 10
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[11]<<16) + ((addr/4)<<8) + BIT7+11; //id 11
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[12]<<16) + ((addr/4)<<8) + BIT7+12; //id 12
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[13]<<16) + ((addr/4)<<8) + BIT7+13; //id 13
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[14]<<16) + ((addr/4)<<8) + BIT7+14; //id 14
}
else if(addr< (ID_SIZE[0]+ID_SIZE[1]+ID_SIZE[2]+ID_SIZE[3]+ID_SIZE[4]+ID_SIZE[5]+ID_SIZE[6]+ID_SIZE[7]+ID_SIZE[8]+ID_SIZE[9]+ID_SIZE[10]+ID_SIZE[11]+ID_SIZE[12]+ID_SIZE[13]+ID_SIZE[14]+ID_SIZE[15])*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = (ID_SIZE[15]<<16) + ((addr/4)<<8) + BIT7+15; //id 15
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x1000)) = 0;
}
}
if(8 == option)
{
//map tx cfg
// printf("START TO INIT MAP TX AXC CFG!");
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 12*4)
if(NR4T4R_7DS2U == MappingMode)//#ifdef CPRI_TIMING_7D2U_TEST
{
//map tx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
// op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
if(addr< 11*4)
if(addr< 5*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
// op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8+1)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
//(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0;
}
}
else if(addr< (12+2)*4)//compress
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (48<<8)+(1<<14)+(32<<16)+(1<<22)+(0<<24)+(3<<30); //need to confirm location
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64)*4)//NR小区0
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64)*4)//NR小区1
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64+49)*4)//Reserve
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else if(addr< (12+2+64+64+49+1)*4)//Agc
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0;
}
}
//map rx cfg
//printf("START TO INIT MAP RX AXC CFG!");
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 12*4)
{ // op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2)*4)//compress
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//Compress NR小区0
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(48<<16)+(2<<22)+(0<<24)+(3<<30);//Compress NR小区1
}
else if(addr< (12+2+64)*4)//NR小区0
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64)*4)//NR小区1
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64+49)*4)//Reserve
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else if(addr< (12+2+64+64+49+1)*4)//AGC
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0;
}
}
}
#endif
#ifdef CPRI_TIMING_LTE_FDD_TEST
//#if 1
//map tx cfg
// printf("START TO INIT MAP TX AXC CFG!");
if(cpri_speed_sel == 8)
//map rx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 5*4)
{
// op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (5+2+64+8+1)*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
//(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0;
}
}
}
if(NR4T4R_LTE2T2R_FDD == MappingMode)
{
//map tx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 5*4)
@ -3024,10 +2973,8 @@ void config_cpri_map_directed(uint32_t cpri_speed_sel)
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0;
}
}
//map rx cfg
//printf("START TO INIT MAP RX AXC CFG!");
//map rx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 5*4)
@ -3068,7 +3015,105 @@ void config_cpri_map_directed(uint32_t cpri_speed_sel)
}
}
}
#endif
}
if(10 == option)
{
if(NR2_4T4R_7DS2U == MappingMode)
{
//map tx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 12*4)
{
// op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
if(addr< 11*4)
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
}
else if(addr< (12+2)*4)//compress
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (48<<8)+(1<<14)+(32<<16)+(1<<22)+(0<<24)+(3<<30); //need to confirm location
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64)*4)//NR小区0
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64)*4)//NR小区1
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(0<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64+49)*4)//Reserve
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0 + BIT4 + BIT5 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else if(addr< (12+2+64+64+49+1)*4)//Agc
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 1 + BIT4 + BIT5 + (32<<8)+(1<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x800)) = 0;
}
}
//map rx cfg
for(addr = 0; addr<0x400;addr = addr +4)
{
if(addr< 12*4)
{ // op 0:pass 1:right 2:left 3:clr
//EN INC VALID AREG SHIFT OP BREG SHIFT OP CREG SHIFT OP
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2)*4)//compress
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//Compress NR小区0
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(3<<14)+(48<<16)+(2<<22)+(0<<24)+(3<<30);//Compress NR小区1
}
else if(addr< (12+2+64)*4)//NR小区0
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64)*4)//NR小区1
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);
addr = addr +4;
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (0<<8)+(0<<14)+(32<<16)+(2<<22)+(0<<24)+(3<<30);
}
else if(addr< (12+2+64+64+49)*4)//Reserve
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + 0 + 0 + (0<<8)+(3<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else if(addr< (12+2+64+64+49+1)*4)//AGC
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 1 + BIT4 + BIT5 + (32<<8)+(2<<14)+(0<<16)+(3<<22)+(0<<24)+(3<<30);//need to confirm location
}
else
{
(*(volatile uint32_t * )(addr+CPRI_CPU_BASE + 0x400)) = 0;
}
}
}
}
CPRI_MAP_TOGGLE = BIT0;
//start_cpri_map();
}

2
public/ecs_rfm_spu1/driver/src/cpri_test_mode.s.c
View File

@ -637,7 +637,6 @@ void cpri_test_mode(uint32_t testmode)
void check_cpri(void)
{
#ifdef DISTRIBUTED_BS
test_cnt1++;
if(1 == test_cnt1)
@ -700,7 +699,6 @@ void check_cpri(void)
{
}
debug_write((DBG_DDR_IDX_CPRI_BASE+1025), test_cnt1); // 0xb7e29004
#endif
}

260
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -27,18 +27,12 @@
#include "cpri_driver.h"
#include "cpri_csu_api.h"
//#include "cpri_csu_nr_7ds2u.h"
#ifdef DISTRIBUTED_BS
#ifdef TEST_ENABLE
#include "cpri_test.h"
uint32_t Tdd_Offset_Int_Falg =0;
#endif
#endif
extern stPhyScsPara* phyPara;
extern stSfnPara gCellSfnPara[2];
//extern stSfnPara gCellSfnPara[2];
extern uint32_t gScsId;
extern uint32_t gMtimerId;
@ -64,10 +58,25 @@ extern uint32_t gCpriDelayOamSetFlag;
extern void rfm1_fapi_callback();
#ifdef DISTRIBUTED_BS
volatile uint32_t reCfgFlag = 0;
void cpri_timer_ecprimode_clk_init()
{
// bit26: cpri_pma_clk_sel, A: cpri_serdes_tx_clk, B: cpri_div33_tx_clk
// bit25: cpri_div33_clk_sel, A: jecs_pma_tx0_ropll_div33_clk, B: pet_tx_ropll_div33_clk
// bit24: cpri_core_clk_sel1, A: tmp_cpri_clk, B: cpri_pma_clk
// bit23: cpri_core_clk_sel0
// bit22: cpri_tx_clk_sel
do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT26|BIT24));
// cpri_core_reset
do_write(&JECS_CRG_CPRI4_RST_CTRL, do_read_volatile(&JECS_CRG_CPRI4_RST_CTRL) | BIT24);
// cpri core clk div
do_write(&JECS_CRG_CPRI_CORE_CLK_CTRL, 0x521000);
}
void cpri_mtimer_init(int32_t nScsId, int32_t nTddSlotNum)
{
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
@ -103,17 +112,17 @@ void cpri_timer_init()
void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
{
int32_t apeId = get_core_id();
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
int32_t flag = 0x10;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBc
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
uint8_t nBsType = get_protocol_sel();
// get cpri delay
#ifdef DISTRIBUTED_BS
stCpriDelayMeasure* pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
#endif
uint32_t tempOffset;
if (0 == gCpriDelayOamSetFlag)
@ -144,22 +153,28 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
reCfgFlag = 1;
set_cpri_tx_rfp();
// if (do_read_volatile(CPRI_ADVANCE_ADDR) != (FIBER_MIN_DELAY+INT_DELAY))
if (do_read_volatile(CPRI_TX_ADVANCE_PP1S_ADDR) != pCpriDelay->cpri10ms2PP1sTxOffset)
if (PROTOCOL_CPRI == nBsType)
{
while (1 == reCfgFlag);
set_cpri_tx_rfp();
if (do_read_volatile(CPRI_TX_ADVANCE_PP1S_ADDR) != pCpriDelay->cpri10ms2PP1sTxOffset)
{
while (1 == reCfgFlag);
}
else
{
gCpriIntStatus.cpriSyncFlag = 1;
}
}
else
{
gCpriIntStatus.cpriSyncFlag = 1;
}
do_write(CPRI_TX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sTxOffset);
do_write(CPRI_RX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sRxOffset);
do_write(CPRI_TDD_ADVANCE_PP1S_ADDR, pCpriDelay->cpriTdd2PP1sOffset);
//set_cpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
do_write(CPRI_TX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sTxOffset);
do_write(CPRI_RX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sRxOffset);
do_write(CPRI_TDD_ADVANCE_PP1S_ADDR, pCpriDelay->cpriTdd2PP1sOffset);
enable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
@ -174,26 +189,24 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
pMtimerSfn->slotMaxNum = my_cpritmr->num_tti_per_sfn;
pMtimerSfn->slotNumPP1s = (pCpriDelay->cpri10ms2PP1sTxOffset / my_cpritmr->t_us) % my_cpritmr->num_tti_per_sfn;
gScsId = my_cpritmr->scsId;
gMtimerId = MTIMER_CPRI_ID;
gCellSfnPara[MTIMER_CPRI_ID].scsId = my_cpritmr->scsId;
do_write_short((&(phyPara[my_cpritmr->scsId].slotNumOfTdd)), my_cpritmr->num_tti);
do_write_short((&(phyPara[my_cpritmr->scsId].mtimerId)), MTIMER_CPRI_ID);
__ucps2_synch(0);
set_cpri_sfn_offset();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
set_cpri_tdd_offset(); // 5ms int, tevent2 for all ape cores, dma
if (PROTOCOL_CPRI == nBsType)
{
set_cpri_tdd_offset(); // 5ms int, tevent2 for all ape cores, dma
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
}
set_cpri_insert_int();
#ifdef PALLADIUM_TEST
@ -201,6 +214,8 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
pMtimerInt->txSlotIntCnt = 0;
pMtimerInt->rxSlotIntCnt = 0;
set_rx_slot_offset();
set_tx_slot_offset();
#ifdef PALLADIUM_TEST
@ -210,6 +225,7 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
if (LTE_SCS_ID == my_cpritmr->scsId)
{
pMtimerInt->lteFapiIntCnt = 0;
set_cpri_lte_fapi_offset();
#ifdef PALLADIUM_TEST
flag++;
@ -217,6 +233,18 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
#endif
}
if (PROTOCOL_ECPRI == nBsType)
{
for (int32_t i = 0; i < SLOT_SYMBOL_NUM; i++)
{
set_cpri_tx_symbol_offset(i);
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
}
reCfgFlag = 3;
}
@ -244,7 +272,9 @@ void cpri_timer_rcfg_act()
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
int32_t nScsId = pMtimerPara->scsId;
uint32_t addr = 0;
uint16_t runCore = pMtimerPara->runCoreId;
uint32_t addr = (uint32_t)&(phyPara[nScsId].runCoreId);
uint16_t cellCore = do_read_volatile_short(addr);
set_cpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
@ -253,6 +283,12 @@ void cpri_timer_rcfg_act()
//pMtimerSfn->rxSfnNum = 0; // 1023;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;
if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
{
pMtimerSfn->txSfnNum = 0;
pMtimerSfn->rxSfnNum = 0; //1023;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
do_write(addr, pMtimerSfn->txSfnNum);
addr = (uint32_t)&(phyPara[nScsId].rxSfnNum);
@ -262,21 +298,19 @@ void cpri_timer_rcfg_act()
addr = (uint32_t)&(phyPara[nScsId].rxSlotNum);
do_write(addr, pMtimerSfn->rxSlotNum);
if (0 == pMtimerSfn->rxSlotNum) // ??
{
//pMtimerSfn->rxSfnNum = 1023;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
debug_write((DBG_DDR_IDX_DRV_BASE+556), cellCore); // 0x8b0
debug_write((DBG_DDR_IDX_DRV_BASE+557), runCore); // 0x8b4
debug_write((DBG_DDR_IDX_DRV_BASE+558), pMtimerSfn->txSfnNum); // 0x8b8
debug_write((DBG_DDR_IDX_DRV_BASE+559), pMtimerSfn->rxSfnNum); // 0x8bc
do_write(CTC_INT_TYPE_ADDR, CTC_INT_TYPE_CAL);
#if 0
for (int32_t i = 0; i < APE_NUM; i++)
do_write(CTC_INT_TYPE_ADDR, (MTIMER_CPRI_ID+1));
if (PROTOCOL_ECPRI == get_protocol_sel())
{
set_ctc_cal_int(i);
// ecs rfm0 cal
set_ctc_cal_int(ECS_RFM_SPU0_CORE_ID);
}
#else
// ape tmrpoints
uint32_t runCore = pMtimerPara->runCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
uint8_t apeId = 0;
__ucps2_synch(0);
@ -294,7 +328,6 @@ void cpri_timer_rcfg_act()
h1Pos = __builtin_clz(runCore);
__ucps2_synch(0);
}
#endif
reCfgFlag = 5;
}
@ -311,7 +344,7 @@ void set_cpri_tmr_period(void)
set_mtimer_period(MTIMER_CPRI_ID, tempL, tempM, tempH);
enable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
//enable_mtimer_cevent_int(MTIMER_CPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
}
void cpri_1pps_src_init(uint8_t srcId)
@ -329,10 +362,11 @@ void set_cpri_1pps_scratch(void)
void set_cpri_sfn_offset(void)
{
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
//#endif
uint32_t tmr0Point = SFN_PERIOD - offset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset; // us
set_mtimer_tmrpoint(MTIMER_CPRI_ID, MTMR_10ms_OFFSET, tmr0Point, MTIMER_MASK_62BIT);
@ -348,10 +382,11 @@ void set_cpri_tx_rfp(void)
void set_cpri_tx_axc_ch_en(void)
{
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
//#endif
uint32_t tmr1Point = SFN_PERIOD - offset - 2; // us
set_mtimer_tmrpoint(MTIMER_CPRI_ID, MTMR_CSU_CH, tmr1Point, MTIMER_MASK_62BIT);
@ -361,10 +396,11 @@ void set_cpri_tdd_offset(void)
{
//stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpriTdd2PP1sOffset; // pEcsDmLocalMgt->pCpriDelay->cpriTddOffset;
#endif
//#endif
uint32_t tmr2Point = 5000 - offset; // us // 5ms
set_mtimer_tmrpoint(MTIMER_CPRI_ID, MTMR_TDD_OFFSET, tmr2Point, MTIMER_MASK_62BIT);
@ -395,10 +431,11 @@ void clear_cpri_tdd_offset(void)
void set_tx_slot_offset()
{
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
//#endif
uint32_t tmr3Point = SFN_PERIOD - offset; // us
set_mtimer_tmrpoint(MTIMER_CPRI_ID, MTMR_TXSLOT_OFFSET, tmr3Point, MTIMER_MASK_32BIT);
@ -431,10 +468,11 @@ void clear_tx_slot_offset()
void set_rx_slot_offset()
{
int32_t offset = 0;
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
#endif
//#endif
uint32_t tmr4Point = 0; // offset; // us
if (offset < 0)
@ -476,10 +514,11 @@ void clear_rx_slot_offset()
void set_cpri_lte_fapi_offset(void)
{
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
//#endif
uint32_t tmr30Point = SFN_PERIOD - offset - 500; // us
set_mtimer_tmrpoint(MTIMER_CPRI_ID, MTMR_LTE_FAPI, tmr30Point, MTIMER_MASK_32BIT);
@ -501,14 +540,14 @@ int32_t set_cpri_ape_slot_offset(uint32_t apeCoreId)
volatile uint32_t h1Pos = 0;
uint8_t apeId = 0;
int32_t tmrId = 0;
#ifdef DISTRIBUTED_BS
//#ifdef INTEGRATED_BS
//#else
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
pMtimerPara->runCoreId = apeCoreId;
txOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
rxOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
#endif
//#endif
uint32_t tmr3Point = SFN_PERIOD - txOffset; // us
uint32_t tmr4Point = 0; // offset; // us
@ -582,13 +621,41 @@ int32_t clear_cpri_ape_slot_offset(uint32_t apeCoreId)
return 0;
}
int32_t set_cpri_tx_symbol_offset(uint8_t symbolId)
{
if (SLOT_SYMBOL_NUM <= symbolId)
{
return -1;
}
uint32_t longCp = (uint32_t)4448*500000/(4448+13*4384); // ns
uint32_t shortCp = (uint32_t)4384*500000/(4448+13*4384); // ns
int32_t tmrPoint = 0 - INT_DELAY;
if (1 >= symbolId)
{
tmrPoint += ((longCp*symbolId)/1000);
}
else
{
tmrPoint += ((longCp + shortCp*(symbolId-1))/1000);
}
set_mtimer_tmrpoint(MTIMER_CPRI_ID, MTMR_ECPRI_TX_SYMBOL0+symbolId, tmrPoint, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_CPRI_ID, MTMR_ECPRI_TX_SYMBOL0+symbolId, MTMR_INT_RFM0_SLOT);
return 0;
}
void set_cpri_insert_int(void)
{
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
//#endif
UINT32 tmr24Point = 8000 - offset; // us
set_mtimer_tmrpoint(MTIMER_CPRI_ID, MTMR_CSU_INSERT, tmr24Point, MTIMER_MASK_62BIT);
@ -669,7 +736,7 @@ void isr_cpri_10ms(void)
{
do_write((tmrBaseAddr+MTMR_CEVENT_REG), BIT17);
do_write(cFlagAddr, BIT17); // clear int flag
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
if (0 == pMtimerInt->pp1sIntCnt)
{
start_cpri_timer();
@ -681,7 +748,7 @@ uint32_t start = GET_STC_CNT();
#endif
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+1), pMtimerInt->pp1sIntCnt); // 0x104
#if 0 //def PALLADIUM_TEST
#ifdef PALLADIUM_TEST
//debug_write((DBG_DDR_IDX_DRV_BASE+576+(gCpriTimerPara.pp1sIntCnt&0x3f)), get_tx_nr_slot(1)); // 0xB7E06900
uint32_t val = 0;
@ -700,7 +767,7 @@ uint32_t start = GET_STC_CNT();
debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 3), val); // 0xd00
}
#endif
debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
}
if (cEventFlag & (1<<MTMR_CEVENT_CNT14H)) // 10ms int
{
@ -712,12 +779,11 @@ debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
#endif
uint16_t runCore = do_read_volatile_short(&(phyPara[gScsId].runCoreId));
if (((runCore & pMtimerPara->runCoreId) == pMtimerPara->runCoreId) && (4 == reCfgFlag))
//if ((runCore == pMtimerPara->runCoreId) && (3 == reCfgFlag))
{
debug_write((DBG_DDR_IDX_DRV_BASE+907), GET_STC_CNT()); // 0xe2c // timer restart finished
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
cpri_timer_rcfg_act();
debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
pMtimerCal->sfnCalFinished = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
@ -760,8 +826,10 @@ void isr_cpri_tdd_offset(void)
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
//#ifdef DISTRIBUTED_BS
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
//#endif
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG); // &CPRI_TMR_INTC_REG);
@ -779,14 +847,14 @@ void isr_cpri_tdd_offset(void)
uint32_t setFlag = tEventFlag & tddVal;
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), setFlag);
do_write(tFlagAddr, setFlag); // clear int flag
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
pMtimerInt->tddOffsetIntCnt++;
// start_csu_timing
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+4), pMtimerInt->tddOffsetIntCnt); // 0x110
// debug_write(((DBG_DDR_IDX_DRV_BASE+576) + (gCpriTimerPara.tddOffsetIntCnt&0x3F)), get_tx_nr_slot(NR_SCS_30K)); // 0x900
#endif
#ifdef CPRI_TIMING_TEST
#if 0 //def CPRI_TIMING_TEST
if (tEventFlag & ((1<<MTMR_TDD_OFFSET_10000)|(1<<MTMR_TDD_OFFSET)))
{
debug_write((DBG_DDR_IDX_DRV_BASE+896+(pMtimerInt->tddOffsetIntCnt&0x3F)), UCP_API_CPRI_GetTxHfnCnt()); // 0xE00
@ -795,7 +863,7 @@ uint32_t start = GET_STC_CNT();
}
#endif
//#ifdef CPRI_TIMING_7D2U_TEST
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
#if 0
if (32 > pMtimerInt->tddOffsetIntCnt)
{
@ -877,8 +945,8 @@ uint32_t start = GET_STC_CNT();
debug_write((DBG_DDR_IDX_DRV_BASE+77), gCpriCsuFifoTxCnt); // 0x134
}
#endif
#endif
debug_write((DBG_DDR_IDX_DRV_BASE+289), (GET_STC_CNT()-start)); // 0x484
//#endif
//debug_write((DBG_DDR_IDX_DRV_BASE+289), (GET_STC_CNT()-start)); // 0x484
}
if (tEventFlag & (1<<MTMR_CSU_INSERT)) // 8ms int
{
@ -889,16 +957,10 @@ debug_write((DBG_DDR_IDX_DRV_BASE+289), (GET_STC_CNT()-start)); // 0x484
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+5), pMtimerInt->insOffsetIntCnt); // 0x114
#endif
#ifdef CPRI_TIMING_7D2U_TEST
Cpri_Header_Tx();
#endif
#ifdef DISTRIBUTED_BS
#ifdef TEST_ENABLE
#ifdef CPRI_TIMING_7D2U_TEST
Cpri_Header_Rx();
#endif
#endif
#endif
//#ifdef TEST_ENABLE
//Cpri_Header_Rx();
//#endif
}
tEventFlag = do_read_volatile(tFlagAddr);
}
@ -934,7 +996,7 @@ void isr_cpri_slot_offset(void)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TXSLOT_OFFSET));
do_write(tFlagAddr, (1<<MTMR_TXSLOT_OFFSET)); // clear int flag
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
if (5 == reCfgFlag)
{
reCfgFlag = 0;
@ -1002,12 +1064,12 @@ uint32_t start = GET_STC_CNT();
__ucps2_synch(f_SMW);
#ifdef DISTRIBUTED_BS
#if 0 // def DISTRIBUTED_BS
#ifdef TEST_ENABLE
cpri_test_move_data();
fh_test_move_data();
#endif
#endif
debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
//debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
#if 0 // def PALLADIUM_TEST
debug_write(((DBG_DDR_IDX_DRV_BASE+8192) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), gCpriTimerPara.txSlotIntCnt); // 0x8000
debug_write(((DBG_DDR_IDX_DRV_BASE+8704) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), get_tx_nr_slot(1)); // 0x8800
@ -1040,7 +1102,7 @@ debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_RXSLOT_OFFSET));
do_write(tFlagAddr, (1<<MTMR_RXSLOT_OFFSET)); // clear int flag
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
pMtimerSfn->rxSlotNum++;
__ucps2_synch(0);
if (pMtimerSfn->rxSlotNum == pMtimerSfn->slotMaxNum)
@ -1069,7 +1131,7 @@ uint32_t start = GET_STC_CNT();
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intNum), APE_INT_RX_SLOT);
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intCnt), pMtimerInt->rxSlotIntCnt);
__ucps2_synch(f_SMW);
debug_write((DBG_DDR_IDX_DRV_BASE+291), (GET_STC_CNT()-start)); // 0x48c
//debug_write((DBG_DDR_IDX_DRV_BASE+291), (GET_STC_CNT()-start)); // 0x48c
}
if (tEventFlag & (1<<MTMR_LTE_FAPI)) // LTE FAPI
{
@ -1099,7 +1161,7 @@ void clear_sfnoffset_int_flag()
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
pMtimerInt->sfnOffsetIntFlag = 0;
}
#if 0
void cpri_tdd_start_csu_timing()
{
#ifdef DISTRIBUTED_BS
@ -1108,22 +1170,22 @@ void cpri_tdd_start_csu_timing()
#endif
#endif
}
#endif
void cpri_tdd_start_csu_7ds2u()
{
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
#if 1
if (CPRI_TEST_MODE == gCpriTestMode)
{
// start csu
#ifdef DISTRIBUTED_BS
#ifdef TEST_ENABLE
cpri_test_case();
fh_test_case();
#endif
#endif
pMtimerInt->csuEnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), pMtimerInt->csuEnCnt); // 0x118
}
else
#endif
{
// start csu
UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
@ -1132,5 +1194,5 @@ void cpri_tdd_start_csu_7ds2u()
}
}
#endif
//#endif

132
public/ecs_rfm_spu1/driver/src/ecpri_driver.s.c Normal file
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@ -0,0 +1,132 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_driver.s.c
* Create Date: 23/08/18
* Description: eCPRI Driver Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_driver.h"
#include "hw_cpri.h"
#include "ecpri_timer.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: vnet_send_packet
* Description: vnet send packet
* Input:
* <name> <type> <desc>
* skb sk_buff * socket buffer
* dev net_device * network device
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void ecpri_init(uint8_t nOption)
{
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
phy_para_init(PROTOCOL_ECPRI, nOption);
ecpri_init_ex(nOption); // (10);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
cpri_ecprimode_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
ecpri_mtimer_init(LTE_SCS_ID, 10);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
}
void ecpri_cprimode_init()
{
// 扩皮模式下，ecpri timer使用cpri_div33_tx_clk，与cpri core clk同源
ecpri_timer_cprimode_clk_init();
ecpri_mtimer_init(LTE_SCS_ID, 10);
}
void ecpri_clk_init(uint32_t ecpri_speed_sel)
{
if (ecpri_speed_sel == 10) //10G
{
do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT11+BIT5+BIT31+BIT16+BIT17+BIT18+BIT19));
do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2 apb_aclk_i
//switch_core_clk_i,
//switch_sch_clk_i,
do_write(&JECS_CRG_CLK_CTRL7, 0x520000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_switch_mae_core_clk
do_write(&JECS_CRG_CLK_CTRL8, 0x520000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_tx_clk
do_write(&JECS_CRG_CLK_CTRL9, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_rx_clk
do_write(&JECS_CRG_CLK_CTRL0, 0x521000);//jecs_pma_rx0_div33_clk
do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
}
else if (ecpri_speed_sel == 25) //25G
{
do_write(&JECS_CRG_PLLSEL, do_read_volatile(&JECS_CRG_PLLSEL) | (BIT11+BIT5+BIT16+BIT17+BIT18+BIT19));
do_write(&JECS_CRG_CLK_CTRL6, 0x521000); //SYSAPB /2 apb_aclk_i
//switch_core_clk_i,
//switch_sch_clk_i,
do_write(&JECS_CRG_CLK_CTRL7, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_switch_mae_core_clk
do_write(&JECS_CRG_CLK_CTRL8, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_tx_clk
do_write(&JECS_CRG_CLK_CTRL9, 0x521000);//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_rx_clk
do_write(&JECS_CRG_CLK_CTRL0, 0x521000);//jecs_pma_rx0_div33_clk
do_write(&JECS_CRG_CLK_CTRL1, 0x520000);
do_write(&JECS_CRG_CLK_CTRL10, 0x520000);
}
}
void ecpri_init_ex(uint32_t ecpri_speed_sel)
{
ecpri_clk_init(10);
ecpri_pcs_rst_ctrl_ex();
init_ecpri_pma_rst_ex();
init_jecspma(10);
init_jecspma_rxtx();
ecpri_roec_init();
ecpri_pcs_init(10);
ecpri_mac_init(10);
ecpri_switch_init(10);
ecpri_pma_rx_adapt();
/* waiting for eCPRI PCS to link up */
while (!ecpri_pcs_link_status_get());
do_write(SERDES_INIT_FLAG_ADDR, 1);
}

751
public/ecs_rfm_spu1/driver/src/ecpri_pma.s.c Normal file
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@ -0,0 +1,751 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_pma.s.c
* Create Date: 23/08/18
* Description: eCPRI PMA Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_pma.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: vnet_send_packet
* Description: vnet send packet
* Input:
* <name> <type> <desc>
* skb sk_buff * socket buffer
* dev net_device * network device
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void ecpri_pcs_rst_ctrl_ex(void)
{
//cancell ecpri's rst
do_write(&JECS_CRG_MANTICORE0_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE0_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE1_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE1_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE2_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE2_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE3_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE3_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE4_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE4_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE5_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE5_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE6_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE6_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE7_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE7_RST_CTRL) | BIT24);
do_write(&JECS_CRG_MANTICORE8_RST_CTRL, do_read_volatile(&JECS_CRG_MANTICORE8_RST_CTRL) | BIT24);
do_write(&ECPRI_RST_CFG_REG, do_read_volatile(&ECPRI_RST_CFG_REG) | BIT24);
}
/**********************************************************************************************************************
* Function: vnet_recv_packet
* Description: vnet receive packet
* Input:
* <name> <type> <desc>
* dev net_device * network device
* data uint8_t * data received
* len uint32_t data length
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void init_ecpri_pma_rst_ex(void)
{
//cancell jecs pma rst
do_write(&JECS_CRG_PMA16_RST_CTRL, do_read_volatile(&JECS_CRG_PMA16_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA8_RST_CTRL, do_read_volatile(&JECS_CRG_PMA8_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA9_RST_CTRL, do_read_volatile(&JECS_CRG_PMA9_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA10_RST_CTRL, do_read_volatile(&JECS_CRG_PMA10_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA11_RST_CTRL, do_read_volatile(&JECS_CRG_PMA11_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA12_RST_CTRL, do_read_volatile(&JECS_CRG_PMA12_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA13_RST_CTRL, do_read_volatile(&JECS_CRG_PMA13_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA14_RST_CTRL, do_read_volatile(&JECS_CRG_PMA14_RST_CTRL) | BIT24);
do_write(&JECS_CRG_PMA15_RST_CTRL, do_read_volatile(&JECS_CRG_PMA15_RST_CTRL) | BIT24);
}
/**********************************************************************************************************************
* Function: vnet_set_mac_address
* Description: vnet set mac address
* Input:
* <name> <type> <desc>
* dev net_device * network device
* addr void * network address
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void init_pma_commonconfig_ex(uint32_t ecpri_speed_sel)
{
uint32_t ate_ref_range ;
uint32_t ate_ref_clk_div2_en ;
uint32_t ate_ref_raw_clk_div2_en ;
uint32_t ate_ref_clk_mplla_div ;
uint32_t ate_lane_ref_sel ;
uint32_t ate_mplla_fb_clk_div4_en ;
uint32_t ate_mplla_multiplier ;
uint32_t ate_mplla_tx_clk_div ;
uint32_t ate_mplla_word_clk_div ;
uint32_t ate_mplla_ssc_en ;
uint32_t ate_mplla_ssc_up_spread ;
uint32_t ate_mplla_ssc_peak ;
uint32_t ate_mplla_ssc_step_size ;
uint32_t ate_mplla_frac_en ;
uint32_t ate_mplla_frac_quot ;
uint32_t ate_mplla_frac_den ;
uint32_t ate_mplla_frac_rem ;
uint32_t ate_refa_lane_clk_en ;
uint32_t ate_bs_rx_level ;
uint32_t ate_bs_tx_lowswing ;
uint32_t ate_bs_rx_bigswing ;
uint32_t ate_mplla_init_cal_disable ;
uint32_t ate_refa_dig_clk_sel ;
uint32_t ate_ref_dco_bypass ;
uint32_t ate_refa_dco_ld_val ;
uint32_t ate_ref_dco_target ;
uint32_t ate_ref_dco_dig_range ;
uint32_t ate_mplla_bw_threshold ;
uint32_t ate_mplla_bw_low ;
uint32_t ate_mplla_bw_high ;
uint32_t ate_mplla_ctl_buf_bypass ;
uint32_t ate_mplla_short_lock_en ;
uint32_t ate_rx_term_offset ;
uint32_t ate_txdn_term_offset ;
uint32_t ate_txup_term_offset ;
uint32_t ate_sup_misc ;
uint32_t ate_rx_vref_ctrl ;
uint32_t ate_rx_ref_ld_val ;
uint32_t ate_rx_vco_ld_val ;
uint32_t ate_rx_cdr_ppm_max ;
//lane
uint32_t ate_tx_misc ;
uint32_t ate_tx_dcc_ctrl_diff_range ;
uint32_t ate_tx_dcc_ctrl_cm_range ;
uint32_t ate_tx_width ;
uint32_t ate_tx_ropll_cp_ctl_intg ;
uint32_t ate_tx_ropll_cp_ctl_prop ;
uint32_t ate_tx_ropll_rc_filter ;
uint32_t ate_tx_ropll_v2i_mode ;
uint32_t ate_tx_ropll_vco_low_freq ;
uint32_t ate_tx_ropll_postdiv ;
uint32_t ate_tx_rate ;
uint32_t ate_tx_ropll_div16p5_clk_en ;
uint32_t ate_tx_ropll_125mhz_clk_en ;
uint32_t ate_tx_term_ctrl ;
uint32_t ate_tx_dly_cal_en ;
uint32_t ate_tx_pll_word_clk_freq ;
uint32_t ate_tx_dig_ropll_div_clk_sel ;
uint32_t ate_tx_dual_cntx_en ;
uint32_t ate_tx_ropll_bypass ;
uint32_t ate_tx_ropll_refdiv ;
uint32_t ate_tx_ropll_refsel ;
uint32_t ate_tx_ropll_fbdiv ;
uint32_t ate_tx_ropll_div_clk_en ;
uint32_t ate_tx_ropll_out_div ;
uint32_t ate_tx_ropll_word_clk_div_sel;
uint32_t txX_ropll_word_clk_div_lte ;
uint32_t ate_tx_fastedge_en ;
uint32_t ate_tx_eq_pre ;
uint32_t ate_tx_eq_post ;
uint32_t ate_tx_eq_main ;
uint32_t ate_tx_align_wide_xfer_en ;
uint32_t ate_rx_eq_att_lvl ;
uint32_t ate_rx_eq_ctle_boost ;
uint32_t ate_rx_eq_ctle_pole ;
uint32_t ate_rx_eq_afe_rate ;
uint32_t ate_rx_eq_vga_gain ;
uint32_t ate_rx_eq_afe_config ;
uint32_t ate_rx_eq_dfe_tap1 ;
uint32_t ate_rx_eq_dfe_tap2 ;
uint32_t ate_rx_delta_iq ;
uint32_t ate_rx_cdr_vco_config ;
uint32_t ate_rx_dcc_ctrl_diff_range ;
uint32_t ate_rx_dcc_ctrl_cm_range ;
uint32_t ate_rx_sigdet_lf_threshold ;
uint32_t ate_rx_sigdet_hf_threshold ;
uint32_t ate_rx_misc ;
uint32_t ate_rx_term_ctrl ;
uint32_t ate_rx_width ;
uint32_t ate_rx_dig_div_clk_sel ;
uint32_t ate_rx_div_clk_en ;
uint32_t ate_rx_div_clk_sel ;
uint32_t ate_rx_rate ;
uint32_t ate_rx_dfe_bypass ;
uint32_t ate_rx_offcan_cont ;
uint32_t ate_rx_adapt_cont ;
uint32_t ate_rx_eq_dfe_float_en ;
uint32_t ate_rx_div16p5_clk_en ;
uint32_t ate_rx_125mhz_clk_en ;
uint32_t ate_rx_cdr_ssc_en ;
uint32_t ate_rx_sigdet_hf_en ;
uint32_t ate_rx_sigdet_lfps_filter_en ;
uint32_t ate_rx_term_acdc ;
uint32_t ate_rx_adapt_sel ;
uint32_t ate_rx_adapt_mode ;
uint32_t ate_rx_adapt_en ;
uint32_t ate_ref_clk_mpllb_div ;
uint32_t ate_mpllb_fb_clk_div4_en ;
uint32_t ate_mpllb_multiplier ;
uint32_t ate_mpllb_tx_clk_div ;
uint32_t ate_mpllb_word_clk_div ;
uint32_t ate_mpllb_ssc_en ;
uint32_t ate_mpllb_ssc_up_spread ;
uint32_t ate_mpllb_ssc_peak ;
uint32_t ate_mpllb_ssc_step_size ;
uint32_t ate_mpllb_frac_en ;
uint32_t ate_mpllb_frac_quot ;
uint32_t ate_mpllb_frac_den ;
uint32_t ate_mpllb_frac_rem ;
uint32_t ate_refb_lane_clk_en ;
uint32_t ate_mpllb_init_cal_disable ;
uint32_t ate_refb_dig_clk_sel ;
uint32_t ate_refb_dco_ld_val ;
uint32_t ate_mpllb_bw_high ;
uint32_t ate_mpllb_bw_low ;
uint32_t ate_mpllb_bw_threshold ;
uint32_t ate_mpllb_ctl_buf_bypass ;
uint32_t ate_mpllb_short_lock_en ;
//const
uint32_t ate_mplla_force_en = 0;//
uint32_t ate_mpllb_force_en = 0;//
uint32_t ate_pcs_pwr_stable = 1;//
uint32_t ate_pg_mode_en = 0;//
uint32_t ate_pg_reset = 0;//
uint32_t ate_pma_pwr_stable = 1;//
uint32_t ate_refa_clk_en = 1;//
uint32_t ate_refb_clk_en = 0;//
uint32_t ate_ref_repeat_clk_en = 1;//
uint32_t ate_rx_pstate = 2;//
uint32_t ate_rx_invert = 0;//
uint32_t ate_rx_lpd = 0;//
uint32_t ate_rx_term_en = 1;//
uint32_t ate_tx_pstate = 2;//
uint32_t ate_tx_clk_rdy = 1;//
uint32_t ate_tx_invert = 0;//
uint32_t ate_tx_lpd = 0;//
uint32_t ate_tx_mpll_en = 1;//
if(ecpri_speed_sel == 10)
{
ate_ref_range = 4 ;
ate_ref_clk_div2_en = 0 ;
ate_ref_raw_clk_div2_en = 1 ;
ate_ref_clk_mplla_div = 1 ;
ate_lane_ref_sel = 0 ;
ate_mplla_fb_clk_div4_en = 0 ;
ate_mplla_multiplier = 120 ;
ate_mplla_tx_clk_div = 1 ;
ate_mplla_word_clk_div = 2 ;
ate_mplla_ssc_en = 0 ;
ate_mplla_ssc_up_spread = 0 ;
ate_mplla_ssc_peak = 0 ;
ate_mplla_ssc_step_size = 0 ;
ate_mplla_frac_en = 0 ;
ate_mplla_frac_quot = 0 ;
ate_mplla_frac_den = 0 ;
ate_mplla_frac_rem = 0 ;
ate_refa_lane_clk_en = 0 ;
ate_bs_rx_level = 7 ;
ate_bs_tx_lowswing = 0 ;
ate_bs_rx_bigswing = 1 ;
ate_mplla_init_cal_disable = 0 ;
ate_refa_dig_clk_sel = 0 ;
ate_ref_dco_bypass = 0 ;
ate_refa_dco_ld_val = 78 ;
ate_ref_dco_target = 150 ;
ate_ref_dco_dig_range = 6 ;
ate_mplla_bw_threshold = 75 ;
ate_mplla_bw_low = 1583 ;
ate_mplla_bw_high = 1583 ;
ate_mplla_ctl_buf_bypass = 0 ;
ate_mplla_short_lock_en = 0 ;
ate_rx_term_offset = 0 ;
ate_txdn_term_offset = 0 ;
ate_txup_term_offset = 0 ;
ate_sup_misc = 3 ;
ate_rx_vref_ctrl = 5 ;
ate_rx_ref_ld_val = 21 ;
ate_rx_vco_ld_val = 1386 ;
ate_rx_cdr_ppm_max = 18 ;
//lane
ate_tx_misc = 0 ;
ate_tx_dcc_ctrl_diff_range = 8 ;
ate_tx_dcc_ctrl_cm_range = 8 ;
ate_tx_width = 4 ;
ate_tx_ropll_cp_ctl_intg = 79 ;
ate_tx_ropll_cp_ctl_prop = 79 ;
ate_tx_ropll_rc_filter = 4 ;
ate_tx_ropll_v2i_mode = 3 ;
ate_tx_ropll_vco_low_freq = 2 ;
ate_tx_ropll_postdiv = 1 ;
ate_tx_rate = 1 ;
ate_tx_ropll_div16p5_clk_en = 1 ;
ate_tx_ropll_125mhz_clk_en = 0 ;
ate_tx_term_ctrl = 0 ;
ate_tx_dly_cal_en = 0 ;
ate_tx_pll_word_clk_freq = 6 ;
ate_tx_dig_ropll_div_clk_sel = 0 ;
ate_tx_dual_cntx_en = 0 ;
ate_tx_ropll_bypass = 0 ;
ate_tx_ropll_refdiv = 5 ;
ate_tx_ropll_refsel = 0 ;
ate_tx_ropll_fbdiv = 11 ;
ate_tx_ropll_div_clk_en = 0 ;
ate_tx_ropll_out_div = 4 ;
ate_tx_ropll_word_clk_div_sel = 2 ;
txX_ropll_word_clk_div_lte = 2 ;
ate_tx_fastedge_en = 0 ;
ate_tx_eq_pre = 0 ;
ate_tx_eq_post = 0 ;
ate_tx_eq_main = 24 ;
ate_tx_align_wide_xfer_en = 0 ;
ate_rx_eq_att_lvl = 0 ;
ate_rx_eq_ctle_boost = 16 ;
ate_rx_eq_ctle_pole = 1 ;
ate_rx_eq_afe_rate = 6 ;
ate_rx_eq_vga_gain = 16 ;
ate_rx_eq_afe_config = 1300;
ate_rx_eq_dfe_tap1 = 12 ;
ate_rx_eq_dfe_tap2 = 128 ;
ate_rx_delta_iq = 6 ;
ate_rx_cdr_vco_config = 1027;
ate_rx_dcc_ctrl_diff_range = 11 ;
ate_rx_dcc_ctrl_cm_range = 11 ;
ate_rx_sigdet_lf_threshold = 4 ;
ate_rx_sigdet_hf_threshold = 2 ;
ate_rx_misc = 0 ;
ate_rx_term_ctrl = 0 ;
ate_rx_width = 4 ;
ate_rx_dig_div_clk_sel = 0 ;
ate_rx_div_clk_en = 0 ;
ate_rx_div_clk_sel = 0 ;
ate_rx_rate = 1 ;
ate_rx_dfe_bypass = 0 ;
ate_rx_offcan_cont = 1 ;
ate_rx_adapt_cont = 1 ;
ate_rx_eq_dfe_float_en = 0 ;
ate_rx_div16p5_clk_en = 1 ;
ate_rx_125mhz_clk_en = 0 ;
ate_rx_cdr_ssc_en = 0 ;
ate_rx_sigdet_hf_en = 0 ;
ate_rx_sigdet_lfps_filter_en = 0 ;
ate_rx_term_acdc = 1 ;
ate_rx_adapt_sel = 0 ;
ate_rx_adapt_mode = 4 ;
ate_rx_adapt_en = 0 ;//1
}
if (ecpri_speed_sel == 25)
{
ate_ref_range = 4 ;
ate_ref_clk_div2_en = 0 ;
ate_ref_raw_clk_div2_en = 1 ;
ate_ref_clk_mplla_div = 1 ;
ate_lane_ref_sel = 0 ;
ate_mplla_fb_clk_div4_en = 0 ;
ate_mplla_multiplier = 120 ;
ate_mplla_tx_clk_div = 1 ;
ate_mplla_word_clk_div = 2 ;
ate_mplla_ssc_en = 0 ;
ate_mplla_ssc_up_spread = 0 ;
ate_mplla_ssc_peak = 0 ;
ate_mplla_ssc_step_size = 0 ;
ate_mplla_frac_en = 0 ;
ate_mplla_frac_quot = 0 ;
ate_mplla_frac_den = 0 ;
ate_mplla_frac_rem = 0 ;
ate_refa_lane_clk_en = 0 ;
ate_bs_rx_level = 7 ;
ate_bs_tx_lowswing = 0 ;
ate_bs_rx_bigswing = 1 ;
ate_mplla_init_cal_disable = 0 ;
ate_refa_dig_clk_sel = 0 ;
ate_ref_dco_bypass = 0 ;
ate_refa_dco_ld_val = 78 ;
ate_ref_dco_target = 150 ;
ate_ref_dco_dig_range = 6 ;
ate_mplla_bw_threshold = 75 ;
ate_mplla_bw_low = 1583 ;
ate_mplla_bw_high = 1583 ;
ate_mplla_ctl_buf_bypass = 0 ;
ate_mplla_short_lock_en = 0 ;
ate_rx_term_offset = 0 ;
ate_txdn_term_offset = 0 ;
ate_txup_term_offset = 0 ;
ate_sup_misc = 3 ;
ate_rx_vref_ctrl = 5 ;
ate_rx_ref_ld_val = 17 ;
ate_rx_vco_ld_val = 1403 ;
ate_rx_cdr_ppm_max = 19 ;
//lane
ate_tx_misc = 0 ;
ate_tx_dcc_ctrl_diff_range = 8 ;
ate_tx_dcc_ctrl_cm_range = 8 ;
ate_tx_width = 4 ;
ate_tx_ropll_cp_ctl_intg = 105 ;
ate_tx_ropll_cp_ctl_prop = 67 ;
ate_tx_ropll_rc_filter = 4 ;
ate_tx_ropll_v2i_mode = 3 ;
ate_tx_ropll_vco_low_freq = 2 ;
ate_tx_ropll_postdiv = 0 ;
ate_tx_rate = 0 ;
ate_tx_ropll_div16p5_clk_en = 1 ;
ate_tx_ropll_125mhz_clk_en = 0 ;
ate_tx_term_ctrl = 0 ;
ate_tx_dly_cal_en = 0 ;
ate_tx_pll_word_clk_freq = 6 ;
ate_tx_dig_ropll_div_clk_sel = 0 ;
ate_tx_dual_cntx_en = 0 ;
ate_tx_ropll_bypass = 0 ;
ate_tx_ropll_refdiv = 4 ;
ate_tx_ropll_refsel = 0 ;
ate_tx_ropll_fbdiv = 11 ;
ate_tx_ropll_div_clk_en = 0 ;
ate_tx_ropll_out_div = 4 ;
ate_tx_ropll_word_clk_div_sel = 2 ;
txX_ropll_word_clk_div_lte = 2 ;
ate_tx_fastedge_en = 0 ;
ate_tx_eq_pre = 0 ;
ate_tx_eq_post = 0 ;
ate_tx_eq_main = 24 ;
ate_tx_align_wide_xfer_en = 1 ;
ate_rx_eq_att_lvl = 0 ;
ate_rx_eq_ctle_boost = 20 ;
ate_rx_eq_ctle_pole = 3 ;
ate_rx_eq_afe_rate = 1 ;
ate_rx_eq_vga_gain = 16 ;
ate_rx_eq_afe_config = 2364 ;
ate_rx_eq_dfe_tap1 = 12 ;
ate_rx_eq_dfe_tap2 = 128 ;
ate_rx_delta_iq = 3 ;
ate_rx_cdr_vco_config = 34 ;
ate_rx_dcc_ctrl_diff_range = 11 ;
ate_rx_dcc_ctrl_cm_range = 11 ;
ate_rx_sigdet_lf_threshold = 4 ;
ate_rx_sigdet_hf_threshold = 2 ;
ate_rx_misc = 0 ;
ate_rx_term_ctrl = 0 ;
ate_rx_width = 4 ;
ate_rx_dig_div_clk_sel = 0 ;
ate_rx_div_clk_en = 0 ;
ate_rx_div_clk_sel = 0 ;
ate_rx_rate = 0 ;
ate_rx_dfe_bypass = 0 ;
ate_rx_offcan_cont = 1 ;
ate_rx_adapt_cont = 1 ;
ate_rx_eq_dfe_float_en = 1 ;
ate_rx_div16p5_clk_en = 1 ;
ate_rx_125mhz_clk_en = 0 ;
ate_rx_cdr_ssc_en = 0 ;
ate_rx_sigdet_hf_en = 0 ;
ate_rx_sigdet_lfps_filter_en = 0 ;
ate_rx_term_acdc = 1 ;
ate_rx_adapt_sel = 0 ;
ate_rx_adapt_mode = 4 ;
ate_rx_adapt_en = 0 ;//
}
ate_tx_term_ctrl = ate_tx_term_ctrl +8;
ate_rx_term_ctrl = ate_rx_term_ctrl +8;
ate_ref_clk_mpllb_div = ate_ref_clk_mplla_div;//
ate_mpllb_fb_clk_div4_en = ate_mplla_fb_clk_div4_en;//
ate_mpllb_multiplier = ate_mplla_multiplier;//
ate_mpllb_tx_clk_div = ate_mplla_tx_clk_div;//
ate_mpllb_word_clk_div = ate_mplla_word_clk_div;//
ate_mpllb_ssc_en = ate_mplla_ssc_en;//
ate_mpllb_ssc_up_spread = ate_mplla_ssc_up_spread;//
ate_mpllb_ssc_peak = ate_mplla_ssc_peak;//
ate_mpllb_ssc_step_size = ate_mplla_ssc_step_size;//
ate_mpllb_frac_en = ate_mplla_frac_en;//
ate_mpllb_frac_quot = ate_mplla_frac_quot;//
ate_mpllb_frac_den = ate_mplla_frac_den;//
ate_mpllb_frac_rem = ate_mplla_frac_den;//
ate_refb_lane_clk_en = ate_refa_lane_clk_en;//
ate_mpllb_init_cal_disable = ate_mplla_init_cal_disable;//
ate_refb_dig_clk_sel = ate_refa_dig_clk_sel;
ate_refb_dco_ld_val = ate_refa_dco_ld_val;
ate_mpllb_bw_high = ate_mplla_bw_high ;//
ate_mpllb_bw_low = ate_mplla_bw_low ;//
ate_mpllb_bw_threshold = ate_mplla_bw_threshold;//
ate_mpllb_ctl_buf_bypass = ate_mplla_ctl_buf_bypass;//
ate_mpllb_short_lock_en = ate_mplla_short_lock_en;//
do_write(&JECS_PMA1_REF_CLK_CTRL, 0x10 + ate_ref_repeat_clk_en +(ate_ref_clk_mplla_div<<8) + (ate_ref_clk_mpllb_div<<12));
do_write(&JECS_PMA1_REFB_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refb_lane_clk_en);
do_write(&JECS_PMA1_REFA_CLK_CTRL2, (ate_ref_raw_clk_div2_en<<8)+(ate_ref_range<<4)+ate_refa_lane_clk_en);
do_write(&JECS_PMA1_BROADCAST_LANE_REFCLK_SEL, ate_lane_ref_sel);
do_write(&JECS_PMA1_MPLLA_PARAM6, (ate_mplla_fb_clk_div4_en<<4));
do_write(&JECS_PMA1_MPLLB_PARAM6, (ate_mpllb_fb_clk_div4_en<<4));
do_write(&JECS_PMA1_MPLLA_PARAM5, (ate_mplla_tx_clk_div<<4)+ate_mplla_short_lock_en+(ate_mplla_word_clk_div<<8));
do_write(&JECS_PMA1_MPLLB_PARAM5, (ate_mpllb_tx_clk_div<<4)+ate_mpllb_short_lock_en+(ate_mpllb_word_clk_div<<8));
do_write(&JECS_PMA1_REFA_CLK_CTRL1, 0x100+(ate_refa_clk_en<<4) + ate_ref_clk_div2_en);
do_write(&JECS_PMA1_REFB_CLK_CTRL1, 0x100+(ate_refb_clk_en<<4) + ate_ref_clk_div2_en);
do_write(&JECS_PMA1_MPLLA_SSC_CTRL2, ate_mplla_ssc_peak);
do_write(&JECS_PMA1_MPLLB_SSC_CTRL2, ate_mpllb_ssc_peak);
do_write(&JECS_PMA1_MPLLA_SSC_CTRL5, ate_mplla_ssc_step_size);
do_write(&JECS_PMA1_MPLLB_SSC_CTRL5, ate_mpllb_ssc_step_size);
do_write(&JECS_PMA1_MPLLA_FRAC_CTRL1, ate_mplla_frac_den);
do_write(&JECS_PMA1_MPLLB_FRAC_CTRL1, ate_mpllb_frac_den);
do_write(&JECS_PMA1_MPLLA_FRAC_CTRL2, ate_mplla_frac_en);
do_write(&JECS_PMA1_MPLLB_FRAC_CTRL2, ate_mpllb_frac_en);
do_write(&JECS_PMA1_MPLLA_FRAC_CTRL3, ate_mplla_frac_quot);
do_write(&JECS_PMA1_MPLLB_FRAC_CTRL3, ate_mpllb_frac_quot);
do_write(&JECS_PMA1_MPLLA_FRAC_CTRL4, ate_mplla_frac_rem);
do_write(&JECS_PMA1_MPLLB_FRAC_CTRL4, ate_mpllb_frac_rem);
do_write(&JECS_PMA1_MPLLA_PARAM3, (ate_mplla_ctl_buf_bypass<<8)+ate_mplla_bw_threshold);
do_write(&JECS_PMA1_MPLLB_PARAM3, (ate_mpllb_ctl_buf_bypass<<8)+ate_mpllb_bw_threshold);
do_write(&JECS_PMA1_MPLLA_SSC_CTRL1, ate_mplla_ssc_en);
do_write(&JECS_PMA1_MPLLB_SSC_CTRL1, ate_mpllb_ssc_en);
do_write(&JECS_PMA1_MPLLA_SSC_CTRL4, ate_mplla_ssc_up_spread);
do_write(&JECS_PMA1_MPLLB_SSC_CTRL4, ate_mpllb_ssc_up_spread);
do_write(&JECS_PMA1_SUP_MISC, ate_sup_misc);
do_write(&JECS_PMA1_MPLLA_PARAM4, ate_mplla_multiplier + (ate_mplla_init_cal_disable<<12));
do_write(&JECS_PMA1_MPLLB_PARAM4, ate_mpllb_multiplier + (ate_mpllb_init_cal_disable<<12));
do_write(&JECS_PMA1_RTUNE_CTRL1, ate_rx_term_offset);
do_write(&JECS_PMA1_RTUNE_CTRL2, ate_txdn_term_offset);
do_write(&JECS_PMA1_RTUNE_CTRL3, ate_txup_term_offset);
do_write(&JECS_PMA1_MPLLA_PARAM1, ate_mplla_bw_high);
do_write(&JECS_PMA1_MPLLB_PARAM1, ate_mpllb_bw_high);
do_write(&JECS_PMA1_MPLLA_PARAM2, ate_mplla_bw_low);
do_write(&JECS_PMA1_MPLLB_PARAM2, ate_mpllb_bw_low);
do_write(&JECS_PMA1_RX_BIAS_CURRENT_CTRL, ate_rx_vref_ctrl+BIT8);//20220214
do_write(&JECS_PMA1_MPLLA_FORCE_EN, ate_mplla_force_en);
do_write(&JECS_PMA1_MPLLB_FORCE_EN, ate_mpllb_force_en);
do_write(&JECS_PMA1_POWER_GATING_SIGNAL1, ate_pcs_pwr_stable + (ate_pg_mode_en<<4) + (ate_pg_reset<<8) + (ate_pma_pwr_stable<<12));
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM7, ate_rx_pstate + (ate_rx_rate<<4) + (ate_rx_ref_ld_val<<8));
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM8, ate_rx_vco_ld_val);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING1, ate_rx_cdr_ppm_max + (ate_rx_cdr_ssc_en<<8) + (ate_rx_invert<<12));
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_CONTROL2, ate_tx_misc + (ate_tx_term_ctrl<<8));
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM2, (ate_tx_width<<4) + ate_tx_rate);
do_write(&JECS_PMA1_BROADCAST_ETH_CLK_CTRL, (ate_tx_pll_word_clk_freq<<12)+(ate_tx_ropll_div16p5_clk_en<<8) + (ate_tx_ropll_125mhz_clk_en<<4) + ate_rx_125mhz_clk_en);
do_write(&JECS_PMA1_BROADCAST_TX_DIV_CLK_CTRL, ate_tx_dig_ropll_div_clk_sel);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_CONTROL, (ate_rx_term_ctrl<<4) +ate_rx_term_acdc + (ate_rx_term_en<<8));
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM4, (ate_rx_eq_ctle_pole<<8) + ate_rx_eq_ctle_boost);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM3, (ate_rx_eq_afe_rate<<4) + ate_rx_dfe_bypass + (ate_rx_eq_att_lvl<<8));
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM9, ate_rx_width);
do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL2, (ate_rx_eq_vga_gain<<8) +ate_rx_eq_dfe_tap2);
do_write(&JECS_PMA1_BROADCAST_RX_EQ_CTRL1, (ate_rx_eq_dfe_float_en<<12) + ate_rx_eq_afe_config);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM2, ate_rx_cdr_vco_config + (ate_rx_delta_iq<<12));
do_write(&JECS_PMA1_BROADCAST_RX_ADAPT_CTRL, ate_rx_adapt_sel);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_ADAPT_SETTING, (ate_rx_adapt_mode<<4) + ate_rx_adapt_cont + (ate_rx_offcan_cont<<8));
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, ate_tx_eq_main);
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, ate_tx_eq_post);
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, ate_tx_eq_pre);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM6, (ate_rx_misc<<8));
do_write(&JECS_PMA1_BROADCAST_RX_DCC_CTRL, ate_rx_dcc_ctrl_cm_range + (ate_rx_dcc_ctrl_diff_range<<4));
do_write(&JECS_PMA1_BROADCAST_RECEIVER_REQ_PARAM5, (ate_rx_lpd<<12) + ate_rx_eq_dfe_tap1);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING2, (ate_rx_sigdet_hf_en<<4) + (ate_rx_sigdet_lf_threshold<<12) + (ate_rx_sigdet_hf_threshold<<8) +ate_rx_div16p5_clk_en);
do_write(&JECS_PMA1_BROADCAST_RECEIVER_DATAPATH_SETTING3, ate_rx_sigdet_lfps_filter_en);
do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL2, ate_tx_ropll_cp_ctl_intg + (ate_tx_ropll_cp_ctl_prop<<8) + (ate_tx_ropll_bypass<<7));
do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL4, ate_tx_ropll_postdiv + (ate_tx_ropll_rc_filter<<4) + (ate_tx_ropll_refdiv<<8) + (ate_tx_ropll_refsel<<12) + (ate_tx_ropll_v2i_mode<<14));
do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL3, ate_tx_ropll_fbdiv + (ate_tx_ropll_out_div<<8) + (ate_tx_ropll_div_clk_en<<7));
do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL5, ate_tx_ropll_vco_low_freq + (ate_tx_ropll_word_clk_div_sel<<4) + 0x100);
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_REQ_PARAM1, (ate_tx_pstate<<8) +ate_tx_lpd+(ate_tx_mpll_en<<4));
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_CLKRDY, ate_tx_clk_rdy);
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_DATAPATH_SETTING, ate_tx_align_wide_xfer_en + (ate_tx_invert<<4));
do_write(&JECS_PMA1_BROADCAST_TRANS_REQ_CTRL1, ate_tx_dcc_ctrl_cm_range + (ate_tx_dcc_ctrl_diff_range<<4)+(ate_tx_fastedge_en<<8));
do_write(&JECS_PMA1_BROADCAST_CONTEXT_RESTORE_CTRL3, ate_tx_dual_cntx_en);
do_write(&JECS_PMA1_BROADCAST_TRANS_INTERFACE_CTRL, ate_tx_dly_cal_en);
do_write(&JECS_PMA1_BROADCAST_RX_DIV_CLK_CTRL, ate_rx_dig_div_clk_sel + (ate_rx_div_clk_en<<4) + (ate_rx_div_clk_sel<<8));
}
/**********************************************************************************************************************
* Function: vnet_set_mac_address
* Description: vnet set mac address
* Input:
* <name> <type> <desc>
* dev net_device * network device
* addr void * network address
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void init_jecspma(uint32_t ecpri_speed_sel)
{
uint32_t i = 0;
//PCS Protocol Sel
do_write(&JECS_CTRL_PROTOCOL_SEL, do_read_volatile(&JECS_CTRL_PROTOCOL_SEL) | BIT1); //??
do_write(&JECS_PMA1_CPRI_PCS_STATUS_CTRL, 0); //""
do_write(&JECS_PMA1_PCS_BIT_REV_CTRL, 0x111);//20220207 modify 32BIT&REVERSE
do_write(&JECS_PMA1_CPRI_SIGDET, BIT4|BIT0);//pcs signal detect sel by manual
do_write(&JECS_PMA1_TX_CLK_SEL, 0x1);
#if 1 //10G
do_write(&JECS_PHY_BS_CTRL, (BIT4 + (7<<6)));
#endif
init_pma_commonconfig_ex(ecpri_speed_sel);
#if 1 //10G
//do_write(&JECS_PMA1_BROADCAST_PMA_LOOPBACK_CTRL, (0x8000 + BIT4));
//do_write(&JECS_PMA1_BROADCAST_PMA_LOOPBACK_CTRL, (0x8000 + BIT4));
//define eq para
do_write(&JECS_PMA1_BROADCAST_EQ_INIT_C0, 0x40);
do_write(&JECS_PMA1_BROADCAST_EQ_INIT_CN1, 0x4);//c-1
do_write(&JECS_PMA1_BROADCAST_EQ_INIT_CP1, 0x1c);
do_write(&JECS_PMA1_BROADCAST_EQ_PRESET_C0, 92);//c0
do_write(&JECS_PMA1_BROADCAST_EQ_PRESET_CN1, 4);//c-1 pre
do_write(&JECS_PMA1_BROADCAST_EQ_PRESET_CP1, 0);//c+1
//do_write(&JECS_PMA1_PCS_PRBS_UDP_SEND, 0x1);
#endif
do_write(&JECS_PMA1_PHY_RESET, 0x1); //phy_reset=1
//printf("[init_jecspma] JECS PHY RESET\n");
do_write(&JECS_PMA1_SRAM_CTRL, 0x101); //SHH:0x1//sram_bootload_bypass=1
do_write(&JECS_PMA1_PHY_RESET, 0x0); //phy_reset=0
while ((do_read_volatile(&JECS_PMA1_SRAM_STATUS) & BIT0) != BIT0); //check sram_init_done=1
//init_fastjecspma();
/* ecpri PMA1 Clock cfg start */
for (i = 0; i < 16384; i++)
{
do_write((JECS_PMA1_CFG + 0xc000ul * 4 + i * 4), do_read_volatile(&pma_fw[i]));
}
do_write((JECS_PMA1_CFG + 0x101ul * 4), do_read_volatile(JECS_PMA1_CFG + 0x101ul * 4) | BIT1);
for (i = 0; i < 16384; i++)
{
do_write((JECS_PMA1_CFG + 0xc000ul * 4 + i * 4), do_read_volatile(&pma_fw[i+16384]));
}
/* ecpri PMA1 Clock cfg end */
//SRAM ECC DisEn and Init Done
do_write(&JECS_PMA1_SRAM_CTRL, 0x1101); //SHH:0x1001//sram_ext_ld_done=1
//printf("[init_jecspma] JECS SRAM EXTDONE\n");
}
/**********************************************************************************************************************
* Function: vnet_init
* Description: vnet module load function
* Input: none
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void init_jecspma_rxtx(void)
{
//Disable Tx and Rx RST
do_write(&JECS_PMA1_LANE0_TRANSMITTER_CONTROL1, 0x0);
do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, 0x0);
//Wait Ack Done
while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0);
while (do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0);
//printf("[init_jecspma_rxtx] JECS TRX ACK DONE\n");
//Enable TX and RX Req
do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1);
do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1);
//Wait ACK and Disable Req
while (!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0));
while (!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0));
do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0);
do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0);
//Wait Ack Done
while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0);
while (do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0);
//printf("[init_jecspma_rxtx] JECS TRX ACK DONE\n");
//P0 PSTATE
do_write(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_PARAM7) & 0xfff0);
do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1, do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_PARAM1) & 0xff);
do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x1);
do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x1);
//Wait ACK and Disable Req
while (!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0));
while (!(do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0));
do_write(&JECS_PMA1_LANE0_TRANSMITTER_REQ, 0x0);
do_write(&JECS_PMA1_LANE0_RECEIVER_REQ, 0x0);
//Wait Ack Done
while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_REQ_ACK) & BIT0);
while (do_read_volatile(&JECS_PMA1_LANE0_TRANSMITTER_REQ_ACK) & BIT0);
//printf("[init_jecspma_rxtx] JECS TRX ACK DONE\n");
//Enable Data
do_write(&JECS_PMA1_LANE0_TRANSMITTER_DATAPATH_EN, 0x1);
do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, 0x1);
while(do_read_volatile(&JECS_PMA1_LANE0_TRANS_PLL_STATE) == 0);
//printf("[init_jecspma_rxtx] JECS TX VALID\n");
//wait rx valid
while(do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) == 0);
//printf("[init_jecspma_rxtx] JECS RX RX VALID\n");
}
/**********************************************************************************************************************
* Function: vnet_exit
* Description: vnet module unload function
* Input: none
* Output: none
* Return: none
* Others: none
**********************************************************************************************************************/
void ecpri_pma_rx_adapt(void)
{
uint32_t i = 0;
#if 1 //10G
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ1, 24);
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ2, 0);
do_write(&JECS_PMA1_BROADCAST_TRANSMITTER_EQ3, 0);
//printf("[ecpri_init] P4\n");
//usleep(100);
ucp_nop(100000);
//delay_us(100);
for (i = 0; i < 1; i++)
{
do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, BIT4);//reg rx_data_en
do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4);//RX_ADAPT_IN_PROG
//do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_MUX_CTRL, 0x1);//cfg sel rxX_adapt_in_prog
//do_write(&JECS_PMA1_LANE0_RECEIVER_CONTROL_MUX_CTRL, 0x1);
do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) | BIT4);//rx0_reset
//usleep(5);
ucp_nop(5000);
//delay_us(5);
do_write(&JECS_PMA1_LANE0_RECEIVER_RESET, do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_RESET) & (~BIT4));
//printf("[ecpri_init]wait ack down\n");
while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK) & BIT0);
//printf("[ecpri_init]pma ack down\n");
do_write(&JECS_PMA1_LANE0_RECEIVER_DATAPATH_EN, (BIT4 + BIT0));//reg
//wait rx0_valid
while ((do_read_volatile(&JECS_PMA1_LANE0_RX_VALID_PHY) & BIT0) != 0x1) ;
do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, (BIT4 + BIT0));//RX_ADAPT_IN_PROG +adapt req
//printf("[ecpri_init]pma valid\n");
while (!(do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK) & BIT0));
//printf("[ecpri_init]pma adpt ack 1\n");
do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, BIT4);
while (do_read_volatile(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ_ACK) & BIT0);
//printf("[ecpri_init]pma adpt ack 0\n");
do_write(&JECS_PMA1_LANE0_RECEIVER_ADAPT_REQ, 0);
//printf("[ecpri_init]pma 12.2 ok\n");
}
#endif
}

46
public/ecs_rfm_spu1/driver/src/ecpri_roec.s.c Normal file
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@ -0,0 +1,46 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_roec.s.c
* Create Date: 23/08/18
* Description: eCPRI ROEC Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_roec.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: ecpri_roec_init
* Description: eCPRI ROEC init
* Input:
* <name> <type> <desc>
* dev net_device * network device
* data uint8_t * data received
* len uint32_t data length
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void ecpri_roec_init(void)
{
do_write(&ROEC_ENABLE, BIT0);
//配置收到包写入DDR里面
do_write(&DESC_PTR_CNT_2, 4);
do_write(&DESC_BEGIN_ADDR_2, (OTHER_DES_ADDR / 32));
do_write(&DESC_END_ADDR_2, (OTHER_DES_ADDR / 32 + OTHER_DES_SIZE / 32));
do_write(&DESC_SHIFT_2, 7);//16k
do_write(&DESC_TAIL_ADDR_2, (OTHER_DES_ADDR / 32) + OTHER_DES_SIZE / 32);
do_write(&DESC_START_2, 1);
}

164
public/ecs_rfm_spu1/driver/src/ecpri_switch.s.c Normal file
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@ -0,0 +1,164 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_switch.s.c
* Create Date: 23/08/18
* Description: eCPRI SWITCH Module Source File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/18 1.0 Build this module
**********************************************************************************************************************/
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "ecpri_switch.h"
/* --------------------------------------------------- <VAR DEF> --------------------------------------------------- */
/* -------------------------------------------------- <FUNC DEF> --------------------------------------------------- */
/**********************************************************************************************************************
* Function: ecpri_pcs_init
* Description: eCPRI PCS init
* Input:
* <name> <type> <desc>
* skb sk_buff * socket buffer
* dev net_device * network device
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void ecpri_pcs_init(uint32_t ecpri_speed_sel)
{
if (ecpri_speed_sel == 10) //10G
{
do_write(&MC_PCS_CONTROL_1, BIT13+BIT6+(0<<2));//0 0 0 0 = 10Gbps
do_write(&MC_PCS_CONTROL_2, 0);//0 0 0 0 = select 10GBASE-R PCS type
do_write(&MC_CFG_TX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_CFG_RX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_GENERAL_TX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_RX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_TX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
do_write(&MC_GENERAL_RX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
}
else if (ecpri_speed_sel == 25) //25G
{
do_write(&MC_PCS_CONTROL_1, BIT13+BIT6+(5<<2));//0 1 0 1 = 25Gbps
do_write(&MC_PCS_CONTROL_2, 0);//0 0 0 0 = select 10GBASE-R PCS type
do_write(&MC_CFG_TX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_CFG_RX, BIT1+BIT3);//rx_elastic_buffer_initial_fill 5
do_write(&MC_GENERAL_TX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_RX, BIT0+BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH +RESET
do_write(&MC_GENERAL_TX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
do_write(&MC_GENERAL_RX, BIT3+(32<<7)); //64b_xgmii_tx 32 SERDES WIDTH
}
}
/**********************************************************************************************************************
* Function: ecpri_mac_init
* Description: eCPRI MAC init
* Input:
* <name> <type> <desc>
* dev net_device * network device
* data uint8_t * data received
* len uint32_t data length
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void ecpri_mac_init(uint32_t ecpri_speed_sel)
{
//设置manticore收到的最大jumbo帧的大小
do_write(&MC_MAXIMUM_FRAME_SIZE, 65535);
}
/**********************************************************************************************************************
* Function: ecpri_switch_init
* Description: eCPRI SWITCH init
* Input:
* <name> <type> <desc>
* dev net_device * network device
* addr void * network address
* Output: none
* Return: operation result - success or failure.
* Others: none
**********************************************************************************************************************/
void ecpri_switch_init(uint32_t ecpri_speed_sel)
{
do_write(&MC_SWITCH_PORT0_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT0_CFG_VLAN) & (~(BIT12|BIT13|BIT14)));
do_write(&MC_SWITCH_PORT1_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT1_CFG_VLAN) & (~(BIT12|BIT13|BIT14)));
do_write(&MC_SWITCH_PORT2_CFG_VLAN, do_read_volatile(&MC_SWITCH_PORT2_CFG_VLAN) & (~(BIT12|BIT13|BIT14)));
//do_write(&MC_SWITCH_PORT0_PORT_MAC_2, 0x0A);
//do_write(&MC_SWITCH_PORT1_PORT_MAC_2, 0x0A);
//do_write(&MC_SWITCH_PORT2_PORT_MAC_2, 0x0A);
//do_write(&MC_SWITCH_PORT0_PORT_MAC_1, 0x09080706);
//do_write(&MC_SWITCH_PORT1_PORT_MAC_1, 0x09080716);
//do_write(&MC_SWITCH_PORT2_PORT_MAC_1, 0x09080726);
//enable vid 2 port 1-3
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
do_write(&MC_SWITCH_PORT_MASK_1, 0xffffffff);
do_write(&MC_SWITCH_PORT_MASK_2, 0xffffffff);
do_write(&MC_SWITCH_VLAN_ID, 0x10);
do_write(&MC_SWITCH_OP_CTRL, 0x110);
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
do_write(&MC_SWITCH_PORT_MASK_1, 0x4);
do_write(&MC_SWITCH_PORT_MASK_2, 0x0);
do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x0a0908);
do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0726<<16)+0xf));
do_write(&MC_SWITCH_OP_CTRL, 0x100);
//RX方向指定插入MAC方式进行转发过滤
while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
do_write(&MC_SWITCH_PORT_MASK_1, 0x2);
do_write(&MC_SWITCH_PORT_MASK_2, 0x0);
do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x0a0908);
do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0716<<16)+0xf));
do_write(&MC_SWITCH_OP_CTRL, 0x100);
//while ((do_read_volatile(&MC_SWITCH_OP_CTRL) & 0xf) != 0);
//do_write(&MC_SWITCH_PORT_MASK_1, 0x1);
//do_write(&MC_SWITCH_PORT_MASK_2, 0x0);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_1, 0x0a0908);
//do_write(&MC_SWITCH_FDB_MAC_INSERT_2, ((0x0706<<16)+0xf));
//do_write(&MC_SWITCH_OP_CTRL, 0x100);
do_write(&MC_SWITCH_CFG_MAE, 0XFFFF0002);
#if 1 //10G
//do_write(&MC_SWITCH_FLOOD_MASK_1, 0xffffffff);
do_write(&MC_SWITCH_FLOOD_MASK_1, 0xfffffff8); //0xfffffff1
#else
do_write(&MC_SWITCH_FLOOD_MASK_1, 0xfffffff1);
#endif
//TX方向指定TRAP方式进行转发（强制转发）
do_write(&MC_SWITCH_PORT1_CFG_TRAP, 0x00000001);
}
/**********************************************************************************************************************
* Function: ecpri_pcs_link_status_get
* Description: eCPRI PCS link status get
* Input: none
* Output: none
* Return: link status - true: link up; false: link down.
* Others: none
**********************************************************************************************************************/
bool ecpri_pcs_link_status_get(void)
{
bool link_status = false;
/* check PCS receive link status is link up or not */
if (0 != (do_read_volatile(&MC_PCS_STATUS_1) & BIT2))
{
link_status = true;
}
return link_status;
}

377
public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c
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@ -1,5 +1,6 @@
#include "ecpri_timer.h"
#include "ucp_sfr_c.h"
#include "ucp_ecpri.h"
#include "phy_para.h"
#include "mtimer_com.h"
@ -10,90 +11,29 @@
#include "ecs_rfm_dm_mgt.h"
#include "mtimer_drv.h"
#include "ucp_js_ctrl.h"
#include "ctc_intr.h"
#include "ucp_handshake.h"
extern stPhyScsPara* phyPara;
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];
void ecpri_init()
extern uint32_t reCfgFlag;
extern void rfm1_fapi_callback();
void ecpri_timer_cprimode_clk_init()
{
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
// bit11：A: eth_src_clk_sel, B: cpri_div33_tx_clk
// bit19: A: PLL0分频，B: cpri_div33_tx_clk分频
JECS_CRG_PLLSEL |= BIT19; //BIT11+
// manticore tx
JECS_CRG_MANTICORE3_RST_CTRL |= BIT24;
// 扩皮模式下，ecpri timer使用cpri_div33_tx_clk，与cpri core clk同源
init_ecpri_clk();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
#if 0
init_ecpri_pma_rst();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
#endif
ecpri_pcs_rst_ctrl();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
ecpri_mtimer_init(LTE_SCS_ID, 10);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+56), flag); // 0xE0
#endif
return;
}
void init_ecpri_clk(void)
{
//JECS_CRG_PLLSEL |=BIT11+BIT4+BIT5+BIT31;
//JECS_CRG_PLLSEL |=BIT11+BIT5+BIT31;
JECS_CRG_PLLSEL |= BIT11;
//JECS_CRG_CLK_CTRL6 = 0x521000; //SYSAPB /2 apb_aclk_i
//switch_core_clk_i,
//switch_sch_clk_i,
//JECS_CRG_CLK_CTRL7 = 0x520000;//jecs_pma_tx0_ropll_div33_clk
//ecpri_switch_mae_core_clk
//JECS_CRG_CLK_CTRL8 = 0x520000;//jecs_pma_tx0_ropll_div33_clk
//ecpri_pcs_xgmii_tx_clk
JECS_CRG_CLK_CTRL9 = 0x521000;//jecs_pcs_xgmii_tx_clk
//ecpri_pcs_xgmii_rx_clk
//JECS_CRG_CLK_CTRL0 = 0x521000;//jecs_pma_rx0_div33_clk
}
void init_ecpri_pma_rst(void)
{
//cancell jecs pma rst
JECS_CRG_PMA16_RST_CTRL |= BIT24;
JECS_CRG_PMA8_RST_CTRL |= BIT24;
JECS_CRG_PMA9_RST_CTRL |= BIT24;
JECS_CRG_PMA10_RST_CTRL |= BIT24;
JECS_CRG_PMA11_RST_CTRL |= BIT24;
JECS_CRG_PMA12_RST_CTRL |= BIT24;
JECS_CRG_PMA13_RST_CTRL |= BIT24;
JECS_CRG_PMA14_RST_CTRL |= BIT24;
JECS_CRG_PMA15_RST_CTRL |= BIT24;
}
void ecpri_pcs_rst_ctrl()
{
//cancell ecpri's rst
//JECS_CRG_MANTICORE0_RST_CTRL |= BIT24;
//JECS_CRG_MANTICORE1_RST_CTRL |= BIT24;
//JECS_CRG_MANTICORE2_RST_CTRL |= BIT24;
JECS_CRG_MANTICORE3_RST_CTRL |= BIT24; // manticore tx
//JECS_CRG_MANTICORE4_RST_CTRL |= BIT24;
//JECS_CRG_MANTICORE5_RST_CTRL |= BIT24; // ecpri_serdes_reset_tx
//JECS_CRG_MANTICORE6_RST_CTRL |= BIT24;
//JECS_CRG_MANTICORE7_RST_CTRL |= BIT24;
//JECS_CRG_MANTICORE8_RST_CTRL |= BIT24;
//ECPRI_RST_CFG_REG |= BIT24;
}
void ecpri_mtimer_init(int32_t nScsId, int32_t nTddSlotNum)
{
@ -128,27 +68,30 @@ void ecpri_timer_reconfig(phy_timer_config_ind_t *my_ecpritmr)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_ECPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_ECPRI_ID];
uint8_t nBsType = get_protocol_sel();
pMtimerPara->scsId = my_ecpritmr->scsId;
pMtimerPara->runCoreId = (uint16_t)my_ecpritmr->runCoreId;
pMtimerPara->tddPeriod = my_ecpritmr->t_period; // us
pMtimerPara->tddSlotNum = my_ecpritmr->num_tti;
pMtimerPara->slotPeriod = my_ecpritmr->t_us;
pMtimerPara->slotMaxNum = my_ecpritmr->num_tti_per_sfn;
pMtimerSfn->slotMaxNum = my_ecpritmr->num_tti_per_sfn;
//gScsId = my_ecpritmr->scsId;
//gMtimerId = MTIMER_ECPRI_ID;
//gCellSfnPara[MTIMER_ECPRI_ID].scsId = my_ecpritmr->scsId;
pMtimerSfn->slotNumPP1s = gMtimerSfnNum[SCS_1st_MTIMER_ID].slotNumPP1s;
if (PROTOCOL_ECPRI == get_protocol_sel())
{
pMtimerPara->symbolMaxNum = SLOT_SYMBOL_NUM;
pMtimerSfn->symbolMaxNum = SLOT_SYMBOL_NUM;
}
do_write_short((&(phyPara[my_ecpritmr->scsId].slotNumOfTdd)), my_ecpritmr->num_tti);
do_write_short((&(phyPara[my_ecpritmr->scsId].mtimerId)), MTIMER_ECPRI_ID);
__ucps2_synch(0);
set_ecpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
//set_ecpri_tdd_offset(); // 5ms int, tevent2 for all ape cores, dma
reCfgFlag = 1;
//set_ecpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
//set_ecpri_tdd_offset(); // 5ms int, tevent2 for all ape cores, dma
enable_mtimer_cevent_int(MTIMER_ECPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
set_ecpri_tx_slot_offset();
set_ecpri_rx_slot_offset();
@ -157,6 +100,15 @@ void ecpri_timer_reconfig(phy_timer_config_ind_t *my_ecpritmr)
set_ecpri_lte_fapi_offset();
}
if (PROTOCOL_ECPRI == nBsType)
{
for (int32_t i = 0; i < SLOT_SYMBOL_NUM; i++)
{
set_ecpri_tx_symbol_offset(i);
}
}
reCfgFlag = 2;
}
void ecpri_timer_clear_cell(uint8_t scsId)
@ -169,19 +121,79 @@ void ecpri_timer_clear_cell(uint8_t scsId)
}
}
void ecpri_timer_rcfg_act()
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_ECPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[SCS_1st_MTIMER_ID];
int32_t nScsId = pMtimerPara->scsId;
uint16_t runCore = pMtimerPara->runCoreId;
uint32_t addr = (uint32_t)&(phyPara[nScsId].runCoreId);
uint16_t cellCore = do_read_volatile_short(addr);
set_ecpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
//pMtimerSfn->txSfnNum = 0;
pMtimerSfn->txSlotNum = pMtimerSfn->slotNumPP1s; // 0
//pMtimerSfn->rxSfnNum = 0; // 1023;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;
if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
{
pMtimerSfn->txSfnNum = 0;
pMtimerSfn->rxSfnNum = 0; //1023;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
do_write(addr, pMtimerSfn->txSfnNum);
addr = (uint32_t)&(phyPara[nScsId].rxSfnNum);
do_write(addr, pMtimerSfn->rxSfnNum);
addr = (uint32_t)&(phyPara[nScsId].txSlotNum);
do_write(addr, pMtimerSfn->txSlotNum);
addr = (uint32_t)&(phyPara[nScsId].rxSlotNum);
do_write(addr, pMtimerSfn->rxSlotNum);
do_write(CTC_INT_TYPE_ADDR, (MTIMER_ECPRI_ID+1));
if (PROTOCOL_ECPRI == get_protocol_sel())
{
// ecs rfm0 cal
set_ctc_cal_int(ECS_RFM_SPU0_CORE_ID);
}
// ape tmrpoints
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
uint8_t apeId = 0;
__ucps2_synch(0);
while (32 > h1Pos)
{
apeId = 31 - h1Pos;
if (8 <= apeId)
{
return;
}
set_ctc_cal_int(apeId);
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
__ucps2_synch(0);
}
reCfgFlag = 5;
}
void ecpri_1pps_src_init(uint8_t srcId)
{
JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 13);
JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 13);
}
void set_ecpri_1pps_scratch(void)
{
set_mtimer_1pps_scratch(MTIMER_ECPRI_ID);
}
void set_ecpri_tmr_period(void)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
@ -193,6 +205,8 @@ void set_ecpri_tmr_period(void)
uint32_t tempH = SFN_PERIOD / pMtimerPara->slotPeriod / 2; //gCpriTimerPara.tddSlotNum;
set_mtimer_period(MTIMER_ECPRI_ID, tempL, tempM, tempH);
//enable_mtimer_cevent_int(MTIMER_ECPRI_ID, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
}
void set_ecpri_tdd_offset(void)
@ -200,9 +214,11 @@ void set_ecpri_tdd_offset(void)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_ECPRI_ID];
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
offset = pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
if (PROTOCOL_CPRI == get_protocol_sel())
{
offset = pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
}
uint32_t tmr2Point = pMtimerPara->tddPeriod - offset; // us // 5ms
set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_TDD_OFFSET, tmr2Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_TDD_OFFSET, MTMR_INT_TDD_OFFSET);
@ -211,28 +227,16 @@ void set_ecpri_tdd_offset(void)
void set_ecpri_tx_slot_offset()
{
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
if (PROTOCOL_CPRI == get_protocol_sel())
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
}
uint32_t tmr3Point = SFN_PERIOD - offset; // us
set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_TXSLOT_OFFSET, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_TXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
//uint32_t tempL = gCpriTimerPara.tmrMsPeriod * (tmr3Point % gCpriTimerPara.slotPeriod) / 1000;
//uint32_t addr = (uint32_t)&(phyPara[gCpriTimerPara.scsId].txSetVal);
//do_write(addr, tempL);
#if 0
// ape tmrpoints
for (int32_t i = 0; i < APE_NUM; i++)
{
int32_t tmrId = MTMR_APE0_TXSLOT + (i<<1);
set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_SLOT_OFFSET+i));
}
#endif
}
void clear_ecpri_tx_slot_offset()
@ -243,10 +247,11 @@ void clear_ecpri_tx_slot_offset()
void set_ecpri_rx_slot_offset()
{
int32_t offset = 0;
#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
#endif
if (PROTOCOL_CPRI == get_protocol_sel())
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
}
uint32_t tmr4Point = 0; // offset; // us
if (offset < 0)
@ -260,19 +265,6 @@ void set_ecpri_rx_slot_offset()
set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_RXSLOT_OFFSET, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
//uint32_t tempL = gCpriTimerPara.tmrMsPeriod * (tmr3Point % gCpriTimerPara.slotPeriod) / 1000;
//uint32_t addr = (uint32_t)&(phyPara[gCpriTimerPara.scsId].txSetVal);
//do_write(addr, tempL);
#if 0
// ape tmrpoints
for (int32_t i = 0; i < APE_NUM; i++)
{
int32_t tmrId = MTMR_APE0_RXSLOT + (i<<1);
set_mtimer_tmrpoint(MTIMER_ECPRI_ID, tmrId, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, tmrId, (MTMR_INT_SLOT_OFFSET+i));
}
#endif
}
void clear_ecpri_rx_slot_offset()
@ -283,10 +275,12 @@ void clear_ecpri_rx_slot_offset()
void set_ecpri_lte_fapi_offset(void)
{
uint32_t offset = 0;
#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
#endif
if (PROTOCOL_CPRI == get_protocol_sel())
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
offset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
}
uint32_t tmr30Point = SFN_PERIOD - offset - 500; // us
set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_LTE_FAPI, tmr30Point, MTIMER_MASK_32BIT);
@ -307,11 +301,12 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId)
volatile uint32_t h1Pos = 0;
uint8_t apeId = 0;
int32_t tmrId = 0;
#ifdef DISTRIBUTED_BS
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
txOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
rxOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
#endif
if (PROTOCOL_CPRI == get_protocol_sel())
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
txOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sTxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msOffset;
rxOffset = pEcsDmLocalMgt->pCpriDelay->cpri10ms2PP1sRxOffset; // pEcsDmLocalMgt->pCpriDelay->cpri10msRxOffset;
}
uint32_t tmr3Point = SFN_PERIOD - txOffset; // us
uint32_t tmr4Point = 0; // offset; // us
@ -325,8 +320,10 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId)
}
// ape tmrpoints
uint8_t i = 0;
h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
__ucps2_synch(0);
debug_write((DBG_DDR_IDX_DRV_BASE+48+i), h1Pos); // 0xb7e060c0
while (32 > h1Pos)
{
apeId = 31 - h1Pos;
@ -346,8 +343,13 @@ int32_t set_ecpri_ape_slot_offset(uint32_t apeCoreId)
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
__ucps2_synch(0);
i++;
debug_write((DBG_DDR_IDX_DRV_BASE+48+i), h1Pos); // 0xb7e060c0
}
reCfgFlag = 4;
return 0;
}
@ -383,6 +385,32 @@ int32_t clear_ecpri_ape_slot_offset(uint32_t apeCoreId)
return 0;
}
int32_t set_ecpri_tx_symbol_offset(uint8_t symbolId)
{
if (SLOT_SYMBOL_NUM <= symbolId)
{
return -1;
}
uint32_t longCp = (uint32_t)4448*500000/(4448+4384); // ns
uint32_t shortCp = (uint32_t)4384*500000/(4448+4384); // ns
uint32_t tmrPoint = SFN_PERIOD - INT_DELAY;
if (1 >= symbolId)
{
tmrPoint += ((longCp*symbolId)/1000);
}
else
{
tmrPoint += ((longCp + shortCp*(symbolId-1))/1000);
}
set_mtimer_tmrpoint(MTIMER_ECPRI_ID, MTMR_ECPRI_TX_SYMBOL0+symbolId, tmrPoint, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(MTIMER_ECPRI_ID, MTMR_ECPRI_TX_SYMBOL0+symbolId, MTMR_INT_RFM0_SLOT);
return 0;
}
void set_ecpri_timer_int(void)
{
int32_t apeId = get_core_id();
@ -407,13 +435,20 @@ void stop_ecpri_timer(void)
stop_mtimer(MTIMER_ECPRI_ID);
}
uint32_t lastEcpriTxSlotCnt = 0;
uint32_t nowEcpriTxSlotCnt = 0;
uint32_t rfmEcpriSlotErrCnt = 0;
uint32_t rfmEcpriSlotErrMax = 0;
void isr_ecpri_timer(void)
{
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
uint32_t cEventFlag = 0;
uint32_t tEventAddr = 0;
uint32_t tFlagAddr = 0;
uint32_t cFlagAddr = 0;
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_ECPRI_ID];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_ECPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_ECPRI_ID];
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_ECPRI_ID);
@ -445,15 +480,53 @@ void isr_ecpri_timer(void)
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+1), pMtimerInt->pp1sIntCnt); // 0xb7e08004
}
if (cEventFlag & (1<<MTMR_CEVENT_CNT14H)) // 10ms int
{
do_write((tmrBaseAddr+MTMR_CEVENT_REG), (1<<MTMR_CEVENT_CNT14H));
do_write(cFlagAddr, (1<<MTMR_CEVENT_CNT14H)); // clear int flag
pMtimerInt->sfnIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+2048+2), pMtimerInt->sfnIntCnt); // 0xb7e08008
#endif
#if 0
nowEcpriTxSlotCnt = GET_STC_CNT();
if ((nowEcpriTxSlotCnt > lastEcpriTxSlotCnt) && (2 < pMtimerInt->sfnIntCnt))
{
uint32_t cost = nowEcpriTxSlotCnt - lastEcpriTxSlotCnt;
if ((10005000 < cost) || (9995000 > cost))
{
rfmEcpriSlotErrCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+108), rfmEcpriSlotErrCnt); // 0x81b0
debug_write((DBG_DDR_IDX_DRV_BASE+2048+109), cost); // 0x81b4
}
if (cost > rfmEcpriSlotErrMax)
{
rfmEcpriSlotErrMax = cost;
}
debug_write((DBG_DDR_IDX_DRV_BASE+2048+110), rfmEcpriSlotErrMax); // 0x81b8
}
lastEcpriTxSlotCnt = nowEcpriTxSlotCnt;
#endif
uint16_t nScsId = pMtimerPara->scsId;
uint16_t runCore = do_read_volatile_short(&(phyPara[nScsId].runCoreId));
if (((runCore & pMtimerPara->runCoreId) == pMtimerPara->runCoreId) && (4 == reCfgFlag))
//if ((runCore == pMtimerPara->runCoreId) && (3 == reCfgFlag))
{
//debug_write((DBG_DDR_IDX_DRV_BASE+907), GET_STC_CNT()); // 0xe2c // timer restart finished
ecpri_timer_rcfg_act();
//pMtimerCal->sfnCalFinished = 1;
}
}
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_10ms)); // clear int
}
if ((tmrIntcFlag & (1 << MTMR_INT_TDD_OFFSET))) /* tmr int */
{
tFlagAddr = tmrBaseAddr + MTMR_TINTF00_REG + 6*(MTMR_INT_TDD_OFFSET<<2);
tEventAddr = tmrBaseAddr + MTMR_TEVENT0_REG;
tEventFlag = do_read_volatile(tFlagAddr);
if (tEventFlag & (1<<MTMR_TDD_OFFSET)) // tdd offset int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET));
do_write(tEventAddr, (1<<MTMR_TDD_OFFSET));
do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET)); // clear int flag
pMtimerInt->tddOffsetIntCnt++;
// start_csu_timing
@ -468,18 +541,23 @@ void isr_ecpri_timer(void)
if ((tmrIntcFlag & (1 << MTMR_INT_SLOT_OFFSET))) /* tmr int */
{
tFlagAddr = tmrBaseAddr + MTMR_TINTF00_REG + 6*(MTMR_INT_SLOT_OFFSET<<2);
tEventAddr = tmrBaseAddr + MTMR_TEVENT0_REG;
tEventFlag = do_read_volatile(tFlagAddr);
if (tEventFlag & ((1<<MTMR_TXSLOT_OFFSET)|(1<<MTMR_RXSLOT_OFFSET)))
if (tEventFlag & ((1<<MTMR_TXSLOT_OFFSET)|(1<<MTMR_RXSLOT_OFFSET)|(1<<MTMR_LTE_FAPI)))
{
if (tEventFlag & (1<<MTMR_TXSLOT_OFFSET)) // tx slot offset
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TXSLOT_OFFSET));
do_write(tEventAddr, (1<<MTMR_TXSLOT_OFFSET));
do_write(tFlagAddr, (1<<MTMR_TXSLOT_OFFSET)); // clear int flag
pMtimerInt->txSlotIntCnt++;
//uint32_t addr = 0;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+2048+4), pMtimerInt->txSlotIntCnt); // 0xb7e08010
#endif
if (5 == reCfgFlag)
{
reCfgFlag = 0;
}
pMtimerSfn->txSlotNum++;
__ucps2_synch(0);
if (pMtimerSfn->txSlotNum == pMtimerSfn->slotMaxNum)
@ -489,6 +567,25 @@ void isr_ecpri_timer(void)
pMtimerSfn->txSlotNum = 0;
}
__ucps2_synch(0);
#if 1
nowEcpriTxSlotCnt = GET_STC_CNT();
if ((nowEcpriTxSlotCnt > lastEcpriTxSlotCnt) && (2 < pMtimerInt->txSlotIntCnt))
{
uint32_t cost = nowEcpriTxSlotCnt - lastEcpriTxSlotCnt;
if ((1005000 < cost) || (995000 > cost))
{
rfmEcpriSlotErrCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+2048+108), rfmEcpriSlotErrCnt); // 0x81b0
debug_write((DBG_DDR_IDX_DRV_BASE+2048+109), cost); // 0x81b4
}
if (cost > rfmEcpriSlotErrMax)
{
rfmEcpriSlotErrMax = cost;
}
debug_write((DBG_DDR_IDX_DRV_BASE+2048+110), rfmEcpriSlotErrMax); // 0x81b8
}
lastEcpriTxSlotCnt = nowEcpriTxSlotCnt;
#endif
}
if (tEventFlag & (1<<MTMR_RXSLOT_OFFSET)) // rx slot offset
{
@ -509,6 +606,18 @@ void isr_ecpri_timer(void)
}
__ucps2_synch(0);
}
if (tEventFlag & (1<<MTMR_LTE_FAPI)) // LTE FAPI
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_LTE_FAPI));
do_write(tFlagAddr, (1<<MTMR_LTE_FAPI)); // clear int flag
pMtimerInt->lteFapiIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+2048+6), pMtimerInt->lteFapiIntCnt); // 0xb7e08018
debug_write((DBG_DDR_IDX_DRV_BASE+672+(pMtimerInt->lteFapiIntCnt&0x1f)), (GET_STC_CNT()-pMtimerSfn->txSlotTiming)); //get_tx_nr_slot(1)); // 0xb7e06a80
#endif
rfm1_fapi_callback();
}
tEventFlag = do_read_volatile(tFlagAddr);
}
do_write((tmrBaseAddr+MTMR_INTC_REG), (1 << MTMR_INT_SLOT_OFFSET)); // clear int

167
public/ecs_rfm_spu1/driver/src/gpio_drv.s.c
View File

@ -13,68 +13,71 @@ uint32_t gGpioDataAddr[4] = {GPIO0A_DATA_REG_ADDR, GPIO0B_DATA_REG_ADDR, GPIO1
int32_t hw_gpio_init()
{
#ifdef INTEGRATED_BS
volatile uint32_t h1Pos = 0;
uint32_t nGpioPin = 0;
uint8_t i = 0;
uint8_t j = 0;
uint8_t k = 0;
uint8_t pinId = 0;
uint32_t pinAddr = 0;
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
for (i = 0; i < 3; i++) // tx, rx, orx
if (PROTOCOL_JESD == get_protocol_sel())
{
volatile uint32_t h1Pos = 0;
uint32_t nGpioPin = 0;
uint8_t i = 0;
uint8_t j = 0;
uint8_t k = 0;
uint8_t pinId = 0;
uint32_t pinAddr = 0;
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
for (i = 0; i < 3; i++) // tx, rx, orx
{
k = 0;
for (j = 0; j < 4; j++)
{
nGpioPin = do_read_volatile(GPIO_JESD_RF_BIT + (i<<5) + (j<<2));
h1Pos = __builtin_clz(nGpioPin); // 从高bit开始，第一个1前面的0的个数
while (32 > h1Pos)
{
pinId = 31 - h1Pos;
pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[k].pinId) + sizeof(stGpioInfo) * JESD_RF_CH_NUM * i;
do_write_byte(pinAddr, (pinId + (j<<5)));
do_write_byte((pinAddr+1), ((do_read_volatile(GPIO_JESD_RF_VALID + (i<<5) + (j<<2)) >> pinId) & 0x1));
do_write(gGpioDirAddr[j], (do_read_volatile(gGpioDirAddr[j])|(1<<pinId)));
k++;
if (JESD_RF_CH_NUM < k)
{
return -1;
}
nGpioPin &= (~(1 << pinId));
h1Pos = __builtin_clz(nGpioPin);
}
}
}
k = 0;
for (j = 0; j < 4; j++)
{
nGpioPin = do_read_volatile(GPIO_JESD_RF_BIT + (i<<5) + (j<<2));
nGpioPin = do_read_volatile(GPIO_JESD_TRIGGER_BIT + (j<<2));
h1Pos = __builtin_clz(nGpioPin); // 从高bit开始，第一个1前面的0的个数
while (32 > h1Pos)
{
pinId = 31 - h1Pos;
pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[k].pinId) + sizeof(stGpioInfo) * JESD_RF_CH_NUM * i;
pinAddr = (uint32_t)(&pGpioInfo->triggerGpioInfo.pinId);
do_write_byte(pinAddr, (pinId + (j<<5)));
do_write_byte((pinAddr+1), ((do_read_volatile(GPIO_JESD_RF_VALID + (i<<5) + (j<<2)) >> pinId) & 0x1));
do_write_byte((pinAddr+1), ((do_read_volatile(GPIO_JESD_TRIGGER_VALID + (j<<2)) >> pinId) & 0x1));
do_write(gGpioDirAddr[j], (do_read_volatile(gGpioDirAddr[j])|(1<<pinId)));
k++;
if (JESD_RF_CH_NUM < k)
{
return -1;
}
nGpioPin &= (~(1 << pinId));
h1Pos = __builtin_clz(nGpioPin);
break;
//nGpioPin &= (~(1 << pinId));
///h1Pos = __builtin_clz(nGpioPin);
}
}
}
k = 0;
for (j = 0; j < 4; j++)
else
{
nGpioPin = do_read_volatile(GPIO_JESD_TRIGGER_BIT + (j<<2));
h1Pos = __builtin_clz(nGpioPin); // 从高bit开始，第一个1前面的0的个数
while (32 > h1Pos)
{
pinId = 31 - h1Pos;
pinAddr = (uint32_t)(&pGpioInfo->triggerGpioInfo.pinId);
do_write_byte(pinAddr, (pinId + (j<<5)));
do_write_byte((pinAddr+1), ((do_read_volatile(GPIO_JESD_TRIGGER_VALID + (j<<2)) >> pinId) & 0x1));
do_write(gGpioDirAddr[j], (do_read_volatile(gGpioDirAddr[j])|(1<<pinId)));
k++;
break;
//nGpioPin &= (~(1 << pinId));
///h1Pos = __builtin_clz(nGpioPin);
}
do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x000F0000)); // pinmux, GPIO1B25 and GPIO1B24, gpio func, 0x3
do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25))); // GPIO1B25, output, 10ms trigger for phy
}
#else
do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x000F0000)); // pinmux, GPIO1B25 and GPIO1B24, gpio func, 0x3
do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25))); // GPIO1B25, output, 10ms trigger for phy
#endif
return 0;
}
@ -132,51 +135,53 @@ int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState)
int32_t set_trigger_state(uint8_t nState)
{
#ifdef INTEGRATED_BS
if ((GPIO_ON != nState) && (GPIO_OFF != nState))
{
return -1;
}
if (PROTOCOL_JESD == get_protocol_sel())
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
uint8_t pinGroup = 0;
uint8_t pinId = 0;
uint8_t valid = 0;
uint32_t dataAddr = 0;
pinId = pGpioInfo->triggerGpioInfo.pinId;
valid = pGpioInfo->triggerGpioInfo.vaFlag;
pinGroup = pinId >> 5;
if (3 < pinGroup)
{
return -1;
}
pinId = pinId & 0x1F;
dataAddr = gGpioDataAddr[pinGroup];
if (((LOW_AS_VALID == valid) && (GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_OFF == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)&(~(1<<pinId))));
}
else if (((LOW_AS_VALID == valid) && (GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_ON == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)|(1<<pinId)));
uint8_t pinGroup = 0;
uint8_t pinId = 0;
uint8_t valid = 0;
uint32_t dataAddr = 0;
pinId = pGpioInfo->triggerGpioInfo.pinId;
valid = pGpioInfo->triggerGpioInfo.vaFlag;
pinGroup = pinId >> 5;
if (3 < pinGroup)
{
return -1;
}
pinId = pinId & 0x1F;
dataAddr = gGpioDataAddr[pinGroup];
if (((LOW_AS_VALID == valid) && (GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_OFF == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)&(~(1<<pinId))));
}
else if (((LOW_AS_VALID == valid) && (GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_ON == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)|(1<<pinId)));
}
else
{
return -1;
}
}
else
{
return -1;
if (GPIO_ON == nState)
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT25)); // GPIO1B25, high
}
else
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT25)))); // GPIO1B25, low
}
}
#else
if (GPIO_ON == nState)
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT25)); // GPIO1B25, high
}
else
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT25)))); // GPIO1B25, low
}
#endif
return 0;
}

81
public/ecs_rfm_spu1/driver/src/hw_cpri.s.c
View File

@ -12,24 +12,30 @@
#include "cpri_csu.h"
#include "cpri_csu_api.h"
#include "cpri_csu_nr_7ds2u.h"
#include "ecpri_driver.h"
#include "phy_para.h"
//stCpriPara cpriPara;
//extern stCpriTimerPara gCpriTimerPara;
volatile stCpriIntStat gCpriIntStatus;
extern uint32_t reCfgFlag;
extern volatile uint32_t gVendorFlag;
stCpriCsuCmdFifoInfo txCmdFifo;
stCpriCsuCmdFifoInfo rxCmdFifo;
void cpri_init(uint32_t option)
void cpri_init(uint32_t option, uint32_t MappingMode)
{
#ifdef PALLADIUM_TEST
int32_t apeId = get_core_id();
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0xB8
#endif
phy_para_init(PROTOCOL_CPRI, option);
do_write(&JECS_CRG_PLLSEL, 0xC21);
ucp_nop(400);
#if 0
// temp, to be change
/**********************************************************************/
//JECS_CTRL_QOS_M3_SRIO_AXIM |= BIT19;
@ -38,16 +44,15 @@ void cpri_init(uint32_t option)
//JECS_CTRL_CPRI_GMAC_PHY_INT = (0x0 << 4) | (0x5 << 7) | (0x6<<10);
//do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x000C0000)); // pinmux, GPIO1B25, gpio func, 0x3
//do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|BIT25)); // GPIO1B25, output, 10ms trigger for phy
#ifdef GPS_PP1S_SYNC
do_write(PB14_CTRL_REG_ADDR, (do_read_volatile(PB14_CTRL_REG_ADDR)|(1<<7)|(1<<6)));
do_write(GPIO0_A29_PINMUX_REG_ADDR, (do_read_volatile(GPIO0_A29_PINMUX_REG_ADDR)|0x20000000)); // pinmux, GPIO0A29, gnss pps int func, 0x2
//do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x30000000)); // pinmux, GPIO1B30, gpio func, 0x3
do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x30000000)); // pinmux, GPIO1B30, gpio func, 0x3
// do_write(&JECS_CTRL_QOS_M3_SRIO_AXIM, do_read_volatile(&JECS_CTRL_QOS_M3_SRIO_AXIM) | BIT19);
do_write(&JECS_CTRL_CPRI_GMAC_PHY_INT, (0x0 << 4) | (0x5 << 7) | (0x5<<10));
#endif
/**********************************************************************/
#endif
cpri_para_init(option);
cpri_delay_init();
@ -72,18 +77,22 @@ void cpri_init(uint32_t option)
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
#ifdef CPRI_TIMING_LTE_FDD_TEST
cpri_mtimer_init(LTE_SCS_ID, 10); // slot:1000us, one tdd has 10 slots
#else
cpri_mtimer_init(NR_SCS_30K, 10); // slot:500us, one tdd has 10 slots
#endif
//start_cpri_timer();
//if (LTE_MODE == NetType)
{
//cpri_mtimer_init(LTE_SCS_ID, 10); // slot:1000us, one tdd has 10 slots
}
//if (NR_MODE == NetType)
{
cpri_mtimer_init(NR_SCS_30K, 10); // slot:500us, one tdd has 10 slots
}
UCP_PRINT_EMPTY("cpri_timer init.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
#if 0
while (1 >= gCpriIntStatus.syncIntCnt)
{
//debug_write((DBG_DDR_IDX_DRV_BASE+126), gCpriIntStatus.syncIntCnt);
@ -93,13 +102,14 @@ void cpri_init(uint32_t option)
UCP_PRINT_EMPTY("AUX CNT1: 0x%x \r\n", AUX_CNT1);
UCP_PRINT_EMPTY("AUX CNT2: 0x%x \r\n", AUX_CNT2);
UCP_PRINT_EMPTY("SELF SYNC finish.\r\n");
#endif
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
config_cpri_map_directed(option);
// config_cpri_map_directed(8);
config_cpri_map_directed(option,MappingMode);
UCP_PRINT_EMPTY("CPRI map config finished.\r\n");
#ifdef PALLADIUM_TEST
@ -107,6 +117,18 @@ void cpri_init(uint32_t option)
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
HeaderTxRam_init(MappingMode);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0xB4
#endif
ecpri_cprimode_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
#if 0
#ifdef CPRI_TIMING_TEST
cpri_csu_init();
@ -159,16 +181,21 @@ void cpri_init(uint32_t option)
#endif
#endif
}
void cpri_ecprimode_init()
{
cpri_timer_ecprimode_clk_init();
cpri_mtimer_init(NR_SCS_30K, 10); // slot:500us, one tdd has 10 slots
}
void cpri_para_init(uint32_t option)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stCpriPara* pCpriPara = NULL; // pEcsDmLocalMgt->pCpriPara;
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
pCpriPara = pEcsDmLocalMgt->pCpriPara;
#endif
//#endif
if (NULL == pCpriPara)
{
return;
@ -265,6 +292,8 @@ void cpri_para_init(uint32_t option)
break;
}
}
debug_write((DBG_DDR_IDX_DRV_BASE+41), pCpriPara->core_clk); // 0xb7e060A4
}
void cpri_int_init(void)
@ -305,8 +334,6 @@ void cpri_int_init(void)
void isr_cpri_int(void)
{
//EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
//stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[MTIMER_CPRI_ID];
uint32_t auxFlag = AUX_INT_FLAG & 0x7;
uint32_t rfpFlag = AUX_RFP_INT_FLAG;
//uint32_t auxFlag = AUX_INT_FLAG & 0x3F;
@ -335,7 +362,7 @@ void isr_cpri_int(void)
debug_write((DBG_DDR_IDX_DRV_BASE+116), gCpriIntStatus.alarmIntCnt); // 0x1d0
if (4 > gCpriIntStatus.alarmIntCnt)
{
debug_write((DBG_DDR_IDX_DRV_BASE+116+gCpriIntStatus.alarmIntCnt), alarmFlag);// 0x1d4
debug_write((DBG_DDR_IDX_DRV_BASE+116+gCpriIntStatus.alarmIntCnt), alarmFlag);// 0x1d0
}
//debug_write((DBG_DDR_IDX_CPRI_BASE+403+((2*gCpriAlarmIntCnt)&0xFF)), gCpriTimerPara.tddOffsetIntCnt);
do_write(&ALARM_FLAG, alarmFlag);
@ -396,3 +423,23 @@ void isr_gmac_int(void)
}
}
void HeaderTxRam_init(uint32_t vendor)
{
uint32_t i,j;
HeaderRam_ins_disable();
for(i=0;i<64;i++)//Ns
{
for(j=0;j<4;j++)//
{
HeaderRam_Tx(i+64*j,0,0,0);//vendor
HeaderRam_Tx(i+64*j,1,0,0);//vendor
HeaderRam_Tx(i+64*j,2,0,0);//vendor
HeaderRam_Tx(i+64*j,3,0,0);//vendor
}
}
do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
__ucps2_synch(f_SM);
do_write(&gVendorFlag,vendor);
}

121
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -21,19 +21,19 @@
#include "gtimer_drv.h"
#include "gpio_drv.h"
#ifdef INTEGRATED_BS
//#ifdef INTEGRATED_BS
#ifdef TEST_ENABLE
#include "jesd_test.h"
#endif
#endif
//#endif
//stJesdTimerPara gJesdTmrPara[2];
extern stPhyScsPara* phyPara;
extern stSfnPara gCellSfnPara[2];
extern uint32_t gScsId;
extern uint32_t gMtimerId;
extern stSfnPara gCellSfnPara[2];
extern uint32_t gScsId;
extern uint32_t gMtimerId;
uint32_t gJesdTestMode = 0;
uint32_t gJesdTestMode = 0;
uint32_t gJesdIOMode = JESD_CSU_CTRL;
uint32_t gJesdTFMode = TDD_MODE;
@ -48,12 +48,12 @@ stJesdDelay gJesdDelay;
int32_t gCsuTxAdvanceSam = JESD_TX_ADVANCE_SAMPLE;
int32_t gCsuRxAdvanceSam = JESD_RX_ADVANCE_SAMPLE - JESD_RRU_TD;
extern void rfm1_fapi_callback();
#ifdef INTEGRATED_BS
//#ifdef INTEGRATED_BS
volatile uint32_t reCfgFlag = 0;
//volatile uint32_t reCfgFlag = 0;
extern uint32_t reCfgFlag;
void jesd_init()
{
@ -62,6 +62,8 @@ void jesd_init()
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0xB8
#endif
phy_para_init(PROTOCOL_JESD, PROTO_OPTION_NULL);
do_write(CSU_RX_TD_SAMPLE, JESD_RRU_TD);
do_write(CSU_TX_ADVANCE_SAMPLE, gCsuTxAdvanceSam);
@ -75,7 +77,7 @@ void jesd_init()
#endif
jesd_mtimer_init(MTIMER_JESD_RX0_ID, NR_SCS_30K, 10);
//jesd_mtimer_init(MTIMER_JESD_RX1_ID, NR_SCS_30K, 10);
jesd_mtimer_init(MTIMER_JESD_RX1_ID, NR_SCS_30K, 10);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0xB8
@ -201,6 +203,10 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
}
jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
#if 0
set_jesd_tmr_period(nTmrId); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
@ -210,6 +216,7 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
}
#endif
enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
@ -264,9 +271,9 @@ int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
clear_jesd_tdd_offset(nTmrId);
clear_jesd_tx_slot_offset(nTmrId);
clear_jesd_rx_slot_offset(nTmrId);
//if (LTE_SCS_ID == scsId)
if (LTE_SCS_ID == scsId)
{
//clear_cpri_lte_fapi_offset();
//clear_jesd_lte_fapi_offset();
}
return 0;
@ -278,7 +285,9 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
int32_t nScsId = pMtimerPara->scsId;
uint32_t addr = 0;
uint16_t runCore = pMtimerPara->runCoreId;
uint32_t addr = (uint32_t)&(phyPara[nScsId].runCoreId);
uint16_t cellCore = do_read_volatile_short(addr);
set_jesd_tmr_period(nTmrId); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
if (MTIMER_JESD_RX0_ID == nTmrId)
@ -291,6 +300,12 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
//pMtimerSfn->rxSfnNum = 0; // 1023;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotNumPP1s; // 0 // pMtimerSfn->slotMaxNum - 1;
if ((0 == pMtimerSfn->slotNumPP1s) && (runCore == cellCore)) // no frame header offset, and the first cell
{
pMtimerSfn->txSfnNum = 0;
pMtimerSfn->rxSfnNum = 0; //1023;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
addr = (uint32_t)&(phyPara[nScsId].txSfnNum);
do_write(addr, pMtimerSfn->txSfnNum);
addr = (uint32_t)&(phyPara[nScsId].rxSfnNum);
@ -300,21 +315,13 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
addr = (uint32_t)&(phyPara[nScsId].rxSlotNum);
do_write(addr, pMtimerSfn->rxSlotNum);
if (0 == pMtimerSfn->rxSlotNum) // ??
{
//pMtimerSfn->rxSfnNum = 1023;
//pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
}
debug_write((DBG_DDR_IDX_DRV_BASE+556), cellCore); // 0x8b0
debug_write((DBG_DDR_IDX_DRV_BASE+557), runCore); // 0x8b4
debug_write((DBG_DDR_IDX_DRV_BASE+558), pMtimerSfn->txSfnNum); // 0x8b8
debug_write((DBG_DDR_IDX_DRV_BASE+559), pMtimerSfn->rxSfnNum); // 0x8bc
do_write(CTC_INT_TYPE_ADDR, CTC_INT_TYPE_CAL);
#if 0
for (int32_t i = 0; i < APE_NUM; i++)
{
set_ctc_cal_int(i);
}
#else
do_write(CTC_INT_TYPE_ADDR, nTmrId+1);
// ape tmrpoints
uint32_t runCore = pMtimerPara->runCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
uint8_t apeId = 0;
__ucps2_synch(0);
@ -332,12 +339,10 @@ void jesd_timer_rcfg_act(int32_t nTmrId)
h1Pos = __builtin_clz(runCore);
__ucps2_synch(0);
}
#endif
reCfgFlag = 5;
}
int32_t jesd_pin_ctrl(int32_t nTmrId)
{
uint32_t tmrBaseAddr = 0;
@ -392,7 +397,7 @@ void set_jesd_tmr_period(int32_t nTmrId)
set_mtimer_period(nTmrId, tempL, tempM, tempH);
enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
//enable_mtimer_cevent_int(nTmrId, MTMR_CEVENT_CNT14H, MTMR_INT_10ms); // 10ms int
}
void jesd_1pps_src_init(uint8_t srcId)
@ -739,8 +744,8 @@ void set_jesd_rxon_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
uint32_t gapSymbolStart = LONGCP_SAM_CNT + (my_jesdtmr->num_t_dl_symb[0]-1) * SHORTCP_SAM_CNT;
uint32_t tmr26Point = (sSymbolStart + gapSymbolStart) * 1000 / pMtimerPara->tmrMsPeriod + JESD_TXRX_CHANGE_GAP;
set_mtimer_tmrpoint(nTmrId, MTMR_JESD_RXON, tmr26Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_RXON, MTMR_INT_TDD_OFFSET);
set_mtimer_tmrpoint(nTmrId, MTMR_TDD_OFFSET_2500, tmr26Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_TDD_OFFSET_2500, MTMR_INT_TDD_OFFSET);
}
void set_jesd_rxoff_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
@ -758,8 +763,8 @@ void set_jesd_rxoff_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
uint32_t tmr27Point = pMtimerPara->tddPeriod - JESD_TXRX_CHANGE_GAP;
set_mtimer_tmrpoint(nTmrId, MTMR_JESD_RXOFF, tmr27Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_JESD_RXOFF, MTMR_INT_TDD_OFFSET);
set_mtimer_tmrpoint(nTmrId, MTMR_TDD_OFFSET_7500, tmr27Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_TDD_OFFSET_7500, MTMR_INT_TDD_OFFSET);
}
void start_jesd_timer(int32_t nTmrId)
@ -862,7 +867,7 @@ void jesd_10ms_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_CEVENT_REG), BIT17);
do_write(cFlagAddr, BIT17); // clear int flag
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
if (0 == pMtimerInt->pp1sIntCnt)
{
gtimer2_start(0);
@ -879,7 +884,7 @@ uint32_t start = GET_STC_CNT();
pMtimerInt->pp1sIntCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+1), pMtimerInt->pp1sIntCnt); // 0x104
#if 0 //def PALLADIUM_TEST
#ifdef PALLADIUM_TEST
uint32_t val = 0;
for (int32_t core = 0; core < 12; core++)
{
@ -896,7 +901,7 @@ uint32_t start = GET_STC_CNT();
debug_write(((DBG_DDR_IDX_DRV_BASE+832+(core<<2)) + 3), val); // 0xd00
}
#endif
debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
}
if (cEventFlag & (1<<MTMR_CEVENT_CNT14H)) // 10ms int
{
@ -911,9 +916,9 @@ debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
//if ((runCore == pMtimerPara->runCoreId) && (3 == reCfgFlag))
{
debug_write((DBG_DDR_IDX_DRV_BASE+907), GET_STC_CNT()); // 0xe2c // timer restart finished
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
jesd_timer_rcfg_act(nTmrId);
debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
//debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
pMtimerCal->sfnCalFinished = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
@ -972,7 +977,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
tEventFlag = do_read_volatile(tFlagAddr);
__ucps2_synch(0);
if ((tEventFlag & ((1<<MTMR_TDD_OFFSET)|(1<<MTMR_JESD_TXOFF)|(1<<MTMR_JESD_TXON)|(1<<MTMR_JESD_RXON)|(1<<MTMR_JESD_RXOFF))) || (cEventFlag & (BIT11|BIT12)))
if ((tEventFlag & ((1<<MTMR_TDD_OFFSET)|(1<<MTMR_JESD_TXOFF)|(1<<MTMR_JESD_TXON)|(1<<MTMR_TDD_OFFSET_2500)|(1<<MTMR_TDD_OFFSET_7500))) || (cEventFlag & (BIT11|BIT12)))
{
if (tEventFlag & (1<<MTMR_TDD_OFFSET)) // tdd offset int
{
@ -997,20 +1002,20 @@ void jesd_tdd_callback(uint8_t nTmrId)
}
#endif
}
if (tEventFlag & (1<<MTMR_JESD_RXON)) // rx on int
if (tEventFlag & (1<<MTMR_TDD_OFFSET_2500)) // rx on int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_RXON));
do_write(tFlagAddr, (1<<MTMR_JESD_RXON)); // clear int flag
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET_2500));
do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET_2500)); // clear int flag
gRxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+5), gRxOnCnt); // 0x114
//RxOn();
set_jesd_rf_state(JESD_RF_RX, GPIO_ON);
jesd_csu_rx_start();
}
if (tEventFlag & (1<<MTMR_JESD_RXOFF)) // rx off int
if (tEventFlag & (1<<MTMR_TDD_OFFSET_7500)) // rx off int
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_JESD_RXOFF));
do_write(tFlagAddr, (1<<MTMR_JESD_RXOFF)); // clear int flag
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TDD_OFFSET_7500));
do_write(tFlagAddr, (1<<MTMR_TDD_OFFSET_7500)); // clear int flag
gRxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), gRxOffCnt); // 0x118
//RxOff();
@ -1067,10 +1072,10 @@ void isr_jesd_tdd_offset_rx0(void)
jesd_tdd_callback(tmrId);
}
uint32_t lastTxSlotCnt = 0;
uint32_t nowTxSlotCnt = 0;
uint32_t rfmSlotErrCnt = 0;
uint32_t rfmSlotErrMax = 0;
extern uint32_t lastTxSlotCnt; // = 0;
extern uint32_t nowTxSlotCnt; // = 0;
extern uint32_t rfmSlotErrCnt; // = 0;
extern uint32_t rfmSlotErrMax; // = 0;
void jesd_slot_callback(uint8_t nTmrId)
{
uint32_t tmrIntcFlag = 0;
@ -1093,7 +1098,7 @@ void jesd_slot_callback(uint8_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_TXSLOT_OFFSET));
do_write(tFlagAddr, (1<<MTMR_TXSLOT_OFFSET)); // clear int flag
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
if (5 == reCfgFlag)
{
reCfgFlag = 0;
@ -1148,7 +1153,7 @@ uint32_t start = GET_STC_CNT();
do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intNum), APE_INT_TX_SLOT);
do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intCnt), pMtimerInt->txSlotIntCnt);
__ucps2_synch(f_SMW);
debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
//debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
#if 0 // def PALLADIUM_TEST
debug_write(((DBG_DDR_IDX_DRV_BASE+8192) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), gCpriTimerPara.txSlotIntCnt); // 0x8000
debug_write(((DBG_DDR_IDX_DRV_BASE+8704) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), get_tx_nr_slot(1)); // 0x8800
@ -1181,7 +1186,7 @@ debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
{
do_write((tmrBaseAddr+MTMR_TEVENT0_REG), (1<<MTMR_RXSLOT_OFFSET));
do_write(tFlagAddr, (1<<MTMR_RXSLOT_OFFSET)); // clear int flag
uint32_t start = GET_STC_CNT();
//uint32_t start = GET_STC_CNT();
pMtimerSfn->rxSlotNum++;
__ucps2_synch(0);
if (pMtimerSfn->rxSlotNum == pMtimerSfn->slotMaxNum)
@ -1210,7 +1215,7 @@ uint32_t start = GET_STC_CNT();
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intNum), APE_INT_RX_SLOT);
do_write(&(apeCoreIntInfo[APE_INT_RX_SLOT].intCnt), pMtimerInt->rxSlotIntCnt);
__ucps2_synch(f_SMW);
debug_write((DBG_DDR_IDX_DRV_BASE+291), (GET_STC_CNT()-start)); // 0x48c
//debug_write((DBG_DDR_IDX_DRV_BASE+291), (GET_STC_CNT()-start)); // 0x48c
}
if (tEventFlag & (1<<MTMR_LTE_FAPI)) // LTE FAPI
{
@ -1242,12 +1247,12 @@ void isr_jesd_slot_rx1(void)
jesd_slot_callback(tmrId);
}
#if 0
void jesd_tdd_start_csu()
{
//uint32_t tmrBaseAddr = JS_RX0_TMR_BASE;
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_JESD_RX0_ID];
#if 0
if (JESD_TEST_MODE == gJesdTestMode)
{
// start csu
@ -1257,16 +1262,16 @@ void jesd_tdd_start_csu()
#endif
#endif
pMtimerInt->csuEnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+7), pMtimerInt->csuEnCnt); // 0x11c
}
else
#endif
{
// start csu
jesd_csu_start();
pMtimerInt->csuEnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+7), pMtimerInt->csuEnCnt); // 0x11c
}
}
#endif
#endif
//#endif

52
public/ecs_rfm_spu1/driver/src/mtimer_cal.s.c
View File

@ -12,16 +12,17 @@
#include "ecs_rfm_dm_mgt.h"
#include "mtimer_drv.h"
#include "gtimer_drv.h"
#ifdef DISTRIBUTED_BS
#include "ucp_handshake.h"
//#ifdef DISTRIBUTED_BS
#include "ucp_cpri.h"
#include "HeaderRam.h"
#include "cpri_timer.h"
extern stCpriIntStat gCpriIntStatus;
#endif
#ifdef INTEGRATED_BS
//#endif
//#ifdef INTEGRATED_BS
#include "jesd_timer.h"
#endif
//#endif
extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
@ -35,6 +36,7 @@ void mtimer_1pps_resync(uint8_t nTmrId)
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerSfnCal* pSfnCal = &gMtimerSfnCalPara[nTmrId];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
uint8_t nBsType = get_protocol_sel();
uint32_t n10msOffset = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+905), GET_STC_CNT()); // 0xe24
@ -43,21 +45,23 @@ void mtimer_1pps_resync(uint8_t nTmrId)
do_write(CSU_STOP_CMD_ADDR, 1);
gtimer2_stop(0);
#ifdef DISTRIBUTED_BS
gCpriIntStatus.cpriSyncFlag = 0;
stop_cpri_timer();
//set_cpri_tx_rfp();
set_cpri_tmr_ctrl();
start_cpri_timer();
stCpriDelayMeasure* pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
n10msOffset = pCpriDelay->cpri10msOffset;
#endif
#ifdef INTEGRATED_BS
stop_jesd_timer(MTIMER_JESD_RX0_ID);
stop_jesd_timer(MTIMER_JESD_TX0_ID);
start_jesd_timer(MTIMER_JESD_RX0_ID);
start_jesd_timer(MTIMER_JESD_TX0_ID);
#endif
if (PROTOCOL_JESD == nBsType)
{
stop_jesd_timer(MTIMER_JESD_RX0_ID);
stop_jesd_timer(MTIMER_JESD_TX0_ID);
start_jesd_timer(MTIMER_JESD_RX0_ID);
start_jesd_timer(MTIMER_JESD_TX0_ID);
}
else // if (DISTRIBUTED_BS == nBsType)
{
gCpriIntStatus.cpriSyncFlag = 0;
stop_cpri_timer();
//set_cpri_tx_rfp();
set_cpri_tmr_ctrl();
start_cpri_timer();
stCpriDelayMeasure* pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
n10msOffset = pCpriDelay->cpri10msOffset;
}
gtimer2_start(0);
uint32_t addr = (uint32_t)&(phyPara[pMtimerPara->scsId].gpsOffset);
@ -73,6 +77,7 @@ void mtimer_1pps_sfn_cal(uint8_t nTmrId)
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerSfnCal* pSfnCal = &gMtimerSfnCalPara[nTmrId];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
uint8_t nBsType = get_protocol_sel();
//stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
pSfnCal->sfnCalCnt = do_read_volatile(ARM_SFN_NUM_ADDR);
@ -115,12 +120,17 @@ void mtimer_1pps_sfn_cal(uint8_t nTmrId)
pMtimerSfn->rxSfnNum = pSfnCal->sfnCalCnt-1;
pMtimerSfn->rxSlotNum = pMtimerSfn->slotMaxNum - 1;
do_write(CTC_INT_TYPE_ADDR, CTC_INT_TYPE_CAL);
do_write(CTC_INT_TYPE_ADDR, (nTmrId+1));
if (PROTOCOL_ECPRI == nBsType)
{
// ecs rfm0 cal
set_ctc_cal_int(ECS_RFM_SPU0_CORE_ID); // sfn calibration for ecs rfm0
}
for (int32_t i = 0; i < APE_NUM; i++)
{
set_ctc_cal_int(i);
}
//set_ctc_cal_int(10); // sfn calibration for ecs rfm0
pAlarmStatus->alarmFlag = ALARM_SFN_CAL;
pAlarmStatus->alarmSfnCalCnt++;
}

299
public/ecs_rfm_spu1/driver/src/mtimer_cell.s.c
View File

@ -1,23 +1,24 @@
#include "mtimer_cell.h"
#include "phy_para.h"
#include "ucp_utility.h"
#ifdef DISTRIBUTED_BS
//#ifdef DISTRIBUTED_BS
#include "cpri_timer.h"
#include "ecpri_timer.h"
#endif
#ifdef INTEGRATED_BS
//#endif
//#ifdef INTEGRATED_BS
#include "jesd_timer.h"
#endif
//#endif
stPhyCellPara* pPhyCellPara = (stPhyCellPara*)PHY_CELL_ADDR;
extern uint32_t gScsId;
extern uint32_t gMtimerId;
extern stSfnPara gCellSfnPara[2]; // cell para
//extern stSfnPara gCellSfnPara[2]; // cell para
extern stPhyScsPara* phyPara;
extern uint32_t reCfgFlag;
extern void check_phy_cell(void);
#if 0
void phy_cell_para_init(int32_t nScsId)
{
memset_ext((void*)pPhyCellPara, 0, sizeof(stPhyCellPara));
@ -35,20 +36,23 @@ void phy_cell_para_init(int32_t nScsId)
gCellSfnPara[gMtimerId].rxSlotNum = gCellSfnPara[gMtimerId].slotMaxNum - 1;
gCellSfnPara[gMtimerId].rxSfnNum = 1023;
}
#endif
void mtimer_init4phy(phy_timer_config_ind_t *mtmr)
{
uint8_t nBsType = get_protocol_sel();
//phy_cell_para_init(mtmr->scsId);
memcpy_ucp((void*)(&pPhyCellPara->phyPara), (void*)mtmr, sizeof(phy_timer_config_ind_t));
__ucps2_synch(f_SM);
gScsId = mtmr->scsId;
#ifdef DISTRIBUTED_BS
gMtimerId = MTIMER_CPRI_ID;
#endif
#ifdef INTEGRATED_BS
gMtimerId = MTIMER_JESD_RX0_ID;
#endif
if (PROTOCOL_JESD == nBsType)
{
gMtimerId = MTIMER_JESD_RX0_ID;
}
else
{
gMtimerId = MTIMER_CPRI_ID;
}
do_write((&(pPhyCellPara->flag)), PHY_CELL_FLAG);
__ucps2_synch(f_SM);
@ -59,7 +63,8 @@ void mtimer_init4phy(phy_timer_config_ind_t *mtmr)
int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
{
int32_t nScsId = my_mtmr->scsId;
short timerId = do_read_volatile_short(&(phyPara[nScsId].mtimerId));
short timerId = 0; // do_read_volatile_short(&(phyPara[nScsId].mtimerId));
uint8_t nBsType = get_protocol_sel();
short runCore = do_read_volatile_short(&(phyPara[nScsId].runCoreId));
__ucps2_synch(f_SMR);
@ -77,84 +82,86 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
}
}
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+33), i); // 0xb7e06084
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+33), i); // 0xb7e06084
// 没有任何scs建过小区
if (PHY_SCS_MAX_NUM == i) // no cell on cpri timer, build cell on cpri timer
{
do_write_short((&(phyPara[nScsId].mtimerId)), SCS_1st_MTIMER_ID);
#ifdef DISTRIBUTED_BS
cpri_timer_reconfig(my_mtmr);
if (-1 == set_cpri_ape_slot_offset(my_mtmr->runCoreId))
{
return -2; // coreId error, ape slot int set error
}
#endif
#ifdef INTEGRATED_BS
jesd_timer_reconfig(MTIMER_JESD_RX0_ID, my_mtmr);
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX0_ID, my_mtmr->runCoreId))
if (PROTOCOL_JESD == nBsType)
{
return -2; // coreId error, ape slot int set error
jesd_timer_reconfig(MTIMER_JESD_RX0_ID, my_mtmr);
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX0_ID, my_mtmr->runCoreId))
{
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // coreId error, ape slot int set error
}
}
else
{
cpri_timer_reconfig(my_mtmr);
if (-1 == set_cpri_ape_slot_offset(my_mtmr->runCoreId))
{
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // coreId error, ape slot int set error
}
}
#endif
timerId = SCS_1st_MTIMER_ID;
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+34), my_mtmr->runCoreId); // 0xb7e06088
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+34), my_mtmr->runCoreId); // 0xb7e06088
}
else // 已建过小区
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
if (my_mtmr->scsId == do_read_volatile_short(&(phyPara[i].scsId))) // 继续在第一个子载波建小区
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+35), my_mtmr->runCoreId); // 0xb7e0608c
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+35), my_mtmr->runCoreId); // 0xb7e0608c
if (0 != (my_mtmr->runCoreId & runCore))
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), runCore); // 0xb7e06090
debug_write((DBG_DDR_IDX_DRV_BASE+36), runCore); // 0xb7e06090
return -1; // 该小区已建过
}
else
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
#ifdef DISTRIBUTED_BS
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
if (-1 == set_cpri_ape_slot_offset(my_mtmr->runCoreId))
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // 输入的coreId有误
}
#endif
#ifdef INTEGRATED_BS
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX0_ID, my_mtmr->runCoreId))
if (PROTOCOL_JESD == nBsType)
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // 输入的coreId有误
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX0_ID, my_mtmr->runCoreId))
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // 输入的coreId有误
}
}
else
{
if (-1 == set_cpri_ape_slot_offset(my_mtmr->runCoreId))
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // 输入的coreId有误
}
}
#endif
}
}
else // 第二个子载波
{
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
for (j = 0; j < PHY_SCS_MAX_NUM; j++)
{
if (SCS_2nd_MTIMER_ID == do_read_volatile_short(&(phyPara[j].mtimerId))) // 已建过第二个子载波小区
@ -163,38 +170,39 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
}
}
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+38), j); // 0xb7e06098
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+38), j); // 0xb7e06098
if (PHY_SCS_MAX_NUM == j) // no cell on ecpri timer, build cell on ecpri timer
{
do_write_short((&(phyPara[nScsId].mtimerId)), SCS_2nd_MTIMER_ID);
#ifdef DISTRIBUTED_BS
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
ecpri_timer_reconfig(my_mtmr);
if (-1 == set_ecpri_ape_slot_offset(my_mtmr->runCoreId))
if (PROTOCOL_JESD == nBsType)
{
return -2; // coreId error, ape slot int set error
jesd_timer_reconfig(MTIMER_JESD_RX1_ID, my_mtmr);
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, my_mtmr->runCoreId))
{
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // coreId error, ape slot int set error
}
}
#endif
#ifdef INTEGRATED_BS
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
jesd_timer_reconfig(MTIMER_JESD_RX1_ID, my_mtmr);
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, my_mtmr->runCoreId))
else
{
return -2; // coreId error, ape slot int set error
ecpri_timer_reconfig(my_mtmr);
if (-1 == set_ecpri_ape_slot_offset(my_mtmr->runCoreId))
{
debug_write((DBG_DDR_IDX_DRV_BASE+41), my_mtmr->runCoreId); // 0xb7e060A4
debug_write((DBG_DDR_IDX_DRV_BASE+37), -2); // 0xb7e06094
return -2; // coreId error, ape slot int set error
}
}
#endif
timerId = SCS_2nd_MTIMER_ID;
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+39), my_mtmr->runCoreId); // 0xb7e0609C
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+32), flag); // 0xb7e06080
debug_write((DBG_DDR_IDX_DRV_BASE+39), my_mtmr->runCoreId); // 0xb7e0609C
}
else
{
@ -206,18 +214,24 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
}
else
{
#ifdef DISTRIBUTED_BS
if (-1 == set_ecpri_ape_slot_offset(my_mtmr->runCoreId))
while (0 != reCfgFlag) // wait last cell built finished
{
debug_write((DBG_DDR_IDX_DRV_BASE+36), reCfgFlag); // 0xb7e06090
}
if (PROTOCOL_JESD == nBsType)
{
return -2; // 输入的coreId有误
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, my_mtmr->runCoreId))
{
return -2; // 输入的coreId有误
}
}
#endif
#ifdef INTEGRATED_BS
if (-1 == set_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, my_mtmr->runCoreId))
else
{
return -2; // 输入的coreId有误
if (-1 == set_ecpri_ape_slot_offset(my_mtmr->runCoreId))
{
return -2; // 输入的coreId有误
}
}
#endif
}
}
}
@ -230,10 +244,11 @@ int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr)
// 删小区，先通知APE删除任务和定时点，再走ecs rfm1的删小区流程
int32_t mtimer_del_cell_cfg(stPhyDelCell* delCell)
{
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
uint8_t nBsType = get_protocol_sel();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
if (NULL == delCell)
{
return -1; // input para error
@ -244,68 +259,76 @@ int32_t mtimer_del_cell_cfg(stPhyDelCell* delCell)
return -1; // input para error
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
int32_t nScsId = delCell->scsId;
short timerId = do_read_volatile_short(&(phyPara[nScsId].mtimerId));
short runCore = do_read_volatile_short(&(phyPara[nScsId].runCoreId));
__ucps2_synch(f_SMR);
while (0 != (runCore & delCell->delCoreId))
{
runCore = do_read_volatile_short(&(phyPara[nScsId].runCoreId));
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
{
runCore = do_read_volatile_short(&(phyPara[nScsId].runCoreId));
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
if (SCS_1st_MTIMER_ID == timerId)
{
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
#ifdef DISTRIBUTED_BS
clear_cpri_ape_slot_offset(delCell->delCoreId);
#endif
#ifdef INTEGRATED_BS
clear_jesd_ape_slot_offset(MTIMER_JESD_RX0_ID, delCell->delCoreId);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
#endif
if (PROTOCOL_JESD == nBsType)
{
clear_jesd_ape_slot_offset(MTIMER_JESD_RX0_ID, delCell->delCoreId);
}
else
{
clear_cpri_ape_slot_offset(delCell->delCoreId);
}
if (0 == runCore) // delete all the interrupts on this mtimer other than pp1s and 10ms offset int
{
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
debug_write((DBG_DDR_IDX_DRV_BASE+54), delCell->delCoreId); // 0xb7e060d8
#endif
#ifdef DISTRIBUTED_BS
cpri_timer_clear_cell(delCell->scsId);
#endif
#ifdef INTEGRATED_BS
jesd_timer_clear_cell(MTIMER_JESD_RX0_ID, delCell->scsId);
#endif
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+53), flag); // 0xb7e060d4
debug_write((DBG_DDR_IDX_DRV_BASE+54), delCell->delCoreId); // 0xb7e060d8
#endif
if (PROTOCOL_JESD == nBsType)
{
jesd_timer_clear_cell(MTIMER_JESD_RX0_ID, delCell->scsId);
}
else
{
cpri_timer_clear_cell(delCell->scsId);
}
do_write_short(&(phyPara[nScsId].mtimerId), MTIMER_NULL);
}
}
else if (SCS_2nd_MTIMER_ID == timerId) // ecpri timer
{
#ifdef DISTRIBUTED_BS
clear_ecpri_ape_slot_offset(delCell->delCoreId);
#endif
#ifdef INTEGRATED_BS
clear_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, delCell->delCoreId);
#endif
if (PROTOCOL_JESD == nBsType)
{
clear_jesd_ape_slot_offset(MTIMER_JESD_RX1_ID, delCell->delCoreId);
}
else
{
clear_ecpri_ape_slot_offset(delCell->delCoreId);
}
if (0 == runCore) // delete all the interrupts on this mtimer other than pp1s and 10ms offset int
{
#ifdef DISTRIBUTED_BS
ecpri_timer_clear_cell(delCell->scsId);
#endif
#ifdef INTEGRATED_BS
jesd_timer_clear_cell(MTIMER_JESD_RX1_ID, delCell->scsId);
#endif
if (PROTOCOL_JESD == nBsType)
{
jesd_timer_clear_cell(MTIMER_JESD_RX1_ID, delCell->scsId);
}
else
{
ecpri_timer_clear_cell(delCell->scsId);
}
do_write_short(&(phyPara[nScsId].mtimerId), MTIMER_NULL);
}
}

71
public/ecs_rfm_spu1/driver/src/mtimer_drv.s.c
View File

@ -24,16 +24,27 @@ int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
uint8_t nBsType = get_protocol_sel();
uint32_t coreClk = 0;
memset(pMtimerPara, 0, sizeof(stMtimerPara));
#ifdef DISTRIBUTED_BS
coreClk = pEcsDmLocalMgt->pCpriPara->core_clk;
#endif
#ifdef INTEGRATED_BS
coreClk = do_read_volatile(JESD_TX_SAMPLE_RATE); // 122880000;
#endif
if (PROTOCOL_CPRI == nBsType)
{
coreClk = pEcsDmLocalMgt->pCpriPara->core_clk;
}
else if (PROTOCOL_JESD == nBsType)
{
coreClk = do_read_volatile(JESD_TX_SAMPLE_RATE); // 122880000;
}
else if (PROTOCOL_ECPRI == nBsType)
{
coreClk = 402832000;
}
else
{
return -1;
}
pMtimerPara->tmrClk = coreClk;
pMtimerPara->tmrMsPeriod = coreClk / 1000;
@ -46,34 +57,40 @@ int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
pMtimerPara->tddSlotNum = nTddSlotNum;
pMtimerPara->tddPeriod = pMtimerPara->slotPeriod * nTddSlotNum;
debug_write((DBG_DDR_IDX_DRV_BASE+42), pMtimerPara->tmrClk); // 0xb7e060A8
debug_write((DBG_DDR_IDX_DRV_BASE+43), pMtimerPara->slotPeriod); // 0xb7e060Ac
return 0;
}
uint32_t mtimer_get_baseaddr(uint8_t nTmrId)
{
uint8_t nBsType = get_protocol_sel();
uint32_t tmrBaseAddr = 0;
#ifdef DISTRIBUTED_BS
if (MTIMER_CPRI_ID == nTmrId)
if (PROTOCOL_JESD == nBsType)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
if (nTmrId >= MTIMER_INTEGRATED_MAX_NUM)
{
return 0;
}
tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
}
else
{
return 0;
if (MTIMER_CPRI_ID == nTmrId)
{
tmrBaseAddr = CPRI_TMR_BASE;
}
else if (MTIMER_ECPRI_ID == nTmrId)
{
tmrBaseAddr = ECPRI_TMR_BASE;
}
else
{
return 0;
}
}
#endif
#ifdef INTEGRATED_BS
if (nTmrId >= MTIMER_MAX_NUM)
{
return 0;
}
tmrBaseAddr = JS_RX0_TMR_BASE + nTmrId * 0x1000;
#endif
return tmrBaseAddr;
}
@ -257,9 +274,9 @@ int32_t set_mtimer_tmrpoint(uint8_t nTmrId, uint8_t nPointId, int32_t nTmrPoint,
do_write((tmrBaseAddr + MTMR_TnL_REG0 + (nPointId<<3)), tempL);
do_write((tmrBaseAddr + MTMR_TnH_REG0 + (nPointId<<3)), ((mask<<30) + (tempH<<16) + tempM));
do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId/32)<<2)), (1<<nPointId));
do_write((tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)), (1<<(nPointId&0x1F)));
__ucps2_synch(0);
while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId/32)<<2)) & (1<<nPointId)); // REQ reg, wait until the T0L and T0H set finished
while(do_read_volatile(tmrBaseAddr + MTMR_TWREQ0_REG + ((nPointId>>5)<<2)) & (1<<(nPointId&0x1F))); // REQ reg, wait until the T0L and T0H set finished
return 0;
}
@ -272,7 +289,7 @@ int32_t enable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nIn
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + ((nPointId/32)<<3) + 6*(nIntcId<<2);
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
do_write(addr, (do_read_volatile(addr) | (1 << (nPointId&0x1F))));
return 0;
@ -286,7 +303,7 @@ int32_t disable_mtimer_tmrpoint_int(uint8_t nTmrId, uint8_t nPointId, uint8_t nI
return -1;
}
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + ((nPointId/32)<<3) + 6*(nIntcId<<2);
uint32_t addr = tmrBaseAddr + MTMR_TINTE00_REG + 2*((nPointId>>5)<<2) + 6*(nIntcId<<2);
do_write(addr, (do_read_volatile(addr) & (~(1 << (nPointId&0x1F)))));
return 0;

65550
public/ecs_rfm_spu1/driver/src/cpri_pma_para.s.c → public/ecs_rfm_spu1/driver/src/pma_para.s.c
View File

File diff suppressed because it is too large Load Diff

86
public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c
View File

@ -16,25 +16,16 @@
#include "ecs_rfm_spu1_heap.h"
#include "mtimer_cell.h"
#include "gpio_drv.h"
#ifdef DISTRIBUTED_BS
#include "hw_cpri.h"
#include "stc_timer.h"
#include "cpri_timer.h"
#include "cpri_delay.h"
#include "ecpri_timer.h"
#include "cpri_driver.h"
#endif
#ifdef INTEGRATED_BS
#include "jesd_timer.h"
#endif
//extern UINT32 g10msOffsetIntFlag;
extern stPhyScsPara* phyPara;
#ifdef CPRI_10G_TEST
uint32_t CPRI_OPTION = CPRI_OPTION_8;
#endif
#ifdef CPRI_24G_TEST
uint32_t CPRI_OPTION = CPRI_OPTION_10;
#ifdef TEST_ENABLE
#include "fh_test.h"
#endif
extern int32_t phy_fh_drv_init();
void ecs_rfm1_drv_init(void)
{
int32_t apeId = get_core_id();
@ -43,7 +34,7 @@ void ecs_rfm1_drv_init(void)
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
//SET_CLK_CFG_EMU();
SET_CLK_CFG_EMU();
//APC0_CSU_ELEVELMASK = 0xFFFFFFFF;
int32_t ret = 0;
#if 1
@ -94,30 +85,6 @@ void ecs_rfm1_drv_init(void)
#endif
#endif
#ifdef DISTRIBUTED_BS
cpri_init(CPRI_OPTION);
UCP_PRINT_EMPTY("cpri init finished. \r\n");
HeaderTxRam_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
ecpri_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
#endif
#ifdef INTEGRATED_BS
jesd_init();
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
hw_gpio_init();
#ifdef PALLADIUM_TEST
flag++;
@ -134,6 +101,22 @@ void ecs_rfm1_drv_init(void)
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
#ifdef TEST_ENABLE
fh_test_init();
#else
phy_fh_drv_init();
#endif
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
rfm_stc_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
#endif
}
void check_phy_cell(void)
@ -176,32 +159,11 @@ void check_phy_cell(void)
void check_10ms_offset(void)
{
#ifdef DISTRIBUTED_BS
if (1 == get_sfnoffset_int_flag())
{
update_cpri_link_status();
cpri_delay_measurement_ck();
clear_sfnoffset_int_flag();
}
#endif
}
void HeaderTxRam_init()
{
#ifdef DISTRIBUTED_BS
uint32_t i,j;
HeaderRam_ins_disable();
for(i=0;i<64;i++)//Ns
{
for(j=0;j<4;j++)//
{
HeaderRam_Tx(i+64*j,0,0,0);//vendor
HeaderRam_Tx(i+64*j,1,0,0);//vendor
HeaderRam_Tx(i+64*j,2,0,0);//vendor
HeaderRam_Tx(i+64*j,3,0,0);//vendor
}
}
do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
#endif
}

362
public/ecs_rfm_spu1/driver/src/stc_timer.s.c Normal file
View File

@ -0,0 +1,362 @@
#include "ucp_cpri.h"
#include "ucp_js_subcrg.h"
#include "ucp_js_ctrl.h"
#include "ucp_sfr_c.h"
#include "stc_timer.h"
#include "phy_para.h"
#include "ucp_drv_common.h"
#include "ucp_utility.h"
#include "ucp_printf.h"
stStcTimerPara gStcTimerPara;
extern stPhyScsPara* phyPara;
extern uint32_t gScsId;
void rfm_stc_init()
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0x4
#endif
uint32_t pClk = stc_pclk_init();
if (0 == pClk)
{
UCP_PRINT_EMPTY("stc_init: pClk get error! \r\n");
#ifdef PALLADIUM_TEST
flag = -1;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
return;
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
stc_timer_init(pClk, STC_RT);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
do_write(&(TOD_REG_NF), (0xC0000000 | pClk)); // init finished
}
uint32_t stc_pclk_init()
{
uint32_t pClk = 0;
int32_t protoSel = get_protocol_sel();
int32_t protoOpt = get_protocol_opt();
if (PROTOCOL_CPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait cpri serdes clk init finished
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (CPRI_OPTION_7):
{
serdesTxClk = 491520000;
break;
}
case (CPRI_OPTION_8):
{
serdesTxClk = 316800000;
break;
}
case (CPRI_OPTION_9):
{
serdesTxClk = 380160000;
break;
}
case (CPRI_OPTION_10):
{
serdesTxClk = 760320000;
break;
}
default:
{
serdesTxClk = 316800000;
break;
}
}
JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
//JECS_CTRL_PROTOCOL_SEL &= (~0x1); // jecs_protocol_sel = 0, sel cpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_ECPRI == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait ecpri serdes clk init finished
uint32_t serdesTxClk = 0;
switch (protoOpt)
{
case (ECPRI_OPTION_10G):
{
serdesTxClk = 322264000; // 805664000; //
break;
}
case (ECPRI_OPTION_25G):
{
serdesTxClk = 805664000; // 2014160000; //
break;
}
default:
{
serdesTxClk = 322264000; // 805664000; //
break;
}
}
// JECS_CRG_PLLSEL &= (~(1 << 22)); // cpri_tx_clk_sel = 0, sel jecs_serdes_tx_clk as cpri_serdes_tx_clk
//JECS_CTRL_PROTOCOL_SEL |= 0x2; // jecs_protocol_sel = 2, sel ecpri protocol
JECS_CTRL_REG39 |= (1 << 6); // enable ecpri_serdes_tx_clk
__ucps2_synch(0);
JECS_CRG_PLLSEL &= (~(1 << 6)); // pma_clk_sel2 = 0, sel jecs_ecpri_serdes_tx_clk
JECS_CRG_PLLSEL |= (0x7 << 7); // stc_src_clk_sel[2:0]=0x7
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
pClk = serdesTxClk;
}
else if (PROTOCOL_JESD == protoSel)
{
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))); // wait jesd serdes clk init finished
JECS_CRG_PLLSEL |= (0x6 << 7); // stc_src_clk_sel[2:0]=0x6
JECS_CRG_CLK_CTRL3 = 0x520000; // jecs3_div=1, stc pclk = cpri_serdes_tx_clk
// laneRate = IQ_sample_rate * M * N' * (10/8)/L // max_laneRate = 12.5Gbps
// serdesTxClk = laneRate/40;
// pClk = serdesTxClk;
uint32_t samClk = do_read_volatile(JESD_TX_SAMPLE_RATE);
uint32_t jesdPara = do_read_volatile(JESD_TX_CH_PARA);
uint8_t paraL = jesdPara & 0xFF;
uint8_t paraM = (jesdPara >> 8) & 0xFF;
uint8_t paraN = (jesdPara >> 16) & 0xFF;
pClk = (uint64_t)(samClk/paraL/40)*paraM*paraN*10/8; // (uint64_t)(122880000/4/40)*8*16*10/8;
}
else
{
PETP_CLK_CFG_REG = 0x523000; // ECS_PCLK=1G/4=250M
JECS_CRG_CLK_CTRL3 = 0x520000; // STC_PCLK=ECS_PCLK/1=250M
// JECS_CRG_PLLSEL &= (~(1 << 9)); // stc_src_clk_sel2=0
pClk = 250000000; // 100000000;
UCP_PRINT_EMPTY("stc_pclk_init: use soc_crg to generate pclk, 250M. \r\n");
}
return pClk;
}
int32_t gcd_stein(uint32_t x, uint32_t y)
{
if (x < y)
{
int32_t tmp = x;
x = y;
y = tmp;
}
if (0 == (x%y))
{
return y;
}
if ((0 == (x%2)) && (0 == (y%2)))
{
return (2*gcd_stein(x>>1, y>>1));
}
else if ((0 == (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x>>1, y));
}
else if ((0 != (x%2)) && (0 == (y%2)))
{
return (gcd_stein(x, y>>1));
}
else if ((0 != (x%2)) && (0 != (y%2)))
{
return (gcd_stein(x, ((x-y)>>1)));
}
else
{
return 0;
}
}
void stc_timer_init(uint32_t pClk, uint32_t valR)
{
int32_t apeId = get_core_id();
#ifdef PALLADIUM_TEST
int32_t flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag); // 0x8
#endif
stc_timer_tod_init(pClk);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
#if 0
stc_pp1s_src_init(STC_PP1S_SRC_GPS); // select gps pp1s as stc ppls input
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+2+(apeId<<2)), flag);
#endif
#endif
stc_timer_para_init(pClk, valR);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer_local_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer0_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
stc_timer1_para_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+2+(apeId<<2)), flag);
#endif
}
void stc_timer_para_init(uint32_t pClk, uint32_t valR)
{
//int apeId = get_core_id();
uint32_t remain = 0;
uint32_t gcd = 0;
memset(&gStcTimerPara, 0, sizeof(stStcTimerPara));
gStcTimerPara.pClk = pClk;
gStcTimerPara.R = valR;
gStcTimerPara.usR = valR / 1000000;
gStcTimerPara.N1 = valR/pClk;
if (gStcTimerPara.N1 * pClk == valR)
{
gStcTimerPara.N1 -= 1;
}
gStcTimerPara.N = gStcTimerPara.N1 + 1;
debug_write((DBG_DDR_IDX_DRV_BASE+24), gStcTimerPara.pClk); // 0x60
debug_write((DBG_DDR_IDX_DRV_BASE+25), gStcTimerPara.N); // 0x64
remain = valR-gStcTimerPara.N1*pClk;
gcd = gcd_stein(pClk, remain);
if (0 == gcd)
{
UCP_PRINT_EMPTY("gcd error! \r\n");
return;
}
gStcTimerPara.A = remain / gcd;
gStcTimerPara.C = pClk / gcd;
UCP_PRINT_EMPTY("pclk = 0x%x. \r\n", gStcTimerPara.pClk);
UCP_PRINT_EMPTY("R = 0x%x. \r\n", gStcTimerPara.R);
UCP_PRINT_EMPTY("N = 0x%x. \r\n", gStcTimerPara.N);
UCP_PRINT_EMPTY("N1 = 0x%x. \r\n", gStcTimerPara.N1);
UCP_PRINT_EMPTY("A = 0x%x. \r\n", gStcTimerPara.A);
UCP_PRINT_EMPTY("C = 0x%x. \r\n", gStcTimerPara.C);
debug_write((DBG_DDR_IDX_DRV_BASE+26), gStcTimerPara.A); // 0x68
debug_write((DBG_DDR_IDX_DRV_BASE+27), gStcTimerPara.C); // 0x6c
}
void stc_timer_tod_init(uint32_t pClk)
{
JECS_CRG_STC_RST_CTRL |= BIT24;
stc_tod_para_init(pClk);
//stc_timer_todint_init();
//do_write(STC_TOD_INT_ADDR, 0); // clear tod int flag
}
void stc_pp1s_src_init(uint8_t srcId)
{
// gnss_sel stc_sel cpri_sel
//JECS_CTRL_CPRI_GMAC_PHY_INT = (0x0 << 4) | (0x5 << 7) | (0x6<<10);
JECS_CTRL_CPRI_GMAC_PHY_INT &= ~(0x7 << 7);
JECS_CTRL_CPRI_GMAC_PHY_INT |= (srcId << 7); // select gps pp1s as stc ppls input
}
void stc_timer_local_init()
{
LTBG_REG_R = gStcTimerPara.R;
LTBG_TIME_SET = 0;
LTBG_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG_REG_A = gStcTimerPara.A;
LTBG_REG_N = gStcTimerPara.N;
LTBG_REG_N1 = gStcTimerPara.N1;
}
void stc_timer0_para_init()
{
LTBG0_REG_R = gStcTimerPara.R;
LTBG0_TIME_SET = 0;
LTBG0_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG0_REG_A = gStcTimerPara.A;
LTBG0_REG_N = gStcTimerPara.N;
LTBG0_REG_N1 = gStcTimerPara.N1;
}
void stc_timer1_para_init()
{
LTBG1_REG_R = gStcTimerPara.R;
LTBG1_TIME_SET = 0;
LTBG1_REG_C = gStcTimerPara.C;
__ucps2_synch(0);
LTBG1_REG_A = gStcTimerPara.A;
LTBG1_REG_N = gStcTimerPara.N;
LTBG1_REG_N1 = gStcTimerPara.N1;
}
void stc_tod_para_init(uint32_t pClk)
{
//TOD_REG_FT_LO = 0; // 0xB0AAAAAA; // 0x11AAAAAA; //
//TOD_REG_FT_HI = 40; // 40; //4; //
double nsOfClk = 1000000000.0 / pClk;
uint32_t hiOfFt = 1000000000 / pClk;
uint64_t coff = (1ULL<<32);
uint32_t loOfFt = (uint32_t)((double)(nsOfClk - hiOfFt) * coff); // ???
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+5), loOfFt); // 0x8
debug_write((DBG_DDR_IDX_DRV_BASE+6), hiOfFt); // 0xc
#endif
do_write((&TOD_REG_FT_LO), loOfFt);
do_write((&TOD_REG_FT_HI), hiOfFt);
uint32_t loOfRt = 0;
uint32_t hiOfRt = 0;
//#ifdef PALLADIUM_TEST
// hiOfRt = STC_RT_PALLADIUM; // one tod period: 100ms
// do_write(STC_RT_ADDR, STC_RT_PALLADIUM);
//#else
hiOfRt = STC_RT;
do_write(STC_RT_ADDR, STC_RT);
//#endif
UCP_PRINT_EMPTY("RT LO = 0x%x. \r\n", loOfRt);
UCP_PRINT_EMPTY("RT HI = 0x%x. \r\n", hiOfRt);
do_write((&TOD_REG_RT_LO), loOfRt);
do_write((&TOD_REG_RT_HI), hiOfRt);
TOD_REG_CONFIG |= (1<<3); // onepps_output_enable
do_write(STC_ONEPPS_OUT_ADDR, 1);
}

34
public/ecs_rfm_spu1/top/src/ecs_rfm_spu1_top.s.c
View File

@ -42,31 +42,9 @@ void ecs_rfm_spu1_drv_init(void)
ucp_spinlock_init();
int32_t core_id = get_core_id();
#ifdef PALLADIUM_TEST
int flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
#endif
ecs_rfm1_drv_init();
UCP_PRINT_EMPTY("ECS: rfm drv init finished.\r\n");
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
#ifdef TEST_ENABLE
fh_test_init();
#endif
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
return;
}
@ -74,11 +52,17 @@ void ecs_rfm_spu1_msg_transfer_init(void)
{
msg_transfer_mem_alloc();
handshake_slave_with_master();
int32_t core_id = get_host_core_id();
handshake_request_from_host(core_id);
//handshake_with_host();
msg_transfer_queue_init();
msg_transfer_queue_init();//initialized local queuecfg from common queuecfg
handshake_master_with_slave();
handshake_response_to_host(core_id);
phy_init();
phy_init();//phy application function:msg_transfer_cfg
return;
}

259
public/ecs_rfm_spu1/top/src/main.s.c
View File

@ -1,148 +1,127 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : main.c
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "ucp_printf.h"
#include "rfm1_drv.h"
#include "ucp_heartbeat.h"
#include "ecs_rfm_spu1_top.h"
#include "msg_transfer_queue.h"
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : main.c
// Author : xianfeng.du
// Created On : 2022-06-25
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "ucp_printf.h"
#include "rfm1_drv.h"
#include "ucp_heartbeat.h"
#include "ecs_rfm_spu1_top.h"
#include "msg_transfer_queue.h"
#include "log_server.h"
#include "ucp_utility.h"
#include "phy_queue_proc.h"
#include "cpri_test_mode.h"
#include "spu_shell.h"
#include "gtimer_drv.h"
#include "rfm1_gtimer2.h"
#include "ecs_rfm_spu1_oam.h"
#include "phy_para.h"
#include "hw_cpri.h"
#include "hwque.h"
#include "cpri_test_mode.h"
#include "spu_shell.h"
#include "gtimer_drv.h"
#include "rfm1_gtimer2.h"
#include "ecs_rfm_spu1_oam.h"
#include "phy_para.h"
#include "hw_cpri.h"
#include "hwque.h"
#ifdef TEST_ENABLE
#include "fh_test.h"
#endif
#include "fh_test.h"
#endif
#ifdef DDR_MONITOR
void spu_ddr_monitor()
{
if (1 == do_read_volatile(DDR_MONITOR_ENABLE))
{
clear_rfm1_gtimer2_1_intcnt();
gtimer2_int_enable(0);
do_write(DDR_MONITOR_ENABLE, 0);
}
volatile uint32_t nMonitorCnt = do_read_volatile(DDR_MONITOR_CNT);
__ucps2_synch(0);
if (nMonitorCnt < get_rfm1_gtimer2_1_intcnt())
{
gtimer2_int_disable(0);
do_write(DDR_MONITOR_CNT, 0);
}
}
#endif
extern uint32_t gCpriCsuDummyFlag;
int32_t main(int32_t argc, char* argv[])
{
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU1,coreId[0x%x]", get_core_id());
debug_write(DBG_DDR_COMMON_IDX(get_core_id(), 0), PLATFORM_BUILD_DATA);
#ifdef DDR_MONITOR
void spu_ddr_monitor()
{
if (1 == do_read_volatile(DDR_MONITOR_ENABLE))
{
clear_rfm1_gtimer2_1_intcnt();
gtimer2_int_enable(0);
do_write(DDR_MONITOR_ENABLE, 0);
}
volatile uint32_t nMonitorCnt = do_read_volatile(DDR_MONITOR_CNT);
__ucps2_synch(0);
if (nMonitorCnt < get_rfm1_gtimer2_1_intcnt())
{
gtimer2_int_disable(0);
do_write(DDR_MONITOR_CNT, 0);
}
}
#endif
extern uint32_t gCpriCsuDummyFlag;
int32_t main(int32_t argc, char* argv[])
{
UCP_PRINT_EMPTY("Hello world from ECS RFM SPU1,coreId[0x%x]", get_core_id());
debug_write(DBG_DDR_COMMON_IDX(get_core_id(), 0), PLATFORM_BUILD_DATA);
/* hw_debug_init */
int32_t core_id = get_core_id();
int ret = 0;
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // 推荐384，实际512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);
}
spu_log_client_init();
/* hw_debug_init */
int32_t core_id = get_core_id();
#ifdef PALLADIUM_TEST
int flag = 1;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag); // 0xB0
#endif
int ret = 0;
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // ÍƼö384£¬Êµ¼Ê512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);
}
spu_log_client_init();
spu_log_server_init();
ecs_rfm_spu1_drv_init();
ecs_rfm_spu1_msg_transfer_init();
spu_shell_init();
spu_shell_cpri_cmd();
oam_msg_init();
while (1)
{
#ifdef TEST_ENABLE
do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
do_write(CSU_RX_TD_SAMPLE, 10000);
check_test_outcome(0);
#endif
#if 0
if (1 == do_read_volatile(0x0A4D726C))
{
#ifdef CPRI_TIMING_7D2U_TEST
ecs_rfm1_build_cell(NR_SCS_30K, 1);
#endif
#ifdef CPRI_TIMING_LTE_FDD_TEST
ecs_rfm1_build_cell(LTE_SCS_ID, 1);
#endif
do_write(0x0A4D726C, 2);
}
if (2 == do_read_volatile(0x0A4D726C))
{
check_phy_cell();
}
if (3 == do_read_volatile(0x0A4D726C))
{
#ifdef CPRI_TIMING_7D2U_TEST
ecs_rfm1_delete_cell(NR_SCS_30K, 0);
#endif
#ifdef CPRI_TIMING_LTE_FDD_TEST
ecs_rfm1_delete_cell(LTE_SCS_ID, 0);
#endif
do_write(0x0A4D726C, 0);
}
if (4 == do_read_volatile(0x0A4D726C))
{
#ifdef CPRI_TIMING_7D2U_TEST
ecs_rfm1_delete_cell(NR_SCS_30K, 1);
#endif
#ifdef CPRI_TIMING_LTE_FDD_TEST
ecs_rfm1_delete_cell(LTE_SCS_ID, 1);
#endif
do_write(0x0A4D726C, 0);
}
#endif
phy_queue_polling();
#ifdef DISTRIBUTED_BS
check_cpri();
check_10ms_offset();
#endif
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
ecs_rfm_spu1_drv_init();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+(core_id<<2)), flag);
#endif
ecs_rfm_spu1_msg_transfer_init();
spu_shell_init();
spu_shell_cpri_cmd();
oam_msg_init();
while (1)
{
#ifdef TEST_ENABLE
do_write(CSU_TX_ADVANCE_SAMPLE, 10000); // 10us
do_write(CSU_RX_TD_SAMPLE, 10000);
check_test_outcome(0);
#endif
phy_queue_polling();
if (PROTOCOL_CPRI == get_protocol_sel())
{
check_cpri();
check_10ms_offset();
}
spu_log_server_proc();
spu_shell_task();
#ifdef DDR_MONITOR
spu_ddr_monitor();
#endif
}
return 0;
}
spu_shell_task();
#ifdef DDR_MONITOR
spu_ddr_monitor();
#endif
}
return 0;
}

119
public/ecs_rfm_spu1/top/src/phy_init.s.c
View File

@ -15,16 +15,34 @@
#include "phy_para.h"
#include "mtimer_cell.h"
#include "ucp_utility.h"
#include "hw_cpri.h"
#include "app_interface.h"
#include "hw_cpri.h"
#include "ecpri_driver.h"
#include "jesd_timer.h"
#define CELL_SETUP_TYPE_SIMULATION (0x5a6b7c8d)
#define ECS_RFM1_TEST_MSG_SIZE (8)
#define ECS_RFM1_MSG_TYPE (0)
uint8_t gu8_send_create_task_cnt = 0;
uint8_t gu8_send_del_task_cnt = 0;
int32_t phy_fh_drv_init()
{
#ifdef DISTRIBUTED_BS
cpri_init(CPRI_OPTION_8, NR4T4R_7DS2U);
#endif
#ifdef ECPRI_DISTRIBUTED_BS
ecpri_init(ECPRI_OPTION_10G);
#endif
#ifdef INTEGRATED_BS
jesd_init();
#endif
return 0;
}
void ecs_rfm1_send_create_task_info(uint8_t dst_core_id)
{
uint32_t core_id = get_core_id();
@ -90,26 +108,23 @@ void ecs_rfm1_send_del_task_info(uint8_t dst_core_id)
debug_write(DBG_DDR_COMMON_IDX(core_id, 63), ++gu8_send_del_task_cnt);
return ;
}
void ecs_rfm1_build_cell(uint32_t scsId, uint32_t flag)
void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
{
phy_timer_config_ind_t my_cpritmr;
my_cpritmr.scsId = scsId;
if ((0 == cellId) || ((1 == cellId)))
{
my_cpritmr.runCoreId = coreId;
}
else
{
my_cpritmr.runCoreId = 0;
}
if (NR_SCS_30K == scsId)
{
my_cpritmr.scsId = NR_SCS_30K;
#ifdef TEST_ENABLE
my_cpritmr.runCoreId = 0;
#else
if (0 == flag)
{
my_cpritmr.runCoreId = 0xF; // 0x3; //
}
else
{
my_cpritmr.runCoreId = 0xF0; // 0x3; //
}
#endif
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;
@ -122,19 +137,6 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t flag)
}
else if (LTE_SCS_ID == scsId)
{
my_cpritmr.scsId = LTE_SCS_ID;
#ifdef TEST_ENABLE
my_cpritmr.runCoreId = 0;
#else
if (0 == flag)
{
my_cpritmr.runCoreId = 0xF; // 0x3; //
}
else
{
my_cpritmr.runCoreId = 0xF0; // 0x3; //
}
#endif
my_cpritmr.t_period = 10000;
my_cpritmr.t_us = 1000;
my_cpritmr.num_tti = 10;
@ -145,12 +147,16 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t flag)
my_cpritmr.num_t_ul_symb[0] = 14;//4; // ul symbol num
my_cpritmr.num_ants[0] = 2;
}
else
{
return;
}
mtimer_init4phy(&my_cpritmr);
uint32_t apeId = 0;
uint32_t runCore = my_cpritmr.runCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
while (h1Pos != 32)
{
apeId = 31 - h1Pos;
@ -171,7 +177,7 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t flag)
}
}
void ecs_rfm1_delete_cell(uint32_t scsId, uint32_t nflag)
void ecs_rfm1_delete_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
{
int32_t ret = 0;
#ifdef PALLADIUM_TEST
@ -181,22 +187,18 @@ void ecs_rfm1_delete_cell(uint32_t scsId, uint32_t nflag)
stPhyDelCell myDelCell;
myDelCell.scsId = scsId;
if (0 == nflag)
if ((0 == cellId) || (1 == cellId))
{
myDelCell.delCoreId = 0xF0;
myDelCell.delCoreId = coreId;
}
else if (1 == nflag)
else
{
myDelCell.delCoreId = 0xF;
}
else
{
return;
myDelCell.delCoreId = 0;
}
uint32_t apeId = 0;
uint32_t runCore = myDelCell.delCoreId;
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
volatile uint32_t h1Pos = __builtin_clz(runCore); // 从高bit开始，第一个1前面的0的个数
while (h1Pos != 32)
{
apeId = 31 - h1Pos;
@ -233,29 +235,35 @@ void phy_msg_proc(uint32_t u32msg_addr, uint32_t u32msg_size)
{
uint32_t msg_buf = do_read(u32msg_addr);
uint32_t msg_type = do_read(msg_buf);
if ((CELL_SETUP_TYPE_SIMULATION == msg_type) && (2 > gCellFlag))
//if ((CELL_SETUP_TYPE_SIMULATION == msg_type) && (0 == gCellFlag))
if (CELL_SETUP_TYPE_SIMULATION == msg_type)
{
#ifdef CPRI_TIMING_7D2U_TEST
ecs_rfm1_build_cell(NR_SCS_30K, gCellFlag);
#endif
uint32_t msg_new_del = do_read(msg_buf+12); // 0; //
uint32_t scs_id = do_read(msg_buf+16); // 1; //
uint32_t cell_id = do_read(msg_buf+20); // 0; //
uint32_t run_core = do_read(msg_buf+24);
#ifdef CPRI_TIMING_LTE_FDD_TEST
ecs_rfm1_build_cell(LTE_SCS_ID, gCellFlag);
#endif
if (0 == gCellFlag)
memcpy_ucp(0x60000000, msg_buf, 32); // temp code
if (1 < msg_new_del)
{
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),2), msg_type);
return;
}
else if (1 == gCellFlag)
if (NR_SCS_120K < scs_id)
{
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),3), msg_type);
return;
}
if (0 == msg_new_del)
{
ecs_rfm1_build_cell(scs_id, cell_id, run_core);
}
else
{
ecs_rfm1_delete_cell(scs_id, cell_id, run_core);
}
++gCellFlag;
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),1), gCellFlag);
debug_write(DBG_DDR_COMMON_IDX(get_core_id(),1), 0x12345678);
}
return;
@ -276,4 +284,3 @@ void rfm1_fapi_callback()
debug_write((DBG_DDR_IDX_DRV_BASE+123), gFapiCallCnt); // 0x1ec
}

2
public/make/makefile.ape_spu
View File

@ -47,6 +47,8 @@ endif
ifeq ($(fronthaul_option),cpri)
DEFINES += DISTRIBUTED_BS
else ifeq ($(fronthaul_option),ecpri)
DEFINES += ECPRI_DISTRIBUTED_BS
else ifeq ($(fronthaul_option),jesd)
DEFINES += INTEGRATED_BS
else

2
public/make/makefile.ecs_rfm_spu0
View File

@ -38,6 +38,8 @@ DIRS_SRC_FOLDER += $(DIR_ECS_SPU0)/top
# ==============================================================================
ifeq ($(fronthaul_option),cpri)
DEFINES += DISTRIBUTED_BS
else ifeq ($(fronthaul_option),ecpri)
DEFINES += ECPRI_DISTRIBUTED_BS
else ifeq ($(fronthaul_option),jesd)
DEFINES += INTEGRATED_BS
else

2
public/make/makefile.ecs_rfm_spu1
View File

@ -41,6 +41,8 @@ TOP_SRC_FILE := $(DIR_ECS_SPU1)/top/src/phy_init.s.c
# ==============================================================================
ifeq ($(fronthaul_option),cpri)
DEFINES += DISTRIBUTED_BS
else ifeq ($(fronthaul_option),ecpri)
DEFINES += ECPRI_DISTRIBUTED_BS
else ifeq ($(fronthaul_option),jesd)
DEFINES += INTEGRATED_BS
else

2
public/make/makefile.test_fh
View File

@ -12,7 +12,7 @@ VERSION = 1.00
# ==============================================================================
DIR_TEST_BENCH := $(DIR_TEST)/testbench_fh
TEST_CASE_DIR := $(DIR_TEST)/testcase/case$(test_id)
TEST_CASE_DIR := $(DIR_TEST)/testcase_fh/case$(test_id)
$(info "CPRI_TEST_CASE_DIR=" $(TEST_CASE_DIR))
DIRS_SRC_FOLDER += $(DIR_TEST_BENCH)

2
public/make/makefile.test_osp
View File

@ -16,7 +16,7 @@ DIR_TEST_BENCH := $(DIR_TEST)/testbench_osp
#TEST_SRC_FILE := $(shell find $(DIR_TEST_CASE) -name "*.s.c")
#TEST_SRC_DIR := $(sort $(dir $(TEST_SRC_FILE)))
#TEST_CASE_DIR := $(patsubst %/src,%,$(abspath $(TEST_SRC_DIR)))
TEST_CASE_DIR := $(DIR_TEST)/testcase/case$(test_id)
TEST_CASE_DIR := $(DIR_TEST)/testcase_osp/case$(test_id)
$(info "TEST_CASE_DIR=" $(TEST_CASE_DIR))
DIRS_SRC_FOLDER += $(DIR_TEST_BENCH)

6
public/pet_rfm_spu0/driver/inc/ucp_pcie_traffic.h
View File

@ -95,9 +95,9 @@ typedef struct tPcieLinkStatus {
//RC和EP通信的counter结构体
typedef struct tPcieTrafficCounter {
uint32_t dlDescNum[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//通道描述符的个数，固定为128 24字节
uint32_t dlTxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//由RC侧来填充，RC侧写下来的数据包的个数 24字节
uint32_t dlRxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//EP侧接收到的数据包的个数 24字节
uint32_t dlDescNum[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//通道描述符的个数，固定为128
uint32_t dlTxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//由RC侧来填充，RC侧写下来的数据包的个数
uint32_t dlRxCounter[MAX_INSTANCE_NUM][MAX_Q_NUM_DL_TRAFFIC];//EP侧接收到的数据包的个数
//int8_t dlDescIdx[MAX_Q_NUM_DL_TRAFFIC][MAX_DESC_NUM];//该通道的DMA描述符的索引计数，最大128
uint32_t ulDescNum[MAX_INSTANCE_NUM][MAX_Q_NUM_UL_TRAFFIC];//通道描述符的个数，固定为12s8

1
public/pet_rfm_spu0/driver/src/dw_pcie_ep.s.c
View File

@ -791,4 +791,3 @@ void pcie_ep_dma_recfg(void)
return;
}

3
public/pet_rfm_spu0/top/src/main.s.c
View File

@ -55,9 +55,6 @@ int32_t main(int32_t argc, char* argv[])
ucp_pcie_worker();
}
#endif
//ucp_pcie_recfg_reset();
//ucp_pcie_worker();
//msg_transfer_recfg();
/*********test code************/
//test_case_recv_msg_pcie();

2
public/pet_rfm_spu1/top/src/main.s.c
View File

@ -29,7 +29,7 @@ int32_t main(int32_t argc, char* argv[])
/* hw_debug_init */
int32_t core_id = get_core_id();
int ret = 0;
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // 推荐384，实际512
ret = smart_hq_debug_init((DBG_DDR_HW_ADDR_BASE+DBG_DDR_HW_LEN*core_id), DBG_DDR_HW_LEN); // 推荐384，实际512
if (0 != ret)
{
debug_write(DBG_DDR_ERR_IDX(core_id, 46), ret);

12
public/pet_rfm_spu1/top/src/pet_rfm_spu1_top.s.c
View File

@ -46,17 +46,11 @@ void pet_rfm_spu1_msg_transfer_init(void)
{
msg_transfer_mem_alloc();
int32_t core_id = get_host_core_id();
handshake_request_from_host(core_id);
//handshake_with_host();
handshake_slave_with_master();
msg_transfer_queue_init();//initialized local queuecfg from common queuecfg
msg_transfer_queue_init();
phy_init();//phy application function:msg_transfer_cfg
handshake_master_with_slave();
handshake_response_to_host(core_id);
phy_init();//phy application function
return;
}

16
public/test/testbench_fh/inc/cpri_test.h
View File

@ -18,9 +18,17 @@
#include "mtimer_com.h"
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case(void);
void fh_data_check(uint32_t times);
void Axc_data_init();
//void AxC_data_check();
void AxC_data_check(uint32_t times);
void Get_Cpri_OptionId();
void HeaderTxRam_data_init();
@ -28,16 +36,12 @@ void HeaderTxRam_init();
void Cpri_Header_test(void);
void Cpri_Header_Rx(void);
void cpri_test_case(void);
void cpri_test_init(void);
void cpri_csu_config();
void cpri_test_tdd_csu_start();
void cpri_test_move_data();
void Cpri_data_init();
void cpri_csu_test_init();
#endif

36
public/test/testbench_fh/inc/ecpri_test.h Normal file
View File

@ -0,0 +1,36 @@
/**********************************************************************************************************************
* Copyright (C), 2022-2026, SMARTLOGIC TECHNOLOGY LTD.
* File Name: ecpri_test.h
* Create Date: 23/08/21
* Description: eCPRI Test Module Header File
* Change History:
* <author> <time> <version> <desc>
* 1. ShangH 23/08/21 1.0 Build this module
**********************************************************************************************************************/
#ifndef _ECPRI_TEST_H_
#define _ECPRI_TEST_H_
/* -------------------------------------------------- <INC FILE> --------------------------------------------------- */
#include "typedef.h"
/* -------------------------------------------------- <MACRO DEF> -------------------------------------------------- */
typedef struct EcpriTestResult
{
uint32_t test_times; /* test times */
uint32_t succ_times; /* success times */
uint32_t fail_times; /* fail times */
} EcpriTestResult_t;
/* -------------------------------------------------- <TYPE DEF> --------------------------------------------------- */
/* --------------------------------------------------- <DECLARE> --------------------------------------------------- */
/* eCPRI test status check */
extern void ecpri_test_status_check(void);
#endif /* _ECPRI_TEST_H_ */

8
public/test/testbench_fh/inc/fh_test.h
View File

@ -17,15 +17,9 @@
#define __UCP_FH_TESTCASE_H__
#include "typedef.h"
#ifdef DISTRIBUTED_BS
#include "cpri_test.h"
#endif
#ifdef INTEGRATED_BS
#include "ecpri_test.h"
#include "jesd_test.h"
extern uint32_t gJesdTestMode;
#endif
void fh_test_init(void);
void check_test_outcome(uint32_t cnt);

18
public/test/testbench_fh/inc/jesd_test.h
View File

@ -16,14 +16,22 @@
#ifndef __UCP_JESD_TESTCASE_H__
#define __UCP_JESD_TESTCASE_H__
//#include "typedef.h"
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x60F00000 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x60FF0400 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0x61380000 // SM5
#define JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0x61290400 // SM4
void jesd_data_init();
void jesd_test_csu_init();
void jesd_test_case(void);
void jesd_test_init(void);
#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case(void);
#endif

24
public/test/testbench_fh/src/fh_test_entry.s.c
View File

@ -14,36 +14,24 @@
#include "typedef.h"
#include "fh_test.h"
#include "phy_para.h"
void check_test_outcome(uint32_t cnt)
{
#ifdef DISTRIBUTED_BS
AxC_data_check(cnt);
#endif
#ifdef INTEGRATED_BS
#endif
fh_data_check(cnt);
return;
}
void fh_test_init(void)
{
#ifdef DISTRIBUTED_BS
Cpri_data_init();
cpri_csu_test_init();
#endif
#ifdef INTEGRATED_BS
jesd_data_init();
jesd_test_csu_init(); // init jesd csu and pin ctrl
#endif
fh_data_init();
fh_drv_init();
fh_csu_test_init();
return;
}

11
public/test/testbench_osp/inc/ucp_testcase.h
View File

@ -17,28 +17,21 @@
#define __UCP_TESTCASE_H__
//#include "typedef.h"
//#include "hw_cpri.h"
#define TEST_MSG_SIZE (100)
//#ifdef CPRI_TIMING_7D2U_TEST
#define SFN_SLOT_NUM (20)
#define TIMER_OFFSET (5000)
#define TIMER_OFFSET (5000)
#define TIMER_SLOT_OFFSET (500000)
#define TIMER_SFN_OFFSET (5000000)
//#endif
#define TIMER_OFFSET_MAX (TIMER_SLOT_OFFSET + TIMER_OFFSET)
#define TIMER_OFFSET_MIN (TIMER_SLOT_OFFSET - TIMER_OFFSET)
//#ifdef CPRI_TIMING_LTE_FDD_TEST
#define SFN_SLOT_NUM_15K (10)
#define TIMER_SLOT_OFFSET_15K (1000000)
#define TIMER_SFN_OFFSET_15K (10000000)
#define TIMER_OFFSET_15K (10000)
#define TIMER_OFFSET_MAX_15K (TIMER_SLOT_OFFSET_15K + TIMER_OFFSET_15K)
#define TIMER_OFFSET_MAX_15K (TIMER_SLOT_OFFSET_15K + TIMER_OFFSET_15K)
#define TIMER_OFFSET_MIN_15K (TIMER_SLOT_OFFSET_15K - TIMER_OFFSET_15K)
//#endif
#define LOOPBACK_APE_OFFSET (100000)
#define TICK_PP1S_OFFSET (1000000000)

1
public/test/testcase/case38/note.txt
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@ -1 +0,0 @@
单音，带压缩，20M，奇偶时隙数据一样

61446
public/test/testcase/case38/src/cpri_test_case38_antdata0.s.c
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File diff suppressed because it is too large Load Diff

61446
public/test/testcase/case38/src/cpri_test_case38_antdata1.s.c
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File diff suppressed because it is too large Load Diff

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