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1. fix UCP4008-SL feature enhancement#1675#;

Browse Source 
2. change pp1s sratching position;
3. modify cpri tx/rxxrx
4. test case: case44, case34, case21.
This commit is contained in:
xinxin.li 2024-02-20 11:36:52 +08:00
parent 7055e0d3ac
commit ba39178f5d
6 changed files with 58 additions and 10 deletions
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2
public/common/driver/inc/mtimer_com.h
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@ -3,7 +3,7 @@
#define APE_NUM (8) //4
#define FIBER_MIN_DELAY 2 // 10 //
#define FIBER_MIN_DELAY 1 // 10 //
#define INT_DELAY 4 // 6 // // us
#define EDMA_OFFSET 50 // 6 // 8 // 2 // us

1
public/ecs_rfm_spu1/driver/inc/rfm1_drv.h
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@ -13,6 +13,7 @@ int32_t fronthaul_drv_cfg(stFrontHaulDrvPara* pFhDrvPara);
void spu_ddr_monitor_start(uint32_t monitorCnt);
int32_t set_mtimer_scratch_tod();
#endif

14
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
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@ -95,13 +95,13 @@ void cpri_timer_init()
mtimer_clear_all_event(MTIMER_CPRI_ID);
set_cpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
set_cpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
set_cpri_tx_rfp(); // cpri_tx_rfn 10ms pulse, tevent0 for ape0, int, delay meaurement
set_cpri_tx_rfp(); // cpri_tx_rfn 10ms pulse, tevent0 for ape0, int, delay meaurement
set_cpri_tx_axc_ch_en(); // axc_ch_en, tevent1 for ape0
cpri_1pps_src_init(MTIMER_PP1S_SRC_TOD); // select stc tod pp1s as cpri pp1s input
set_cpri_1pps_scratch(); // 1pps scratch, cevent17 for ape0, int, pp1s precision
set_cpri_timer_int(); // cpri timer int enable
cpri_1pps_src_init(MTIMER_PP1S_SRC_TOD); // select stc tod pp1s as cpri pp1s input
//set_cpri_1pps_scratch(); // 1pps scratch, cevent17 for ape0, int, pp1s precision
set_cpri_timer_int(); // cpri timer int enable
pMtimerInt->tmrIntInitFinished = 1;
}
@ -131,10 +131,10 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
}
tempOffset = (uint32_t)(((float)pCpriDelay->cpriTxOffset/1000)+0.5); // ns -> us
pCpriDelay->cpri10msOffset = (tempOffset < (FIBER_MIN_DELAY+INT_DELAY)) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset);
pCpriDelay->cpri10msOffset = (tempOffset < (FIBER_MIN_DELAY+INT_DELAY)) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset+FIBER_MIN_DELAY+INT_DELAY);
tempOffset = (uint32_t)(((float)pCpriDelay->cpriRxOffset/1000)+0.5); // ns -> us
pCpriDelay->cpri10msRxOffset = (tempOffset < (FIBER_MIN_DELAY+INT_DELAY)) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset);
pCpriDelay->cpri10msRxOffset = (tempOffset < (FIBER_MIN_DELAY+INT_DELAY)) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset+FIBER_MIN_DELAY+INT_DELAY);
pCpriDelay->cpriTddOffset = pCpriDelay->cpri10msOffset + EDMA_OFFSET;

2
public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c
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@ -57,7 +57,7 @@ void ecpri_timer_init(int32_t nScsId, int32_t nTddSlotNum)
mtimer_clear_all_event(MTIMER_ECPRI_ID);
set_ecpri_tmr_period();
ecpri_1pps_src_init(MTIMER_PP1S_SRC_TOD);
set_ecpri_1pps_scratch();
//set_ecpri_1pps_scratch();
set_ecpri_timer_int();
pMtimerInt->tmrIntInitFinished = 1;

14
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
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@ -159,7 +159,7 @@ int32_t jesd_timer_init(int32_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
jesd_1pps_src_init(MTIMER_PP1S_SRC_TOD);
mtimer_clear_all_event(nTmrId);
set_jesd_tmr_period(nTmrId);
set_jesd_1pps_scratch(nTmrId);
//set_jesd_1pps_scratch(nTmrId);
set_jesd_sfn_offset(nTmrId);
if (MTIMER_JESD_RX0_ID == nTmrId)
@ -272,6 +272,18 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
debug_write((DBG_DDR_IDX_DRV_BASE+993+(i<<2)), pMtimerTxPara->txCsuOff[i].timerPoint); // 0xF84
debug_write((DBG_DDR_IDX_DRV_BASE+994+(i<<2)), pMtimerPara->rxCsuOn[i].timerPoint); // 0xF88
debug_write((DBG_DDR_IDX_DRV_BASE+995+(i<<2)), pMtimerPara->rxCsuOff[i].timerPoint); // 0xF8C
#if 0
debug_write((DBG_DDR_IDX_DRV_BASE+960+(i<<3)), pMtimerTxPara->txCsuOn[i].timerPoint); // 0xF00
debug_write((DBG_DDR_IDX_DRV_BASE+961+(i<<3)), pMtimerTxPara->txCsuOn[i].timerPoint+pMtimerTxPara->tddPeriod); // 0xF04
debug_write((DBG_DDR_IDX_DRV_BASE+962+(i<<3)), pMtimerTxPara->txCsuOn[i].pointL); // 0xF04
debug_write((DBG_DDR_IDX_DRV_BASE+963+(i<<3)), pMtimerTxPara->txCsuOn[i].pointM); // 0xF08
debug_write((DBG_DDR_IDX_DRV_BASE+964+(i<<3)), pMtimerTxPara->txCsuOff[i].timerPoint); // 0xF10
debug_write((DBG_DDR_IDX_DRV_BASE+965+(i<<3)), pMtimerTxPara->txCsuOff[i].timerPoint+pMtimerTxPara->tddPeriod); // 0xF04
debug_write((DBG_DDR_IDX_DRV_BASE+966+(i<<3)), pMtimerTxPara->txCsuOff[i].pointL); // 0xF14
debug_write((DBG_DDR_IDX_DRV_BASE+967+(i<<3)), pMtimerTxPara->txCsuOff[i].pointM); // 0xF18
//debug_write((DBG_DDR_IDX_DRV_BASE+967+(i<<3)), pMtimerTxPara->txCsuOff[i].pointH); // 0xF1C
#endif
}
}

35
public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c
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@ -113,6 +113,17 @@ void ecs_rfm1_drv_init(void)
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
#if 1
//delay_us(800000);
//delay_us(800000);
//delay_us(800000);
set_mtimer_scratch_tod();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag); // 0xB4
#endif
#endif
}
int32_t check_phy_cell(void)
@ -193,6 +204,30 @@ void spu_ddr_monitor_start(uint32_t monitorCnt)
do_write(DDR_MONITOR_CNT, monitorCnt);
}
int32_t set_mtimer_scratch_tod()
{
uint32_t protocolSel = get_protocol_sel();
if (PROTOCOL_CPRI == protocolSel)
{
set_cpri_1pps_scratch();
set_ecpri_1pps_scratch();
}
else if (PROTOCOL_ECPRI == protocolSel)
{
set_cpri_1pps_scratch();
set_ecpri_1pps_scratch();
}
else if (PROTOCOL_JESD == protocolSel)
{
set_jesd_1pps_scratch(0);
set_jesd_1pps_scratch(1);
}
else
{
return -1;
}
return 0;
}