Merge branch 'dev_ck_v2.1_jesd_gpio' into 'dev_ck_v2.1'

修改jesd的gpio功能，改为由配置文件配置

See merge request ucp/driver/ucp4008_platform_spu!25

EVB/driver/inc/hw_gpio.h

@@ -15,7 +15,7 @@
 //                                            rx off
 #define   RxOff()    {GPIO1_SWPORTB_DR |= (GPIO_Pin_17|GPIO_Pin_16|GPIO_Pin_19|GPIO_Pin_18); }
 
-void hw_gpio_init();
+//void hw_gpio_init();
 
 void rfm1_set_trigger_high();
 

EVB/driver/src/hw_gpio.s.c

@@ -4,12 +4,13 @@
 #include "ucp_utility.h"
 #include "ucp_param.h"
 
+#if 0
 void hw_gpio_init()
 {
 	do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x000F0000));	// pinmux, GPIO1B25 and GPIO1B24, gpio func, 0x3
 	do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25|BIT19|BIT18|BIT17|BIT16|BIT15|BIT14|BIT13|BIT12)));				// GPIO1B25, output, 10ms trigger for phy
 }
-
+#endif
 void rfm1_set_trigger_high()
 {
 	do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT25)); // GPIO1B25, high

EVMY/driver/inc/hw_gpio.h

@@ -11,7 +11,7 @@
 #define   RxOn()     {GPIO1_SWPORTB_DR &= (~(GPIO_Pin_24|GPIO_Pin_25)); }
 #define   RxOff()    {GPIO1_SWPORTB_DR |= (GPIO_Pin_24|GPIO_Pin_25);}
 
-void hw_gpio_init();
+//void hw_gpio_init();
 
 void rfm1_set_trigger_high();
 

EVMY/driver/src/hw_gpio.s.c

@@ -4,12 +4,13 @@
 #include "ucp_utility.h"
 #include "ucp_param.h"
 
+#if 0
 void hw_gpio_init()
 {
     do_write(RF_LVDS_PMUX0_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX0_REG_ADDR)|0x00030000));	// pinmux, GPIO1B8, gpio func, 0x3
     do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25|BIT24|BIT8|BIT7|BIT6|BIT5|BIT4)));				// GPIO1B8, output, 10ms trigger for phy
 }
-
+#endif
 
 void rfm1_set_trigger_high()
 {

public/common/driver/inc/dw_apb_gpio.h

@@ -14,11 +14,22 @@
 
 #define GPIO0_A29_PINMUX_REG_ADDR	0x04458180
 #define PB14_CTRL_REG_ADDR			0x044580BC	// PB14_CTRL_REG
+
 #define RF_LVDS_PMUX0_REG_ADDR      0x04DA0094
 #define RF_LVDS_PMUX1_REG_ADDR		0x04DA0098
-#define GPIO1B_EXT_REG_ADDR			0x04D10054
+
-#define GPIO1B_DIR_REG_ADDR			0x04D10010
+#define GPIO0A_DATA_REG_ADDR		0x04450000
+#define GPIO0A_DIR_REG_ADDR			0x04450004
+
+#define GPIO0B_DATA_REG_ADDR		0x0445000C
+#define GPIO0B_DIR_REG_ADDR			0x04450010
+
+#define GPIO1A_DATA_REG_ADDR		0x04D10000
+#define GPIO1A_DIR_REG_ADDR			0x04D10004
+
 #define GPIO1B_DATA_REG_ADDR		0x04D1000C
+#define GPIO1B_DIR_REG_ADDR			0x04D10010
+#define GPIO1B_EXT_REG_ADDR			0x04D10054
 
 #define DW_APB_GPIO0_BASE 0x04450000
 #define DW_APB_GPIO1_BASE 0x04d10000

public/common/driver/inc/phy_para.h

@@ -6,43 +6,52 @@
 #define PHY_SCS_MAX_NUM			4
 #define SFN_PERIOD				10000		// 10ms
 
-#define PROTO_SEL_ADDR			(0x0A4D7000)
+#define SPU_DRV_SM_ADDR			(0x0A4D7000)
-#define PROTO_OPT_ADDR			(0x0A4D7004)
-#define PHY_PARA_ADDR			(0x0A4D7008)
-#define PHY_CELL_ADDR			(0x0A4D7100)
 
-#define STC_TOD_INT_ADDR		(0x0A4D7200)
+#define PROTO_SEL_ADDR			(SPU_DRV_SM_ADDR+0x0)
-#define STC_RT_ADDR				(0x0A4D7204)
+#define PROTO_OPT_ADDR			(SPU_DRV_SM_ADDR+0x4)
-#define STC_CTW_EN_ADDR			(0x0A4D7208)
+#define PHY_PARA_ADDR			(SPU_DRV_SM_ADDR+0x8)
+#define PHY_CELL_ADDR			(SPU_DRV_SM_ADDR+0x100)
 
-#define CPRI_DELAY_ADDR			(0x0A4D7210)
+#define STC_TOD_INT_ADDR		(SPU_DRV_SM_ADDR+0x200)
-#define CPRI_ADVANCE_ADDR		(0x0A4D7214)
+#define STC_RT_ADDR				(SPU_DRV_SM_ADDR+0x204)
-#define CPRI_TDD_ADVANCE_ADDR	(0x0A4D7218)
+#define STC_CTW_EN_ADDR			(SPU_DRV_SM_ADDR+0x208)
 
-#define CTC_INT_TYPE_ADDR		(0x0A4D721C)
+#define CPRI_DELAY_ADDR			(SPU_DRV_SM_ADDR+0x210)
+#define CPRI_ADVANCE_ADDR		(SPU_DRV_SM_ADDR+0x214)
+#define CPRI_TDD_ADVANCE_ADDR	(SPU_DRV_SM_ADDR+0x218)
 
-#define ARM_SFN_VALID_ADDR		(0x0A4D7220) // 0xAA not valid, 0x55 valid
+#define CTC_INT_TYPE_ADDR		(SPU_DRV_SM_ADDR+0x21C)
-#define ARM_SFN_NUM_ADDR		(0x0A4D7224)
+
-#define ARM_SFN_FLIP_ADDR		(0x0A4D7228)
+#define ARM_SFN_VALID_ADDR		(SPU_DRV_SM_ADDR+0x220) // 0xAA not valid, 0x55 valid
-#define ARM_LOCK_FLAG_ADDR		(0x0A4D722C)
+#define ARM_SFN_NUM_ADDR		(SPU_DRV_SM_ADDR+0x224)
+#define ARM_SFN_FLIP_ADDR		(SPU_DRV_SM_ADDR+0x228)
+#define ARM_LOCK_FLAG_ADDR		(SPU_DRV_SM_ADDR+0x22C)
 
 #define ARM_SFN_VALID_FLAG		(0x55)
 #define ARM_SFN_NOTVALID_FLAG	(0xAA)
 
-#define CSU_STOP_CMD_ADDR		(0x0A4D7230)
+#define CSU_STOP_CMD_ADDR		    (SPU_DRV_SM_ADDR+0x230)
-#define CSU_UL_HEADER_DATA_OFFSET	(0x0A4D7234)	// ul, the interval of frame header and frame data, ns as unit
+#define CSU_UL_HEADER_DATA_OFFSET	(SPU_DRV_SM_ADDR+0x234)	// ul, the interval of frame header and frame data, ns as unit
-#define CSU_RX_TD_SAMPLE		(0x0A4D7238)
+#define CSU_RX_TD_SAMPLE		    (SPU_DRV_SM_ADDR+0x238)
-#define CSU_TX_ADVANCE_SAMPLE	(0x0A4D723C)
+#define CSU_TX_ADVANCE_SAMPLE	    (SPU_DRV_SM_ADDR+0x23C)
 
-#define SERDES_INIT_FLAG_ADDR	(0x0A4D7240) // cpri or jesd clk init finished
+#define SERDES_INIT_FLAG_ADDR	    (SPU_DRV_SM_ADDR+0x240) // cpri or jesd clk init finished
-#define STC_ONEPPS_OUT_ADDR		(0x0A4D7244)
+#define STC_ONEPPS_OUT_ADDR		    (SPU_DRV_SM_ADDR+0x244)
 
-#define DDR_MONITOR_ENABLE		(0x0A4D7250)	// 开始监测ddr性能
+#define DDR_MONITOR_ENABLE		    (SPU_DRV_SM_ADDR+0x250)	// 开始监测ddr性能
-#define DDR_MONITOR_CNT			(0x0A4D7254)
+#define DDR_MONITOR_CNT			    (SPU_DRV_SM_ADDR+0x254)
 
-#define CPRI_TX_ADVANCE_PP1S_ADDR	(0x0A4D7260)
+#define CPRI_TX_ADVANCE_PP1S_ADDR	(SPU_DRV_SM_ADDR+0x260)
-#define CPRI_RX_ADVANCE_PP1S_ADDR	(0x0A4D7264)
+#define CPRI_RX_ADVANCE_PP1S_ADDR	(SPU_DRV_SM_ADDR+0x264)
-#define CPRI_TDD_ADVANCE_PP1S_ADDR	(0x0A4D7268)
+#define CPRI_TDD_ADVANCE_PP1S_ADDR	(SPU_DRV_SM_ADDR+0x268)
+
+// GPIO JESD TX/RX/ORX bit
+#define GPIO_FROM_CFG_FILE 		(SPU_DRV_SM_ADDR+0x280)
+#define GPIO_JESD_RF_BIT		(GPIO_FROM_CFG_FILE+0x0)
+#define GPIO_JESD_RF_VALID		(GPIO_FROM_CFG_FILE+0x10)
+#define GPIO_JESD_TRIGGER_BIT	(GPIO_FROM_CFG_FILE+0x60)
+#define GPIO_JESD_TRIGGER_VALID	(GPIO_FROM_CFG_FILE+0x70)
 
 #define SLOT_NUM_DEBUG_ADDR		(0x0A4D7300)
 #define APE_INT_INFO_ADDR		(0x0A4D7400)

public/common/ecs_dm/inc/ecs_rfm_dm_mgt.h

@@ -20,6 +20,7 @@
 #include "cpri_delay.h"
 #include "mtimer_com.h"
 #include "phy_para.h"
+#include "gpio_drv.h"
 
 typedef struct tEcsRfmDmLocalMgt {
 #ifdef DISTRIBUTED_BS
@@ -30,6 +31,8 @@ typedef struct tEcsRfmDmLocalMgt {
 #ifdef INTEGRATED_BS
 
 #endif
+	stGpioOnBoard* 			pGpioInfo;
+
 	stFhAlarmStat*			pAlarmStatus;
 	stMtimerPara*			pMtimerPara[MTIMER_MAX_NUM];
     stOamMsgTransferHeader* pOamMsgPtr;

public/common/ecs_dm/inc/gpio_drv.h

@@ -0,0 +1,64 @@
+#ifndef _GPIO_DRV_H_
+#define _GPIO_DRV_H_
+
+#include "dw_apb_gpio.h"
+#include "typedef.h"
+
+#define JESD_RF_CH_NUM	4
+
+typedef enum _tagGpioLValid
+{
+	LOW_AS_VALID	= 0,
+	HIGH_AS_VALID
+}gpioLValid;
+
+typedef enum _tagJesdGpioTRCH
+{
+	JESD_RF_TX = 0,
+	JESD_RF_RX = 1,
+	JESD_RF_ORX = 2,
+	JESD_TRCH_MAXNUM = 3
+}jesdGpioTRch;
+
+typedef enum _tagJesdGpioState
+{
+	JESD_GPIO_OFF = 0,
+	JESD_GPIO_ON = 1
+}jesdGpioState;
+
+typedef struct _tagGpioInfo
+{
+	uint8_t pinId;	// 0~31
+	uint8_t vaFlag;	// 0: low as valid; 1: high as valid
+}stGpioInfo;
+
+typedef struct _tagGpioJesd
+{
+	stGpioInfo txGpioInfo[JESD_RF_CH_NUM];
+	stGpioInfo rxGpioInfo[JESD_RF_CH_NUM];
+	stGpioInfo orxGpioInfo[JESD_RF_CH_NUM];
+}stGpioJesd;
+
+typedef struct _tagGpioOnBoard
+{
+	stGpioJesd jesdGpioInfo;
+	stGpioInfo triggerGpioInfo;
+}stGpioOnBoard;
+
+int32_t hw_gpio_init();
+
+int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState);
+
+int32_t set_trigger_state(uint8_t nState);
+
+#if 0
+int32_t set_tx_on();
+
+int32_t set_tx_off();
+
+int32_t set_rx_on();
+
+int32_t set_rx_off();
+#endif
+#endif
+

public/common/ecs_dm/src/ecs_rfm_dm_mgt.s.c

@@ -34,6 +34,12 @@ void ecs_rfm_dm_alloc(void)
     pEcsDmLocalMgt->pCpriPara = (stCpriPara*)memSectionAlloc(pMemSection, sizeof(stCpriPara), MEM_ALIGNED_4BYTES, "pCpriPara");
     pEcsDmLocalMgt->pCpriDelay = (stCpriDelayMeasure*)memSectionAlloc(pMemSection, sizeof(stCpriDelayMeasure), MEM_ALIGNED_4BYTES, "pCpriDelay");
 #endif
+#ifdef INTEGRATED_BS
+	//pEcsDmLocalMgt->pJesdGpioInfo = (stGpioJesd*)memSectionAlloc();
+#endif
+	//stGpioOnBoard* pGpioInfo = (stGpioOnBoard*)0x0A4D7400;
+	pEcsDmLocalMgt->pGpioInfo = (stGpioOnBoard*)memSectionAlloc(pMemSection, sizeof(stGpioOnBoard), MEM_ALIGNED_4BYTES, "pGpioInfo"); // (stGpioOnBoard*)0x0A4D7400;
+
     pEcsDmLocalMgt->pAlarmStatus = (stFhAlarmStat*)memSectionAlloc(pMemSection, sizeof(stFhAlarmStat), MEM_ALIGNED_4BYTES, "pAlarmStatus");
     pEcsDmLocalMgt->pOamMsgPtr  = (stOamMsgTransferHeader*)memSectionAlloc(pMemSection, sizeof(stOamMsgTransferHeader), MEM_ALIGNED_4BYTES, "pOamMsg");
     pEcsDmLocalMgt->pOamBaseDelaySetRspPtr  =  (stCpriSetLinkDelay*)memSectionAlloc(pMemSection, sizeof(stCpriSetLinkDelay), MEM_ALIGNED_4BYTES, "pOamBaseDelaySetRsp");

public/ecs_rfm_spu1/driver/src/gpio_drv.s.c

@@ -0,0 +1,272 @@
+#include "gpio_drv.h"
+
+#include "dw_apb_gpio.h"
+#include "ucp_utility.h"
+#include "ucp_param.h"
+#include "phy_para.h"
+#include "ecs_rfm_dm_mgt.h"
+
+//stGpioOnBoard* pGpioInfo = (stGpioOnBoard*)0x0A4D7400;
+
+uint32_t   gGpioDirAddr[4] = {GPIO0A_DIR_REG_ADDR, GPIO0B_DIR_REG_ADDR, GPIO1A_DIR_REG_ADDR, GPIO1B_DIR_REG_ADDR};
+uint32_t   gGpioDataAddr[4] = {GPIO0A_DATA_REG_ADDR, GPIO0B_DATA_REG_ADDR, GPIO1A_DATA_REG_ADDR, GPIO1B_DATA_REG_ADDR};
+
+int32_t hw_gpio_init()
+{
+#ifdef INTEGRATED_BS
+	volatile uint32_t h1Pos = 0;
+	uint32_t nGpioPin = 0;
+	uint8_t i = 0;
+	uint8_t j = 0;
+	uint8_t k = 0;
+	uint8_t pinId = 0;
+	uint32_t pinAddr = 0;
+
+    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
+	stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
+
+	for (i = 0; i < 3; i++) // tx, rx, orx
+	{
+		k = 0;
+		for (j = 0; j < 4; j++)
+		{
+			nGpioPin = do_read_volatile(GPIO_JESD_RF_BIT + (i<<5) + (j<<2));
+			h1Pos = __builtin_clz(nGpioPin); // 从高bit开始，第一个1前面的0的个数
+			while (32 > h1Pos)
+			{
+				pinId = 31 - h1Pos;
+				pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[k].pinId) + sizeof(stGpioInfo) * JESD_RF_CH_NUM * i;
+				do_write_byte(pinAddr, (pinId + (j<<5)));
+				do_write_byte((pinAddr+1), ((do_read_volatile(GPIO_JESD_RF_VALID + (i<<5) + (j<<2)) >> pinId) & 0x1));
+				do_write(gGpioDirAddr[j], (do_read_volatile(gGpioDirAddr[j])|(1<<pinId)));
+				k++;
+				if (JESD_RF_CH_NUM < k)
+				{
+					return -1;
+				}
+				
+				nGpioPin &= (~(1 << pinId));
+				h1Pos = __builtin_clz(nGpioPin);
+			}
+		}
+	}
+
+	k = 0;
+	for (j = 0; j < 4; j++)
+	{
+		nGpioPin = do_read_volatile(GPIO_JESD_TRIGGER_BIT + (j<<2));
+		h1Pos = __builtin_clz(nGpioPin); // 从高bit开始，第一个1前面的0的个数
+		while (32 > h1Pos)
+		{
+			pinId = 31 - h1Pos;
+			pinAddr = (uint32_t)(&pGpioInfo->triggerGpioInfo.pinId);
+			do_write_byte(pinAddr, (pinId + (j<<5)));
+			do_write_byte((pinAddr+1), ((do_read_volatile(GPIO_JESD_TRIGGER_VALID + (j<<2)) >> pinId) & 0x1));
+			do_write(gGpioDirAddr[j], (do_read_volatile(gGpioDirAddr[j])|(1<<pinId)));
+			k++;
+			
+			break;
+			
+			//nGpioPin &= (~(1 << pinId));
+			///h1Pos = __builtin_clz(nGpioPin);
+		}
+	}
+#else
+	do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x000F0000));	// pinmux, GPIO1B25 and GPIO1B24, gpio func, 0x3
+	do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25)));				// GPIO1B25, output, 10ms trigger for phy
+#endif
+
+	return 0;
+}
+
+int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState)
+{
+	if (JESD_TRCH_MAXNUM <= nTRCh)
+	{
+		return -1;
+	}
+	if ((JESD_GPIO_ON != nState) && (JESD_GPIO_OFF != nState))
+	{
+		return -1;
+	}
+
+    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
+	stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
+
+	uint8_t pinGroup = 0;
+	uint8_t pinId = 0;
+	uint8_t valid = 0;
+	uint32_t dataAddr = 0;
+	uint32_t pinAddr = 0;
+	uint32_t validAddr = 0;
+	
+	for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
+	{
+		pinAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[i].pinId) + sizeof(stGpioInfo)*JESD_RF_CH_NUM*nTRCh;
+		validAddr = (uint32_t)(&pGpioInfo->jesdGpioInfo.txGpioInfo[i].vaFlag) + sizeof(stGpioInfo)*JESD_RF_CH_NUM*nTRCh;
+		pinId = do_read_volatile_byte(pinAddr);
+		valid = do_read_volatile_byte(validAddr);
+		pinGroup = pinId >> 5;
+		if (3 < pinGroup)
+		{
+			return -1;
+		}
+		pinId = pinId & 0x1F;
+		dataAddr = gGpioDataAddr[pinGroup];
+		if (((LOW_AS_VALID == valid) && (JESD_GPIO_ON == nState)) || 	((HIGH_AS_VALID == valid) && (JESD_GPIO_OFF == nState)))
+		{
+			do_write(dataAddr, (do_read_volatile(dataAddr)&(~(1<<pinId))));
+		}
+		else if (((LOW_AS_VALID == valid) && (JESD_GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (JESD_GPIO_ON == nState)))
+		{
+			do_write(dataAddr, (do_read_volatile(dataAddr)|(1<<pinId)));
+		}
+		else
+		{
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+int32_t set_trigger_state(uint8_t nState)
+{
+	if ((JESD_GPIO_ON != nState) && (JESD_GPIO_OFF != nState))
+	{
+		return -1;
+	}
+
+    EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
+	stGpioOnBoard* pGpioInfo = pEcsDmLocalMgt->pGpioInfo;
+
+	uint8_t pinGroup = 0;
+	uint8_t pinId = 0;
+	uint8_t valid = 0;
+	uint32_t dataAddr = 0;
+	
+	pinId = pGpioInfo->triggerGpioInfo.pinId;
+	valid =  pGpioInfo->triggerGpioInfo.vaFlag;
+	pinGroup = pinId >> 5;
+	if (3 < pinGroup)
+	{
+		return -1;
+	}
+	pinId = pinId & 0x1F;
+	dataAddr = gGpioDataAddr[pinGroup];
+	if (((LOW_AS_VALID == valid) && (JESD_GPIO_ON == nState)) ||	((HIGH_AS_VALID == valid) && (JESD_GPIO_OFF == nState)))
+	{
+		do_write(dataAddr, (do_read_volatile(dataAddr)&(~(1<<pinId))));
+	}
+	else if (((LOW_AS_VALID == valid) && (JESD_GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (JESD_GPIO_ON == nState)))
+	{
+		do_write(dataAddr, (do_read_volatile(dataAddr)|(1<<pinId)));
+	}
+	else
+	{
+		return -1;
+	}
+
+	return 0;
+}
+#if 0
+int32_t set_tx_on()
+{
+	return 0;
+}
+
+int32_t set_tx_off()
+{
+	uint8_t pinGroup = 0;
+	uint8_t pinId = 0;
+	uint32_t addr = 0;
+	
+	for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
+	{
+		pinGroup = pGpioInfo->jesdGpioInfo.txGpioInfo[i].pinId >> 5;
+		if (3 < pinGroup)
+		{
+			return -1;
+		}
+		pinId = pGpioInfo->jesdGpioInfo.txGpioInfo[i].pinId & 0x1F;
+		addr = gGpioDataAddr[pinGroup];
+		if (LOW_AS_VALID == pGpioInfo->jesdGpioInfo.txGpioInfo[i].vaFlag)
+		{
+			do_write(addr, (do_read_volatile(addr)|(1<<pinId)));
+		}
+		else if (HIGH_AS_VALID == pGpioInfo->jesdGpioInfo.txGpioInfo[i].vaFlag)
+		{
+			do_write(addr, (do_read_volatile(addr)&(~(1<<pinId))));
+		}
+		else
+		{
+			return -1;
+		}
+	}
+	return 0;
+}
+
+int32_t set_rx_on()
+{
+	uint8_t pinGroup = 0;
+	uint8_t pinId = 0;
+	uint32_t addr = 0;
+	
+	for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
+	{
+		pinGroup = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId >> 5;
+		if (3 < pinGroup)
+		{
+			return -1;
+		}
+		pinId = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId & 0x1F;
+		addr = gGpioDataAddr[pinGroup];
+		if (LOW_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
+		{
+			do_write(addr, (do_read_volatile(addr)&(~(1<<pinId))));
+		}
+		else if (HIGH_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
+		{
+			do_write(addr, (do_read_volatile(addr)|(1<<pinId)));
+		}
+		else
+		{
+			return -1;
+		}
+	}
+	return 0;
+}
+
+int32_t set_rx_off()
+{
+	uint8_t pinGroup = 0;
+	uint8_t pinId = 0;
+	uint32_t addr = 0;
+	
+	for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
+	{
+		pinGroup = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId >> 5;
+		if (3 < pinGroup)
+		{
+			return -1;
+		}
+		pinId = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId & 0x1F;
+		addr = gGpioDataAddr[pinGroup];
+		if (LOW_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
+		{
+			do_write(addr, (do_read_volatile(addr)|(1<<pinId)));
+		}
+		else if (HIGH_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
+		{
+			do_write(addr, (do_read_volatile(addr)&(~(1<<pinId))));
+		}
+		else
+		{
+			return -1;
+		}
+	}
+	return 0;
+}
+#endif
+
+

public/ecs_rfm_spu1/driver/src/jesd_timer.s.c

@@ -20,6 +20,7 @@
 #include "log_server.h"
 #include "gtimer_drv.h"
 #include "hw_gpio.h"
+#include "gpio_drv.h"
 
 #ifdef INTEGRATED_BS
 #ifdef TEST_ENABLE
@@ -352,9 +353,9 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
 		do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), (1<<(4+(nTmrId>>1))));	//IO ctrl
 		if (MTIMER_JESD_RX0_ID == nTmrId)
 		{
-			RxOff();
+			set_jesd_rf_state(JESD_RF_RX, JESD_GPIO_OFF); // RxOff();
 			delay_us(5);
-			TxOn();
+			set_jesd_rf_state(JESD_RF_TX, JESD_GPIO_ON); // TxOn();
 		}
 	}
 
@@ -981,7 +982,8 @@ void jesd_tdd_callback(uint8_t nTmrId)
 				do_write(tFlagAddr, (1<<MTMR_JESD_RXON));	// clear int flag
 				gRxOnCnt++;
 				debug_write((DBG_DDR_IDX_DRV_BASE+64+5), gRxOnCnt); // 0x114
-			RxOn();
+			//RxOn();
+			set_jesd_rf_state(JESD_RF_RX, JESD_GPIO_ON);
 				jesd_csu_rx_start();
 			}
 			if (tEventFlag & (1<<MTMR_JESD_RXOFF)) 		// rx off int
@@ -990,7 +992,8 @@ void jesd_tdd_callback(uint8_t nTmrId)
 				do_write(tFlagAddr, (1<<MTMR_JESD_RXOFF));	// clear int flag
 				gRxOffCnt++;
 				debug_write((DBG_DDR_IDX_DRV_BASE+64+6), gRxOffCnt); // 0x118
-			RxOff();
+			//RxOff();
+			set_jesd_rf_state(JESD_RF_RX, JESD_GPIO_OFF);
 			}
 			if (tEventFlag & (1<<MTMR_JESD_TXON)) 		// tx on int
 			{
@@ -998,7 +1001,8 @@ void jesd_tdd_callback(uint8_t nTmrId)
 				do_write(tFlagAddr, (1<<MTMR_JESD_TXON));	// clear int flag
 				gTxOnCnt++;
 				debug_write((DBG_DDR_IDX_DRV_BASE+76), gTxOnCnt); // 0x130
-			TxOn();
+			//TxOn();
+			set_jesd_rf_state(JESD_RF_TX, JESD_GPIO_ON);
 				//jesd_csu_start();
 			}
 			if (tEventFlag & (1<<MTMR_JESD_TXOFF)) 		// tx off int
@@ -1007,7 +1011,8 @@ void jesd_tdd_callback(uint8_t nTmrId)
 				do_write(tFlagAddr, (1<<MTMR_JESD_TXOFF));	// clear int flag
 				gTxOffCnt++;
 				debug_write((DBG_DDR_IDX_DRV_BASE+77), gTxOffCnt); // 0x134
-			TxOff();
+			//TxOff();
+			set_jesd_rf_state(JESD_RF_TX, JESD_GPIO_OFF);
 			}
 			if (cEventFlag & BIT11)
 			{
@@ -1100,11 +1105,13 @@ uint32_t start = GET_STC_CNT();
 				// test for trigger
 				if (0 == pMtimerSfn->txSlotNum)
 				{
-					rfm1_set_trigger_high();
+					//rfm1_set_trigger_high();
+					set_trigger_state(JESD_GPIO_ON);
 				}
 				else if ((pMtimerSfn->slotMaxNum >> 1) == pMtimerSfn->txSlotNum)
 				{
-					rfm1_set_trigger_low();
+					//rfm1_set_trigger_low();
+					set_trigger_state(JESD_GPIO_OFF);
 				}
 				__ucps2_synch(0);
 				if (8 > pMtimerInt->txSlotIntCnt)

public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c

@@ -11,11 +11,12 @@
 #include "spu_hw_queue.h"
 #include "spu_log.h"
 #include "app_interface.h"
-#include "hw_gpio.h"
 #include "gtimer_drv.h"
 #include "rfm1_gtimer2.h"
 #include "ecs_rfm_spu1_heap.h"
 #include "mtimer_cell.h"
+#include "hw_gpio.h"
+#include "gpio_drv.h"
 
 #ifdef DISTRIBUTED_BS
 #include "hw_cpri.h"
@@ -85,12 +86,6 @@ void ecs_rfm1_drv_init(void)
     debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
 #endif
 
-	hw_gpio_init();
-#ifdef PALLADIUM_TEST
-    flag++;
-    debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
-#endif
-
 #if 1
 	gtimer2_init(0);
 	rfm1_gtimer2_1_set_int();
@@ -124,6 +119,12 @@ void ecs_rfm1_drv_init(void)
     debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
 #endif
 
+	hw_gpio_init();
+#ifdef PALLADIUM_TEST
+    flag++;
+    debug_write((DBG_DDR_IDX_DRV_BASE+1+(apeId<<2)), flag);
+#endif
+
     ecs_hw_que_init(apeId);
     ecs_hw_que_init_noirq(apeId, apeId);
     ecs_msg_que_init(apeId);