jinhong/YB_Platform
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'dev_ck_v2.1_feature#1256#' into 'dev_ck_v2.1'

Browse Source 
UCP4008_SL new feature #1256

See merge request ucp/driver/ucp4008_platform_spu!56
This commit is contained in:
Xianfeng Du 2023-11-02 06:24:21 +00:00
commit c7c2891312
16 changed files with 168 additions and 103 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
public/common/driver/inc/phy_para.h
View File

@ -7,23 +7,23 @@
#define SFN_PERIOD 10000 // 10ms
#define SLOT_SYMBOL_NUM 14
#define SPU_DRV_SM_ADDR (0x0A4F2000) // (0x0A4D7000)
#define SPU_DRV_SM_ADDR (0x0A4F2000) // (0x0A4D7000) //
#define PROTO_SEL_ADDR (SPU_DRV_SM_ADDR+0x0)
#define PROTO_OPT_ADDR (SPU_DRV_SM_ADDR+0x4)
#define PHY_PARA_ADDR (SPU_DRV_SM_ADDR+0x8)
#define PHY_CELL_ADDR (SPU_DRV_SM_ADDR+0x100)
#define ORX_ADJUST_FLAG_ADDR (SPU_DRV_SM_ADDR+0x140)
#define ORX_ADJUST_FLAG_ADDR (SPU_DRV_SM_ADDR+0x140)
#define ORX_ADJUST_VAL_ADDR (SPU_DRV_SM_ADDR+0x144)
#define STC_TOD_INT_ADDR (SPU_DRV_SM_ADDR+0x200)
#define STC_RT_ADDR (SPU_DRV_SM_ADDR+0x204)
#define STC_RT_ADDR (SPU_DRV_SM_ADDR+0x204)
#define STC_CTW_EN_ADDR (SPU_DRV_SM_ADDR+0x208)
#define CPRI_DELAY_ADDR (SPU_DRV_SM_ADDR+0x210)
#define CPRI_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x214)
#define CPRI_TDD_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x218)
#define CPRI_TDD_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x218)
#define CTC_INT_TYPE_ADDR (SPU_DRV_SM_ADDR+0x21C)
@ -33,7 +33,7 @@
#define ARM_LOCK_FLAG_ADDR (SPU_DRV_SM_ADDR+0x22C)
#define ARM_SFN_VALID_FLAG (0x55)
#define ARM_SFN_NOTVALID_FLAG (0xAA)
#define ARM_SFN_NOTVALID_FLAG (0xAA)
#define CSU_STOP_CMD_ADDR (SPU_DRV_SM_ADDR+0x230)
#define CSU_UL_HEADER_DATA_OFFSET (SPU_DRV_SM_ADDR+0x234) // ul, the interval of frame header and frame data, ns as unit
@ -43,14 +43,14 @@
#define SERDES_INIT_FLAG_ADDR (SPU_DRV_SM_ADDR+0x240) // cpri or jesd clk init finished
#define STC_ONEPPS_OUT_ADDR (SPU_DRV_SM_ADDR+0x244)
#define JESD_RX_CH_PARA (SPU_DRV_SM_ADDR+0x248)
#define JESD_RX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x24C)
#define JESD_RX_CH_PARA (SPU_DRV_SM_ADDR+0x248)
#define JESD_RX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x24C)
#define JESD_ORX_CH_PARA (SPU_DRV_SM_ADDR+0x250)
#define JESD_ORX_CH_PARA (SPU_DRV_SM_ADDR+0x250)
#define JESD_ORX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x254)
#define JESD_TX_CH_PARA (SPU_DRV_SM_ADDR+0x258)
#define JESD_TX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x25C)
#define JESD_TX_CH_PARA (SPU_DRV_SM_ADDR+0x258)
#define JESD_TX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x25C)
#define CPRI_TX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x260)
#define CPRI_RX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x264)
@ -59,35 +59,35 @@
#define DDR_MONITOR_ENABLE (SPU_DRV_SM_ADDR+0x270) // 开始监测ddr性能
#define DDR_MONITOR_CNT (SPU_DRV_SM_ADDR+0x274)
#define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // us as unit
#define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C)
#define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // us as unit
#define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C)
// GPIO JESD TX/RX/ORX bit
#define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280)
#define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0)
#define GPIO_JESD_RF_VALID (GPIO_FROM_CFG_FILE+0x10)
#define GPIO_JESD_TRIGGER_BIT (GPIO_FROM_CFG_FILE+0x60)
#define GPIO_JESD_TRIGGER_VALID (GPIO_FROM_CFG_FILE+0x70)
#define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280)
#define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0)
#define GPIO_JESD_RF_VALID (GPIO_FROM_CFG_FILE+0x10)
#define GPIO_JESD_TRIGGER_BIT (GPIO_FROM_CFG_FILE+0x60)
#define GPIO_JESD_TRIGGER_VALID (GPIO_FROM_CFG_FILE+0x70)
#define SLOT_NUM_DEBUG_ADDR (0x0A4D7300)
#define APE_INT_INFO_ADDR (0x0A4D7400)
#define SLOT_NUM_DEBUG_ADDR (0x0A4D7300)
#define APE_INT_INFO_ADDR (0x0A4D7400)
#define PHY_CELL_FLAG 0xAFAFAFAF
#define ARM_SFN_UPDATE_FLAG 0xA5A5A5A5
#define PHY_CELL_FLAG 0xAFAFAFAF
#define ARM_SFN_UPDATE_FLAG 0xA5A5A5A5
#define ENABLE_SFNCAL // 使能与arm的帧号校准功能
#define ENABLE_SFNCAL // 使能与arm的帧号校准功能
//#define DISTRIBUTED_BS
//#define INTEGRATION_BS
//#define GPS_PP1S_SYNC
#define GPS_LTE_OFFSET 0 // 700 // us
#define GPS_NR_OFFSET 0 // 2700 // us
#define LTE_NR_OFFSET 0 // 2000 // us
#define GPS_LTE_OFFSET 0 // 700 // us
#define GPS_NR_OFFSET 0 // 2700 // us
#define LTE_NR_OFFSET 0 // 2000 // us
#define SCS_MAX_NUM 2
#define SCS_MAX_NUM 2
#define MTIMER_INTEGRATED_MAX_NUM 4
#define MTIMER_DISTRIBUTED_MAX_NUM 2
#define MTIMER_INTEGRATED_MAX_NUM 4
#define MTIMER_DISTRIBUTED_MAX_NUM 2
typedef enum _tagScsId
{

12
public/common/driver/src/phy_para.s.c
View File

@ -5,20 +5,18 @@
#include "ucp_utility.h"
#include "ucp_printf.h"
uint32_t* pProtoSel = (uint32_t*)PROTO_SEL_ADDR;
uint32_t* pProtoOpt = (uint32_t*)PROTO_OPT_ADDR;
uint32_t* pProtoSel = (uint32_t*)PROTO_SEL_ADDR;
uint32_t* pProtoOpt = (uint32_t*)PROTO_OPT_ADDR;
stPhyScsPara* phyPara = (stPhyScsPara*)PHY_PARA_ADDR;
stSfnPara gCellSfnPara[2]; // cell para
uint32_t gScsId = 0;
uint32_t gMtimerId = 0;
uint32_t* gCpriCsuStopCmd = (uint32_t*)CSU_STOP_CMD_ADDR;
uint32_t gScsId = 0;
uint32_t gMtimerId = 0;
uint32_t* gCpriCsuStopCmd = (uint32_t*)CSU_STOP_CMD_ADDR;
void sfn_para_init(void)
{
//gScsId = SCS_NULL;
memset(&gCellSfnPara[0], 0, sizeof(stSfnPara) * SCS_MAX_NUM);
//gMtimerId = SCS_1st_MTIMER_ID; // protecting overflow
gCellSfnPara[SCS_1st_MTIMER_ID].scsId = SCS_NULL;
gCellSfnPara[SCS_2nd_MTIMER_ID].scsId = SCS_NULL;
}

3
public/common/ecs_dm/inc/cpri_delay.h
View File

@ -136,15 +136,18 @@ typedef struct _tagCpriFrameHeadOffsetReq {
uint16_t u16frame_head_offset;
uint8_t u8rsv[2];
} stCpriFrameHeadOffsetReq;
typedef struct _tagCpriFrameHeadOffsetRsp {
uint8_t u8result;
uint8_t u8rsv[3];
} stCpriFrameHeadOffsetRsp;
typedef struct _tagCpriGetFrameHeadOffset {
uint8_t u8result;
uint8_t u8rsv;
uint16_t u16frame_head_offset;
}stCpriGetFrameHeadOffset;
typedef struct _tagOamMsgTransferHeader {
uint8_t numMsg;
uint8_t cellIndex;

1
public/common/ecs_dm/inc/ecs_rfm_dm_mgt.h
View File

@ -38,6 +38,7 @@ typedef struct tEcsRfmDmLocalMgt {
stCpriCsuCmdFifoInfo* tx_cmd_fifo_ptr;
stCpriCsuCmdFifoInfo* rx_cmd_fifo_ptr;
JesdOrxPara_t* jesd_orx_para_ptr;
JesdDelay_t* jesd_delay_ptr;
} EcsRfmDmLocalMgt_t;
EcsRfmDmLocalMgt_t* get_ecs_rfm_dm_local_mgt(void);

14
public/common/ecs_dm/inc/jesd_drv_para.h
View File

@ -3,6 +3,20 @@
#include "typedef.h"
typedef struct JesdDelay
{
// 10ms offset, us as unit
uint32_t tx_offset;
uint32_t rx_offset;
uint32_t tdd_offset;
uint32_t gps_offset;
// 10ms tx/rx offset to pp1s
int32_t jesd_10ms2pp1s_txoffset;
int32_t jesd_10ms2pp1s_rxoffset;
int32_t jesd_tdd2pp1s_offset;
}JesdDelay_t;
typedef struct JesdOrxPara
{
uint32_t orx_calldrv_cnt;

20
public/common/ecs_dm/src/ecs_rfm_dm_mgt.s.c
View File

@ -40,11 +40,13 @@ int32_t ecs_rfm_dm_alloc(void)
{
return -1;
}
pEcsDmLocalMgt->pCpriDelay = (stCpriDelayMeasure*)memSectionAlloc(pMemSection, sizeof(stCpriDelayMeasure), MEM_ALIGNED_4BYTES, "pCpriDelay");
if (NULL == pEcsDmLocalMgt->pCpriDelay)
{
return -1;
}
//stGpioOnBoard* pGpioInfo = (stGpioOnBoard*)0x0A4D7400;
pEcsDmLocalMgt->pGpioInfo = (stGpioOnBoard*)memSectionAlloc(pMemSection, sizeof(stGpioOnBoard), MEM_ALIGNED_4BYTES, "pGpioInfo"); // (stGpioOnBoard*)0x0A4D7400;
if (NULL == pEcsDmLocalMgt->pGpioInfo)
@ -57,21 +59,25 @@ int32_t ecs_rfm_dm_alloc(void)
{
return -1;
}
pEcsDmLocalMgt->pOamMsgPtr = (stOamMsgTransferHeader*)memSectionAlloc(pMemSection, sizeof(stOamMsgTransferHeader), MEM_ALIGNED_4BYTES, "pOamMsg");
if (NULL == pEcsDmLocalMgt->pOamMsgPtr)
{
return -1;
}
pEcsDmLocalMgt->pOamBaseDelaySetRspPtr = (stCpriSetLinkDelay*)memSectionAlloc(pMemSection, sizeof(stCpriSetLinkDelay), MEM_ALIGNED_4BYTES, "pOamBaseDelaySetRsp");
if (NULL == pEcsDmLocalMgt->pOamBaseDelaySetRspPtr)
{
return -1;
}
pEcsDmLocalMgt->pOamBaseDelayQryRspPtr = (stCpriGetLinkDelay*)memSectionAlloc(pMemSection, sizeof(stCpriGetLinkDelay), MEM_ALIGNED_4BYTES, "pOamBaseDelayQryRsp");
if (NULL == pEcsDmLocalMgt->pOamBaseDelayQryRspPtr)
{
return -1;
}
pEcsDmLocalMgt->pOamFiberDelayQryRspPtr = (stCpriGetRndDelay*)memSectionAlloc(pMemSection, sizeof(stCpriGetRndDelay), MEM_ALIGNED_4BYTES, "OamFiberDelayQryRsp");
if (NULL == pEcsDmLocalMgt->pOamFiberDelayQryRspPtr)
{
@ -83,11 +89,13 @@ int32_t ecs_rfm_dm_alloc(void)
{
return -1;
}
pEcsDmLocalMgt->pOamFrameHeadOffsetQryRspPtr = (stCpriGetFrameHeadOffset*)memSectionAlloc(pMemSection, sizeof(stCpriGetFrameHeadOffset), MEM_ALIGNED_4BYTES, "pOamFrameHeadOffsetQryRspPtr");
if (NULL == pEcsDmLocalMgt->pOamFrameHeadOffsetQryRspPtr)
{
return -1;
}
for (int i = 0; i < MTIMER_INTEGRATED_MAX_NUM; i++)
{
pEcsDmLocalMgt->pMtimerPara[i] = (stMtimerPara*)memSectionAlloc(pMemSection, sizeof(stMtimerPara), MEM_ALIGNED_4BYTES, "pMtimerPara[i]");
@ -115,6 +123,12 @@ int32_t ecs_rfm_dm_alloc(void)
return -1;
}
pEcsDmLocalMgt->jesd_delay_ptr = (JesdDelay_t*)memSectionAlloc(pMemSection, sizeof(JesdDelay_t), MEM_ALIGNED_4BYTES, "jesd_delay");
if (NULL == pEcsDmLocalMgt->jesd_delay_ptr)
{
return -1;
}
return 0;
}
@ -213,6 +227,12 @@ int32_t ecs_rfm1_dm_init(void)
}
memset_ucp(pEcsDmLocalMgt->jesd_orx_para_ptr, 0, sizeof(JesdOrxPara_t));
if (NULL == pEcsDmLocalMgt->jesd_delay_ptr)
{
return -1;
}
memset_ucp(pEcsDmLocalMgt->jesd_delay_ptr, 0, sizeof(JesdDelay_t));
return 0;
}

3
public/ecs_rfm_spu1/driver/inc/cpri_driver.h
View File

@ -69,4 +69,7 @@ uint32_t UCP_API_CPRI_GetTxXCnt();
uint32_t UCP_API_CPRI_GetRxHfnCnt();
int32_t set_cpri_rru_msg(CpriRruMsg_t rru_msg);
uint32_t get_cpri_rru_msg_addr();

2
public/ecs_rfm_spu1/driver/inc/mtimer_cell.h
View File

@ -7,7 +7,7 @@
//void phy_cell_para_init(int32_t nScsId);
void mtimer_init4phy(phy_timer_config_ind_t *mtmr);
int32_t mtimer_init4phy(phy_timer_config_ind_t *mtmr);
// 建小区，先走ecs rfm1的建小区流程，再通知APE
int32_t mtimer_reconfig(phy_timer_config_ind_t *my_mtmr);

2
public/ecs_rfm_spu1/driver/inc/rfm1_drv.h
View File

@ -5,7 +5,7 @@
void ecs_rfm1_drv_init(void);
void check_phy_cell(void);
int32_t check_phy_cell(void);
void check_10ms_offset(void);

7
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -823,10 +823,8 @@ void isr_cpri_tdd_offset(void)
uint32_t tmrIntcFlag = 0;
uint32_t tEventFlag = 0;
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
//#ifdef DISTRIBUTED_BS
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
//#endif
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG); // &CPRI_TMR_INTC_REG);
@ -859,8 +857,6 @@ void isr_cpri_tdd_offset(void)
cpri_tdd_start_csu_timing();
}
#endif
//#ifdef CPRI_TIMING_7D2U_TEST
//#ifdef DISTRIBUTED_BS
#if 0
if (32 > pMtimerInt->tddOffsetIntCnt)
{
@ -942,7 +938,6 @@ void isr_cpri_tdd_offset(void)
debug_write((DBG_DDR_IDX_DRV_BASE+77), gCpriCsuFifoTxCnt); // 0x134
}
#endif
//#endif
//debug_write((DBG_DDR_IDX_DRV_BASE+289), (GET_STC_CNT()-start)); // 0x484
}
if (tEventFlag & (1<<MTMR_CSU_INSERT)) // 8ms int
@ -1059,7 +1054,7 @@ void isr_cpri_slot_offset(void)
debug_write(((DBG_DDR_IDX_DRV_BASE+9728) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), (nowTxSlotStcCnt-lastTxSlotStcCnt)); // 0x9800
lastTxSlotStcCnt = nowTxSlotStcCnt;
#endif
#if 1
#if 0
nowTxSlotCnt = GET_STC_CNT();
if ((nowTxSlotCnt > lastTxSlotCnt) && (2 < pMtimerInt->txSlotIntCnt))
{

2
public/ecs_rfm_spu1/driver/src/gpio_drv.s.c
View File

@ -116,7 +116,7 @@ int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState)
}
pinId = pinId & 0x1F;
dataAddr = gGpioDataAddr[pinGroup];
if (((LOW_AS_VALID == valid) && (GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_OFF == nState)))
if (((LOW_AS_VALID == valid) && (GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_OFF == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)&(~(1<<pinId))));
}

118
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -40,8 +40,6 @@ extern stMtimerIntStat gMtimerIntCnt[SCS_MAX_NUM];
extern stMtimerPhyPara gMtimerSfnNum[SCS_MAX_NUM];
extern stMtimerSfnCal gMtimerSfnCalPara[SCS_MAX_NUM];
stJesdDelay gJesdDelay;
int32_t gCsuTxAdvanceNs = JESD_TX_ADVANCE_NS;
int32_t gCsuRxAdvanceNs = JESD_RX_ADVANCE_NS - JESD_RRU_TD;
@ -101,9 +99,12 @@ void jesd_init()
void jesd_delay_init()
{
gJesdDelay.txOffset = INT_DELAY; //CPRI_RE_TOFFSET;
gJesdDelay.rxOffset = INT_DELAY; //CPRI_RE_TOFFSET;
gJesdDelay.tddOffset = INT_DELAY + EDMA_OFFSET; //CPRI_RE_TOFFSET + CPRI_EDMA_OFFSET;
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
JesdDelay_t* jesd_delay_ptr = pEcsDmLocalMgt->jesd_delay_ptr;
jesd_delay_ptr->tx_offset = INT_DELAY;
jesd_delay_ptr->rx_offset = INT_DELAY;
jesd_delay_ptr->tdd_offset = INT_DELAY + EDMA_OFFSET;
}
int32_t jesd_mtimer_init(int32_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
@ -194,7 +195,8 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerPara* pMtimerTxPara = pEcsDmLocalMgt->pMtimerPara[nTmrId+2];
uint32_t tdd = pMtimerPara->tddPeriod;
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
uint32_t tdd = pMtimerPara->tddPeriod; // us
uint32_t slotUs = pMtimerPara->slotPeriod;
uint32_t longSymbCost = slotUs*1000*LONGCP_SAM_CNT/SLOT_SAM_CNT; // ns
uint32_t shortSymbCost = slotUs*1000*SHORTCP_SAM_CNT/SLOT_SAM_CNT; // ns
@ -218,11 +220,11 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
dlSlotCnt = my_jesdtmr->num_t_dl[0];
dlSymbolCnt = my_jesdtmr->num_t_dl_symb[0];
}
pMtimerTxPara->txCsuOn[i].timerPoint = tdd - gCsuTxAdvanceNs/1000;
pMtimerTxPara->txCsuOn[i].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOn[i].timerPoint, &pMtimerTxPara->txCsuOn[i].pointL,
&pMtimerTxPara->txCsuOn[i].pointM, &pMtimerTxPara->txCsuOn[i].pointH);
pMtimerTxPara->txCsuOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000;
pMtimerTxPara->txCsuOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOff[i].timerPoint, &pMtimerTxPara->txCsuOff[i].pointL,
&pMtimerTxPara->txCsuOff[i].pointM, &pMtimerTxPara->txCsuOff[i].pointH);
@ -230,7 +232,7 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOn[i].timerPoint, &pMtimerPara->rxCsuOn[i].pointL,
&pMtimerPara->rxCsuOn[i].pointM, &pMtimerPara->rxCsuOn[i].pointH);
pMtimerPara->rxCsuOff[i].timerPoint = tdd - gCsuRxAdvanceNs/1000;
pMtimerPara->rxCsuOff[i].timerPoint = tdd - gCsuRxAdvanceNs/1000 - pJesdDelay->gps_offset; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOff[i].timerPoint, &pMtimerPara->rxCsuOff[i].pointL,
&pMtimerPara->rxCsuOff[i].pointM, &pMtimerPara->rxCsuOff[i].pointH);
@ -252,6 +254,7 @@ int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdt
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
uint32_t tdd = pMtimerPara->tddPeriod;
uint32_t slotUs = pMtimerPara->slotPeriod;
uint32_t longSymbCost = slotUs*1000*LONGCP_SAM_CNT/SLOT_SAM_CNT; // ns
@ -276,11 +279,11 @@ int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdt
dlSlotCnt = my_jesdtmr->num_t_dl[0];
dlSymbolCnt = my_jesdtmr->num_t_dl_symb[0];
}
pMtimerPara->txRfOn[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXON2PP1S); //JESD_RF_ON_GAP; // tdd-8us
pMtimerPara->txRfOn[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXON2PP1S) - pJesdDelay->gps_offset; // pJesdDelay->jesd_10ms2pp1s_txoffset; //JESD_RF_ON_GAP; // tdd-8us
get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOn[i].timerPoint, &pMtimerPara->txRfOn[i].pointL,
&pMtimerPara->txRfOn[i].pointM, &pMtimerPara->txRfOn[i].pointH);
pMtimerPara->txRfOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000;
pMtimerPara->txRfOff[i].timerPoint = dlSlotCnt*slotUs + (longSymbCost+(dlSymbolCnt-1)*shortSymbCost)/1000 - pJesdDelay->gps_offset; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId, pMtimerPara->txRfOff[i].timerPoint, &pMtimerPara->txRfOff[i].pointL,
&pMtimerPara->txRfOff[i].pointM, &pMtimerPara->txRfOff[i].pointH);
@ -288,7 +291,7 @@ int32_t jesd_timer_get_rf_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdt
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxRfOn[i].timerPoint, &pMtimerPara->rxRfOn[i].pointL,
&pMtimerPara->rxRfOn[i].pointM, &pMtimerPara->rxRfOn[i].pointH);
pMtimerPara->rxRfOff[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXOFF2RXON); //JESD_TXRX_CHANGE_GAP; // tdd-13us
pMtimerPara->rxRfOff[i].timerPoint = tdd - do_read_volatile(JESD_RF_TXOFF2RXON) - pJesdDelay->gps_offset; // pJesdDelay->jesd_10ms2pp1s_txoffset; //JESD_TXRX_CHANGE_GAP; // tdd-13us
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxRfOff[i].timerPoint, &pMtimerPara->rxRfOff[i].pointL,
&pMtimerPara->rxRfOff[i].pointM, &pMtimerPara->rxRfOff[i].pointH);
@ -317,6 +320,19 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerPara* pMtimerTxPara = pEcsDmLocalMgt->pMtimerPara[nTmrId+2];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
uint32_t addr = (uint32_t)&(phyPara[pMtimerPara->scsId].gpsOffset);
uint16_t gpsOffset = do_read_volatile_short(addr);
pJesdDelay->gps_offset = gpsOffset;
pJesdDelay->jesd_10ms2pp1s_txoffset = pJesdDelay->tx_offset + gpsOffset; // advance us
pJesdDelay->jesd_10ms2pp1s_rxoffset = pJesdDelay->rx_offset + gpsOffset; // gpsOffset - pJesdDelay->rxOffset; // delay us
pJesdDelay->jesd_tdd2pp1s_offset = gpsOffset + pJesdDelay->tdd_offset; // advance us as positive number
do_write(CPRI_TX_ADVANCE_PP1S_ADDR, pJesdDelay->jesd_10ms2pp1s_txoffset);
do_write(CPRI_RX_ADVANCE_PP1S_ADDR, pJesdDelay->jesd_10ms2pp1s_rxoffset);
do_write(CPRI_TDD_ADVANCE_PP1S_ADDR, pJesdDelay->jesd_tdd2pp1s_offset);
int32_t scsId = my_jesdtmr->scsId;
pMtimerPara->frameType = my_jesdtmr->frameType;
@ -384,12 +400,6 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
set_jesd_tdd_offset(nTmrId); // 5ms int, dma
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
set_jesd_tx_slot_offset(nTmrId);
set_jesd_rx_slot_offset(nTmrId);
#ifdef PALLADIUM_TEST
@ -397,27 +407,36 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
if ((JESD_CSU_CTRL == gJesdIOMode) && (MTIMER_JESD_RX0_ID == nTmrId))
if (MTIMER_JESD_RX0_ID == nTmrId)
{
gCsuRxAdvanceNs = JESD_RX_ADVANCE_NS - do_read_volatile(CSU_RX_TD_SAMPLE);
gCsuTxAdvanceNs = do_read_volatile(CSU_TX_ADVANCE_SAMPLE);
#if 0
set_jesd_csu_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csu_point(MTIMER_JESD_TX0_ID, 0);
#else
set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuoff_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
set_jesd_csuoff_point(MTIMER_JESD_TX0_ID, 0);
#endif
set_jesd_rxon_point(nTmrId, 0);
set_jesd_rxoff_point(nTmrId, 0);
set_jesd_txon_point(nTmrId, 0);
set_jesd_txoff_point(nTmrId, 0);
set_jesd_tdd_offset(nTmrId); // 5ms int, dma
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
if ((JESD_CSU_CTRL == gJesdIOMode) && (MTIMER_JESD_RX0_ID == nTmrId))
{
gCsuRxAdvanceNs = JESD_RX_ADVANCE_NS - do_read_volatile(CSU_RX_TD_SAMPLE);
gCsuTxAdvanceNs = do_read_volatile(CSU_TX_ADVANCE_SAMPLE);
#if 0
set_jesd_csu_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csu_point(MTIMER_JESD_TX0_ID, 0);
#else
set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuoff_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
set_jesd_csuoff_point(MTIMER_JESD_TX0_ID, 0);
#endif
set_jesd_rxon_point(nTmrId, 0);
set_jesd_rxoff_point(nTmrId, 0);
set_jesd_txon_point(nTmrId, 0);
set_jesd_txoff_point(nTmrId, 0);
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
#endif
}
}
reCfgFlag = 1;
@ -427,9 +446,10 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
int32_t jesd_timer_clear_cell(int32_t nTmrId, uint8_t scsId)
{
//UCP_API_CPRI_CSU_STOP(); // 是否需要等几个ms
clear_jesd_tdd_offset(nTmrId);
if (MTIMER_JESD_RX0_ID == nTmrId)
{
clear_jesd_tdd_offset(nTmrId);
}
clear_jesd_tx_slot_offset(nTmrId);
clear_jesd_rx_slot_offset(nTmrId);
if (LTE_SCS_ID == scsId)
@ -581,8 +601,8 @@ void set_jesd_1pps_scratch(int32_t nTmrId)
// 10ms
void set_jesd_sfn_offset(int32_t nTmrId)
{
//EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
uint32_t tmr0Point = SFN_PERIOD - gJesdDelay.txOffset; // us
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
uint32_t tmr0Point = SFN_PERIOD - pEcsDmLocalMgt->jesd_delay_ptr->jesd_10ms2pp1s_txoffset; // us
set_mtimer_tmrpoint(nTmrId, MTMR_10ms_OFFSET, tmr0Point, MTIMER_MASK_62BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_10ms_OFFSET, MTMR_INT_10ms);
@ -592,8 +612,9 @@ void set_jesd_tdd_offset(int32_t nTmrId)
{
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
uint32_t tmr2Point = pMtimerPara->tddPeriod - gJesdDelay.tddOffset; // us // 5ms
uint32_t tmr2Point = pMtimerPara->tddPeriod - pJesdDelay->jesd_tdd2pp1s_offset; // us // 5ms
set_mtimer_tmrpoint(nTmrId, MTMR_TDD_OFFSET, tmr2Point, MTIMER_MASK_48BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_TDD_OFFSET, MTMR_INT_TDD_OFFSET);
}
@ -605,7 +626,10 @@ void clear_jesd_tdd_offset(int32_t nTmrId)
void set_jesd_tx_slot_offset(int32_t nTmrId)
{
uint32_t tmr3Point = SFN_PERIOD - gJesdDelay.txOffset; // us
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
int32_t tmr3Point = SFN_PERIOD - pJesdDelay->jesd_10ms2pp1s_txoffset; // pJesdDelay->tx_offset; // us
set_mtimer_tmrpoint(nTmrId, MTMR_TXSLOT_OFFSET, tmr3Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_TXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}
@ -617,10 +641,14 @@ void clear_jesd_tx_slot_offset(int32_t nTmrId)
void set_jesd_rx_slot_offset(int32_t nTmrId)
{
int32_t tmr4Point = SFN_PERIOD - gJesdDelay.txOffset; //gJesdDelay.rxOffset; // // us
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
int32_t tmr4Point = SFN_PERIOD - pJesdDelay->jesd_10ms2pp1s_txoffset; //gJesdDelay.rxOffset; // // us
set_mtimer_tmrpoint(nTmrId, MTMR_RXSLOT_OFFSET, tmr4Point, MTIMER_MASK_32BIT);
enable_mtimer_tmrpoint_int(nTmrId, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
}
void clear_jesd_rx_slot_offset(int32_t nTmrId)
{
disable_mtimer_tmrpoint_int(nTmrId, MTMR_RXSLOT_OFFSET, MTMR_INT_SLOT_OFFSET);
@ -637,9 +665,10 @@ int32_t set_jesd_ape_slot_offset(int32_t nTmrId, uint32_t apeCoreId)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
JesdDelay_t* pJesdDelay = pEcsDmLocalMgt->jesd_delay_ptr;
pMtimerPara->runCoreId = apeCoreId;
txOffset = gJesdDelay.txOffset;
rxOffset = gJesdDelay.rxOffset;
txOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;
rxOffset = pJesdDelay->jesd_10ms2pp1s_txoffset;
uint32_t tmr3Point = SFN_PERIOD - txOffset; // us
uint32_t tmr4Point = SFN_PERIOD - txOffset; // us
@ -1050,7 +1079,6 @@ void jesd_10ms_callback(uint8_t nTmrId)
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[nTmrId];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[nTmrId];
//stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[nTmrId];
tmrIntcFlag = do_read_volatile(tmrBaseAddr+MTMR_INTC_REG) ;
__ucps2_synch(0);

2
public/ecs_rfm_spu1/driver/src/mtimer_cal.s.c
View File

@ -165,6 +165,7 @@ int32_t mtimer_1pps_func(uint8_t nTmrId)
orx_para_ptr->pp1s_adjust_flag = 0;
}
// gps unlock -> lock, adjust pp1s
pMtimerCal->pp1sLockFlag = do_read_volatile(ARM_LOCK_FLAG_ADDR);
__ucps2_synch(f_SMR);
if ((0 == pMtimerCal->pp1sLockFlagPre) && (1 == pMtimerCal->pp1sLockFlag)) // pp1s刚锁定
@ -181,6 +182,7 @@ int32_t mtimer_1pps_func(uint8_t nTmrId)
}
pMtimerCal->pp1sLockFlagPre = pMtimerCal->pp1sLockFlag;
// sfn num calibration
pMtimerCal->sfnValidFlag = do_read_volatile(ARM_SFN_VALID_ADDR);
pMtimerCal->sfnFlipFlag = do_read_volatile(ARM_SFN_FLIP_ADDR);
__ucps2_synch(f_SMR);

6
public/ecs_rfm_spu1/driver/src/mtimer_cell.s.c
View File

@ -16,9 +16,9 @@ extern uint32_t gMtimerId;
extern stPhyScsPara* phyPara;
extern uint32_t reCfgFlag;
extern void check_phy_cell(void);
extern int32_t check_phy_cell(void);
void mtimer_init4phy(phy_timer_config_ind_t *mtmr)
int32_t mtimer_init4phy(phy_timer_config_ind_t *mtmr)
{
uint8_t nBsType = get_protocol_sel();
//phy_cell_para_init(mtmr->scsId);
@ -37,7 +37,7 @@ void mtimer_init4phy(phy_timer_config_ind_t *mtmr)
do_write((&(pPhyCellPara->flag)), PHY_CELL_FLAG);
__ucps2_synch(f_SM);
check_phy_cell();
return check_phy_cell();
}
// 建小区，先走ecs rfm1的建小区流程，再通知APE

8
public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c
View File

@ -117,7 +117,7 @@ void ecs_rfm1_drv_init(void)
#endif
}
void check_phy_cell(void)
int32_t check_phy_cell(void)
{
//uint32_t clockBegin,clockEnd;
//int32_t clockCnt;
@ -142,10 +142,10 @@ void check_phy_cell(void)
//clockCnt = clockEnd - clockBegin;
//debug_write((DBG_DDR_IDX_DRV_BASE+900), clockCnt); // 0xe10
if (-1 == ret)
if (0 != ret)
{
UCP_PRINT_ERROR("mtimer_reconfig failed. \r\n");
return;
return ret;
}
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),6), 6);
@ -153,6 +153,8 @@ void check_phy_cell(void)
__ucps2_synch(f_SM);
//debug_write(DBG_DDR_COMMON_IDX(get_core_id(),7), 7);
}
return 0;
}
void check_10ms_offset(void)

11
public/ecs_rfm_spu1/top/src/phy_init.s.c
View File

@ -178,7 +178,11 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
return;
}
mtimer_init4phy(&my_cpritmr);
int32_t ret = mtimer_init4phy(&my_cpritmr);
if (0 != ret)
{
return;
}
uint32_t apeId = 0;
uint32_t runCore = my_cpritmr.runCoreId;
@ -195,11 +199,6 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId)
runCore &= (~(1 << apeId));
h1Pos = __builtin_clz(runCore);
}
//for (int32_t coreId = 0; coreId < 4; coreId++)
{
//ecs_rfm1_send_create_task_info(coreId);
}
}