diff --git a/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c b/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c
index 0c37fe8..3938d7d 100644
--- a/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c
+++ b/public/ecs_rfm_spu1/driver/src/jesd_csu.s.c
@@ -128,8 +128,9 @@ int32_t jesd_orx_csu_init(uint8_t margin)
 {
     gJesdCsuPara.orxMargin = margin;
 	//uint32_t val = (((gJesdCsuPara.m>>1)-1)<<26)+((gJesdCsuPara.seq-1)<<24)+(((gJesdCsuPara.nTotal*gJesdCsuPara.m)/gJesdCsuPara.seq)<<16)+((gJesdCsuPara.n-8)<<8)+(gJesdCsuPara.margin<<4)+gJesdCsuPara.cs;
-	uint32_t val = (((JS_204B_ORX_M>>1)-1)<<26)+((gJesdCsuPara.nTotal*JS_204B_ORX_M)<<16)+((gJesdCsuPara.n-8)<<8)+(gJesdCsuPara.orxMargin<<4)+gJesdCsuPara.cs;
+	uint32_t val = (((JS_204B_ORX_M>>1)-1)<<26)+((gJesdCsuPara.nTotal*JS_204B_ORX_M)<<16)+((gJesdCsuPara.n-8)<<8)+(margin<<4)+gJesdCsuPara.cs;
 	do_write((&JS_CSU_JESDRX1SET), val);
+	do_write((&JS_CSU_FINDDMATAG), 0x60);						// st wait wr resp
 	do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x80048010);	// [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write
 	do_write((&JS_CSU_EM_BS_SMSEL_PREDATANUM), ((0x3<<14) | (0x5<<5) | 0x8));
 
@@ -299,7 +300,7 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
 		stLinkDesc.cmdFifoH = rxListCmdH & 0x3FFF;
 		stLinkDesc.dmaAddrL = pListNode[i].dataAddr;
 		stLinkDesc.dmaXNum = 0x20 * (1<<mrg);	// 32*(2^margin)
-		if (2 >= gJesdCsuPara.antNum)
+		if ((2 >= gJesdCsuPara.antNum) && (1 != orxFlag))
 		{
 		    stLinkDesc.dmaYStep = stLinkDesc.dmaXNum;
 			stLinkDesc.dmaYNum = pListNode[i].allNum / stLinkDesc.dmaXNum;
@@ -518,11 +519,22 @@ int32_t jesd_csu_rx_start(uint8_t nListId)
 	return 0;
 }
 
+//uint32_t gOrxCsuStartCnt = 0;
 int32_t jesd_csu_orx_start(uint8_t nListId)
 {
-	jesd_csu_rx_start_ch(1, nListId);
-
-	do_write(&(JS_CSU_TAGMASK2), BIT2);
+	int32_t ret = jesd_csu_rx_start_ch(1, nListId);
+	if (0 == ret)
+	{
+	    do_write(&(JS_CSU_TAGMASK2), BIT2);
+		//gOrxCsuStartCnt++;
+	    //debug_write((DBG_DDR_IDX_DRV_BASE+51), gOrxCsuStartCnt); // 0xCC
+	}
+	else
+	{
+		//debug_write((DBG_DDR_IDX_DRV_BASE+52), gJesdRxListPara[1][0].listAddr); // 0xD0
+		//debug_write((DBG_DDR_IDX_DRV_BASE+53), gJesdRxListPara[1][0].listNodeNum); // 0xD4
+		return -1;
+	}
 
 	return 0;
 }
diff --git a/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c b/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c
index d332c0c..134e8bd 100644
--- a/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c
+++ b/public/ecs_rfm_spu1/driver/src/jesd_orx_timer.s.c
@@ -20,6 +20,7 @@ extern int32_t jesd_sniffer_orx_csu_init();
 
 extern stPhyScsPara* phyPara;
 extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
+//extern stJesdListPara gJesdRxListPara[JESD_CH_NUM][JESD_LIST_NUM];
 
 int32_t jesd_orx_mtimer_init(int32_t nTmrId, int32_t nScsId)
 {
@@ -168,12 +169,15 @@ int32_t phy_sniffer_start(uint32_t nOffsetUs)
     {
         //jesd_sniffer_orx_csu_init(); // test
         jesd_orx_timer_init();
-        //debug_write((DBG_DDR_IDX_DRV_BASE+64+7), 1); // 0x11c
+        
+        //debug_write((DBG_DDR_IDX_DRV_BASE+48), gJesdRxListPara[1][0].listAddr); // 0xC0
+	    //debug_write((DBG_DDR_IDX_DRV_BASE+49), gJesdRxListPara[1][0].listNodeNum); // 0xC4
     } 
 	set_jesd_rf_state(JESD_ANT_ORX, GPIO_ON);
 	set_jesd_rf_state(JESD_RF_ORX, GPIO_ON);
 	set_jesd_rf_state(JESD_TRANS_ORX, GPIO_ON);
 
+	debug_write((DBG_DDR_IDX_DRV_BASE+59), nOffsetUs); // 0xEC
     orx_para_ptr->orx_start_offset_us = nOffsetUs;
     if (0 != nOffsetUs)
 	{