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Merge branch 'dev_ck_v2.1_jesd' into 'dev_ck_v2.1'

Browse Source 
驱动入库v2.1

See merge request ucp/driver/ucp4008_platform_spu!3
This commit is contained in:
Xianfeng Du 2023-07-24 09:59:36 +00:00
commit e7be6ab607
14 changed files with 297 additions and 121 deletions
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18
public/ape_spu/driver/src/ape_mtimer.s.c
View File

@ -26,7 +26,6 @@ extern stStcTimerPara gStcTimerPara;
int32_t gApeCalFlag = 0;
int32_t gApeCalCnt = 0;
void ape_mtimer_int_init(void)
{
#ifdef DISTRIBUTED_BS
@ -157,6 +156,7 @@ void ape_slot_ctw_set(uint8_t nTmrId)
uint32_t lastTxStcCnt = 0;
uint32_t nowTxStcCnt = 0;
uint32_t apeSlotErrCnt = 0;
uint32_t apeSlotInterMax = 0;
int32_t mtimer_ape_slot_callback(uint8_t nTmrId)
{
uint32_t tmrBaseAddr = 0;
@ -236,17 +236,19 @@ uint32_t start = GET_STC_CNT();
}
#endif
gCellSfnPara[nTmrId].txSlotIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+84+(apeId<<1)), gCellSfnPara[nTmrId].txSlotIntCnt); // 0x150
#if 0 //def PALLADIUM_TEST
uint32_t irqAddr = DBG_DDR_IRQ_ADDR_BASE + apeId*DBG_DDR_IRQ_LEN + 0x98 + 4*(APC_CPRI_TMR_INTR0+MTMR_INT_APE0_SLOT+apeId);
debug_write((DBG_DDR_IDX_DRV_BASE+24+apeId), do_read_volatile(irqAddr));
#endif
debug_write((DBG_DDR_IDX_DRV_BASE+84+(apeId<<1)), gCellSfnPara[nTmrId].txSlotIntCnt); // 0x150
// write sm
do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intNum), APE_INT_TX_SLOT);
do_write(&(apeCoreIntInfo[APE_INT_TX_SLOT].intCnt), gCellSfnPara[nTmrId].txSlotIntCnt);
#if 0
#if 1
//debug_write(((DBG_DDR_IDX_DRV_BASE+448) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), gCellSfnPara[nTmrId].txSlotIntCnt); // 0x700
//debug_write(((DBG_DDR_IDX_DRV_BASE+512) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), get_tx_nr_slot(NR_SCS_30K)); // 0x800
nowTxStcCnt = GET_STC_CNT();
if (nowTxStcCnt > lastTxStcCnt)
if ((nowTxStcCnt > lastTxStcCnt) && (2 < gCellSfnPara[nTmrId].txSlotIntCnt))
{
uint32_t cost = nowTxStcCnt - lastTxStcCnt;
//debug_write(((DBG_DDR_IDX_DRV_BASE+576) + (gCellSfnPara[nTmrId].txSlotIntCnt&0x3F)), nowTxStcCnt); // 0x900
@ -255,7 +257,11 @@ uint32_t start = GET_STC_CNT();
{
apeSlotErrCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+92+(apeId<<1)), apeSlotErrCnt); // 0x170
debug_write((DBG_DDR_IDX_DRV_BASE+93+(apeId<<1)), cost); // 0x174
}
if (apeSlotInterMax < cost)
{
apeSlotInterMax = cost;
debug_write((DBG_DDR_IDX_DRV_BASE+93+(apeId<<1)), apeSlotInterMax); // 0x174
}
}
lastTxStcCnt = nowTxStcCnt;

59
public/common/driver/inc/ape_csu.h
View File

@ -232,35 +232,6 @@ typedef struct _tagCsuLinkDesc2L3D
*/
void ape_csu_init();
/*!
* @brief: 根据tag号，获取空闲的寄存器组和FIFO，寄存器组有8组（0~7），FIFO通道有4个（0~3）
* @author: xinxin.li
* @Date: 2023年3月15日
* @param: tag : [DMA Tag: 0~31，用户可用于分配DMA资源]
* @return: -1：没有可用的DMA资源
!=-1: bit0~7:寄存器组id（0~7），bit8~15:FIFO ID（0~3）
*/
int32_t get_free_reg_group(uint8_t tag);
/*!
* @brief: 获取空闲的DMA资源，获取到才退出
* @author: xinxin.li
* @Date: 2023年3月15日
* @param: 无
* @return: bit0~7:寄存器组id（0~7），bit8~15:FIFO ID（0~3），bit16~23:tag ID（0~31）
*/
uint32_t get_free_channel();
/*!
* @brief: 一维搬移到一维，如果目前没有可用的DMA资源，会一直等待，直至获取到可用资源才配置，配置完即退出，不会等待搬移完成
* @author: xinxin.li
* @Date: 2023年3月15日
* @param: addrSrc : [源地址 ]
* @param: addrDst : [目的地址 ]
* @param: dataLen : [搬移总字节数 ]
*/
uint32_t spu_csu_dma_1D_transfer(uint64_t addrSrc, uint64_t addrDst, uint32_t dataLen);
/*!
* @brief: 查看tag号对应的dma任务是否完成，未完成返回0，完成返回1
* 如果isWait==1，则等待该tag对应的任务完成，再返回，返回1
@ -406,5 +377,35 @@ uint32_t qounit_wait_complete();
*/
int16_t qounit_equal_wait_complete();
/*!
* @brief: 根据tag号，获取空闲的寄存器组和FIFO，寄存器组有8组（0~7），FIFO通道有4个（0~3）
* @author: xinxin.li
* @Date: 2023年3月15日
* @param: tag : [DMA Tag: 0~31，用户可用于分配DMA资源]
* @return: -1：没有可用的DMA资源
!=-1: bit0~7:寄存器组id（0~7），bit8~15:FIFO ID（0~3）
*/
int32_t get_free_reg_group(uint8_t tag);
/*!
* @brief: 获取空闲的DMA资源，获取到才退出
* @author: xinxin.li
* @Date: 2023年3月15日
* @param: 无
* @return: bit0~7:寄存器组id（0~7），bit8~15:FIFO ID（0~3），bit16~23:tag ID（0~31）
*/
uint32_t get_free_channel();
/*!
* @brief: 一维搬移到一维，如果目前没有可用的DMA资源，会一直等待，直至获取到可用资源才配置，配置完即退出，不会等待搬移完成
* @author: xinxin.li
* @Date: 2023年3月15日
* @param: addrSrc : [源地址 ]
* @param: addrDst : [目的地址 ]
* @param: dataLen : [搬移总字节数 ]
*/
uint32_t spu_csu_dma_1D_transfer(uint64_t addrSrc, uint64_t addrDst, uint32_t dataLen);
#endif

2
public/common/driver/inc/mtimer_com.h
View File

@ -3,7 +3,7 @@
#define APE_NUM (4) //4
#define FIBER_MIN_DELAY 2
#define FIBER_MIN_DELAY 2 // 10 //
#define INT_DELAY 4 // 6 // // us
#define EDMA_OFFSET 50 // 6 // 8 // 2 // us

6
public/common/driver/inc/phy_para.h
View File

@ -20,6 +20,8 @@
#define CPRI_ADVANCE_ADDR (0x0A4D7214)
#define CPRI_TDD_ADVANCE_ADDR (0x0A4D7218)
#define CTC_INT_TYPE_ADDR (0x0A4D721C)
#define ARM_SFN_VALID_ADDR (0x0A4D7220) // 0xAA not valid, 0x55 valid
#define ARM_SFN_NUM_ADDR (0x0A4D7224)
#define ARM_SFN_FLIP_ADDR (0x0A4D7228)
@ -29,9 +31,7 @@
#define ARM_SFN_NOTVALID_FLAG (0xAA)
#define CSU_STOP_CMD_ADDR (0x0A4D7230)
//#define CSU_ADVANCE_US_ADDR (0x0A4D7234)
#define CTC_INT_TYPE_ADDR (0x0A4D7234)
#define CSU_UL_HEADER_DATA_OFFSET (0x0A4D7234) // ul, the interval of frame header and frame data, ns as unit
#define CSU_RX_TD_SAMPLE (0x0A4D7238)
#define CSU_TX_ADVANCE_SAMPLE (0x0A4D723C)

125
public/common/driver/src/ape_csu.s.c
View File

@ -83,68 +83,6 @@ int32_t get_free_reg_group(uint8_t tag)
return ((fifoNum<<16) | regGroup); // [31:16]fifoNum(0~3), [15:0]reg group(0~7)
}
uint32_t get_free_channel()
{
while (1)
{
for (int tag = 0; tag < 32; tag++)
{
if (0 == (do_read_volatile(&APC_CSU_DMASTATUS) & (1<<tag)))
{
continue;
}
else
{
uint32_t temp = get_free_reg_group(tag);
if (-1 == temp)
{
continue;
}
else
{
uint8_t regGroup = temp & 0xFF;
uint8_t fifoNum = (temp>>16) & 0xFF;
uint32_t ret = regGroup | (fifoNum<<8) | (tag<<16);
return ret;
}
}
}
}
}
uint32_t spu_csu_dma_1D_transfer(uint64_t addrSrc, uint64_t addrDst, uint32_t dataLen)
{
uint8_t regGroup = 0;
uint8_t fifoNum = 0;
uint8_t tag = 0;
uint32_t temp = get_free_channel();
// printf("get free channle: 0x%x. \r\n", temp);
regGroup = temp & 0xFF;
fifoNum = (temp>>8) & 0xFF;
tag = (temp>>16)&0xFF;
uint8_t offset_w = regGroup << 4;
// src reg
do_write(((uint32_t*)(&APC_CSU_DMAADDRL0) + offset_w), addrSrc & 0xFFFFFFFF);
do_write(((uint32_t*)(&APC_CSU_DMAADDRH0) + offset_w), (uint32_t)(addrSrc >> 32));
do_write(((uint32_t*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), ((0xF<<28) | (0xE<<24) | dataLen)); // DM,CGran=1,Gran=6;size=0xF
// dst reg
do_write(((uint32_t*)(&APC_CSU_DMAADDRL1) + offset_w), addrDst & 0xFFFFFFFF);
do_write(((uint32_t*)(&APC_CSU_DMAADDRH1) + offset_w), (uint32_t)(addrDst >> 32));
do_write(((uint32_t*)(&APC_CSU_DMASIZEGRANALLNUM1) + offset_w), ((0xF<<28) | (0xE<<24) | dataLen));
stCsuDmaCmdL dmaCmdL;
*(uint32_t*)(&dmaCmdL) = 0;
dmaCmdL.dmaType = 1;
dmaCmdL.idSrc = 0 + (regGroup<<1);
dmaCmdL.idDst = 1 + (regGroup<<1);
dmaCmdL.dmaTag = tag;
do_write(((stCsuDmaCmdL*)(&APC_CSU_CMDFIFO0) + fifoNum), (*(uint32_t*)(&dmaCmdL)));
return tag;
}
/*!
* @brief: 查看tag号对应的dma任务是否完成，未完成返回0，完成返回1
* 如果isWait==1，则等待该tag对应的任务完成，再返回，返回1
@ -833,3 +771,66 @@ int16_t qounit_equal_wait_complete()
return (data & 0xffff);
}
}
uint32_t get_free_channel()
{
while (1)
{
for (int tag = 0; tag < 32; tag++)
{
if (0 == (do_read_volatile(&APC_CSU_DMASTATUS) & (1<<tag)))
{
continue;
}
else
{
uint32_t temp = get_free_reg_group(tag);
if (-1 == temp)
{
continue;
}
else
{
uint8_t regGroup = temp & 0xFF;
uint8_t fifoNum = (temp>>16) & 0xFF;
uint32_t ret = regGroup | (fifoNum<<8) | (tag<<16);
return ret;
}
}
}
}
}
uint32_t spu_csu_dma_1D_transfer(uint64_t addrSrc, uint64_t addrDst, uint32_t dataLen)
{
uint8_t regGroup = 0;
uint8_t fifoNum = 0;
uint8_t tag = 0;
uint32_t temp = get_free_channel();
// printf("get free channle: 0x%x. \r\n", temp);
regGroup = temp & 0xFF;
fifoNum = (temp>>8) & 0xFF;
tag = (temp>>16)&0xFF;
uint8_t offset_w = regGroup << 4;
// src reg
do_write(((uint32_t*)(&APC_CSU_DMAADDRL0) + offset_w), addrSrc & 0xFFFFFFFF);
do_write(((uint32_t*)(&APC_CSU_DMAADDRH0) + offset_w), (uint32_t)(addrSrc >> 32));
do_write(((uint32_t*)(&APC_CSU_DMASIZEGRANALLNUM0) + offset_w), ((0xF<<28) | (0xE<<24) | dataLen)); // DM,CGran=1,Gran=6;size=0xF
// dst reg
do_write(((uint32_t*)(&APC_CSU_DMAADDRL1) + offset_w), addrDst & 0xFFFFFFFF);
do_write(((uint32_t*)(&APC_CSU_DMAADDRH1) + offset_w), (uint32_t)(addrDst >> 32));
do_write(((uint32_t*)(&APC_CSU_DMASIZEGRANALLNUM1) + offset_w), ((0xF<<28) | (0xE<<24) | dataLen));
stCsuDmaCmdL dmaCmdL;
*(uint32_t*)(&dmaCmdL) = 0;
dmaCmdL.dmaType = 1;
dmaCmdL.idSrc = 0 + (regGroup<<1);
dmaCmdL.idDst = 1 + (regGroup<<1);
dmaCmdL.dmaTag = tag;
do_write(((stCsuDmaCmdL*)(&APC_CSU_CMDFIFO0) + fifoNum), (*(uint32_t*)(&dmaCmdL)));
return tag;
}

12
public/ecs_rfm_spu1/driver/inc/cpri_csu_api.h
View File

@ -42,6 +42,14 @@ typedef enum _tagCpriDummyFlag
CPRI_DUMMY_USE_DDR_ADDR =1
}numCpriDummyFlag;
typedef enum _tagCpriCsuLatchFlushID
{
CPRI_CSU_TX0_LATCH_FLUSH_ID = 0,
CPRI_CSU_RX0_LATCH_FLUSH_ID,
CPRI_CSU_TX1_LATCH_FLUSH_ID,
CPRI_CSU_RX1_LATCH_FLUSH_ID
}numCpriCsuLatchFlushID;
typedef struct
{
uint32_t cmd32l;
@ -156,6 +164,10 @@ extern void UCP_API_CPRI_CSU_Get_CmdFIFO(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpr
void UCP_API_CPRI_CSU_START(stCpriCsuCmdFifoInfo tx_cmdfifo, stCpriCsuCmdFifoInfo rx_cmdfifo);
void UCP_API_CPRI_CSU_STOP();
void UCP_API_CPRI_CSU_Flush_Latch(uint8_t latch_id);
void UCP_API_CPRI_CSU_CH_Enable(uint32_t axc_id_num, uint32_t latch_num);
void UCP_API_CPRI_CSU_CH_Disable(uint32_t axc_id_num, uint32_t latch_num);

1
public/ecs_rfm_spu1/driver/inc/jesd_csu_nr_7ds2u.h
View File

@ -46,6 +46,7 @@
#define JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
int32_t jesd_csu_init_nr_7ds2u();
int32_t jesd_csu_init_nr_7d2u_slot0();
int32_t jesd_csu_init_nr_7ds2u_iomode();
int32_t jesd_csu_init_nr_7ds2u_8t8r();
int32_t jesd_csu_init_nr_7ds2u_4t4r_98();

3
public/ecs_rfm_spu1/driver/inc/jesd_timer.h
View File

@ -6,13 +6,12 @@
#include "dw_apb_gpio.h"
#define JESD_TXRX_CHANGE_GAP 13
#define JESD_RF_ON_GAP 4
#define JESD_RF_ON_GAP 8
#define JESD_RF_OFF_GAP 2
#define JESD_TX_ADVANCE_SAMPLE 0 // 500 // sample
#define JESD_RX_ADVANCE_SAMPLE 1600 // sample
#define JESD_RRU_TD 0 // 480 // sample
typedef enum _tagJesdSndRcvMode
{
JESD_IO_CTRL = 0,

22
public/ecs_rfm_spu1/driver/src/cpri_csu_api.s.c
View File

@ -914,6 +914,28 @@ void UCP_API_CPRI_CSU_START(stCpriCsuCmdFifoInfo tx_cmdfifo, stCpriCsuCmdFifoInf
}
void UCP_API_CPRI_CSU_STOP()
{
do_write(CSU_STOP_CMD_ADDR, 1); // csu stop
//delay_us(5000); // delay 5ms, wait fifo empty
//do_write(&JECS_CSU_CPRITX0FLUSH, 1); // flush latch
//do_write(&JECS_CSU_CPRITX1FLUSH, 1);
//do_write(&JECS_CSU_CPRIRX0FLUSH, 1);
//do_write(&JECS_CSU_CPRIRX1FLUSH, 1);
// wait fifo empty
while ((0 != do_read(&JECS_CSU_CMDFIFO0_NUM)) || (0 != do_read(&JECS_CSU_CMDFIFO1_NUM)) || (0 != do_read(&JECS_CSU_CMDFIFO2_NUM)) || (0 != do_read(&JECS_CSU_CMDFIFO3_NUM)));
}
void UCP_API_CPRI_CSU_Flush_Latch(uint8_t latch_id)
{
uint32_t addr = (uint32_t)(&JECS_CSU_CPRITX0FLUSH) + 0x200 * latch_id;
do_write(addr, 1); // flush latch
__ucps2_synch(0);
//ucp_nop(5);
do_write(addr, 0); // flush latch
__ucps2_synch(0);
}
void UCP_API_CPRI_CSU_CH_Enable(uint32_t axc_id_num, uint32_t latch_num)
{
UCP_API_CPRI_CSU_RXAxcData_ChannelCtrl(1, latch_num);

4
public/ecs_rfm_spu1/driver/src/cpri_delay.s.c
View File

@ -12,7 +12,7 @@
//extern stCpriPara cpriPara;
//stCpriDelayMeasure cpriDelay;
stCpriLinkStatus cpriLinkStatus;
uint32_t gCpriDelayOamSetFlag = 0;
// 告警标志
//uint32_t gCpriAlarmFlag = CPRI_NO_ALARM; // cpri告警标志，后续应该上报给OM
//uint32_t gCpriAlarmMeasureCnt = 0;
@ -412,6 +412,8 @@ stCpriSetDelayRsp* set_cpri_link_delay(stCpriSetLinkDelay* pCpriSetDelay)
debug_write((DBG_DDR_IDX_DRV_BASE+278), pCpriDelay->cpriRxOffset); // 0x458
gCpriSetDelayRep.u8result = 1;
gCpriDelayOamSetFlag = 1;
return &gCpriSetDelayRep;
}

7
public/ecs_rfm_spu1/driver/src/cpri_test_mode.s.c
View File

@ -2,6 +2,7 @@
#include "typedef.h"
#include "ucp_utility.h"
#include "cpri_csu_nr_7ds2u.h"
#include "mtimer_drv.h"
#include "cpri_timer.h"
#include "ape_csu.h"
#include "mem_sections.h"
@ -26,6 +27,7 @@ extern stCpriCsuCmdFifoInfo txCmdFifo;
extern stCpriCsuCmdFifoInfo rxCmdFifo;
extern volatile uint32_t CsuStopFlag ;
extern uint32_t gCpriCsuCmdCnt;
//extern stCpriIntStat gCpriIntStatus;
uint32_t NormalToTest = 0;
uint32_t TestToNormal = 0;
@ -647,9 +649,14 @@ void check_cpri(void)
{
if((do_read_volatile(&CPRI_FRAME_RX_STAT))!= 0x1e)//失步
{
//gCpriIntStatus.cpriSyncFlag = 0; // cpri sync flag = 0
//UCP_API_CPRI_CSU_STOP();
jecspma_recrx_reset();
ResetSyncCnt0++;
debug_write((DBG_DDR_IDX_CPRI_BASE+1027), ResetSyncCnt0);
//set_cpri_tmr_ctrl();
}
}

84
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -59,6 +59,7 @@ uint32_t gCpriAlarmSfnCnt = 0;
uint32_t gCpriTestMode = 0;
extern uint32_t* gCpriCsuStopCmd;
extern uint32_t gCpriDelayOamSetFlag;
extern void rfm1_fapi_callback();
@ -124,11 +125,19 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
stCpriDelayMeasure* pCpriDelay = pEcsDmLocalMgt->pCpriDelay;
#endif
uint32_t tempOffset;
if (0 == gCpriDelayOamSetFlag)
{
pCpriDelay->cpriTxOffset = do_read_volatile(CSU_TX_ADVANCE_SAMPLE);
pCpriDelay->cpriRxOffset = do_read_volatile(CSU_RX_TD_SAMPLE); // ns
__ucps2_synch(0);
}
tempOffset = (uint32_t)(((float)pCpriDelay->cpriTxOffset/1000)+0.5); // ns -> us
pCpriDelay->cpri10msOffset = (tempOffset < FIBER_MIN_DELAY) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset+INT_DELAY);
pCpriDelay->cpri10msOffset = (tempOffset < (FIBER_MIN_DELAY+INT_DELAY)) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset);
tempOffset = (uint32_t)(((float)pCpriDelay->cpriRxOffset/1000)+0.5); // ns -> us
pCpriDelay->cpri10msRxOffset = (tempOffset < FIBER_MIN_DELAY) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset+INT_DELAY);
pCpriDelay->cpri10msRxOffset = (tempOffset < (FIBER_MIN_DELAY+INT_DELAY)) ? (FIBER_MIN_DELAY+INT_DELAY) : (tempOffset);
pCpriDelay->cpriTddOffset = pCpriDelay->cpri10msOffset + EDMA_OFFSET;
@ -143,7 +152,8 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
#endif
set_cpri_sfn_offset();
//set_cpri_sfn_offset();
set_cpri_tx_rfp();
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag);
@ -518,6 +528,7 @@ debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
debug_write((DBG_DDR_IDX_DRV_BASE+206), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0x338
debug_write((DBG_DDR_IDX_DRV_BASE+207), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0x33C
}
rfm1_set_trigger_high();
}
if (tEventFlag & (1<<MTMR_10ms_OFFSET)) // 10ms offset int
{
@ -556,7 +567,7 @@ void isr_cpri_tdd_offset(void)
uint32_t tEventFlag = 0;
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
stMtimerSfnCal* pMtimerCal = &gMtimerSfnCalPara[MTIMER_CPRI_ID];
//stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
stMtimerPhyPara* pMtimerSfn = &gMtimerSfnNum[MTIMER_CPRI_ID];
uint32_t tmrBaseAddr = mtimer_get_baseaddr(MTIMER_CPRI_ID);
tmrIntcFlag = do_read_volatile(tmrBaseAddr + MTMR_INTC_REG); // &CPRI_TMR_INTC_REG);
@ -591,13 +602,41 @@ uint32_t start = GET_STC_CNT();
#endif
//#ifdef CPRI_TIMING_7D2U_TEST
#ifdef DISTRIBUTED_BS
if (32 > pMtimerInt->tddOffsetIntCnt)
{
debug_write((DBG_DDR_IDX_DRV_BASE+896+(pMtimerInt->tddOffsetIntCnt<<2)), pMtimerSfn->txSlotNum); // 0xe00
debug_write((DBG_DDR_IDX_DRV_BASE+897+(pMtimerInt->tddOffsetIntCnt<<2)), pMtimerSfn->rxSlotNum); // 0xe04
debug_write((DBG_DDR_IDX_DRV_BASE+898+(pMtimerInt->tddOffsetIntCnt<<2)), pMtimerInt->txSlotIntCnt); // 0xe08
debug_write((DBG_DDR_IDX_DRV_BASE+899+(pMtimerInt->tddOffsetIntCnt<<2)), tEventFlag); // 0xe0c
}
debug_write((DBG_DDR_IDX_DRV_BASE+394), pMtimerCal->sfnCalFinished); // 0x628
debug_write((DBG_DDR_IDX_DRV_BASE+395), gCpriIntStatus.cpriSyncFlag); // 0x62c
if ((1 == pMtimerCal->sfnCalFinished) && (1 == gCpriIntStatus.cpriSyncFlag))
{
gCpriIntStatus.cpriSyncFlag = 0;
UCP_API_CPRI_CSU_CH_Disable(UCP_API_CPRI_CSU_Get_AxcIdNum(), UCP_API_CPRI_CSU_Get_LatchNum());
do_write(CSU_STOP_CMD_ADDR, 0);
pMtimerInt->csuEnCnt = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+395), GET_STC_CNT()); // 0x62c
// wait fifo num empty
if ((0 == do_read(&JECS_CSU_CMDFIFO0_NUM)) && (0 == do_read(&JECS_CSU_CMDFIFO1_NUM)) && (0 == do_read(&JECS_CSU_CMDFIFO2_NUM)) && (0 == do_read(&JECS_CSU_CMDFIFO3_NUM)))
{
#if 0
do_write(&JECS_CSU_CPRITX0FLUSH, 1); // flush latch
//do_write(&JECS_CSU_CPRITX1FLUSH, 1);
do_write(&JECS_CSU_CPRIRX0FLUSH, 1);
//do_write(&JECS_CSU_CPRIRX1FLUSH, 1);
ucp_nop(6);
do_write(&JECS_CSU_CPRITX0FLUSH, 0); // flush latch
//do_write(&JECS_CSU_CPRITX1FLUSH, 0);
do_write(&JECS_CSU_CPRIRX0FLUSH, 0);
//do_write(&JECS_CSU_CPRIRX1FLUSH, 0);
#else
UCP_API_CPRI_CSU_Flush_Latch(CPRI_CSU_TX0_LATCH_FLUSH_ID); // flush csu latch
UCP_API_CPRI_CSU_Flush_Latch(CPRI_CSU_RX0_LATCH_FLUSH_ID);
#endif
gCpriIntStatus.cpriSyncFlag = 0;
UCP_API_CPRI_CSU_CH_Disable(UCP_API_CPRI_CSU_Get_AxcIdNum(), UCP_API_CPRI_CSU_Get_LatchNum());
do_write(CSU_STOP_CMD_ADDR, 0);
pMtimerInt->csuEnCnt = 0;
debug_write((DBG_DDR_IDX_DRV_BASE+396), GET_STC_CNT()); // 0x630
debug_write((DBG_DDR_IDX_DRV_BASE+397), tEventFlag); // 0x634
}
}
if (((0 == do_read_volatile(CSU_STOP_CMD_ADDR)) && (0 == pMtimerInt->csuEnCnt) && (tEventFlag & (1<<MTMR_TDD_OFFSET_10000))) || (0 != pMtimerInt->csuEnCnt))
{
@ -608,10 +647,14 @@ uint32_t start = GET_STC_CNT();
if ((1 == pMtimerInt->csuEnCnt) && (tEventFlag & (BIT25)))
{
UCP_API_CPRI_CSU_CH_Enable(UCP_API_CPRI_CSU_Get_AxcIdNum(), UCP_API_CPRI_CSU_Get_LatchNum());
debug_write((DBG_DDR_IDX_DRV_BASE+396), GET_STC_CNT()); // 0x630
debug_write((DBG_DDR_IDX_DRV_BASE+398), GET_STC_CNT()); // 0x638
debug_write((DBG_DDR_IDX_DRV_BASE+192), UCP_API_CPRI_GetTxHfnCnt()); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), UCP_API_CPRI_GetRxHfnCnt()); // 0x304
debug_write((DBG_DDR_IDX_DRV_BASE+194), pMtimerInt->tddOffsetIntCnt); // 0x308
debug_write((DBG_DDR_IDX_DRV_BASE+196), pMtimerSfn->txSlotNum); // 0x310
debug_write((DBG_DDR_IDX_DRV_BASE+197), pMtimerSfn->txSfnNum); // 0x310
debug_write((DBG_DDR_IDX_DRV_BASE+198), pMtimerSfn->rxSlotNum); // 0x318
debug_write((DBG_DDR_IDX_DRV_BASE+199), pMtimerSfn->rxSfnNum); // 0x318
}
}
#if 1
@ -678,6 +721,8 @@ debug_write((DBG_DDR_IDX_DRV_BASE+289), (GET_STC_CNT()-start)); // 0x484
}
}
uint32_t gCpriCsuFifoErrCnt = 0;
uint32_t gCpriCsuFifoErrFlag = 0;
void isr_cpri_slot_offset(void)
{
uint32_t tmrIntcFlag = 0;
@ -737,13 +782,24 @@ uint32_t start = GET_STC_CNT();
// test for trigger
if (0 == pMtimerSfn->txSlotNum)
{
rfm1_set_trigger_high();
//rfm1_set_trigger_high();
}
else if ((pMtimerSfn->slotMaxNum >> 1) == pMtimerSfn->txSlotNum)
{
rfm1_set_trigger_low();
}
__ucps2_synch(0);
#if 0
uint32_t readFlag = do_read_volatile(0x0A4D7248);
__ucps2_synch(0);
if ((1 == readFlag) && (pMtimerSfn->txSlotNum & 0x1))
{
// 0xB4800000, 0x1EF00
ape_csu_dma_1D_G2L_ch0ch1_transfer(0xB4800000, 0x60000000, 0x1EF00, 0, 0);
do_write(0x0A4D7248, 0);
}
#endif
#ifdef PALLADIUM_TEST
if (8 > pMtimerInt->txSlotIntCnt)
@ -779,7 +835,7 @@ debug_write((DBG_DDR_IDX_DRV_BASE+290), (GET_STC_CNT()-start)); // 0x488
debug_write(((DBG_DDR_IDX_DRV_BASE+9728) + (gCpriTimerPara.txSlotIntCnt&0x1FF)), (nowTxSlotStcCnt-lastTxSlotStcCnt)); // 0x9800
lastTxSlotStcCnt = nowTxSlotStcCnt;
#endif
#if 0
#if 1
nowTxSlotCnt = GET_STC_CNT();
if ((nowTxSlotCnt > lastTxSlotCnt) && (2 < pMtimerInt->txSlotIntCnt))
{
@ -840,7 +896,7 @@ debug_write((DBG_DDR_IDX_DRV_BASE+291), (GET_STC_CNT()-start)); // 0x48c
do_write(tFlagAddr, (1<<MTMR_LTE_FAPI)); // clear int flag
pMtimerInt->lteFapiIntCnt++;
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+64+2), pMtimerInt->lteFapiIntCnt); // 0x108
debug_write((DBG_DDR_IDX_DRV_BASE+64+14), pMtimerInt->lteFapiIntCnt); // 0x138
debug_write((DBG_DDR_IDX_DRV_BASE+672+(pMtimerInt->lteFapiIntCnt&0x1f)), (GET_STC_CNT()-pMtimerSfn->txSlotTiming)); //get_tx_nr_slot(1)); // 0xb7e06a80
#endif
rfm1_fapi_callback();

62
public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c
View File

@ -130,6 +130,68 @@ int32_t jesd_csu_init_nr_7d2u()
return 0;
}
int32_t jesd_csu_init_nr_7d2u_slot0()
{
jesd_csu_init(JESD_NR7DS2U_ANT_NUM, JESD_NR7DS2U_MARGIN);
stJesdCsuNodePara txCsuNode[JESD_NR7DS2U_TX_NODENUM];
stJesdCsuNodePara rxCsuNode[JESD_NR7DS2U_RX_NODENUM];
//tx的链表地址
uint32_t txListAddr = JESD_TX_LIST_ADDR; // 0x721F000; //
//rx的链表地址
uint32_t rxListAddr = JESD_RX_LIST_ADDR; // 0x721F600; //
int32_t i = 0;
// tx, slot0~6
for (i = 0; i < 14; i++)
{
if (0 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR;
txCsuNode[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2);
txCsuNode[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4);
}
else if (1 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR;
txCsuNode[i].yStep = ((7*SHORTCP_SAM_CNT)<<2);
txCsuNode[i].allNum = ((7*SHORTCP_SAM_CNT)<<4);
}
else if (2 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2);
txCsuNode[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4);
}
else if (3 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR;
txCsuNode[i].yStep = ((7*SHORTCP_SAM_CNT)<<2);
txCsuNode[i].allNum = ((7*SHORTCP_SAM_CNT)<<4);
}
}
// rx list nodes
// slot7, slots
rxCsuNode[0].dataAddr = JESD_NR7DS2U_RX_SLOTS_DATA_ADDR;
rxCsuNode[0].yStep = (SHORTCP_SAM_CNT*4)<<2;
rxCsuNode[0].allNum = (SHORTCP_SAM_CNT*4)<<4;
// slot8
rxCsuNode[1].dataAddr = JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode[1].yStep = (LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<2;
rxCsuNode[1].allNum = (LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4;
// slot9
rxCsuNode[2].dataAddr = JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode[2].yStep = (LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<2;
rxCsuNode[2].allNum = (LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4;
jesd_csu_tx_list_init(txListAddr, 2, txCsuNode);
jesd_csu_tx_dmaReg_Cfg(JESD_CSU_CH0, txListAddr, 2);
jesd_csu_rx_list_init(rxListAddr, JESD_NR7DS2U_RX_NODENUM, rxCsuNode);
jesd_csu_rx_dmaReg_Cfg(JESD_CSU_CH0, rxListAddr, JESD_NR7DS2U_RX_NODENUM);
return 0;
}
int32_t jesd_csu_init_nr_7ds2u_iomode()
{
jesd_csu_init(JESD_NR7DS2U_ANT_NUM, JESD_NR7DS2U_MARGIN);

13
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -58,7 +58,7 @@ void jesd_init()
do_write(CSU_RX_TD_SAMPLE, JESD_RRU_TD);
do_write(CSU_TX_ADVANCE_SAMPLE, gCsuTxAdvanceSam);
while (1 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))) // wait jesd serdes clk init finished
while (1 > (do_read_volatile(SERDES_INIT_FLAG_ADDR))) // wait jesd serdes clk init finished
{
ucp_nop(1);
}
@ -143,8 +143,8 @@ int32_t jesd_timer_init(int32_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
if (MTIMER_JESD_RX0_ID == nTmrId)
{
jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
mtimer_clear_all_event(MTIMER_JESD_TX0_ID);
set_jesd_tmr_period(MTIMER_JESD_TX0_ID);
}
@ -182,6 +182,13 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
do_write_short((&(phyPara[scsId].mtimerId)), nTmrId);
__ucps2_synch(0);
while (2 != (do_read_volatile(SERDES_INIT_FLAG_ADDR))) // wait jesd serdes clk init finished
{
ucp_nop(1);
}
jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
set_jesd_tmr_period(nTmrId); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
if (MTIMER_JESD_RX0_ID == nTmrId)
{