1.add NR FDD 15K testcase80~83;2.add 25g testcase72;3.modify cpri map typedef

public/common/driver/inc/phy_para.h

@@ -243,9 +243,9 @@ typedef struct _tagSfnPara
 
 typedef enum _tagCpriMapType
 {
-	NR4T4R_7DS2U = 0,
+	OTIC_MAP_FIGURE10 = 0, //option8,双模，4T4R NR小区 + 2T2R LTE小区
-	NR4T4R_LTE2T2R_FDD,
+	OTIC_MAP_FIGURE12,     //option8,NR 4T4R单小区	
-	NR2_4T4R_7DS2U
+	OTIC_MAP_FIGURE16      //option10,NR 4T4R的2小区 
 }CpriMapType;
 
 typedef enum _tagCpriMode

public/ecs_rfm_spu1/driver/src/HeaderRam.s.c

@@ -26,7 +26,7 @@ void Cpri_Header_Tx(void)
 
 	uint32_t j= 0;
 	uint32_t  CurrentHfnCnt =0;
-	if(NR4T4R_7DS2U == gVendorFlag)
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
 	{
 	CurrentHfnCnt = UCP_API_CPRI_GetTxHfnCnt();
 

public/ecs_rfm_spu1/driver/src/cpri_driver.s.c

@@ -23,6 +23,7 @@
 //10    option10    24330.24Mbit/s     64B/66B
 extern DDR0 uint32_t pma_fw[16384*2];
 //extern volatile int32_t gCpriSyncIntCnt;
+extern volatile uint32_t gVendorFlag;
 
 uint32_t PLLSEL_temp = 0;
 //切换xtal_clk时钟
@@ -2304,7 +2305,7 @@ void jecspma_recrx_eq()
 	uint32_t j=0;
 	init_jecspma_recrx();
 	//for(uint32_t i = 0;i<10 ; i++)
-//	while(1)
+	//while(1)
 	{
 		i++;
 		//rx adapt eq
@@ -2673,28 +2674,24 @@ void config_cpri_map_directed(uint32_t option,uint32_t MappingMode)
 
 	if(8 == option)
 	{
-		if(NR4T4R_7DS2U == MappingMode)
+		if(OTIC_MAP_FIGURE12 == MappingMode)
 		{
-			//ID_SIZE[16] = {1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0};
 			memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64);
 		}
-		else if(NR4T4R_LTE2T2R_FDD == MappingMode)
+		else if(OTIC_MAP_FIGURE10 == MappingMode)
 		{
 			memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[1], 64);
-		  // ID_SIZE[16] = {1,1,8,8,8,8,2,2,1,0,0,0,0,0,0,0};
 		}	
 	}
 	else if(10 == option)
 	{
-		if(NR2_4T4R_7DS2U == MappingMode)
+		if(OTIC_MAP_FIGURE16 == MappingMode)
 		{
 			memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[2], 64);
-		//	ID_SIZE[16] = {1,1,8,8,8,8,8,8,8,8,1,0,0,0,0,0};
 		}
 	}
 	else
 	{	
-		//ID_SIZE[16] = {1,8,8,8,8,1,0,0,0,0,0,0,0,0,0,0};//默认NR4T4R_7DS2U  option8
 		memcpy_ucp_sm2dm(ID_SIZE, ID_SIZE_buf[0], 64);
 	}
 
@@ -2846,7 +2843,7 @@ void config_cpri_map_directed(uint32_t option,uint32_t MappingMode)
 
 	if(8 == option)
 	{
-		if(NR4T4R_7DS2U == MappingMode)//#ifdef CPRI_TIMING_7D2U_TEST
+		if(OTIC_MAP_FIGURE12 == MappingMode)//#ifdef CPRI_TIMING_7D2U_TEST
    		{
    			//map tx cfg
 		 	for(addr = 0; addr<0x400;addr = addr +4)
@@ -2920,7 +2917,7 @@ void config_cpri_map_directed(uint32_t option,uint32_t MappingMode)
 				}
 		  }
    		}
-		if(NR4T4R_LTE2T2R_FDD == MappingMode)	
+		if(OTIC_MAP_FIGURE10 == MappingMode)	
 		{
 			//map tx cfg
 			for(addr = 0; addr<0x400;addr = addr +4)
@@ -3019,7 +3016,7 @@ void config_cpri_map_directed(uint32_t option,uint32_t MappingMode)
 	
 	if(10 == option)
 	{
-		if(NR2_4T4R_7DS2U == MappingMode)
+		if(OTIC_MAP_FIGURE16 == MappingMode)
 		{
 		 	//map tx cfg
 			for(addr = 0; addr<0x400;addr = addr +4)
@@ -3573,5 +3570,23 @@ uint32_t UCP_API_CPRI_GetRxHfnCnt()
 
 }
 
+void HeaderTxRam_init(uint32_t vendor)
+{
+	uint32_t i,j;
+	HeaderRam_ins_disable();
+	for(i=0;i<64;i++)//Ns
+	{
+		for(j=0;j<4;j++)//
+		{
+			HeaderRam_Tx(i+64*j,0,0,0);//vendor
+			HeaderRam_Tx(i+64*j,1,0,0);//vendor
+			HeaderRam_Tx(i+64*j,2,0,0);//vendor
+			HeaderRam_Tx(i+64*j,3,0,0);//vendor
+		}
+	}
+	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
+	__ucps2_synch(f_SM);
+	do_write(&gVendorFlag,vendor);
+}
 
 

public/ecs_rfm_spu1/driver/src/hw_cpri.s.c

@@ -423,23 +423,5 @@ void isr_gmac_int(void)
 	}
 }
 
-void HeaderTxRam_init(uint32_t vendor)
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-	__ucps2_synch(f_SM);
-	do_write(&gVendorFlag,vendor);
-}
 
 

public/ecs_rfm_spu1/top/src/main.s.c

@@ -99,6 +99,12 @@ int32_t main(int32_t argc, char* argv[])
 
     while (1)
     {
+	 	if (PROTOCOL_CPRI == get_protocol_sel())
+        {
+            check_cpri();
+
+            check_10ms_offset();
+        }
 #ifdef TEST_ENABLE
         do_write(CSU_TX_ADVANCE_SAMPLE, 10000);     // 10us
         do_write(CSU_RX_TD_SAMPLE, 10000);
@@ -108,13 +114,6 @@ int32_t main(int32_t argc, char* argv[])
 
         phy_queue_polling();
 
-        if (PROTOCOL_CPRI == get_protocol_sel())
-        {
-            check_cpri();
-
-            check_10ms_offset();
-        }
-
         spu_log_server_proc();
         spu_shell_task();
 #ifdef DDR_MONITOR

public/ecs_rfm_spu1/top/src/phy_init.s.c

@@ -31,7 +31,7 @@ uint8_t gu8_send_del_task_cnt = 0;
 int32_t phy_fh_drv_init()
 {
 #ifdef DISTRIBUTED_BS
-    cpri_init(CPRI_OPTION_8, NR4T4R_7DS2U);
+    cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
 #endif
 #ifdef ECPRI_DISTRIBUTED_BS
     ecpri_init(ECPRI_OPTION_10G);

public/test/testbench_fh/inc/cpri_test.h

@@ -33,7 +33,6 @@ void Axc_data_init();
 void Get_Cpri_OptionId();
 void HeaderTxRam_data_init();
 void HeaderTxRam_init();
-void Cpri_Header_test(void);
 
 void Cpri_Header_Rx(void);
 void cpri_test_init(void);

public/test/testcase_fh/case21/src/rfm_test_case21.s.c

@@ -30,7 +30,7 @@ int32_t fh_data_init(void)
 int32_t fh_drv_init()
 {
 #ifdef DISTRIBUTED_BS
-	cpri_init(CPRI_OPTION_8, NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
 #endif
 #ifdef ECPRI_DISTRIBUTED_BS
 	ecpri_init(ECPRI_OPTION_10G);

public/test/testcase_fh/case22/src/rfm_test_case22.s.c

@@ -29,7 +29,7 @@ int32_t fh_data_init(void)
 int32_t fh_drv_init()
 {
 #ifdef DISTRIBUTED_BS
-	cpri_init(CPRI_OPTION_8, NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
 #endif
 #ifdef ECPRI_DISTRIBUTED_BS
 	ecpri_init(ECPRI_OPTION_10G);

public/test/testcase_fh/case30/src/cpri_test_case30.s.c

@@ -55,6 +55,48 @@ uint32_t cpri_AxC_test_cnt1 =0;
 #define ID4_SIZE      8
 #define ID5_SIZE      1
 
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	stCpriCsuCmdFifoInfo		txTestCmdFifo;
+	stCpriCsuCmdFifoInfo		rxTestCmdFifo;
+	
+	cpri_csu_axc_init_nr_7ds2u(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
+	cpri_csu_axcctrl_init_timing();
+	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
+
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
 #if 1
 void Axc_data_init()
 
@@ -152,31 +194,11 @@ void HeaderTxRam_data_init()
 #endif
 }
 
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	//HeaderRam_ins_enable();
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
 uint32_t CtrlAxCDataErrorCnt= 0;
 uint32_t CtrlAxCDataCheckCnt= 0;
 uint32_t CtrlAxCDataCheckCycle= 0;
-void AxC_data_check(uint32_t times)
+void fh_data_check(uint32_t times)
 {
 	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
 #if 1	
@@ -256,522 +278,13 @@ void Cpri_data_init()
 
 }
 
-void cpri_test_init()
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
 }
 
-
-#if 0
-void Cpri_AxC_test(uint32_t Ping_Pong_Flag,uint32_t times)
-{
-
-   uint32_t i=0;
-   uint32_t j=0;
-
-   uint32_t test_axc_error0 =0;
-   uint32_t test_axc_error1 =0;
-	
-	//uint32_t memcpy_len = 32*1024;
-	uint32_t memcpy_len = 2*256*75;//ID0前75帧数据;
-	uint32_t mem_cycle = ID_NUM*ID_DATA_STEP/memcpy_len;
-
-	
-	//uint32_t memcpy_len = 512*1024;
-	//uint32_t mem_cycle = 14;
-
-	if(Ping_Pong_Flag == 0)
-	{
-
-		/**************test ping addr*************/
-		uint32_t startTick0 = GET_STC_CNT();
-
-		#if 0	
-
-		uint32_t CSU_Rx_AxC_Data =0;
-  		uint32_t CSU_Tx_AxC_Data =0;
-		uint32_t cycle = ID_NUM*ID_DATA_STEP/4;
-		for(i=0;i<cycle;i=i+1)
-		{		
-			CSU_Rx_AxC_Data = do_read((uint32_t *)(CSU_RX_AXC_ADDR + i*4));
-			CSU_Tx_AxC_Data = do_read((uint32_t *)(CSU_TX_AXC_ADDR + i*4));
-			if((CSU_Rx_AxC_Data ^ CSU_Tx_AxC_Data) !=0)
-			{
-			  test_axc_error0++;
-			}
-		}
-		#endif
-
-		#if 0
-		for(i=0;i<mem_cycle;i=i+1)
-		{
-			memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			for(j=0;j<(memcpy_len>>2);j=j+1)
-			{
-				if((pSrcData[j]  ^ pSrcData[(memcpy_len>>2) + j] ) !=0)
-				{
-				  test_axc_error0++;
-				}
-			}
-		}
-		#endif
-
-		 #if 0
-		 {
-			 memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR + (mem_cycle -1)*memcpy_len), memcpy_len);
-			 memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR +  (mem_cycle -1)*memcpy_len), memcpy_len);
-			 for(j=0;j<(memcpy_len>>2);j=j+1)
-			 {
-				 if((pSrcData[j]  ^ pSrcData[(memcpy_len>>2) + j] ) !=0)
-				 {
-				   test_axc_error0++;
-				 }
-			 }
-		 }
-		#endif
-
-		
-		for(i=0;i<mem_cycle;i=i+1)
-		{
-			memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			#if 0
-
-			if ((memcmp((void*)pSrcData,(void*)(pSrcData + memcpy_len),memcpy_len)) != 0)
-			{
-			 	test_axc_error0++;
-			}
-			#endif		
-			for(j=0;j<(memcpy_len>>2);j=j+1)
-			{
-				if((pSrcData[j]  ^ pSrcData[(memcpy_len>>2) + j] ) !=0)
-				{
-				  test_axc_error0++;
-				}
-			}
-			
-		}
-		
-#if 0
-
-		 for(i=0;i<mem_cycle;i=i+1)
-		 {
-			 //memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			 //memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			 //if ((memcmp((void*)pSrcData,(void*)(pSrcData + memcpy_len),memcpy_len)) != 0)
-
-			
-			 if ((memcmp((void*)(CSU_TX_AXC_ADDR + i*memcpy_len),(void*)(CSU_RX_AXC_ADDR + i*memcpy_len),memcpy_len)) != 0)//512k
-			 {
-				 test_axc_error0++;
-			 }
-		 }
-#endif
-
-
-		
-		 uint32_t cost0 = GET_STC_CNT() - startTick0;
-		 debug_write((DBG_DDR_IDX_CPRI_BASE+210+times),cost0);
-		 debug_write((DBG_DDR_IDX_CPRI_BASE+220+times),test_axc_error0);
-
-		 if(test_axc_error0 == 0) 
-		{
-			UCP_PRINT_LOG("Test axc data pass.\r\n");
-		}
-		else
-		{
-			UCP_PRINT_LOG("Test axc data error!!!!!!!!!!!!!!!!!\r\n");
-		}
-
-	}
-	if(Ping_Pong_Flag == 1)
-	{
-		 /**************test pong addr**********/
-		 uint32_t startTick1 = GET_STC_CNT();
-		 #if 0
-		 for(i=0;i<cycle;i=i+1)//pong
-		{		
-			CSU_Rx_AxC_Data = do_read((uint32_t *)(CSU_RX_AXC_ADDR +ID_NUM*ID_DATA_STEP + i*4));
-			CSU_Tx_AxC_Data = do_read((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*ID_DATA_STEP+ i*4));
-			if((CSU_Rx_AxC_Data ^ CSU_Tx_AxC_Data) !=0)
-			{
-			  test_axc_error1++;
-			}
-		}
-		#endif
-
-		#if 0
-		 for(i=0;i<mem_cycle;i=i+1)
-		 {
-			 memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR +ID_NUM*ID_DATA_STEP+i*memcpy_len), memcpy_len);
-			 memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR +ID_NUM*ID_DATA_STEP+ i*memcpy_len), memcpy_len);
-			 for(j=0;j<(memcpy_len>>2);j=j+1)
-			 {
-				 if((pSrcData[j]  ^ pSrcData[(memcpy_len>>2) + j] ) !=0)
-				 {
-				   test_axc_error1++;
-				 }
-			 }
-		 }
-		#endif
-
-#if 0
-		 //for(i=0;i<mem_cycle;i=i+1)
-		 {
-			 memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR +ID_NUM*ID_DATA_STEP+(mem_cycle -1)*memcpy_len), memcpy_len);
-			 memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR +ID_NUM*ID_DATA_STEP+ (mem_cycle -1)*memcpy_len), memcpy_len);
-			 for(j=0;j<(memcpy_len>>2);j=j+1)
-			 {
-				 if((pSrcData[j]  ^ pSrcData[(memcpy_len>>2) + j] ) !=0)
-				 {
-				   test_axc_error1++;
-				 }
-			 }
-		 }
-#endif
-
-
-		 for(i=0;i<mem_cycle;i=i+1)
-		 {
-			 memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR +ID_NUM*ID_DATA_STEP+ i*memcpy_len), memcpy_len);
-			 memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR +ID_NUM*ID_DATA_STEP+ i*memcpy_len), memcpy_len);
-
-			#if 0
-
-			 if ((memcmp((void*)pSrcData,(void*)(pSrcData + memcpy_len),memcpy_len) )!= 0)
-			 {
-				 test_axc_error1++;
-			 }
-			#endif
-			 for(j=0;j<(memcpy_len>>2);j=j+1)
-			 {
-				 if((pSrcData[j]  ^ pSrcData[(memcpy_len>>2) + j] ) !=0)
-				 {
-				   test_axc_error0++;
-				 }
-			 }
-	
-		 }
-
-		#if 0
-
-		 for(i=0;i<mem_cycle;i=i+1)
-		  {
-			  memcpy_ucp((void*)pSrcData,(void*)(CSU_TX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			  memcpy_ucp((void*)(pSrcData + memcpy_len),(void*)(CSU_RX_AXC_ADDR + i*memcpy_len), memcpy_len);
-			  if ((memcmp((void*)pSrcData,(void*)(pSrcData + memcpy_len),memcpy_len)) != 0)
- 
-			 
-			  //if ((memcmp((void*)(CSU_TX_AXC_ADDR +ID_NUM*ID_DATA_STEP+ i*memcpy_len),(void*)(CSU_RX_AXC_ADDR+ID_NUM*ID_DATA_STEP + i*memcpy_len),memcpy_len)) != 0)//512k
-			  {
-				  test_axc_error1++;
-			  }
-		  }
-
-		#endif
-
-		 
-		 uint32_t cost1 = GET_STC_CNT() - startTick1;
-		 debug_write((DBG_DDR_IDX_CPRI_BASE+230+times),cost1);
-		debug_write((DBG_DDR_IDX_CPRI_BASE+240+times),test_axc_error1);
-
-		if(test_axc_error1 == 0) 
-		{
-			UCP_PRINT_LOG("Test axc data pass.\r\n");
-		}
-		else
-		{
-			UCP_PRINT_LOG("Test axc data error!!!!!!!!!!!!!!!!!\r\n");
-		}
-
-	}
-		
-
-}
-
-#endif
-
-#if 0
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-
-uint32_t HeaderTxtimes = 0;
-
-void Cpri_Header_test(void)
-{
-	
-	//uint32_t Header_error0=0;
-	//uint32_t Header_error1 = 0;
-	//uint32_t Get_Rx_HFN = 0;
-	uint32_t j= 0;
-
-//	if ((2 <= gCpriTimerPara.tddOffsetIntCnt) && (20 >= gCpriTimerPara.tddOffsetIntCnt))
-	if (2 <= gCpriTimerPara.tddOffsetIntCnt) 
-	{
-		if (1 == (gCpriTimerPara.tddOffsetIntCnt & 0x1))
-		{	
-						
-			HeaderTxtimes++;
-			#if 0
-			if(HeaderTxtimes == 1 )
-			{
-				AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
-				AUX_Rx_enable(0x2);
-				//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-				//debug_write((DBG_DDR_IDX_DRV_BASE+394 + ), Get_Rx_HFN); // 0x628
-			}
-			#endif
-			//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-			//Get_Rx_HFN = UCP_API_CPRI_GetRxHfnCnt();
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+ HeaderTxtimes), Get_Rx_HFN); // 0xb7e28000				
-			UCP_PRINT_LOG("Header insert start.\r\n");
-
-			/*********************1st HyperFrame*********************/
-			//when BFN=111,header Tx insert
-		//	uint32_t startTick = GET_STC_CNT();
-		 //if(HeaderTxtimes == 1 )
-		 {
-
-			
-			while(1)
-			{
-				if((UCP_API_CPRI_GetTxHfnCnt() ==HeaderTxHFN0) && ( UCP_API_CPRI_GetTxXCnt() <10))
-				//if((UCP_API_CPRI_GetTxHfnCnt() ==HeaderTxHFN0))
-				{
-					HeaderRam_ins_disable();
-					break;
-				}
-			}
-		 }
-			//uint32_t startTick0 = GET_STC_CNT();
-			//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-			//Get_Rx_HFN = UCP_API_CPRI_GetRxHfnCnt();
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+20+HeaderTxtimes), Get_Rx_HFN); // 
-#if 1
-		 //if(HeaderTxtimes == 1 )
-		 {
-
-			//uint32_t startTick0 = GET_STC_CNT();
-			//memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes-1)*64)), 64);
-			memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*64)), 64);
-			for(j=0;j<4;j++)
-			{
-				HeaderRam_Tx(3+64*j,0,Txdata[j*4],0xF);//vendor
-				HeaderRam_Tx(3+64*j,1,Txdata[1+j*4],0xF);//vendor
-				HeaderRam_Tx(3+64*j,2,Txdata[2+j*4],0xF);//vendor
-				HeaderRam_Tx(3+64*j,3,Txdata[3+j*4],0xF);//vendor
-
-			}
-			//uint32_t cost0 = GET_STC_CNT() - startTick0;
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+170+gCpriTimerPara.tddOffsetIntCnt),cost0);//17us左右
-#endif
-
-			
-			HeaderRam_ins_enable();
-			debug_write((DBG_DDR_IDX_CPRI_BASE+141), do_read_volatile(&AUX_CNT0));
-
-			
-			//delay_us(10);
-
-		 }
-#if 0
-			//when BFN=112,header Tx insert enable
-			while(1)
-			{
-				if((UCP_API_CPRI_GetTxHfnCnt() ==  (HeaderTxHFN0+1)) && ( UCP_API_CPRI_GetTxXCnt() <2))
-				{
-					HeaderRam_ins_enable();
-					break;
-				}
-			}
-			//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+40+HeaderTxtimes), Get_Rx_HFN); // 
-
-#endif
-#if 1
-			//when BFN=113,header Rx
-			while(1)
-			{
-				//if((UCP_API_CPRI_GetTxHfnCnt() ==(HeaderTxHFN0+2)) && ( UCP_API_CPRI_GetTxXCnt() ==0))
-				//if(UCP_API_CPRI_GetTxHfnCnt() ==(HeaderTxHFN0+3))
-				//if((UCP_API_CPRI_GetTxHfnCnt() ==(HeaderTxHFN0+1)) && ( UCP_API_CPRI_GetTxXCnt() >=200))//BFN=112
-				if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-				{
-					//HeaderRam_ins_disable();
-					break;
-				}
-			}
-			debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-			debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-			//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-			//Get_Rx_HFN = UCP_API_CPRI_GetRxHfnCnt();
-			///debug_write((DBG_DDR_IDX_CPRI_BASE+60+HeaderTxtimes), Get_Rx_HFN); // 
-			for(j=0;j<4;j++)
-			{
-				//Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor	
-				Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-				Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-				Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-				Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-			
-			}
-			//do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-			//memcpy_ucp((uint32_t*)(HeaderRxDataAddr0 +((HeaderTxtimes-1)*64)),(uint32_t*)Rxdata0, 64);
-			memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-#endif	
-
-			#if 1
-			for(j=0;j<16;j++)
-			{
-				if (Rxdata0[j] != Txdata[j])//vendor
-				{
-					Header_error0++;
-					Header_error1++;
-				}
-			
-			}
-			#endif
-			if(Header_error1!=0)
-			{
-			
-				memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-				Header_error1 =0;
-			}
-
-#if 0
-
-				for(j=0;j<16;j++)
-			{
-				if(j%4 == 3)
-				{
-					continue;
-				}
-				if (Rxdata0[j] != Txdata[j])//vendor
-				{
-					Header_error0++;
-				}
-			
-			}
-#endif
-			//if(memcmp((uint32_t*)HeaderTxDataAddr0 ,(uint32_t*)(HeaderRxDataAddr0 + (HeaderTxtimes*64)),64) != 0)
-			//{
-			//	Header_error0++;
-			//}
-	
-
-			/*********************2nd HyperFrame*********************/
-
-#if 0
-			//when BFN=114,header Tx insert
-			while(1)
-			{
-				if((UCP_API_CPRI_GetTxHfnCnt() == HeaderTxHFN1) && ( UCP_API_CPRI_GetTxXCnt() < 10))
-				//if(UCP_API_CPRI_GetTxHfnCnt() == HeaderTxHFN1)
-				{
-					HeaderRam_ins_disable();
-					break;
-				}
-			}
-			//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-			Get_Rx_HFN = UCP_API_CPRI_GetRxHfnCnt();
-			debug_write((DBG_DDR_IDX_CPRI_BASE+80+HeaderTxtimes), Get_Rx_HFN); // 
-			
-			memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr1+ ((HeaderTxtimes-1)*64)), 64);			
-			for(j=0;j<4;j++)
-			{
-				HeaderRam_Tx(3+64*j,0,Txdata[j*4]);//vendor
-				HeaderRam_Tx(3+64*j,1,Txdata[1+j*4]);//vendor
-				HeaderRam_Tx(3+64*j,2,Txdata[2+j*4]);//vendor
-				HeaderRam_Tx(3+64*j,3,Txdata[3+j*4]);//vendor
-
-			}
-			HeaderRam_ins_enable();
-			
-	#if 0
-			//when BFN=115,header Tx insert enable
-			while(1)
-			{
-				if((UCP_API_CPRI_GetTxHfnCnt() ==(HeaderTxHFN1+1)) && ( UCP_API_CPRI_GetTxXCnt() ==0))
-				{
-					HeaderRam_ins_enable();
-					break;
-				}
-			}
-	#endif
-			//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+100+HeaderTxtimes), Get_Rx_HFN); // 
-
-			//when BFN=116,header Rx
-			while(1)
-			{
-				//if((UCP_API_CPRI_GetTxHfnCnt() ==(HeaderTxHFN1+2)) && ( UCP_API_CPRI_GetTxXCnt() ==0))
-				//if(UCP_API_CPRI_GetTxHfnCnt() ==(HeaderTxHFN1+2))
-				if((UCP_API_CPRI_GetTxHfnCnt() ==(HeaderTxHFN1+1)) && ( UCP_API_CPRI_GetTxXCnt() >=200))//
-				{
-					//HeaderRam_ins_disable();
-					break;
-				}
-			}
-			//Get_Rx_HFN = HeaderRam_Rx(64,0);//get Rx HFN
-			Get_Rx_HFN = UCP_API_CPRI_GetRxHfnCnt();
-			debug_write((DBG_DDR_IDX_CPRI_BASE+120+HeaderTxtimes), Get_Rx_HFN); // 
-			
-			for(j=0;j<4;j++)
-			{
-				Rxdata1[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-				Rxdata1[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-				Rxdata1[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor
-				Rxdata1[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor	
-			
-			}
-			memcpy_ucp((uint32_t*)(HeaderRxDataAddr1 +((HeaderTxtimes-1)*64)),(uint32_t*)Rxdata1, 64);
-
-			//if(memcmp((uint32_t*)HeaderTxDataAddr1 ,(uint32_t*)(HeaderRxDataAddr1 + (HeaderTxtimes*64)),64) != 0)
-			//{
-			//	Header_error1++;
-			//}
-#if 0
-			for(j=0;j<16;j++)
-			{
-				if (Rxdata[j] != Txdata[j])//vendor
-				{
-					Header_error1++;
-				}
-			
-			}
-#endif
-#endif
-			//uint32_t cost0 = GET_STC_CNT() - startTick0;
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+160+gCpriTimerPara.tddOffsetIntCnt),cost0);
-
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+140+(HeaderTxtimes*2)), Header_error0); 
-			debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-			//debug_write((DBG_DDR_IDX_CPRI_BASE+140+(HeaderTxtimes*2+1)), Header_error1); 
-
-#if 0
-			if(Header_error0 !=0)
-			{
-				UCP_PRINT_LOG("1st HF Header fail.\r\n");
-				
-			}
-			if(Header_error1 !=0)
-			{
-				UCP_PRINT_LOG("2nd HF Header fail.\r\n");
-			}
-#endif
-
-
-		//uint32_t cost = GET_STC_CNT() - startTick;
-		//debug_write((DBG_DDR_IDX_CPRI_BASE+180+gCpriTimerPara.tddOffsetIntCnt),cost);
-
-		}
-	}
-	
-}
-#endif
-
 void cpri_AxCData_test(void)
 {				
 		stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
@@ -810,42 +323,7 @@ void cpri_AxCData_test(void)
 
 void cpri_test_case(void)
 {
-#if 0
-#if 1
-	//if (6 <= gCpriTimerPara.tddOffsetIntCnt)
-	if (4 <= gCpriTimerPara.tddOffsetIntCnt)
-	//if (2 == gCpriTimerPara.tddOffsetIntCnt)
-	{
 
-		if (0 == (gCpriTimerPara.tddOffsetIntCnt & 0x3))
-		//if ((0x94 <= UCP_API_CPRI_GetTxHfnCnt()	) && (UCP_API_CPRI_GetTxHfnCnt() <= 0x95))
-		//if (0x95 == UCP_API_CPRI_GetTxHfnCnt() )
-		{
-#ifdef CPRI_TIMING_TEST
-//						UINT32 startTick = GET_STC_CNT();
-			
-		    cpri_csu_start_timing();
-//						UINT32 cost = GET_STC_CNT() - startTick;
-//						do_write(DDR_ADDR_90, cost);
-#endif
-#ifdef CPRI_NOTIMING_TEST
-			cpri_csu_start_notiming();
-#endif
-			#if 0	
-			if (20 >= gCpriTimerPara.tddOffsetIntCnt)
-			{
-
-				debug_write((DBG_DDR_IDX_CPRI_BASE+280 + gCpriTimerPara.tddOffsetIntCnt), UCP_API_CPRI_GetRxHfnCnt()); // 0x628
-				//debug_write((DBG_DDR_IDX_CPRI_BASE+280), UCP_API_CPRI_GetRxHfnCnt()); 
-			}
-			#endif
-		}
-	}
-#endif
-//	cpri_AxCData_test();
-
-	Cpri_Header_test();
-#endif
 	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
 	//if(gCpriTimerPara.tddOffsetIntCnt <= 8)
 	if(pMtimerInt->csuEnCnt > 4 )
@@ -859,10 +337,6 @@ void cpri_test_case(void)
 			
 }
 
-void cpri_test_move_data()
-{
-}
-
 void Cpri_Header_Rx(void)
 {
 }

public/test/testcase_fh/case31/inc/cpri_test_case31.h

@@ -42,8 +42,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case31/src/cpri_test_case31.s.c

@@ -71,11 +71,14 @@ void Get_Cpri_OptionId()
     return;
 }
 
-void cpri_test_init()
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
 }
 
+
 void HeaderTxRam_data_init()
 {
 	for(int i=0;i<16*HeaderTestCnt;i++)

public/test/testcase_fh/case32/inc/cpri_test_case32.h

@@ -42,8 +42,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case32/src/cpri_test_case32.s.c

@@ -98,11 +98,14 @@ void cpri_csu_test_init()
 	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
 }
 
-void cpri_test_init()
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
 }
 
+
 void Axc_data_init()
 {
 	uint8_t idID = 0;

public/test/testcase_fh/case33/inc/cpri_test_case33.h

@@ -58,8 +58,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case33/src/cpri_test_case33.s.c

@@ -54,9 +54,9 @@ int32_t fh_data_init(void)
 	return 0;
 }
 
-int32_t fh_hw_test_init(void)
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
 
 	return 0;
 }

public/test/testcase_fh/case34/inc/cpri_test_case34.h

@@ -45,7 +45,6 @@ void Axc_data_init();
 
 void cpri_csu_config();
 
-void Cpri_Header_test();
 
 void cpri_test_move_data();
 

public/test/testcase_fh/case34/src/cpri_test_case34.s.c

@@ -62,7 +62,7 @@ int32_t fh_data_init(void)
 
 int32_t fh_drv_init(void)
 {
-	cpri_init(CPRI_OPTION_8, NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
 
 	return 0;
 }
@@ -117,6 +117,7 @@ void fh_data_check(uint32_t times)
 				cnt++;				
 			}
 		}
+		Cpri_Header_Rx();
 	}
 }
 
@@ -418,13 +419,70 @@ void Axc_data_init()
 	spu_csu_dma_1D_transfer(srcAddr, dstAddr, dataLen);
 }
 
-void fh_test_move_data()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void Cpri_Header_test()
-{
-}
 
 void cpri_check_slot_data(uint32_t slotNum)
 {
@@ -632,112 +690,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	if(NR4T4R_7DS2U == gVendorFlag)
-	{
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-	}
-}
-

public/test/testcase_fh/case35/inc/cpri_test_case35.h

@@ -40,8 +40,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case35/src/cpri_test_case35.s.c

@@ -71,11 +71,14 @@ void Get_Cpri_OptionId()
 	//CPRI_OPTION = CPRI_OPTION_8;
     return;
 }
-void cpri_test_init()
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
 }
 
+
 void HeaderTxRam_data_init()
 {
 #if 0

public/test/testcase_fh/case36/inc/cpri_test_case36.h

@@ -40,8 +40,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case36/src/cpri_test_case36.s.c

@@ -69,9 +69,12 @@ void Get_Cpri_OptionId()
 //	CPRI_OPTION = CPRI_OPTION_8;
     return;
 }
-void cpri_test_init()
+
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
 }
 
 void HeaderTxRam_data_init()

public/test/testcase_fh/case37/inc/cpri_test_case37.h

@@ -40,8 +40,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case37/src/cpri_test_case37.s.c

@@ -72,9 +72,12 @@ void Get_Cpri_OptionId()
 	//CPRI_OPTION = CPRI_OPTION_8;
     return;
 }
-void cpri_test_init()
+
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
 }
 
 void HeaderTxRam_data_init()

public/test/testcase_fh/case38/inc/cpri_test_case38.h

@@ -41,8 +41,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case38/src/cpri_test_case38.s.c

@@ -73,11 +73,14 @@ void Get_Cpri_OptionId()
     return;
 }
 
-void cpri_test_init()
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
+
+	return 0;
 }
 
+
 void HeaderTxRam_data_init()
 {
 #if 0

public/test/testcase_fh/case39/inc/cpri_test_case39.h

@@ -40,8 +40,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case39/src/cpri_test_case39.s.c

@@ -74,11 +74,12 @@ void Get_Cpri_OptionId()
     return;
 }
 
-void cpri_test_init()
+int32_t fh_drv_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_8,NR4T4R_7DS2U);
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);
-}
 
+	return 0;
+}
 
 void HeaderTxRam_data_init()
 {

public/test/testcase_fh/case60/inc/cpri_test_case60.h

@@ -21,8 +21,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case60/src/cpri_test_case60.s.c

@@ -42,25 +42,13 @@ extern uint32_t			gCpriCsuDummyFlag;
 
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
 //	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
@@ -68,17 +56,25 @@ void Cpri_data_init()
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
 }
 
 void HeaderTxRam_data_init()
@@ -94,85 +90,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -391,36 +309,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -457,6 +410,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -856,109 +810,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case61/inc/cpri_test_case61.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case61/src/cpri_test_case61.s.c

@@ -47,30 +47,15 @@ extern uint32_t Nr_antData23[122880];
 extern uint32_t Lte_antData[30720];
 extern uint32_t Agc_Data[2280];
 
-
-
-
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
 //	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
@@ -78,19 +63,28 @@ void Cpri_data_init()
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-//	CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
 }
 
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
 void HeaderTxRam_data_init()
 {
 	for(int i=0;i<16*HeaderTestCnt;i++)
@@ -104,85 +98,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -367,36 +283,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -433,6 +384,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -788,109 +740,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case62/inc/cpri_test_case62.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case62/src/cpri_test_case62.s.c

@@ -47,50 +47,44 @@ extern uint32_t Nr_antData23[122880];
 extern uint32_t Lte_antData[30720];
 extern uint32_t Agc_Data[2280];
 
-
-
-
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
-	//debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
 	UCP_PRINT_EMPTY("Axc data init.\r\n");
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
 }
 
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
 void HeaderTxRam_data_init()
 {
 	for(int i=0;i<16*HeaderTestCnt;i++)
@@ -104,85 +98,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -367,36 +283,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -433,6 +384,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -788,109 +740,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case63/inc/cpri_test_case63.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case63/src/cpri_test_case63.s.c

@@ -53,25 +53,13 @@ DDR0 uint32_t Data_temp[122880] = {0};
 
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
 //	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
@@ -79,19 +67,28 @@ void Cpri_data_init()
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-//	CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
 }
 
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
 void HeaderTxRam_data_init()
 {
 	for(int i=0;i<16*HeaderTestCnt;i++)
@@ -105,85 +102,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -371,36 +290,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -437,6 +391,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -792,109 +747,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case64/inc/cpri_test_case64.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case64/src/cpri_test_case64.s.c

@@ -53,45 +53,42 @@ DDR0 uint32_t Data_temp[122880] = {0};
 
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
-	//debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
 	UCP_PRINT_EMPTY("Axc data init.\r\n");
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
 }
 
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
 void HeaderTxRam_data_init()
 {
 	for(int i=0;i<16*HeaderTestCnt;i++)
@@ -105,85 +102,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -371,36 +290,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -437,6 +391,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -792,109 +747,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case65/inc/cpri_test_case65.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case65/src/cpri_test_case65.s.c

@@ -53,25 +53,13 @@ DDR0 uint32_t Data_temp[122880] = {0};
 
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
 //	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
@@ -79,17 +67,25 @@ void Cpri_data_init()
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
 }
 
 void HeaderTxRam_data_init()
@@ -105,85 +101,9 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
 
-#if 0
-void Axc_data_init()
 
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -371,36 +291,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -437,6 +392,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -792,109 +748,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case66/inc/cpri_test_case66.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case66/src/cpri_test_case66.s.c

@@ -47,30 +47,15 @@ extern uint32_t Nr_antData23[122880];
 extern uint32_t Lte_antData[30720];
 extern uint32_t Agc_Data[2280];
 
-
-
-
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
 //	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
@@ -78,19 +63,28 @@ void Cpri_data_init()
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
 }
 
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
 void HeaderTxRam_data_init()
 {
 	for(int i=0;i<16*HeaderTestCnt;i++)
@@ -104,85 +98,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -367,36 +283,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -433,6 +384,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -788,109 +740,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case67/inc/cpri_test_case67.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case67/src/cpri_test_case67.s.c

@@ -47,30 +47,15 @@ extern uint32_t Nr_antData23[122880];
 extern uint32_t Lte_antData[30720];
 extern uint32_t Agc_Data[2280];
 
-
-
-
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
 //	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
@@ -78,16 +63,25 @@ void Cpri_data_init()
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-//	CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
-void cpri_test_init()
+
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
 }
 
 void HeaderTxRam_data_init()
@@ -103,85 +97,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -366,36 +282,71 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
@@ -432,6 +383,7 @@ void AxC_data_check(uint32_t times)
 			}			
 		}
 		#endif
+		Cpri_Header_Rx();
 	}
 }
 
@@ -786,110 +738,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
 	}
 }
-
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case68/inc/cpri_test_case68.h

@@ -22,8 +22,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case68/src/cpri_test_case68.s.c

@@ -47,30 +47,15 @@ extern uint32_t Nr_antData23[122880];
 extern uint32_t Lte_antData[30720];
 extern uint32_t Agc_Data[2280];
 
-
-
-
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	//stCpriCsuCmdFifoInfo		txTestCmdFifo;
-	//stCpriCsuCmdFifoInfo		rxTestCmdFifo;
-	
-//	cpri_csu_axc_init_lte_fdd(CPRI_DUMMY_USE_DDR_ADDR, &txTestCmdFifo, &rxTestCmdFifo);
-//	cpri_csu_axcctrl_init_timing();
-//	UCP_API_CPRI_CSU_Get_CmdFIFO(&txTestCmdFifo, &rxTestCmdFifo);
-
-	Config_Cpri_Csu_Lte();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
 	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
 //	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
@@ -78,17 +63,25 @@ void Cpri_data_init()
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_8;
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE10);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(LTE_MODE,CPRI_OPTION_8,NR4T4R_LTE2T2R_FDD);
+	Config_Cpri_Csu_Lte();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
 }
 
 void HeaderTxRam_data_init()
@@ -104,85 +97,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 
-
-#if 0
-void Axc_data_init()
-
-{
-
-   uint32_t i,j,k,t,m,n =0;
-	
-	 for(i=0;i<RF_NUM;i=i+1)//2 frame
-	 {
-		 for(j=0;j<2;j=j+1)//0-74HF/75-149HF
-		 {
-			for(k=0;k<ID_NUM;k=k+1)//ID
-			{
-				//bit31:28为RFN,bit27:20为HFN,bit19:12为BasicFN,bit11:8为AXC ID,bit7:0为AXC data
-				if(0==k || 5==k)
-				{
-					for(t=0;t<75;t=t+1)//HF
-				   {	
-				  		for(m=0;m<256;m=m+1)//bfn
-			  			{
-			  				for(n=0;n<ID0_SIZE;n=n+1)//
-		  					{		  	
-					   			//STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-								do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID0_SIZE*4 + m*ID0_SIZE*4 + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+0x1);
-
-							}
-				  		}
-
-				   }
-
-				}
-				else//ID1~ID4
-				{
-					for(t=0;t<75;t=t+1)//HF
-					{
-						 for(m=0;m<256;m=m+1)//bfn
-						 {
-							 for(n=0;n<ID1_SIZE*8/4;n=n+1)//
-							 {
-								// STORE_EX_W(((uint32_t *)(CSU_TX_AXC_ADDR +ID_NUM*2*ID_DATA_STEP+ i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-								 do_write(((uint32_t *)(CSU_TX_AXC_ADDR + i*ID_DATA_STEP*ID_NUM*2 + j*ID_DATA_STEP*ID_NUM + k*ID_DATA_STEP + t*256*ID1_SIZE*8 + m*(ID1_SIZE*8) + n*4)), (i<<28)+((j*75+t)<<20)+(m<<12)+(k<<8)+n);
-					
-							 }
-					
-							 
-						 }
-					
-					}
-
-
-				}
-			}
-		 }
-		 
-	 }
-
-}
-
-#else
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -367,43 +282,79 @@ void Axc_data_init()
 	}
 
 }
-#endif
 
-void cpri_csu_config()
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
-}
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
-
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
-
-//uint32_t testcasecnt = 0;
-
-void cpri_test_case()
-{
-  //  testcasecnt++;
- //   if(6 > testcasecnt)
 	{
-		UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+//		HeaderRxtimes++;
-	}
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
 
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+		}
 }
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
 uint32_t gCompSlotIdCnt = 0;
 uint32_t gBfStartErr = 0;
 uint32_t cnt = 0;
-void AxC_data_check(uint32_t times)
+void fh_data_check(uint32_t times)
 {
 	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
 	if (4 <= pMtimerInt->csuEnCnt)
@@ -788,109 +739,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-#if 0
-uint32_t Txdata[16] ={0};
-uint32_t Rxdata0[16] ={0};
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*4] = HeaderRam_Rx(3+64*j,0);//vendor
-		Rxdata0[1+j*4] = HeaderRam_Rx(3+64*j,1);//vendor
-		Rxdata0[2+j*4] = HeaderRam_Rx(3+64*j,2);//vendor			
-		Rxdata0[3+j*4] = HeaderRam_Rx(3+64*j,3);//vendor
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 64);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*64)), 64);
-	for(j=0;j<16;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-#endif
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-

public/test/testcase_fh/case70/inc/cpri_test_case70.h

@@ -27,8 +27,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case70/src/cpri_test_case70.s.c

@@ -42,36 +42,40 @@ extern uint32_t			gCpriCsuDummyFlag;
 
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	 Phy_Timer_Csu_Config_Nr();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
-	debug_write((DBG_DDR_IDX_CPRI_BASE+12), gCpriTestMode); // 0x300
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
-//	debug_write((DBG_DDR_IDX_CPRI_BASE+13), CPRI_OPTION); // 0x304
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
 	UCP_PRINT_EMPTY("Axc data init.\r\n");
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_10;
+	cpri_init(CPRI_OPTION_10, OTIC_MAP_FIGURE16);
-    return;
+
+	return 0;
 }
 
-void cpri_test_init()
+
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_10,NR2_4T4R_7DS2U);
+	 Phy_Timer_Csu_Config_Nr();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
 }
 
 void HeaderTxRam_data_init()
@@ -87,24 +91,7 @@ void HeaderTxRam_data_init()
 	}
 #endif
 }
-#if 0
+
-void HeaderTxRam_init()
-{
-	uint32_t i,j;
-	HeaderRam_ins_disable();
-	for(i=0;i<64;i++)//Ns
-	{
-		for(j=0;j<4;j++)//
-		{
-			HeaderRam_Tx(i+64*j,0,0,0);//vendor
-			HeaderRam_Tx(i+64*j,1,0,0);//vendor
-			HeaderRam_Tx(i+64*j,2,0,0);//vendor
-			HeaderRam_Tx(i+64*j,3,0,0);//vendor
-		}
-	}
-	do_write(&CPRI_FRAME_RX_HDR_ADDR,0);
-}
-#endif
 void Axc_data_init()
 {
 	uint8_t idID = 0;
@@ -459,34 +446,80 @@ void Axc_data_init()
 	*****************/
 }
 
-void cpri_csu_config()
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
 }
 
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
 
-void cpri_test_case()
-{
-	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
-}
-
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
 uint32_t gCompSlotIdCnt = 0;
 uint32_t gBfStartErr = 0;
 uint32_t cnt = 0;
-void AxC_data_check(uint32_t times)
+void fh_data_check(uint32_t times)
 {
 	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
 	if (4 <= pMtimerInt->csuEnCnt)
@@ -518,6 +551,7 @@ void AxC_data_check(uint32_t times)
 		}
 #endif
 	}
+	Cpri_Header_Rx();
 }
 
 
@@ -769,64 +803,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-
-

public/test/testcase_fh/case71/inc/cpri_test_case71.h

@@ -27,8 +27,6 @@ void cpri_csu_config();
 
 void cpri_test_case();
 
-void Cpri_Header_test();
-
 void cpri_test_move_data();
 
 void AxC_data_check(uint32_t times);

public/test/testcase_fh/case71/src/cpri_test_case71.s.c

@@ -49,35 +49,40 @@ extern uint32_t			gCpriCsuDummyFlag;
 
 #define HeaderTestCnt   10
 
-void cpri_csu_test_init()
+int32_t fh_data_init(void)
-{
-	 Phy_Timer_Csu_Config_Nr();
-}
-
-void Cpri_data_init()
 {
 	gCpriTestMode = CPRI_TEST_MODE;
 	gCpriCsuDummyFlag  = 1;
-	debug_write((DBG_DDR_IDX_CPRI_BASE+12), gCpriTestMode); // 0x300
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
 
-	Get_Cpri_OptionId();//get cpri option value
+//	Get_Cpri_OptionId();//get cpri option value
-//	debug_write((DBG_DDR_IDX_CPRI_BASE+13), CPRI_OPTION); // 0x304
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
 		
 	Axc_data_init();//init axc data
 	UCP_PRINT_EMPTY("Axc data init.\r\n");
 	HeaderTxRam_data_init();
 	//HeaderTxRam_init();
 	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
 }
 
-void Get_Cpri_OptionId()
+int32_t fh_drv_init(void)
 {
-	//CPRI_OPTION = CPRI_OPTION_10;
+	cpri_init(CPRI_OPTION_10, OTIC_MAP_FIGURE16);
-    return;
+
+	return 0;
 }
-void cpri_test_init()
+
+
+int32_t fh_csu_test_init(void)
 {
-	cpri_init(NR_MODE,CPRI_OPTION_10,NR2_4T4R_7DS2U);
+	 Phy_Timer_Csu_Config_Nr();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
 }
 
 void HeaderTxRam_data_init()
@@ -264,34 +269,80 @@ void Axc_data_init()
 
 }
 
-void cpri_csu_config()
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
 {
-//	 cpri_csu_axc_init_nr_7ds2u();
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
 }
 
-void cpri_prepare_data(uint32_t slotNum)
-{
-}
 
-void cpri_test_case()
-{
-	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
-}
 
-void cpri_test_move_data()
-{
-}
-
-void Cpri_Header_test()
-{
-}
 
 uint32_t gCompWordCnt = 0;
 uint32_t gErrSlotIdCnt = 0;
 uint32_t gCompSlotIdCnt = 0;
 uint32_t gBfStartErr = 0;
 uint32_t cnt = 0;
-void AxC_data_check(uint32_t times)
+void fh_data_check(uint32_t times)
 {
 	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
 	if (4 <= pMtimerInt->csuEnCnt)
@@ -323,6 +374,7 @@ void AxC_data_check(uint32_t times)
 		}
 #endif
 	}
+	Cpri_Header_Rx();
 }
 
 
@@ -574,64 +626,3 @@ void cpri_check_slot_data(uint32_t slotNum)
 	}
 }
 
-
-uint32_t Txdata[48] ={0};
-uint32_t Rxdata0[48] ={0};
-
-uint32_t Header_error0=0;
-uint32_t Header_error1 = 0;
-uint32_t HeaderRxtimes = 0;
-
-void Cpri_Header_Rx(void)
-{
-	uint32_t j= 0;
-	HeaderRxtimes++;
-#if 1
-	while(1)
-	{
-		if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
-		{
-			break;
-		}
-	}
-#endif
-	debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
-	debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
-
-	for(j=0;j<4;j++)
-	{
-		Rxdata0[j*12]   = HeaderRam_Rx(8+64*j, 0);
-		Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
-		Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
-		Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
-		Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
-		Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
-		Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
-		Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
-		Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
-		Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
-		Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
-		Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
-
-	}
-	memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
-	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
-	for(j=0;j<48;j++)
-	{
-		if (Rxdata0[j] != Txdata[j])//vendor
-		{
-			Header_error0++;
-			Header_error1++;
-		}
-	}
-
-	
-	if(Header_error1!=0)
-	{
-		memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
-		Header_error1 =0;
-	}
-	debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
-}
-
-

public/test/testcase_fh/case72/inc/cpri_test_case72.h

@@ -0,0 +1,39 @@
+#ifndef _CPRI_TEST_CASE70_H_
+#define _CPRI_TEST_CASE70_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE72_SLOT_NUM				20
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+
+#define CPRI_NR7DS2U_RX_DUMMY_COM_LEN			0x73B8
+#define CPRI_NR7DS2U_RX_DUMMY_AXC_LEN			0x1CEE00
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcase_fh/case72/inc/nr_mem_def.h

@@ -0,0 +1,233 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl.h"
+//#include "interface_fapi_deofdm.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_pdcch.h"
+//#include "interface_fapi_ssb.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+#define SM0_BASE_1                    	(0x009D00000)//1M
+#define SM1_BASE_1                    	(0x009E00000)//1M
+#define SM2_BASE_1                    	(0x009F00000)//1.5M
+#define SM3_BASE_1                    	(0x00A080000)//1.5M
+#define SM4_BASE_1                    	(0x00A200000)//1.5M
+#define SM5_BASE_1                    	(0x00A380000)//1.5M
+
+/***************************************SM0-SM1--2M*********************************************/
+//len define
+//SM0
+#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
+#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
+#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K
+
+#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
+#define SM0_RESERVED0_LEN                          0X00000400  //1K
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED1_LEN                          0x00000400  //1K
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED2_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
+#define SM0_RESERVED3_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED4_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED5_LEN                          0x00005900  //22.25
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079400  //485k (480k+3.75k+1.25K)
+#define SM1_RESERVED0_LEN                          0x0001EC00  //123k
+
+#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE_1)
+#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
+#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+
+#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
+#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
+#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 
+
+#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
+#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
+#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
+#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
+#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)
+
+/***************************************SM2-SM5--6M*********************************************/
+
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM5_RESERVED0_LEN                          0x00034400  //209k
+#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x00010000  //64k
+#define SM5_ERROR_RECORD_CNT_LEN                   0x00003000  //12k
+#define SM5_NR_STATISTIC_CNT_LEN                   0x00000120  //288byte
+#define SM5_STATE_RECORD_CNT_LEN                   0x4E0 //1248byte
+#define SM5_COMMON_DEBUG_LEN                       0x400 //1K
+#define SM5_PDCCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PDSCH_DEBUG_LEN                        0x400 //1K
+#define SM5_SSB_DEBUG_LEN                          0x400 //1K
+#define SM5_CSIRS_DEBUG_LEN                        0x400 //1K
+#define SM5_DEOFDM_DEBUG_LEN                       0x400 //1K
+#define SM5_PUCCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PUSCH_DEBUG_LEN                        0x400 //1K
+#define SM5_PRACH_DEBUG_LEN                        0x400 //1K
+#define SM5_SRS_DEBUG_LEN                          0x400 //1K
+#define SM5_RESERVED3_LEN                          0x00011000  //76.5K
+
+
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE_1)
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
+#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
+#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
+#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
+#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)
+#define SM5_ERROR_RECORD_CNT_ADDR                  (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)
+#define SM5_NR_STATISTIC_CNT_ADDR                  (SM5_ERROR_RECORD_CNT_ADDR + SM5_ERROR_RECORD_CNT_LEN)
+#define SM5_STATE_RECORD_CNT_ADDR                  (SM5_NR_STATISTIC_CNT_ADDR + SM5_NR_STATISTIC_CNT_LEN)
+#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_CNT_ADDR + SM5_STATE_RECORD_CNT_LEN)
+#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
+#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
+#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
+#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
+#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
+#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
+#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
+#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
+#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)
+#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
+
+#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
+/**************************************DDR***************************************************/
+/*******************************共180M可用0x84C00000-0x8FFFFFFF******************************/
+
+#define DDR_NR_CELL0_RX_LEN            (0xA00000)//为多小区预留10M, NR单小区CPRI:120*1024*4*3//120K 4ant 3slot
+#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
+#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
+#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
+#define JESD_CSU_LINK_TX_TABLE_LEN     (0x8000)//JESD TX link 32k
+#define JESD_CSU_LINK_RX_TABLE_LEN     (0x8000)//JESD RX link 32k
+#define DDR_TEST_MAC_DL_DATA_BUF_LEN  (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+#define DDR_WRITE_MONITOR_LEN         (0x400000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_ELN          (0X400000)//预留4M空间给读DDR检查功能
+
+
+//#define DDR_PHY_BASE                   (0x6BC00000) //共180M可用0x84C00000-0x8FFFFFFF
+#define DDR_PHY_BASE                   (0x84C00000) 
+
+#define DDR_PHY_RECORD_ADDR            (DDR_PHY_BASE + DDR_NR_CELL0_RX_LEN)//0x85600000
+#define DDR_NR_DL_RECORD_ADDR          (DDR_PHY_RECORD_ADDR)             //0x85600000 - 0x87600000
+#define DDR_NR_UL_RECORD_ADDR          (DDR_NR_DL_RECORD_ADDR + DDR_NR_DL_RECORD_LEN)//0x87600000 - 0x89600000
+
+#define DDR_TEST_MAC_NR_CELL0_EVEN_RX_DATA_ADDR   (0x89600000)//0x89600000
+#define DDR_TEST_MAC_NR_CELL0_ODD_RX_DATA_ADDR    (0x89700000)//0x89700000
+#define DDR_TEST_MAC_NR_CELL1_EVEN_RX_DATA_ADDR   (0x89800000)//0x89600000
+#define DDR_TEST_MAC_NR_CELL1_ODD_RX_DATA_ADDR    (0x89900000)//0x89700000
+#define JESD_CSU_LINK_TX_TABLE_ADDR    (0x8A000000)//jesd 模式下Tx 链表地址 32k
+#define JESD_CSU_LINK_RX_TABLE_ADDR    (0x8A008000)//jesd 模式下Rx 链表地址 32k
+
+#define DDR_TEST_MAC_DL_DATA_BUF_ADDR  (0x8A010000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+
+#define DDR_WRITE_MONITOR_ADDR         (0x8B410000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_ADDR          (0x8B810000)//预留4M空间给读DDR检查功能
+
+#define FAPI_PDCCH_MSG_ADDR            (0x8BC10000)
+#define FAPI_SSB_MSG_ADDR              (0x8BC10400)
+#define FAPI_CSIRS_MSG_ADDR            (0x8BC10800)
+
+#define DDR_NR_CELL0_RX_ADDR           (DDR_PHY_BASE)//0x84C00000-0x85600000 10M
+#define DDR_NR_CELL0_RX_AGC_ADDR       (DDR_NR_CELL0_RX_ADDR + DDR_NR_CELL0_RX_LEN*2)
+
+#define DDR_MAX_ADDR                   (0X90000000)
+
+#define CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR                  (0xB4200000)
+#define CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR                  (0XB4230000)
+
+#define CPRI_NRCELL_TXDUMMY_SLOTS_COMPRESS_ADDR             (0xB4260000)
+#define CPRI_NRCELL_TXDUMMY_SLOTS_AGC_ADDR                  (0XB4265000)
+#define CPRI_NRCELL_TXDUMMY_SLOTS_AXCDATA_ADDR              (0XB426f000)//len:0x269000
+
+#define CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR             (0xB44D8000)//0xE770
+#define CPRI_NRCELL_RXDUMMY_SLOTS_AGC_ADDR                  (0XB44E6770)//0x1CEE0
+#define CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR              (0XB4503650)//len:0x73B800  --0xB4C3EE50
+
+
+#endif

public/test/testcase_fh/case72/inc/phy_timer_csu_config.h

@@ -0,0 +1,120 @@
+/******************************************************************
+ * @file  phy_timer_csu_config.h
+ * @brief:    [file description] 
+ * @author: guicheng.liu
+ * @Date 2022年7月7日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
+ * Change_date         Owner         Change_content
+ * 2022年7月7日        guicheng.liu       create file
+
+*****************************************************************/
+
+#ifndef     FPHY_TIMER_CSU_CONFIG_H
+#define     FPHY_TIMER_CSU_CONFIG_H
+//#include <type_define.h>
+#include "typedef.h"
+#include "phy_para.h"
+
+//#include "phy_nr_context.h"
+//#include "drv_rfm.h"
+
+#define CPRI_LINK_START_ADDR						0x721E800 //ECS SM后8K
+
+#define NR_LONGCP_SAM_CNT								4448
+#define NR_SHORTCP_SAM_CNT								4384
+
+typedef struct
+{
+    uint16_t period;//=t_us*num_t;
+    uint16_t rev;
+
+    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
+    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
+}timer_info_t;
+
+typedef struct
+{
+    uint8_t flag;//0:default timer, 1:inuse timer
+    uint8_t rev[3];
+
+    timer_info_t default_timer;
+    timer_info_t inuse_timer;
+}phy_timer_t;
+
+typedef struct
+{
+    uint8_t total_ants;
+    uint8_t scs;
+    uint8_t num_dl_symbols;
+    uint8_t rev;
+
+    uint16_t num_dl_tti;
+    uint16_t rev1;
+
+    phy_timer_config_ind_t jesd_timer;
+    phy_timer_config_ind_t cpri_timer;
+}phy_csu_timer_t;
+
+typedef struct
+{
+    uint32_t sampling_rate;
+
+    uint8_t tatol_tx_ants;
+    uint8_t tatol_rx_ants;
+    uint16_t rev;
+
+    uint8_t num_tx0_ants;
+    uint8_t num_tx1_ants;
+    uint8_t num_rx0_ants;
+    uint8_t num_rx1_ants;
+
+    //tx的链表地址
+    uint32_t tx0_even_f7_link_addr;
+    uint32_t tx0_even_b7_link_addr;
+    uint32_t tx0_odd_f7_link_addr;
+    uint32_t tx0_odd_b7_link_addr;
+    uint32_t tx0_s_link_addr;
+    uint32_t tx0_1st_dummy_link_addr;
+    uint32_t tx0_2nd_dummy_link_addr;
+
+    //rx的链表地址
+    uint32_t rx0_1st_dummy_link_addr;
+    uint32_t rx0_2nd_dummy_link_addr;
+    uint32_t rx0_s_link_addr;
+    uint32_t rx0_normal0_link_addr;
+    uint32_t rx0_normal1_link_addr;
+    uint32_t rx0_normal2_link_addr;
+}phy_csu_link_info_t;
+
+
+void Phy_Timer_Csu_Init();
+
+//void Csu_Dma_Init();
+//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx0_ants, 
+//                                uint16_t num_rx_tti);
+//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx1_ants, 
+//                                uint16_t num_rx_tti);
+void Config_Csu_Timer(uint16_t dl_bw,
+                            uint16_t num_tx_ants,
+                            uint8_t nrOfSlots,
+                            uint16_t num_dl_tti,
+                            uint8_t num_dl_symbols,
+                            uint8_t num_ul_symbols,
+                            uint8_t scs,
+                            uint32_t run_core_id_map);
+//void Update_Phy_Timer(uint8_t tdd_period);
+//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
+//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);
+void Phy_Timer_Csu_Config_Nr();
+void Phy_Timer_Csu_Config_Lte();
+
+
+#endif

public/test/testcase_fh/case72/src/cpri_test_case72.s.c

@@ -0,0 +1,630 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+#include "cpri_csu_api.h"
+#include "cpri_test_case72.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "nr_mem_def.h"
+#include "phy_timer_csu_config.h"
+#include "mem_sections.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+
+extern uint32_t compressData0[1920];
+extern uint32_t compressData1[1920];
+extern uint32_t antData0[122880];
+extern uint32_t antData1[122880];
+extern uint32_t antData2[122880];
+extern uint32_t antData3[122880];
+
+//DDR0 uint32_t srcImData[5*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 		gMtimerIntCnt[SCS_MAX_NUM];
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t gCpriTestMode;
+//extern uint32_t           CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_10, OTIC_MAP_FIGURE16);
+
+	return 0;
+}
+
+
+int32_t fh_csu_test_init(void)
+{
+	 Phy_Timer_Csu_Config_Nr();
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+//	uint8_t idSymbol = 0;
+//	uint16_t idBF = 0;
+//	uint16_t idWord = 0;
+
+	uint32_t* pSrcAddr = NULL;
+//	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*13;
+	uint32_t  f7BfCnt = LONGCP_BF_CNT+SHORTCP_BF_CNT*6;//前7symbol
+	uint32_t  b7BfCnt = SHORTCP_BF_CNT*7;//后7symbol
+//	uint32_t  symbolBfCnt = 0;
+	uint32_t  idSlotBf = 0;
+//	uint32_t  val = 0;
+	uint32_t cpyCnt = 0;
+	
+	cpyCnt++;
+	memset_ucp(antData1, 0, (4*122880));//clear 0
+	memset_ucp(antData2, 0, (4*122880));//clear 0
+	memset_ucp(antData3, 0, (4*122880));//clear 0
+	// valid data
+	/********** compress factor*********/
+	for(idID =0 ; idID < 2; idID++)
+	{
+     	for (idSlot = 0; idSlot <= 1; idSlot++)//NR cell
+		{
+			bfByteCnt = 2;
+			if (0 == idSlot)	// even slot
+			{
+				if(0 == idID)
+				{
+					pSrcAddr =compressData0;
+					dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;				
+				}
+				else
+				{
+					dstAddr = SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR;
+					pSrcAddr =compressData1;
+				}			
+			}
+			else				// odd slot
+			{
+				if(0 == idID)
+				{
+					dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
+					pSrcAddr =compressData0 + (1920>>1);
+				}
+				else
+				{
+					dstAddr = SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR;
+					pSrcAddr =compressData1 + (1920>>1);
+				}
+				
+			}
+			dataLen = (bfByteCnt*slotBfCnt); 
+		    memcpy_ucp((void*)dstAddr,(void*)pSrcAddr, dataLen);
+		}
+	}
+	
+	// IQ data	NR 
+	for (idID = 2; idID < 6; idID++)
+	{
+		bfByteCnt = 64*2;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			idSlotBf = 0;
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0;
+							dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1;
+							dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2;
+							dstAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3;
+							dstAddr = SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+					}
+					dataLen = f7BfCnt*bfByteCnt;
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0 + 30752;
+							dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1  + 30752;
+							dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2  + 30752;
+							dstAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3  + 30752;
+							dstAddr = SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+					}
+					dataLen = b7BfCnt*bfByteCnt;
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0 + 61440;
+							dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1  + 61440;
+							dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR+(idID-2)*(f7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2  + 61440;
+							dstAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3  + 61440;
+							dstAddr = SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR+(idID-4)*(f7BfCnt<<7);
+							break;
+					}
+					dataLen = f7BfCnt*bfByteCnt;
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					switch(idID)
+					{
+						case 2:
+							pSrcAddr = antData0 + 61440 + 30752 ;
+							dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;
+						case 3:
+							pSrcAddr = antData1 + 61440 + 30752;
+							dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR+(idID-2)*(b7BfCnt<<7);
+							break;	
+						case 4:
+							pSrcAddr = antData2 + 61440 + 30752;
+							dstAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+						case 5:
+							pSrcAddr = antData3 + 61440 + 30752;
+							dstAddr = SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR+(idID-4)*(b7BfCnt<<7);
+							break;
+					}
+					dataLen = b7BfCnt*bfByteCnt;
+				}
+			    memcpy_ucp((void*)dstAddr,(void*)pSrcAddr, dataLen);
+			}
+		}
+	}
+
+}
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE72_SLOT_NUM>>1); i++)
+	//	for (int32_t i = 7; i < (CPRI_CASE70_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}
+		}
+#endif
+		Cpri_Header_Rx();
+
+	}
+}
+
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	// move data from sm to ddr
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t srcAddr1 = 0;
+	uint32_t realSrcAddr = 0;
+	uint32_t dataLen = 0;
+	uint8_t bitOffset = 0;
+	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13);
+	uint8_t	bfWordCnt = 0;
+
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+	
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)//no agc
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		if ((slotId >=0) && (slotId <= 6))
+		{
+			slotVal = slotId & 0x1;
+#if 1
+			if (2 > i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN; //CPRI_CASE33_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset); //CPRI_CASE33_RX_SLOT_EVEN_AXCDATA_ADDR + ((i-1)<<bitOffset);
+			}
+			dataLen = slotBfCnt << bitOffset;
+#endif
+		}
+		else if (7 == slotId)		// compare S slot, odd slot
+		{
+			bfStart = (LONGCP_BF_CNT+SHORTCP_BF_CNT*9);
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset);//Rx symbol 0~5地址
+				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR;//Rx symbol 6~13地址
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 2B
+				bfWordCnt = 1;
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_COMPRESS_ADDR+slotId*(slotBfCnt<<bitOffset)+i*CPRI_NR7DS2U_RX_DUMMY_COM_LEN;
+				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
+				srcAddr1 = CPRI_NRCELL0_RX_SLOTS_COMPRESS_ADDR + 0x448+(i-2)*((SHORTCP_BF_CNT*4)<<bitOffset);//0x448是cell0的压缩因子的长度
+			}
+			else //if((4 == i)||(5 == i))
+			{
+				bitOffset = 7;	// one BF, 64*2B
+				bfWordCnt = (128>>2);
+				srcAddr = CPRI_NRCELL_RXDUMMY_SLOTS_AXCDATA_ADDR+((i-2)*CPRI_NR7DS2U_RX_DUMMY_AXC_LEN)+slotId*(slotBfCnt<<bitOffset);
+				srcAddr1 = CPRI_NRCELL1_RX_SLOTS_COMPRESS_ADDR +  0x448+(i-4)*((SHORTCP_BF_CNT*4)<<bitOffset);
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (8 == slotId)		// current slot is even slot, compare even slot, slot8
+		{
+			slotVal = 0;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_EVEN_COMPRESS_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR + 0xF00 +((i-2)*(slotBfCnt<<bitOffset));
+			}
+			else// if((4 == i)||(5 == i))
+			{
+			    bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM4_NR_CELL1_EVEN_RX_DATA_ADDR + 0xF00 + ((i-4)*(slotBfCnt<<bitOffset));
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+		else if (9 == slotId)	// compare odd slot, slot9
+		{
+			slotVal = 1;
+			if (0 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;//CPRI_NR7DS2U_RX_SLOT_ODD_COMPRESS_ADDR;
+			}
+			else if(1 == i)
+			{
+				bitOffset = 1;	// one BF, 4B
+				bfWordCnt = 1;
+				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR;
+			}
+			else if((2 == i)||(3 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR +  0xF00 +((i-2)*(slotBfCnt<<bitOffset));
+			}
+			else //if((4 == i)||(5 == i))
+			{
+				bitOffset = 7;	// one BF, 128B
+				bfWordCnt = (128>>2);
+				srcAddr = SM5_NR_CELL1_ODD_RX_DATA_ADDR +  0xF00+ ((i-4)*(slotBfCnt<<bitOffset));
+			}
+			
+			dataLen = slotBfCnt << bitOffset;
+		}
+
+		if (2 > i)	// NR cell compress factor
+		{
+			for (int32_t idBf = 0; idBf <  (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (idVal<<24) | ((idBf<<1)<<8) | (i);
+					
+					//do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+								
+						if ((7 == slotId) && (686 <= idBf))
+						{
+							recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-(bfStart>>1))*bfWordCnt + idWord);
+							if (0 > (idBf-(bfStart>>1)))
+							{
+								gBfStartErr++;
+								debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+							}
+							realSrcAddr = srcAddr1;
+						}
+						else 
+						{
+							recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+							realSrcAddr = srcAddr;
+						}
+					
+						recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+						__ucps2_synch(0);
+						if (recvVal != compVal)
+						{
+							if (gErrSlotIdCnt < 0x100)
+							{
+								debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+								debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+								debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+								debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+								debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+								debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+								debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+							}
+							gErrSlotIdCnt++;
+						}				
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else //if((1 < i)	&& (6 > i))// NR CELL0
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<5)+idWord)<<8) | (idWord);
+					
+//					do_write((CPRI_CASE34_COMPARE_DATA_ADDR+(gCompWordCnt<<2)), compVal);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					__ucps2_synch(0);
+					
+					if ((7 == slotId) && (1372 <= idBf))
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr1 + (idBf-bfStart)*bfWordCnt + idWord);
+						realSrcAddr = srcAddr1;
+						if (0 > (idBf-bfStart))
+						{
+							gBfStartErr++;
+							debug_write((DBG_DDR_IDX_DRV_BASE+1027), gBfStartErr); 
+						}
+					}
+					else 
+					{
+						recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+						realSrcAddr = srcAddr;
+					}
+					
+//					__ucps2_synch(0);
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+					}
+				}
+			}
+		}
+		
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}

public/test/testcase_fh/case72/src/cpri_test_case72_antdata1.s.c

@@ -0,0 +1,5 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t antData1[122880] = {0};
+

public/test/testcase_fh/case72/src/cpri_test_case72_antdata2.s.c

@@ -0,0 +1,5 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t antData2[122880] = {0};
+

public/test/testcase_fh/case72/src/cpri_test_case72_antdata3.s.c

@@ -0,0 +1,5 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t antData3[122880] = {0};
+

public/test/testcase_fh/case80/inc/cpri_test_case80.h

@@ -0,0 +1,36 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE80_SLOT_NUM				20
+
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcase_fh/case80/inc/nr_mem_def.h

@@ -0,0 +1,316 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0-SM1--2M*********************************************/
+//len define
+//SM0
+#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
+#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
+#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K
+
+#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
+#define SM0_RESERVED0_LEN                          0X00000400  //1K
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED1_LEN                          0x00000400  //1K
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED2_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
+#define SM0_RESERVED3_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED4_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED5_LEN                          0x00005900  //22.25
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM1_NR_CELL0_EVNE_RX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_LEN                0x00001400  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_LEN                0x00001400  //5k
+#define SM1_RESERVED0_LEN                          0x00014C00  //83k
+
+#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE)
+#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
+#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+
+#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
+#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
+#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 
+
+#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
+#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
+#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
+#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_ADDR               (SM1_NR_CELL0_EVNE_RX_AGC_ADDR+SM1_NR_CELL0_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_ODD_RX_AGC_ADDR+SM1_NR_CELL0_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_ADDR               (SM1_NR_CELL1_EVNE_RX_AGC_ADDR+SM1_NR_CELL1_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_ADDR              (SM1_NR_CELL1_ODD_RX_AGC_ADDR+SM1_NR_CELL1_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_ADDR               (SM1_NR_CELL0_EVNE_TX_AGC_ADDR+SM1_NR_CELL0_EVNE_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_ADDR              (SM1_NR_CELL0_ODD_TX_AGC_ADDR+SM1_NR_CELL0_ODD_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_ADDR               (SM1_NR_CELL1_EVNE_TX_AGC_ADDR+SM1_NR_CELL1_EVNE_TX_AGC_LEN)  //5k
+#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL1_ODD_TX_AGC_ADDR+SM1_NR_CELL1_ODD_TX_AGC_LEN)
+
+/***************************************SM2-SM5--6M*********************************************/
+//len define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM5_RESERVED0_LEN                          0x00034400  //209k
+#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x0000E000  //56k
+#define SM5_CPRI_CSU_LINK_TABLE_LEN                0x00002000  //8k
+
+#define SM5_ERROR_RECORD_LEN                       0x00003000 //12k
+#define SM5_NR_STATISTIC_LEN                       0x00000120 //288byte
+#define SM5_STATE_RECORD_LEN                       0x000004E0 //1248byte
+#define SM5_COMMON_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PDCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PDSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SSB_DEBUG_LEN                          0x00000400 //1K
+#define SM5_CSIRS_DEBUG_LEN                        0x00000400 //1K
+#define SM5_DEOFDM_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PUCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PUSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PRACH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SRS_DEBUG_LEN                          0x00000400 //1K
+
+#define SM5_ERROR_RECORD_CELL1_LEN                 SM5_ERROR_RECORD_LEN //12k
+#define SM5_NR_STATISTIC_CELL1_LEN                 SM5_NR_STATISTIC_LEN //288byte
+#define SM5_STATE_RECORD_CELL1_LEN                 SM5_STATE_RECORD_LEN //1248byte
+#define SM5_COMMON_DEBUG_CELL1_LEN                 SM5_COMMON_DEBUG_LEN //1K
+#define SM5_PDCCH_DEBUG_CELL1_LEN                  SM5_PDCCH_DEBUG_LEN  //1K
+#define SM5_PDSCH_DEBUG_CELL1_LEN                  SM5_PDSCH_DEBUG_LEN  //1K
+#define SM5_SSB_DEBUG_CELL1_LEN                    SM5_SSB_DEBUG_LEN    //1K
+#define SM5_CSIRS_DEBUG_CELL1_LEN                  SM5_CSIRS_DEBUG_LEN  //1K
+#define SM5_DEOFDM_DEBUG_CELL1_LEN                 SM5_DEOFDM_DEBUG_LEN //1K
+#define SM5_PUCCH_DEBUG_CELL1_LEN                  SM5_PUCCH_DEBUG_LEN  //1K
+#define SM5_PUSCH_DEBUG_CELL1_LEN                  SM5_PUSCH_DEBUG_LEN  //1K
+#define SM5_PRACH_DEBUG_CELL1_LEN                  SM5_PRACH_DEBUG_LEN  //1K
+#define SM5_SRS_DEBUG_CELL1_LEN                    SM5_SRS_DEBUG_LEN    //1K
+
+#define SM5_RESERVED3_LEN                          0x0000D400 //53K
+
+#define SM5_NR_CELL_TRACE_LEN \
+    (SM5_ERROR_RECORD_LEN+SM5_NR_STATISTIC_LEN+SM5_STATE_RECORD_LEN+SM5_COMMON_DEBUG_LEN \
+    +SM5_PDCCH_DEBUG_LEN+SM5_PDSCH_DEBUG_LEN+SM5_SSB_DEBUG_LEN+SM5_CSIRS_DEBUG_LEN+SM5_DEOFDM_DEBUG_LEN \
+    +SM5_PUCCH_DEBUG_LEN+SM5_PUSCH_DEBUG_LEN+SM5_PRACH_DEBUG_LEN+SM5_SRS_DEBUG_LEN)
+
+//addr define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE)
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
+#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
+#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
+#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
+#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)
+
+#define SM5_CPRI_CSU_LINK_TABLE_ADDR               (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)//0x0A4E5A00
+
+#define SM5_ERROR_RECORD_ADDR                      (SM5_CPRI_CSU_LINK_TABLE_ADDR + SM5_CPRI_CSU_LINK_TABLE_LEN)
+#define SM5_NR_STATISTIC_ADDR                      (SM5_ERROR_RECORD_ADDR + SM5_ERROR_RECORD_LEN)
+#define SM5_STATE_RECORD_ADDR                      (SM5_NR_STATISTIC_ADDR + SM5_NR_STATISTIC_LEN)
+#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_ADDR + SM5_STATE_RECORD_LEN)
+#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
+#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
+#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
+#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
+#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
+#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
+#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
+#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
+#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)
+
+#define SM5_ERROR_RECORD_CELL1_ADDR                (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
+#define SM5_NR_STATISTIC_CELL1_ADDR                (SM5_ERROR_RECORD_CELL1_ADDR + SM5_ERROR_RECORD_CELL1_LEN)
+#define SM5_STATE_RECORD_CELL1_ADDR                (SM5_NR_STATISTIC_CELL1_ADDR + SM5_NR_STATISTIC_CELL1_LEN)
+#define SM5_COMMON_DEBUG_CELL1_ADDR                (SM5_STATE_RECORD_CELL1_ADDR + SM5_STATE_RECORD_CELL1_LEN)
+#define SM5_PDCCH_DEBUG_CELL1_ADDR                 (SM5_COMMON_DEBUG_CELL1_ADDR + SM5_COMMON_DEBUG_CELL1_LEN)
+#define SM5_PDSCH_DEBUG_CELL1_ADDR                 (SM5_PDCCH_DEBUG_CELL1_ADDR + SM5_PDCCH_DEBUG_CELL1_LEN)
+#define SM5_SSB_DEBUG_CELL1_ADDR                   (SM5_PDSCH_DEBUG_CELL1_ADDR + SM5_PDSCH_DEBUG_CELL1_LEN)
+#define SM5_CSIRS_DEBUG_CELL1_ADDR                 (SM5_SSB_DEBUG_CELL1_ADDR + SM5_SSB_DEBUG_CELL1_LEN)
+#define SM5_DEOFDM_DEBUG_CELL1_ADDR                (SM5_CSIRS_DEBUG_CELL1_ADDR + SM5_CSIRS_DEBUG_CELL1_LEN)
+#define SM5_PUCCH_DEBUG_CELL1_ADDR                 (SM5_DEOFDM_DEBUG_CELL1_ADDR + SM5_DEOFDM_DEBUG_CELL1_LEN)
+#define SM5_PUSCH_DEBUG_CELL1_ADDR                 (SM5_PUCCH_DEBUG_CELL1_ADDR + SM5_PUCCH_DEBUG_CELL1_LEN)
+#define SM5_PRACH_DEBUG_CELL1_ADDR                 (SM5_PUSCH_DEBUG_CELL1_ADDR + SM5_PUSCH_DEBUG_CELL1_LEN)
+#define SM5_SRS_DEBUG_CELL1_ADDR                   (SM5_PRACH_DEBUG_CELL1_ADDR + SM5_PRACH_DEBUG_CELL1_LEN)
+
+#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_CELL1_ADDR + SM5_SRS_DEBUG_CELL1_LEN)
+
+#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
+/**************************************DDR****************************************************/
+/*******************************PUSCH HARQ 0x14400000-0x84C00000******************************/
+#define DDR_NR_CELL0_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL0_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+#define DDR_NR_CELL1_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL1_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+//0x14400000-0x4C800000
+#define DDR_NR_CELL0_SOFTBIT_PING_ADDR       (0x14400000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_ADDR       (DDR_NR_CELL0_SOFTBIT_PING_ADDR+DDR_NR_CELL0_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL0_SOFTBIT_PANG_ADDR+DDR_NR_CELL0_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_ADDR           (DDR_NR_CELL0_MME_FREQ_CPTS_ADDR+DDR_NR_CELL0_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL0_RNTI_ADDR               (DDR_NR_CELL0_SCRAMBLE_ADDR+DDR_NR_CELL0_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_ADDR          (DDR_NR_CELL0_RNTI_ADDR+DDR_NR_CELL0_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_ADDR          (DDR_NR_CELL0_HARQ_INFO_ADDR+DDR_NR_CELL0_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_ADDR             (DDR_NR_CELL0_TB_DECODE_ADDR+DDR_NR_CELL0_TB_DECODE_LEN)   //(500*1024)
+
+//0x4C800000-0x84C00000
+#define DDR_NR_CELL1_SOFTBIT_PING_ADDR       (0x4C800000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_ADDR       (DDR_NR_CELL1_SOFTBIT_PING_ADDR+DDR_NR_CELL1_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL1_SOFTBIT_PANG_ADDR+DDR_NR_CELL1_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_ADDR           (DDR_NR_CELL1_MME_FREQ_CPTS_ADDR+DDR_NR_CELL1_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL1_RNTI_ADDR               (DDR_NR_CELL1_SCRAMBLE_ADDR+DDR_NR_CELL1_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_ADDR          (DDR_NR_CELL1_RNTI_ADDR+DDR_NR_CELL1_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_ADDR          (DDR_NR_CELL1_HARQ_INFO_ADDR+DDR_NR_CELL1_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_ADDR             (DDR_NR_CELL1_TB_DECODE_ADDR+DDR_NR_CELL1_TB_DECODE_LEN)   //(500*1024)
+
+/*******************************共180+192M可用0x84C00000-0x9C000000***************************/
+//len
+#define DDR_NR_CELL0_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_CELL1_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
+#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
+#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
+#define DDR_TEST_MAC_DL_DATA_BUF_LEN   (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+#define DDR_WRITE_MONITOR_LEN          (0x400000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_LEN           (0X400000)//预留4M空间给读DDR检查功能
+
+//addr
+#define DDR_PHY_BASE                         (0x84C00000)
+#define DDR_TEST_MAC_NR_CELL0_RX_DATA_ADDR   (0x84C00000)//0x84C00000 ~ 0x85100000 
+#define DDR_TEST_MAC_NR_CELL1_RX_DATA_ADDR   (0x85100000)//0x85100000 ~ 0x85600000
+
+#define DDR_PHY_RECORD_ADDR                  (0x85600000)//0x85600000 ~ 0x86000000
+#define DDR_NR_DL_RECORD_ADDR                (0x85600000)//0x85600000 ~ 0x87600000 32M
+#define DDR_NR_UL_RECORD_ADDR                (0x87600000)//0x87600000 ~ 0x89600000 32M
+#define DDR_NR_DL1_RECORD_ADDR               (0x89600000)//0x89600000 ~ 0x8B600000 32M
+#define DDR_NR_UL1_RECORD_ADDR               (0x8B600000)//0x8B600000 ~ 0x8D600000 32M
+
+#define DDR_TEST_MAC_DL_DATA_BUF_ADDR        (0x8D600000)//testmac预留20M,缓存DL的IQ数据      		//0x8D600000 ~ 0x8EA00000
+
+#define DDR_WRITE_MONITOR_ADDR               (0x8EA00000)//预留4M空间给写DDR检查功能					//0x8B400000 ~ 0X8EE00000
+#define DDR_READ_MONITOR_ADDR                (0x8EE00000)//预留4M空间给读DDR检查功能
+
+#define DDR_MAX_ADDR                         (0x90000000)
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+//void Config_Cpri_Csu_Lte();
+void Config_Cpri_Csu_Nr(uint8_t slot_format);
+
+
+#endif
+

public/test/testcase_fh/case80/inc/phy_timer_csu_config.h

@@ -0,0 +1,114 @@
+/******************************************************************
+ * @file  phy_timer_csu_config.h
+ * @brief:    [file description] 
+ * @author: guicheng.liu
+ * @Date 2022年7月7日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
+ * Change_date         Owner         Change_content
+ * 2022年7月7日        guicheng.liu       create file
+
+*****************************************************************/
+
+#ifndef     FPHY_TIMER_CSU_CONFIG_H
+#define     FPHY_TIMER_CSU_CONFIG_H
+//#include <type_define.h>
+//#include "phy_nr_context.h"
+//#include "drv_rfm.h"
+
+
+#include "typedef.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+
+//#define CPRI_LINK_START_ADDR						0x721E000 //ECS SM后8K 0x721E000- 0x7220000
+#define CPRI_NR_FDD_LINK_START_ADDR                 SM5_CPRI_CSU_LINK_TABLE_ADDR//更换为SM的地址
+
+#define NR_LONGCP_SAM_CNT								4448
+#define NR_SHORTCP_SAM_CNT								4384
+
+typedef struct
+{
+    uint16_t period;//=t_us*num_t;
+    uint16_t rev;
+
+    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
+    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
+}timer_info_t;
+
+typedef struct
+{
+    uint8_t flag;//0:default timer, 1:inuse timer
+    uint8_t rev[3];
+
+    timer_info_t default_timer;
+    timer_info_t inuse_timer;
+}phy_timer_t;
+
+typedef struct
+{
+    uint8_t total_ants;
+    uint8_t scs;
+    uint8_t num_dl_symbols;
+    uint8_t rev;
+
+    uint16_t num_dl_tti;
+    uint16_t rev1;
+
+    phy_timer_config_ind_t jesd_timer;
+    phy_timer_config_ind_t cpri_timer;
+}phy_csu_timer_t;
+
+typedef struct
+{
+    uint32_t state;//0:idle, 1:configured
+
+    //tx的链表地址
+    uint32_t tx0_even_f7_link_addr;
+    uint32_t tx0_even_b7_link_addr;
+    uint32_t tx0_odd_f7_link_addr;
+    uint32_t tx0_odd_b7_link_addr;
+    uint32_t tx0_s_link_addr;
+    uint32_t tx0_1st_dummy_link_addr;
+    uint32_t tx0_2nd_dummy_link_addr;
+
+    //rx的链表地址
+    uint32_t rx0_first_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot尾部的数据
+    uint32_t rx0_dummy_link_addr;
+    uint32_t rx0_s_link_addr;
+    uint32_t rx0_normal0_link_addr;
+    uint32_t rx0_normal1_link_addr;
+    uint32_t rx0_last_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot头部的数据
+}phy_csu_link_info_t;
+
+
+void Phy_Timer_Csu_Init();
+
+//void Csu_Dma_Init();
+//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx0_ants, 
+//                                uint16_t num_rx_tti);
+//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx1_ants, 
+//                                uint16_t num_rx_tti);
+void Config_Csu_Timer(uint16_t dl_bw,
+                            uint16_t num_tx_ants,
+                            uint8_t nrOfSlots,
+                            uint16_t num_dl_tti,
+                            uint8_t num_dl_symbols,
+                            uint8_t num_ul_symbols,
+                            uint8_t scs,
+                            uint32_t run_core_id_map);
+//void Update_Phy_Timer(uint8_t tdd_period);
+
+//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
+//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);
+
+
+#endif
+

public/test/testcase_fh/case80/readme.txt

@@ -0,0 +1,3 @@
+场景：OTIC协议中图12，10g速率下4T4R单NR小区
+模式：NR FDD
+csu时隙不带偏移的回环校验

public/test/testcase_fh/case80/src/cpri_test_case80.s.c

@@ -0,0 +1,514 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case80.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+
+extern uint32_t compressData[3840];
+extern uint32_t antData0[61440*2];
+extern uint32_t antData1[61440*2];
+extern uint32_t antData2[61440*2];
+extern uint32_t antData3[61440*2];
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);//NR TDD和FDD的mapping是一样的
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Nr(0);
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint8_t idSymbol = 0;
+	uint16_t idBF = 0;
+	uint16_t idWord = 0;
+
+	uint32_t* pSrcAddr = 0;
+//	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t  f7BfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*6)*2;
+	uint32_t  b7BfCnt = (SHORTCP_BF_CNT*7)*2;
+	uint32_t  symbolBfCnt = 0;
+	uint32_t  idSlotBf = 0;
+	uint32_t  val = 0;
+	
+	// valid data
+	// compress factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;
+		
+		if (0 == idSlot)	// even slot
+		{		
+			dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
+		}
+		else				// odd slot
+		{			
+			dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
+		}
+		pSrcAddr = ((uint32_t*)dstAddr);
+		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
+		{
+			val = (idSlot<<28) | (0<<24) | ((idBF<<1)<<8) | (0);
+			do_write(((uint32_t)pSrcAddr), val);			
+			pSrcAddr++;
+		}
+	//	dataLen = (bfByteCnt*slotBfCnt); 
+	
+	//	memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+	}
+
+	// IQ data	
+	for (idID = 1; idID < 5; idID++)
+	{
+		bfByteCnt = 64;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			idSlotBf = 0;
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				pSrcAddr = ((uint32_t*)dstAddr);
+				for (idSymbol = 0; idSymbol < 7; idSymbol++)
+				{
+					//pSrcAddr = srcImData;
+					
+					if ((0 == idSymbol) && (0 == idSymbolBlock))
+					{
+						symbolBfCnt = (LONGCP_BF_CNT*2);
+					}
+					else
+					{
+						symbolBfCnt = (SHORTCP_BF_CNT*2);
+					}
+					for (idBF = 0; idBF < symbolBfCnt; idBF++)	// basic frame
+			 		{
+						for (idWord = 0; idWord < (bfByteCnt>>2); idWord++)
+						{
+								val = (idSlot<<28) | (idID<<24) | ((idSlotBf++)<<8) | (idWord);
+								//*pSrcAddr = val;
+								do_write(((uint32_t)pSrcAddr), val);
+								pSrcAddr++;
+						}
+			 		}
+					dataLen = symbolBfCnt*bfByteCnt;
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//					cpyCnt++;
+					//memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+					//dstAddr += dataLen;
+				}
+			}
+		}
+	}
+	
+}
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE80_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+#endif
+		Cpri_Header_Rx();
+	}
+}
+
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t totalSlotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint8_t	bfWordCnt = 0;
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM3_NR_CELL0_ODD_RX_DATA_ADDR + (2*slotBfCnt) + ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_ODD_RX_AGC_ADDR;
+			}
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + (2*slotBfCnt)+ ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVNE_RX_AGC_ADDR;
+			}
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					//compVal = do_read_volatile(compressData+idBf*bfWordCnt + idWord);//Nr_CompressData[idBf*bfWordCnt + idWord];
+					compVal = (slotVal<<28) | (idVal<<24) | ((idBf<<1)<<8) | (idWord);
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+					#if 1
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+					#endif
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 <= i) && (2 >= i))		// 天线0,1
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+				#if 0
+					if(1 == i)//天线0
+					{
+						compVal = do_read_volatile(antData0+idBf*bfWordCnt + idWord);//Lte_antData[idBf*bfWordCnt + idWord];
+					}
+					else//天线1
+					{
+						compVal = do_read_volatile(antData1+idBf*bfWordCnt + idWord);//Nr_antData23[idBf*bfWordCnt + idWord];
+					}
+				#endif
+					compVal = (slotVal<<28) | (idVal<<24) | (((idBf<<4)+idWord)<<8) | (idWord);
+				
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else
+		{
+		}
+	
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}

public/test/testcase_fh/case81/inc/cpri_test_case81.h

@@ -0,0 +1,36 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE81_SLOT_NUM				20
+
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcase_fh/case81/inc/nr_mem_def.h

@@ -0,0 +1,316 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0-SM1--2M*********************************************/
+//len define
+//SM0
+#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
+#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
+#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K
+
+#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
+#define SM0_RESERVED0_LEN                          0X00000400  //1K
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED1_LEN                          0x00000400  //1K
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED2_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
+#define SM0_RESERVED3_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED4_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED5_LEN                          0x00005900  //22.25
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM1_NR_CELL0_EVNE_RX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_LEN                0x00001400  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_LEN                0x00001400  //5k
+#define SM1_RESERVED0_LEN                          0x00014C00  //83k
+
+#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE)
+#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
+#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+
+#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
+#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
+#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 
+
+#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
+#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
+#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
+#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_ADDR               (SM1_NR_CELL0_EVNE_RX_AGC_ADDR+SM1_NR_CELL0_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_ODD_RX_AGC_ADDR+SM1_NR_CELL0_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_ADDR               (SM1_NR_CELL1_EVNE_RX_AGC_ADDR+SM1_NR_CELL1_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_ADDR              (SM1_NR_CELL1_ODD_RX_AGC_ADDR+SM1_NR_CELL1_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_ADDR               (SM1_NR_CELL0_EVNE_TX_AGC_ADDR+SM1_NR_CELL0_EVNE_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_ADDR              (SM1_NR_CELL0_ODD_TX_AGC_ADDR+SM1_NR_CELL0_ODD_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_ADDR               (SM1_NR_CELL1_EVNE_TX_AGC_ADDR+SM1_NR_CELL1_EVNE_TX_AGC_LEN)  //5k
+#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL1_ODD_TX_AGC_ADDR+SM1_NR_CELL1_ODD_TX_AGC_LEN)
+
+/***************************************SM2-SM5--6M*********************************************/
+//len define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM5_RESERVED0_LEN                          0x00034400  //209k
+#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x0000E000  //56k
+#define SM5_CPRI_CSU_LINK_TABLE_LEN                0x00002000  //8k
+
+#define SM5_ERROR_RECORD_LEN                       0x00003000 //12k
+#define SM5_NR_STATISTIC_LEN                       0x00000120 //288byte
+#define SM5_STATE_RECORD_LEN                       0x000004E0 //1248byte
+#define SM5_COMMON_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PDCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PDSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SSB_DEBUG_LEN                          0x00000400 //1K
+#define SM5_CSIRS_DEBUG_LEN                        0x00000400 //1K
+#define SM5_DEOFDM_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PUCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PUSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PRACH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SRS_DEBUG_LEN                          0x00000400 //1K
+
+#define SM5_ERROR_RECORD_CELL1_LEN                 SM5_ERROR_RECORD_LEN //12k
+#define SM5_NR_STATISTIC_CELL1_LEN                 SM5_NR_STATISTIC_LEN //288byte
+#define SM5_STATE_RECORD_CELL1_LEN                 SM5_STATE_RECORD_LEN //1248byte
+#define SM5_COMMON_DEBUG_CELL1_LEN                 SM5_COMMON_DEBUG_LEN //1K
+#define SM5_PDCCH_DEBUG_CELL1_LEN                  SM5_PDCCH_DEBUG_LEN  //1K
+#define SM5_PDSCH_DEBUG_CELL1_LEN                  SM5_PDSCH_DEBUG_LEN  //1K
+#define SM5_SSB_DEBUG_CELL1_LEN                    SM5_SSB_DEBUG_LEN    //1K
+#define SM5_CSIRS_DEBUG_CELL1_LEN                  SM5_CSIRS_DEBUG_LEN  //1K
+#define SM5_DEOFDM_DEBUG_CELL1_LEN                 SM5_DEOFDM_DEBUG_LEN //1K
+#define SM5_PUCCH_DEBUG_CELL1_LEN                  SM5_PUCCH_DEBUG_LEN  //1K
+#define SM5_PUSCH_DEBUG_CELL1_LEN                  SM5_PUSCH_DEBUG_LEN  //1K
+#define SM5_PRACH_DEBUG_CELL1_LEN                  SM5_PRACH_DEBUG_LEN  //1K
+#define SM5_SRS_DEBUG_CELL1_LEN                    SM5_SRS_DEBUG_LEN    //1K
+
+#define SM5_RESERVED3_LEN                          0x0000D400 //53K
+
+#define SM5_NR_CELL_TRACE_LEN \
+    (SM5_ERROR_RECORD_LEN+SM5_NR_STATISTIC_LEN+SM5_STATE_RECORD_LEN+SM5_COMMON_DEBUG_LEN \
+    +SM5_PDCCH_DEBUG_LEN+SM5_PDSCH_DEBUG_LEN+SM5_SSB_DEBUG_LEN+SM5_CSIRS_DEBUG_LEN+SM5_DEOFDM_DEBUG_LEN \
+    +SM5_PUCCH_DEBUG_LEN+SM5_PUSCH_DEBUG_LEN+SM5_PRACH_DEBUG_LEN+SM5_SRS_DEBUG_LEN)
+
+//addr define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE)
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
+#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
+#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
+#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
+#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)
+
+#define SM5_CPRI_CSU_LINK_TABLE_ADDR               (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)//0x0A4E5A00
+
+#define SM5_ERROR_RECORD_ADDR                      (SM5_CPRI_CSU_LINK_TABLE_ADDR + SM5_CPRI_CSU_LINK_TABLE_LEN)
+#define SM5_NR_STATISTIC_ADDR                      (SM5_ERROR_RECORD_ADDR + SM5_ERROR_RECORD_LEN)
+#define SM5_STATE_RECORD_ADDR                      (SM5_NR_STATISTIC_ADDR + SM5_NR_STATISTIC_LEN)
+#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_ADDR + SM5_STATE_RECORD_LEN)
+#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
+#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
+#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
+#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
+#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
+#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
+#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
+#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
+#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)
+
+#define SM5_ERROR_RECORD_CELL1_ADDR                (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
+#define SM5_NR_STATISTIC_CELL1_ADDR                (SM5_ERROR_RECORD_CELL1_ADDR + SM5_ERROR_RECORD_CELL1_LEN)
+#define SM5_STATE_RECORD_CELL1_ADDR                (SM5_NR_STATISTIC_CELL1_ADDR + SM5_NR_STATISTIC_CELL1_LEN)
+#define SM5_COMMON_DEBUG_CELL1_ADDR                (SM5_STATE_RECORD_CELL1_ADDR + SM5_STATE_RECORD_CELL1_LEN)
+#define SM5_PDCCH_DEBUG_CELL1_ADDR                 (SM5_COMMON_DEBUG_CELL1_ADDR + SM5_COMMON_DEBUG_CELL1_LEN)
+#define SM5_PDSCH_DEBUG_CELL1_ADDR                 (SM5_PDCCH_DEBUG_CELL1_ADDR + SM5_PDCCH_DEBUG_CELL1_LEN)
+#define SM5_SSB_DEBUG_CELL1_ADDR                   (SM5_PDSCH_DEBUG_CELL1_ADDR + SM5_PDSCH_DEBUG_CELL1_LEN)
+#define SM5_CSIRS_DEBUG_CELL1_ADDR                 (SM5_SSB_DEBUG_CELL1_ADDR + SM5_SSB_DEBUG_CELL1_LEN)
+#define SM5_DEOFDM_DEBUG_CELL1_ADDR                (SM5_CSIRS_DEBUG_CELL1_ADDR + SM5_CSIRS_DEBUG_CELL1_LEN)
+#define SM5_PUCCH_DEBUG_CELL1_ADDR                 (SM5_DEOFDM_DEBUG_CELL1_ADDR + SM5_DEOFDM_DEBUG_CELL1_LEN)
+#define SM5_PUSCH_DEBUG_CELL1_ADDR                 (SM5_PUCCH_DEBUG_CELL1_ADDR + SM5_PUCCH_DEBUG_CELL1_LEN)
+#define SM5_PRACH_DEBUG_CELL1_ADDR                 (SM5_PUSCH_DEBUG_CELL1_ADDR + SM5_PUSCH_DEBUG_CELL1_LEN)
+#define SM5_SRS_DEBUG_CELL1_ADDR                   (SM5_PRACH_DEBUG_CELL1_ADDR + SM5_PRACH_DEBUG_CELL1_LEN)
+
+#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_CELL1_ADDR + SM5_SRS_DEBUG_CELL1_LEN)
+
+#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
+/**************************************DDR****************************************************/
+/*******************************PUSCH HARQ 0x14400000-0x84C00000******************************/
+#define DDR_NR_CELL0_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL0_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+#define DDR_NR_CELL1_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL1_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+//0x14400000-0x4C800000
+#define DDR_NR_CELL0_SOFTBIT_PING_ADDR       (0x14400000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_ADDR       (DDR_NR_CELL0_SOFTBIT_PING_ADDR+DDR_NR_CELL0_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL0_SOFTBIT_PANG_ADDR+DDR_NR_CELL0_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_ADDR           (DDR_NR_CELL0_MME_FREQ_CPTS_ADDR+DDR_NR_CELL0_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL0_RNTI_ADDR               (DDR_NR_CELL0_SCRAMBLE_ADDR+DDR_NR_CELL0_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_ADDR          (DDR_NR_CELL0_RNTI_ADDR+DDR_NR_CELL0_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_ADDR          (DDR_NR_CELL0_HARQ_INFO_ADDR+DDR_NR_CELL0_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_ADDR             (DDR_NR_CELL0_TB_DECODE_ADDR+DDR_NR_CELL0_TB_DECODE_LEN)   //(500*1024)
+
+//0x4C800000-0x84C00000
+#define DDR_NR_CELL1_SOFTBIT_PING_ADDR       (0x4C800000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_ADDR       (DDR_NR_CELL1_SOFTBIT_PING_ADDR+DDR_NR_CELL1_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL1_SOFTBIT_PANG_ADDR+DDR_NR_CELL1_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_ADDR           (DDR_NR_CELL1_MME_FREQ_CPTS_ADDR+DDR_NR_CELL1_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL1_RNTI_ADDR               (DDR_NR_CELL1_SCRAMBLE_ADDR+DDR_NR_CELL1_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_ADDR          (DDR_NR_CELL1_RNTI_ADDR+DDR_NR_CELL1_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_ADDR          (DDR_NR_CELL1_HARQ_INFO_ADDR+DDR_NR_CELL1_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_ADDR             (DDR_NR_CELL1_TB_DECODE_ADDR+DDR_NR_CELL1_TB_DECODE_LEN)   //(500*1024)
+
+/*******************************共180+192M可用0x84C00000-0x9C000000***************************/
+//len
+#define DDR_NR_CELL0_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_CELL1_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
+#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
+#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
+#define DDR_TEST_MAC_DL_DATA_BUF_LEN   (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+#define DDR_WRITE_MONITOR_LEN          (0x400000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_LEN           (0X400000)//预留4M空间给读DDR检查功能
+
+//addr
+#define DDR_PHY_BASE                         (0x84C00000)
+#define DDR_TEST_MAC_NR_CELL0_RX_DATA_ADDR   (0x84C00000)//0x84C00000 ~ 0x85100000 
+#define DDR_TEST_MAC_NR_CELL1_RX_DATA_ADDR   (0x85100000)//0x85100000 ~ 0x85600000
+
+#define DDR_PHY_RECORD_ADDR                  (0x85600000)//0x85600000 ~ 0x86000000
+#define DDR_NR_DL_RECORD_ADDR                (0x85600000)//0x85600000 ~ 0x87600000 32M
+#define DDR_NR_UL_RECORD_ADDR                (0x87600000)//0x87600000 ~ 0x89600000 32M
+#define DDR_NR_DL1_RECORD_ADDR               (0x89600000)//0x89600000 ~ 0x8B600000 32M
+#define DDR_NR_UL1_RECORD_ADDR               (0x8B600000)//0x8B600000 ~ 0x8D600000 32M
+
+#define DDR_TEST_MAC_DL_DATA_BUF_ADDR        (0x8D600000)//testmac预留20M,缓存DL的IQ数据      		//0x8D600000 ~ 0x8EA00000
+
+#define DDR_WRITE_MONITOR_ADDR               (0x8EA00000)//预留4M空间给写DDR检查功能					//0x8B400000 ~ 0X8EE00000
+#define DDR_READ_MONITOR_ADDR                (0x8EE00000)//预留4M空间给读DDR检查功能
+
+#define DDR_MAX_ADDR                         (0x90000000)
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+//void Config_Cpri_Csu_Lte();
+void Config_Cpri_Csu_Nr(uint8_t slot_format);
+
+
+#endif
+

public/test/testcase_fh/case81/inc/phy_timer_csu_config.h

@@ -0,0 +1,114 @@
+/******************************************************************
+ * @file  phy_timer_csu_config.h
+ * @brief:    [file description] 
+ * @author: guicheng.liu
+ * @Date 2022年7月7日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
+ * Change_date         Owner         Change_content
+ * 2022年7月7日        guicheng.liu       create file
+
+*****************************************************************/
+
+#ifndef     FPHY_TIMER_CSU_CONFIG_H
+#define     FPHY_TIMER_CSU_CONFIG_H
+//#include <type_define.h>
+//#include "phy_nr_context.h"
+//#include "drv_rfm.h"
+
+
+#include "typedef.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+
+//#define CPRI_LINK_START_ADDR						0x721E000 //ECS SM后8K 0x721E000- 0x7220000
+#define CPRI_NR_FDD_LINK_START_ADDR                 SM5_CPRI_CSU_LINK_TABLE_ADDR//更换为SM的地址
+
+#define NR_LONGCP_SAM_CNT								4448
+#define NR_SHORTCP_SAM_CNT								4384
+
+typedef struct
+{
+    uint16_t period;//=t_us*num_t;
+    uint16_t rev;
+
+    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
+    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
+}timer_info_t;
+
+typedef struct
+{
+    uint8_t flag;//0:default timer, 1:inuse timer
+    uint8_t rev[3];
+
+    timer_info_t default_timer;
+    timer_info_t inuse_timer;
+}phy_timer_t;
+
+typedef struct
+{
+    uint8_t total_ants;
+    uint8_t scs;
+    uint8_t num_dl_symbols;
+    uint8_t rev;
+
+    uint16_t num_dl_tti;
+    uint16_t rev1;
+
+    phy_timer_config_ind_t jesd_timer;
+    phy_timer_config_ind_t cpri_timer;
+}phy_csu_timer_t;
+
+typedef struct
+{
+    uint32_t state;//0:idle, 1:configured
+
+    //tx的链表地址
+    uint32_t tx0_even_f7_link_addr;
+    uint32_t tx0_even_b7_link_addr;
+    uint32_t tx0_odd_f7_link_addr;
+    uint32_t tx0_odd_b7_link_addr;
+    uint32_t tx0_s_link_addr;
+    uint32_t tx0_1st_dummy_link_addr;
+    uint32_t tx0_2nd_dummy_link_addr;
+
+    //rx的链表地址
+    uint32_t rx0_first_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot尾部的数据
+    uint32_t rx0_dummy_link_addr;
+    uint32_t rx0_s_link_addr;
+    uint32_t rx0_normal0_link_addr;
+    uint32_t rx0_normal1_link_addr;
+    uint32_t rx0_last_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot头部的数据
+}phy_csu_link_info_t;
+
+
+void Phy_Timer_Csu_Init();
+
+//void Csu_Dma_Init();
+//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx0_ants, 
+//                                uint16_t num_rx_tti);
+//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx1_ants, 
+//                                uint16_t num_rx_tti);
+void Config_Csu_Timer(uint16_t dl_bw,
+                            uint16_t num_tx_ants,
+                            uint8_t nrOfSlots,
+                            uint16_t num_dl_tti,
+                            uint8_t num_dl_symbols,
+                            uint8_t num_ul_symbols,
+                            uint8_t scs,
+                            uint32_t run_core_id_map);
+//void Update_Phy_Timer(uint8_t tdd_period);
+
+//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
+//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);
+
+
+#endif
+

public/test/testcase_fh/case81/readme.txt

@@ -0,0 +1,3 @@
+场景：OTIC协议中图12，10g速率下4T4R单NR小区
+模式：NR FDD
+csu带Rx时隙带偏移的回环校验

public/test/testcase_fh/case81/src/cpri_test_case81.s.c

@@ -0,0 +1,522 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case81.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+
+extern uint32_t compressData[3840];
+extern uint32_t antData0[61440*2];
+extern uint32_t antData1[61440*2];
+extern uint32_t antData2[61440*2];
+extern uint32_t antData3[61440*2];
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);//NR TDD和FDD的mapping是一样的
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Nr(0);
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint8_t idSymbol = 0;
+	uint16_t idBF = 0;
+	uint16_t idWord = 0;
+
+	uint32_t* pSrcAddr = 0;
+//	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t  f7BfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*6)*2;
+	uint32_t  b7BfCnt = (SHORTCP_BF_CNT*7)*2;
+	uint32_t  symbolBfCnt = 0;
+	uint32_t  idSlotBf = 0;
+	uint32_t  val = 0;
+	
+	// valid data
+	// compress factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;
+		
+		if (0 == idSlot)	// even slot
+		{		
+			dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
+		}
+		else				// odd slot
+		{			
+			dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
+		}
+		pSrcAddr = ((uint32_t*)dstAddr);
+		for (idBF = 0; idBF < (slotBfCnt>>1); idBF++)	// basic frame
+		{
+			val = (idSlot<<28) | (0<<24) | ((idBF<<1)<<8) | (0);
+			do_write(((uint32_t)pSrcAddr), val);			
+			pSrcAddr++;
+		}
+	//	dataLen = (bfByteCnt*slotBfCnt); 
+	
+	//	memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+	}
+
+	// IQ data	
+	for (idID = 1; idID < 5; idID++)
+	{
+		bfByteCnt = 64;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			idSlotBf = 0;
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR+(idID-1)*(f7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					//dstAddr = CPRI_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR+(idID-1)*(b7BfCnt<<6);
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				pSrcAddr = ((uint32_t*)dstAddr);
+				for (idSymbol = 0; idSymbol < 7; idSymbol++)
+				{
+					//pSrcAddr = srcImData;
+					
+					if ((0 == idSymbol) && (0 == idSymbolBlock))
+					{
+						symbolBfCnt = (LONGCP_BF_CNT*2);
+					}
+					else
+					{
+						symbolBfCnt = (SHORTCP_BF_CNT*2);
+					}
+					for (idBF = 0; idBF < symbolBfCnt; idBF++)	// basic frame
+			 		{
+						for (idWord = 0; idWord < (bfByteCnt>>2); idWord++)
+						{
+								val = (idSlot<<28) | (idID<<24) | ((idSlotBf++)<<8) | (idWord);
+								//*pSrcAddr = val;
+								do_write(((uint32_t)pSrcAddr), val);
+								pSrcAddr++;
+						}
+			 		}
+					dataLen = symbolBfCnt*bfByteCnt;
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcImData); // 0x310
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+//					debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+//					cpyCnt++;
+					//memcpy_ucp((void*)dstAddr,(void*)srcImData, dataLen);
+					//dstAddr += dataLen;
+				}
+			}
+		}
+	}
+	
+}
+
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE81_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+		#endif
+		Cpri_Header_Rx();
+	}
+}
+
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+//	uint32_t CompAddr = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t totalSlotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint8_t	bfWordCnt = 0;
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+	uint32_t idBf_temp = 0;
+	uint32_t slotVal_last4Bf = 0;
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		idBf_temp = 0;
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			slotVal_last4Bf = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;
+			//	CompAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM3_NR_CELL0_ODD_RX_DATA_ADDR + (2*slotBfCnt) + ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_ODD_RX_AGC_ADDR;
+			}
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			slotVal_last4Bf = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;
+			//	CompAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + (2*slotBfCnt)+ ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVNE_RX_AGC_ADDR;
+			}
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(idBf < ((slotBfCnt-4)>>1))//按照csu配置，Rx csu延迟了4BF
+					{
+						compVal = (slotVal<<28) | (idVal<<24) | (((idBf+2)<<1)<<8) | (idWord);
+					}
+					else
+					{
+						compVal = (slotVal_last4Bf<<28) | (idVal<<24) | (((idBf_temp++)<<1)<<8) | (idWord);
+					}
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 <= i) && (2 >= i))		// 天线0,1
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(idBf < (slotBfCnt-4))//按照csu配置，Rx csu延迟了4BF
+					{
+						compVal = (slotVal<<28) | (idVal<<24) | ((((idBf + 4)<<4)+idWord)<<8) | (idWord);
+					}
+					else
+					{						
+						compVal = (slotVal_last4Bf<<28) | (idVal<<24) | (((idBf_temp++))<<8)| (idWord);
+					}
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else
+		{
+		}
+	
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}

public/test/testcase_fh/case82/inc/cpri_test_case82.h

@@ -0,0 +1,36 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE82_SLOT_NUM				20
+
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcase_fh/case82/inc/nr_mem_def.h

@@ -0,0 +1,315 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0-SM1--2M*********************************************/
+//len define
+//SM0
+#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
+#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
+#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K
+
+#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
+#define SM0_RESERVED0_LEN                          0X00000400  //1K
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED1_LEN                          0x00000400  //1K
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED2_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
+#define SM0_RESERVED3_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED4_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED5_LEN                          0x00005900  //22.25
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM1_NR_CELL0_EVNE_RX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_LEN                0x00001400  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_LEN                0x00001400  //5k
+#define SM1_RESERVED0_LEN                          0x00014C00  //83k
+
+#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE)
+#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
+#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+
+#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
+#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
+#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 
+
+#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
+#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
+#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
+#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_ADDR               (SM1_NR_CELL0_EVNE_RX_AGC_ADDR+SM1_NR_CELL0_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_ODD_RX_AGC_ADDR+SM1_NR_CELL0_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_ADDR               (SM1_NR_CELL1_EVNE_RX_AGC_ADDR+SM1_NR_CELL1_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_ADDR              (SM1_NR_CELL1_ODD_RX_AGC_ADDR+SM1_NR_CELL1_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_ADDR               (SM1_NR_CELL0_EVNE_TX_AGC_ADDR+SM1_NR_CELL0_EVNE_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_ADDR              (SM1_NR_CELL0_ODD_TX_AGC_ADDR+SM1_NR_CELL0_ODD_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_ADDR               (SM1_NR_CELL1_EVNE_TX_AGC_ADDR+SM1_NR_CELL1_EVNE_TX_AGC_LEN)  //5k
+#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL1_ODD_TX_AGC_ADDR+SM1_NR_CELL1_ODD_TX_AGC_LEN)
+
+/***************************************SM2-SM5--6M*********************************************/
+//len define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM5_RESERVED0_LEN                          0x00034400  //209k
+#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x0000E000  //56k
+#define SM5_CPRI_CSU_LINK_TABLE_LEN                0x00002000  //8k
+
+#define SM5_ERROR_RECORD_LEN                       0x00003000 //12k
+#define SM5_NR_STATISTIC_LEN                       0x00000120 //288byte
+#define SM5_STATE_RECORD_LEN                       0x000004E0 //1248byte
+#define SM5_COMMON_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PDCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PDSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SSB_DEBUG_LEN                          0x00000400 //1K
+#define SM5_CSIRS_DEBUG_LEN                        0x00000400 //1K
+#define SM5_DEOFDM_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PUCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PUSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PRACH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SRS_DEBUG_LEN                          0x00000400 //1K
+
+#define SM5_ERROR_RECORD_CELL1_LEN                 SM5_ERROR_RECORD_LEN //12k
+#define SM5_NR_STATISTIC_CELL1_LEN                 SM5_NR_STATISTIC_LEN //288byte
+#define SM5_STATE_RECORD_CELL1_LEN                 SM5_STATE_RECORD_LEN //1248byte
+#define SM5_COMMON_DEBUG_CELL1_LEN                 SM5_COMMON_DEBUG_LEN //1K
+#define SM5_PDCCH_DEBUG_CELL1_LEN                  SM5_PDCCH_DEBUG_LEN  //1K
+#define SM5_PDSCH_DEBUG_CELL1_LEN                  SM5_PDSCH_DEBUG_LEN  //1K
+#define SM5_SSB_DEBUG_CELL1_LEN                    SM5_SSB_DEBUG_LEN    //1K
+#define SM5_CSIRS_DEBUG_CELL1_LEN                  SM5_CSIRS_DEBUG_LEN  //1K
+#define SM5_DEOFDM_DEBUG_CELL1_LEN                 SM5_DEOFDM_DEBUG_LEN //1K
+#define SM5_PUCCH_DEBUG_CELL1_LEN                  SM5_PUCCH_DEBUG_LEN  //1K
+#define SM5_PUSCH_DEBUG_CELL1_LEN                  SM5_PUSCH_DEBUG_LEN  //1K
+#define SM5_PRACH_DEBUG_CELL1_LEN                  SM5_PRACH_DEBUG_LEN  //1K
+#define SM5_SRS_DEBUG_CELL1_LEN                    SM5_SRS_DEBUG_LEN    //1K
+
+#define SM5_RESERVED3_LEN                          0x0000D400 //53K
+
+#define SM5_NR_CELL_TRACE_LEN \
+    (SM5_ERROR_RECORD_LEN+SM5_NR_STATISTIC_LEN+SM5_STATE_RECORD_LEN+SM5_COMMON_DEBUG_LEN \
+    +SM5_PDCCH_DEBUG_LEN+SM5_PDSCH_DEBUG_LEN+SM5_SSB_DEBUG_LEN+SM5_CSIRS_DEBUG_LEN+SM5_DEOFDM_DEBUG_LEN \
+    +SM5_PUCCH_DEBUG_LEN+SM5_PUSCH_DEBUG_LEN+SM5_PRACH_DEBUG_LEN+SM5_SRS_DEBUG_LEN)
+
+//addr define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE)
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
+#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
+#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
+#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
+#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)
+
+#define SM5_CPRI_CSU_LINK_TABLE_ADDR               (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)//0x0A4E5A00
+
+#define SM5_ERROR_RECORD_ADDR                      (SM5_CPRI_CSU_LINK_TABLE_ADDR + SM5_CPRI_CSU_LINK_TABLE_LEN)
+#define SM5_NR_STATISTIC_ADDR                      (SM5_ERROR_RECORD_ADDR + SM5_ERROR_RECORD_LEN)
+#define SM5_STATE_RECORD_ADDR                      (SM5_NR_STATISTIC_ADDR + SM5_NR_STATISTIC_LEN)
+#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_ADDR + SM5_STATE_RECORD_LEN)
+#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
+#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
+#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
+#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
+#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
+#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
+#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
+#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
+#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)
+
+#define SM5_ERROR_RECORD_CELL1_ADDR                (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
+#define SM5_NR_STATISTIC_CELL1_ADDR                (SM5_ERROR_RECORD_CELL1_ADDR + SM5_ERROR_RECORD_CELL1_LEN)
+#define SM5_STATE_RECORD_CELL1_ADDR                (SM5_NR_STATISTIC_CELL1_ADDR + SM5_NR_STATISTIC_CELL1_LEN)
+#define SM5_COMMON_DEBUG_CELL1_ADDR                (SM5_STATE_RECORD_CELL1_ADDR + SM5_STATE_RECORD_CELL1_LEN)
+#define SM5_PDCCH_DEBUG_CELL1_ADDR                 (SM5_COMMON_DEBUG_CELL1_ADDR + SM5_COMMON_DEBUG_CELL1_LEN)
+#define SM5_PDSCH_DEBUG_CELL1_ADDR                 (SM5_PDCCH_DEBUG_CELL1_ADDR + SM5_PDCCH_DEBUG_CELL1_LEN)
+#define SM5_SSB_DEBUG_CELL1_ADDR                   (SM5_PDSCH_DEBUG_CELL1_ADDR + SM5_PDSCH_DEBUG_CELL1_LEN)
+#define SM5_CSIRS_DEBUG_CELL1_ADDR                 (SM5_SSB_DEBUG_CELL1_ADDR + SM5_SSB_DEBUG_CELL1_LEN)
+#define SM5_DEOFDM_DEBUG_CELL1_ADDR                (SM5_CSIRS_DEBUG_CELL1_ADDR + SM5_CSIRS_DEBUG_CELL1_LEN)
+#define SM5_PUCCH_DEBUG_CELL1_ADDR                 (SM5_DEOFDM_DEBUG_CELL1_ADDR + SM5_DEOFDM_DEBUG_CELL1_LEN)
+#define SM5_PUSCH_DEBUG_CELL1_ADDR                 (SM5_PUCCH_DEBUG_CELL1_ADDR + SM5_PUCCH_DEBUG_CELL1_LEN)
+#define SM5_PRACH_DEBUG_CELL1_ADDR                 (SM5_PUSCH_DEBUG_CELL1_ADDR + SM5_PUSCH_DEBUG_CELL1_LEN)
+#define SM5_SRS_DEBUG_CELL1_ADDR                   (SM5_PRACH_DEBUG_CELL1_ADDR + SM5_PRACH_DEBUG_CELL1_LEN)
+
+#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_CELL1_ADDR + SM5_SRS_DEBUG_CELL1_LEN)
+
+#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
+/**************************************DDR****************************************************/
+/*******************************PUSCH HARQ 0x14400000-0x84C00000******************************/
+#define DDR_NR_CELL0_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL0_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+#define DDR_NR_CELL1_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL1_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+//0x14400000-0x4C800000
+#define DDR_NR_CELL0_SOFTBIT_PING_ADDR       (0x14400000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_ADDR       (DDR_NR_CELL0_SOFTBIT_PING_ADDR+DDR_NR_CELL0_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL0_SOFTBIT_PANG_ADDR+DDR_NR_CELL0_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_ADDR           (DDR_NR_CELL0_MME_FREQ_CPTS_ADDR+DDR_NR_CELL0_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL0_RNTI_ADDR               (DDR_NR_CELL0_SCRAMBLE_ADDR+DDR_NR_CELL0_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_ADDR          (DDR_NR_CELL0_RNTI_ADDR+DDR_NR_CELL0_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_ADDR          (DDR_NR_CELL0_HARQ_INFO_ADDR+DDR_NR_CELL0_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_ADDR             (DDR_NR_CELL0_TB_DECODE_ADDR+DDR_NR_CELL0_TB_DECODE_LEN)   //(500*1024)
+
+//0x4C800000-0x84C00000
+#define DDR_NR_CELL1_SOFTBIT_PING_ADDR       (0x4C800000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_ADDR       (DDR_NR_CELL1_SOFTBIT_PING_ADDR+DDR_NR_CELL1_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL1_SOFTBIT_PANG_ADDR+DDR_NR_CELL1_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_ADDR           (DDR_NR_CELL1_MME_FREQ_CPTS_ADDR+DDR_NR_CELL1_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL1_RNTI_ADDR               (DDR_NR_CELL1_SCRAMBLE_ADDR+DDR_NR_CELL1_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_ADDR          (DDR_NR_CELL1_RNTI_ADDR+DDR_NR_CELL1_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_ADDR          (DDR_NR_CELL1_HARQ_INFO_ADDR+DDR_NR_CELL1_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_ADDR             (DDR_NR_CELL1_TB_DECODE_ADDR+DDR_NR_CELL1_TB_DECODE_LEN)   //(500*1024)
+
+/*******************************共180+192M可用0x84C00000-0x9C000000***************************/
+//len
+#define DDR_NR_CELL0_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_CELL1_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
+#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
+#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
+#define DDR_TEST_MAC_DL_DATA_BUF_LEN   (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+#define DDR_WRITE_MONITOR_LEN          (0x400000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_LEN           (0X400000)//预留4M空间给读DDR检查功能
+
+//addr
+#define DDR_PHY_BASE                         (0x84C00000)
+#define DDR_TEST_MAC_NR_CELL0_RX_DATA_ADDR   (0x84C00000)//0x84C00000 ~ 0x85100000 
+#define DDR_TEST_MAC_NR_CELL1_RX_DATA_ADDR   (0x85100000)//0x85100000 ~ 0x85600000
+
+#define DDR_PHY_RECORD_ADDR                  (0x85600000)//0x85600000 ~ 0x86000000
+#define DDR_NR_DL_RECORD_ADDR                (0x85600000)//0x85600000 ~ 0x87600000 32M
+#define DDR_NR_UL_RECORD_ADDR                (0x87600000)//0x87600000 ~ 0x89600000 32M
+#define DDR_NR_DL1_RECORD_ADDR               (0x89600000)//0x89600000 ~ 0x8B600000 32M
+#define DDR_NR_UL1_RECORD_ADDR               (0x8B600000)//0x8B600000 ~ 0x8D600000 32M
+
+#define DDR_TEST_MAC_DL_DATA_BUF_ADDR        (0x8D600000)//testmac预留20M,缓存DL的IQ数据      		//0x8D600000 ~ 0x8EA00000
+
+#define DDR_WRITE_MONITOR_ADDR               (0x8EA00000)//预留4M空间给写DDR检查功能					//0x8B400000 ~ 0X8EE00000
+#define DDR_READ_MONITOR_ADDR                (0x8EE00000)//预留4M空间给读DDR检查功能
+
+#define DDR_MAX_ADDR                         (0x90000000)
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+//void Config_Cpri_Csu_Lte();
+void Config_Cpri_Csu_Nr(uint8_t slot_format);
+
+
+#endif

public/test/testcase_fh/case82/inc/phy_timer_csu_config.h

@@ -0,0 +1,113 @@
+/******************************************************************
+ * @file  phy_timer_csu_config.h
+ * @brief:    [file description] 
+ * @author: guicheng.liu
+ * @Date 2022年7月7日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
+ * Change_date         Owner         Change_content
+ * 2022年7月7日        guicheng.liu       create file
+
+*****************************************************************/
+
+#ifndef     FPHY_TIMER_CSU_CONFIG_H
+#define     FPHY_TIMER_CSU_CONFIG_H
+//#include <type_define.h>
+//#include "phy_nr_context.h"
+//#include "drv_rfm.h"
+
+
+#include "typedef.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+
+//#define CPRI_LINK_START_ADDR						0x721E000 //ECS SM后8K 0x721E000- 0x7220000
+#define CPRI_NR_FDD_LINK_START_ADDR                 SM5_CPRI_CSU_LINK_TABLE_ADDR//更换为SM的地址
+
+#define NR_LONGCP_SAM_CNT								4448
+#define NR_SHORTCP_SAM_CNT								4384
+
+typedef struct
+{
+    uint16_t period;//=t_us*num_t;
+    uint16_t rev;
+
+    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
+    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
+}timer_info_t;
+
+typedef struct
+{
+    uint8_t flag;//0:default timer, 1:inuse timer
+    uint8_t rev[3];
+
+    timer_info_t default_timer;
+    timer_info_t inuse_timer;
+}phy_timer_t;
+
+typedef struct
+{
+    uint8_t total_ants;
+    uint8_t scs;
+    uint8_t num_dl_symbols;
+    uint8_t rev;
+
+    uint16_t num_dl_tti;
+    uint16_t rev1;
+
+    phy_timer_config_ind_t jesd_timer;
+    phy_timer_config_ind_t cpri_timer;
+}phy_csu_timer_t;
+
+typedef struct
+{
+    uint32_t state;//0:idle, 1:configured
+
+    //tx的链表地址
+    uint32_t tx0_even_f7_link_addr;
+    uint32_t tx0_even_b7_link_addr;
+    uint32_t tx0_odd_f7_link_addr;
+    uint32_t tx0_odd_b7_link_addr;
+    uint32_t tx0_s_link_addr;
+    uint32_t tx0_1st_dummy_link_addr;
+    uint32_t tx0_2nd_dummy_link_addr;
+
+    //rx的链表地址
+    uint32_t rx0_first_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot尾部的数据
+    uint32_t rx0_dummy_link_addr;
+    uint32_t rx0_s_link_addr;
+    uint32_t rx0_normal0_link_addr;
+    uint32_t rx0_normal1_link_addr;
+    uint32_t rx0_last_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot头部的数据
+}phy_csu_link_info_t;
+
+
+void Phy_Timer_Csu_Init();
+
+//void Csu_Dma_Init();
+//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx0_ants, 
+//                                uint16_t num_rx_tti);
+//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx1_ants, 
+//                                uint16_t num_rx_tti);
+void Config_Csu_Timer(uint16_t dl_bw,
+                            uint16_t num_tx_ants,
+                            uint8_t nrOfSlots,
+                            uint16_t num_dl_tti,
+                            uint8_t num_dl_symbols,
+                            uint8_t num_ul_symbols,
+                            uint8_t scs,
+                            uint32_t run_core_id_map);
+//void Update_Phy_Timer(uint8_t tdd_period);
+
+//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
+//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);
+
+
+#endif

public/test/testcase_fh/case82/readme.txt

@@ -0,0 +1,3 @@
+场景：OTIC协议中图12，10g速率下4T4R单NR小区
+模式：NR FDD
+单音测试:中心频点2.13990GHz，单音频偏5MHz

public/test/testcase_fh/case82/src/cpri_test_case82.s.c

@@ -0,0 +1,525 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case82.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+
+extern uint32_t compressData[1920];
+extern uint32_t antData0[61440];
+extern uint32_t antData1[61440];
+extern uint32_t antData2[61440];
+extern uint32_t antData3[61440];
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);//NR TDD和FDD的mapping是一样的
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Nr(0);
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t  f7BfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*6)*2;
+	uint32_t  b7BfCnt = (SHORTCP_BF_CNT*7)*2;
+
+	uint32_t cpyCnt = 0;
+	// valid data
+	// compress factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;
+		
+		if (0 == idSlot)	// even slot
+		{
+			srcAddr = (uint32_t)(&compressData[0]);
+			dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
+		}
+		else				// odd slot
+		{
+			//srcAddr = (uint32_t)(&compressData[3840>>1]);
+			srcAddr = (uint32_t)(&compressData[0]);
+			dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+	}
+
+	// IQ data	
+	for (idID = 1; idID < 5; idID++)
+	{
+		bfByteCnt = 64;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[0]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[0]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[0]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[0]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[0]);
+					if(idID < 3)
+					{
+						dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+					
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[15376*2]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[15376*2]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[15376*2]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[15376*2]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[15376]);
+					
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[0]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[0]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[0]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[0]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720]);
+					
+					if(idID < 3)
+					{
+						dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[15376*2]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[15376*2]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[15376*2]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[15376*2]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720+15376]);
+					
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+				cpyCnt++;
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+			}
+		}
+	}
+	
+}
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE82_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+#endif
+		Cpri_Header_Rx();
+
+	}
+}
+
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t totalSlotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint8_t	bfWordCnt = 0;
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM3_NR_CELL0_ODD_RX_DATA_ADDR + (2*slotBfCnt) + ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_ODD_RX_AGC_ADDR;
+			}
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + (2*slotBfCnt)+ ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVNE_RX_AGC_ADDR;
+			}
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = do_read_volatile(compressData+idBf*bfWordCnt + idWord);//Nr_CompressData[idBf*bfWordCnt + idWord];
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 <= i) && (2 >= i))		// 天线0,1
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(1 == i)//天线0
+					{
+						compVal = do_read_volatile(antData0+idBf*bfWordCnt + idWord);//Lte_antData[idBf*bfWordCnt + idWord];
+					}
+					else//天线1
+					{
+						compVal = do_read_volatile(antData1+idBf*bfWordCnt + idWord);//Nr_antData23[idBf*bfWordCnt + idWord];
+					}
+
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else
+		{
+		}
+	
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}
+

public/test/testcase_fh/case82/src/cpri_test_case82_AGC.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Agc_Data[1920] = {
+	0
+};
+

public/test/testcase_fh/case83/inc/cpri_test_case83.h

@@ -0,0 +1,36 @@
+#ifndef _CPRI_TEST_CASE60_H_
+#define _CPRI_TEST_CASE60_H_
+
+// 4 ant, 7DS2U
+
+#define CPRI_CASE83_SLOT_NUM				20
+
+
+#define LONGCP_BF_CNT								139
+#define SHORTCP_BF_CNT								137
+
+void cpri_csu_test_init();
+
+void Cpri_data_init();
+
+void Get_Cpri_OptionId();
+
+void HeaderTxRam_data_init();
+//void HeaderTxRam_init();
+
+void Axc_data_init();
+
+void cpri_csu_config();
+
+void cpri_test_case();
+
+void cpri_test_move_data();
+
+void AxC_data_check(uint32_t times);
+
+void cpri_check_slot_data(uint32_t slotNum);
+
+
+
+#endif
+

public/test/testcase_fh/case83/inc/nr_mem_def.h

@@ -0,0 +1,315 @@
+/******************************************************************
+ * @file  ucp_mem_def.h
+ * @brief:   两片UCP的内存分布头文件
+ * @author: xuekun.zhang
+ * @Date 2021年1月5日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved.
+ * Change_date         Owner         Change_content
+ * 2021年1月5日        xuekun.zhang       create file
+
+*****************************************************************/
+
+#ifndef     UCP_MEM_DEF_H
+#define     UCP_MEM_DEF_H
+
+//#include "interface_fapi_tasks.h"
+//#include "interface_fapi_dl_lte.h"
+//#include "interface_fapi_pusch.h"
+//#include "interface_fapi_pucch.h"
+//#include "interface_fapi_srs.h"
+//#include "interface_fapi_dlctrl_lte.h"
+//#include "interface_fapi_pbch_lte.h"
+//#include "interface_pdcch_dl.h"
+//#include "interface_fapi_prach.h"
+#include "typedef.h"
+
+
+
+//！命名宏定义时需要注意UCP使用的地址
+/*********************************UCP************************************************/
+//#define SM0_BASE                             (0x09D00000)//1M
+//#define SM1_BASE                             (0x09E00000)//1M
+//#define SM2_BASE                             (0x09F00000)//1.5M
+//#define SM3_BASE                             (0x0A080000)//1.5M
+//#define SM4_BASE                             (0x0A200000)//1.5M
+//#define SM5_BASE                             (0x0A380000)//1.5M
+
+/***************************************SM0-SM1--2M*********************************************/
+//len define
+//SM0
+#define SM0_NR_PUCCH_LUT_LEN		               0x00040000  //256K
+#define SM0_PHY_MSG_BUFFER_LEN                     0x00000400  //1K
+#define SM0_PHY_TASKS_MGR_LEN                      0x00000100  //0.25K
+
+#define SM0_NR_CELL0_FAPI_MSG_LEN		           0x0000EB00  //58.75K, 实际使用0xE3DC
+#define SM0_RESERVED0_LEN                          0X00000400  //1K
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL0_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL0_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL0_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED1_LEN                          0x00000400  //1K
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED2_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_FAPI_MSG_LEN		           0x0000F000  //60K
+#define SM0_RESERVED3_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN     0x00015C00  //87K
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN            0x00000180  //0.375K
+#define SM0_NR_CELL1_HARQ_INFO_LEN                 0x00001000  //4K
+#define SM0_NR_CELL1_SCH_CB_INFO_LEN               0x00004400  //17K
+#define SM0_NR_CELL1_UCI_CB_INFO_LEN               0x00001000  //4K
+#define SM0_RESERVED4_LEN                          0x00000400  //1K
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN         0x00002400  //9K
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN       0x0000B400  //45K
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN       0x0001B000  //108K
+#define SM0_RESERVED5_LEN                          0x00005900  //22.25
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm0:72k, sm1:168.25k)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN          0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN        0x00001E00//0x00000F00  //3.75k
+#define SM1_NR_CELL0_EVEN_RX_DATA_LEN              0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM1_NR_CELL0_EVNE_RX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_LEN                0x00001400  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_LEN               0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_LEN                0x00001E00//0x00001400  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_LEN               0x00001400  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_LEN                0x00001400  //5k
+#define SM1_RESERVED0_LEN                          0x00014C00  //83k
+
+#define SM0_NR_PUCCH_LUT_ADDR                      (SM0_BASE)
+#define SM0_PHY_MSG_BUFFER_ADDR                    (SM0_NR_PUCCH_LUT_ADDR + SM0_NR_PUCCH_LUT_LEN)
+#define SM0_PHY_TASKS_MGR_ADDR                     (SM0_PHY_MSG_BUFFER_ADDR + SM0_PHY_MSG_BUFFER_LEN)
+
+#define SM0_NR_CELL0_FAPI_MSG_ADDR                 (SM0_PHY_TASKS_MGR_ADDR + SM0_PHY_TASKS_MGR_LEN)
+#define SM0_RESERVED_ADDR                          (SM0_NR_CELL0_FAPI_MSG_ADDR + SM0_NR_CELL0_FAPI_MSG_LEN)
+#define SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED_ADDR + SM0_RESERVED0_LEN)
+#define SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL0_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL0_HARQ_INFO_ADDR                (SM0_NR_CELL0_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL0_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL0_SCH_CB_INFO_ADDR              (SM0_NR_CELL0_HARQ_INFO_ADDR + SM0_NR_CELL0_HARQ_INFO_LEN)
+#define SM0_NR_CELL0_UCI_CB_INFO_ADDR              (SM0_NR_CELL0_SCH_CB_INFO_ADDR + SM0_NR_CELL0_SCH_CB_INFO_LEN)
+#define SM0_RESERVED1_ADDR                         (SM0_NR_CELL0_UCI_CB_INFO_ADDR + SM0_NR_CELL0_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED1_ADDR + SM0_RESERVED1_LEN)
+#define SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL0_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL0_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL0_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED2_ADDR                         (SM0_NR_CELL0_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL0_CSIRS_REMAPPING_TAB_LEN) 
+
+#define SM0_NR_CELL1_FAPI_MSG_ADDR                 (SM0_RESERVED2_ADDR + SM0_RESERVED2_LEN)
+#define SM0_RESERVED3_ADDR                         (SM0_NR_CELL1_FAPI_MSG_ADDR + SM0_NR_CELL1_FAPI_MSG_LEN)
+#define SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR    (SM0_RESERVED3_ADDR + SM0_RESERVED3_LEN)
+#define SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR           (SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_ADDR + SM0_NR_CELL1_PUSCH_SCRAMBLE_BUFFER_LEN)
+#define SM0_NR_CELL1_HARQ_INFO_ADDR                (SM0_NR_CELL1_DEOFDM_SRS_MSG_ADDR + SM0_NR_CELL1_DEOFDM_SRS_MSG_LEN)
+#define SM0_NR_CELL1_SCH_CB_INFO_ADDR              (SM0_NR_CELL1_HARQ_INFO_ADDR + SM0_NR_CELL1_HARQ_INFO_LEN)
+#define SM0_NR_CELL1_UCI_CB_INFO_ADDR              (SM0_NR_CELL1_SCH_CB_INFO_ADDR + SM0_NR_CELL1_SCH_CB_INFO_LEN)
+#define SM0_RESERVED4_ADDR                         (SM0_NR_CELL1_UCI_CB_INFO_ADDR + SM0_NR_CELL1_UCI_CB_INFO_LEN)
+#define SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR        (SM0_RESERVED4_ADDR + SM0_RESERVED4_LEN)
+#define SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_SSB_REMAPPING_TAB_ADDR + SM0_NR_CELL1_SSB_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR      (SM0_NR_CELL1_PDCCH_REMAPPING_TAB_ADDR + SM0_NR_CELL1_PDCCH_REMAPPING_TAB_LEN)
+#define SM0_RESERVED5_ADDR                         (SM0_NR_CELL1_CSIRS_REMAPPING_TAB_ADDR + SM0_NR_CELL1_CSIRS_REMAPPING_TAB_LEN)
+#define SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR          (SM0_RESERVED5_ADDR + SM0_RESERVED5_LEN)
+//SM1
+#define SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR         (SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + SM0_NR_CELL0_EVEN_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR           (SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR + SM1_NR_CELL0_EVEN_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR       (SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + SM1_NR_CELL0_ODD_F7_TX_DATA_LEN)
+#define SM1_NR_CELL0_EVEN_RX_DATA_ADDR             (SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR + SM1_NR_CELL0_ODD_TX_COMP_FACTOR_LEN)
+#define SM1_NR_CELL0_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + SM1_NR_CELL0_EVEN_RX_DATA_LEN)  //5k
+#define SM1_NR_CELL0_ODD_RX_AGC_ADDR               (SM1_NR_CELL0_EVNE_RX_AGC_ADDR+SM1_NR_CELL0_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_RX_AGC_ADDR              (SM1_NR_CELL0_ODD_RX_AGC_ADDR+SM1_NR_CELL0_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_RX_AGC_ADDR               (SM1_NR_CELL1_EVNE_RX_AGC_ADDR+SM1_NR_CELL1_EVNE_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_EVNE_TX_AGC_ADDR              (SM1_NR_CELL1_ODD_RX_AGC_ADDR+SM1_NR_CELL1_ODD_RX_AGC_LEN)  //5k
+#define SM1_NR_CELL0_ODD_TX_AGC_ADDR               (SM1_NR_CELL0_EVNE_TX_AGC_ADDR+SM1_NR_CELL0_EVNE_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_EVNE_TX_AGC_ADDR              (SM1_NR_CELL0_ODD_TX_AGC_ADDR+SM1_NR_CELL0_ODD_TX_AGC_LEN)  //5k
+#define SM1_NR_CELL1_ODD_TX_AGC_ADDR               (SM1_NR_CELL1_EVNE_TX_AGC_ADDR+SM1_NR_CELL1_EVNE_TX_AGC_LEN)  //5k
+#define SM1_RESERVED0_ADDR                         (SM1_NR_CELL1_ODD_TX_AGC_ADDR+SM1_NR_CELL1_ODD_TX_AGC_LEN)
+
+/***************************************SM2-SM5--6M*********************************************/
+//len define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN         0x000B3400 //717K
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN          0x000B3400 //717K
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN           0x0003C100  //240.25k  (sm2:102k, sm3:138.25k)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN          0x00000F00  //3.75k
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_LEN            0x0003C100  //240.25k
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN        0x00000F00  //3.75k
+#define SM3_NR_CELL0_ODD_RX_DATA_LEN               0x00079E00//0x00079400  //485k (480k+3.75k+1.25K)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN         0x000B3400  //717K (sm3:665k, sm4:52k)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN          0x000B3400  //717K
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM4_NR_CELL1_EVEN_RX_DATA_LEN              0x00079400  //485k (sm4:287k, sm5:198k)(480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_RX_DATA_LEN               0x00079400  //485k (480k+3.75k+1.25K)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_LEN            0x0003C000  //240k
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN           0x0003C000  //240k
+#define SM5_RESERVED0_LEN                          0x00034400  //209k
+#define SM5_RESERVED_FOR_APE_PLATFORM_LEN          0x0000E000  //56k
+#define SM5_CPRI_CSU_LINK_TABLE_LEN                0x00002000  //8k
+
+#define SM5_ERROR_RECORD_LEN                       0x00003000 //12k
+#define SM5_NR_STATISTIC_LEN                       0x00000120 //288byte
+#define SM5_STATE_RECORD_LEN                       0x000004E0 //1248byte
+#define SM5_COMMON_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PDCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PDSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SSB_DEBUG_LEN                          0x00000400 //1K
+#define SM5_CSIRS_DEBUG_LEN                        0x00000400 //1K
+#define SM5_DEOFDM_DEBUG_LEN                       0x00000400 //1K
+#define SM5_PUCCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PUSCH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_PRACH_DEBUG_LEN                        0x00000400 //1K
+#define SM5_SRS_DEBUG_LEN                          0x00000400 //1K
+
+#define SM5_ERROR_RECORD_CELL1_LEN                 SM5_ERROR_RECORD_LEN //12k
+#define SM5_NR_STATISTIC_CELL1_LEN                 SM5_NR_STATISTIC_LEN //288byte
+#define SM5_STATE_RECORD_CELL1_LEN                 SM5_STATE_RECORD_LEN //1248byte
+#define SM5_COMMON_DEBUG_CELL1_LEN                 SM5_COMMON_DEBUG_LEN //1K
+#define SM5_PDCCH_DEBUG_CELL1_LEN                  SM5_PDCCH_DEBUG_LEN  //1K
+#define SM5_PDSCH_DEBUG_CELL1_LEN                  SM5_PDSCH_DEBUG_LEN  //1K
+#define SM5_SSB_DEBUG_CELL1_LEN                    SM5_SSB_DEBUG_LEN    //1K
+#define SM5_CSIRS_DEBUG_CELL1_LEN                  SM5_CSIRS_DEBUG_LEN  //1K
+#define SM5_DEOFDM_DEBUG_CELL1_LEN                 SM5_DEOFDM_DEBUG_LEN //1K
+#define SM5_PUCCH_DEBUG_CELL1_LEN                  SM5_PUCCH_DEBUG_LEN  //1K
+#define SM5_PUSCH_DEBUG_CELL1_LEN                  SM5_PUSCH_DEBUG_LEN  //1K
+#define SM5_PRACH_DEBUG_CELL1_LEN                  SM5_PRACH_DEBUG_LEN  //1K
+#define SM5_SRS_DEBUG_CELL1_LEN                    SM5_SRS_DEBUG_LEN    //1K
+
+#define SM5_RESERVED3_LEN                          0x0000D400 //53K
+
+#define SM5_NR_CELL_TRACE_LEN \
+    (SM5_ERROR_RECORD_LEN+SM5_NR_STATISTIC_LEN+SM5_STATE_RECORD_LEN+SM5_COMMON_DEBUG_LEN \
+    +SM5_PDCCH_DEBUG_LEN+SM5_PDSCH_DEBUG_LEN+SM5_SSB_DEBUG_LEN+SM5_CSIRS_DEBUG_LEN+SM5_DEOFDM_DEBUG_LEN \
+    +SM5_PUCCH_DEBUG_LEN+SM5_PUSCH_DEBUG_LEN+SM5_PRACH_DEBUG_LEN+SM5_SRS_DEBUG_LEN)
+
+//addr define
+#define SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR        (SM2_BASE)
+#define SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR         (SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_EVEN_SLOT_FREQ_LEN)
+#define SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR          (SM2_NR_CELL0_RX_ODD_SLOT_FREQ_ADDR + SM2_NR_CELL0_RX_ODD_SLOT_FREQ_LEN)
+#define SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR         (SM2_NR_CELL1_EVEN_F7_TX_DATA_ADDR + SM2_NR_CELL1_EVEN_F7_TX_DATA_LEN)
+#define SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR           (SM3_NR_CELL1_EVEN_COMP_FACTOR_ADDR + SM3_NR_CELL1_EVEN_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR       (SM3_NR_CELL1_ODD_F7_TX_DATA_ADDR + SM3_NR_CELL1_ODD_F7_TX_DATA_LEN)
+#define SM3_NR_CELL0_ODD_RX_DATA_ADDR              (SM3_NR_CELL1_ODD_TX_COMP_FACTOR_ADDR + SM3_NR_CELL1_ODD_TX_COMP_FACTOR_LEN)
+#define SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR        (SM3_NR_CELL0_ODD_RX_DATA_ADDR + SM3_NR_CELL0_ODD_RX_DATA_LEN)
+#define SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR         (SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_ADDR + SM3_NR_CELL1_RX_EVEN_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR          (SM4_NR_CELL1_RX_ODD_SLOT_FREQ_ADDR + SM4_NR_CELL1_RX_ODD_SLOT_FREQ_LEN)
+#define SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR           (SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + SM4_NR_CELL0_EVEN_B7_TX_DATA_LEN)
+#define SM4_NR_CELL1_EVEN_RX_DATA_ADDR             (SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + SM4_NR_CELL0_ODD_B7_TX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_RX_DATA_ADDR              (SM4_NR_CELL1_EVEN_RX_DATA_ADDR + SM4_NR_CELL1_EVEN_RX_DATA_LEN)
+#define SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR           (SM5_NR_CELL1_ODD_RX_DATA_ADDR + SM5_NR_CELL1_ODD_RX_DATA_LEN)
+#define SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR          (SM5_NR_CELL1_ODD_B7_TX_DATA_ADDR + SM5_NR_CELL1_ODD_B7_TX_DATA_LEN)
+#define SM5_RESERVED0_ADDR                         (SM5_NR_CELL1_EVEN_B7_TX_DATA_ADDR + SM5_NR_CELL1_EVEN_B7_TX_DATA_LEN)
+#define SM5_RESERVED_FOR_APE_PLATFORM_ADDR         (SM5_RESERVED0_ADDR + SM5_RESERVED0_LEN)
+
+#define SM5_CPRI_CSU_LINK_TABLE_ADDR               (SM5_RESERVED_FOR_APE_PLATFORM_ADDR + SM5_RESERVED_FOR_APE_PLATFORM_LEN)//0x0A4E5A00
+
+#define SM5_ERROR_RECORD_ADDR                      (SM5_CPRI_CSU_LINK_TABLE_ADDR + SM5_CPRI_CSU_LINK_TABLE_LEN)
+#define SM5_NR_STATISTIC_ADDR                      (SM5_ERROR_RECORD_ADDR + SM5_ERROR_RECORD_LEN)
+#define SM5_STATE_RECORD_ADDR                      (SM5_NR_STATISTIC_ADDR + SM5_NR_STATISTIC_LEN)
+#define SM5_COMMON_DEBUG_ADDR                      (SM5_STATE_RECORD_ADDR + SM5_STATE_RECORD_LEN)
+#define SM5_PDCCH_DEBUG_ADDR                       (SM5_COMMON_DEBUG_ADDR + SM5_COMMON_DEBUG_LEN)
+#define SM5_PDSCH_DEBUG_ADDR                       (SM5_PDCCH_DEBUG_ADDR + SM5_PDCCH_DEBUG_LEN)
+#define SM5_SSB_DEBUG_ADDR                         (SM5_PDSCH_DEBUG_ADDR + SM5_PDSCH_DEBUG_LEN)
+#define SM5_CSIRS_DEBUG_ADDR                       (SM5_SSB_DEBUG_ADDR + SM5_SSB_DEBUG_LEN)
+#define SM5_DEOFDM_DEBUG_ADDR                      (SM5_CSIRS_DEBUG_ADDR + SM5_CSIRS_DEBUG_LEN)
+#define SM5_PUCCH_DEBUG_ADDR                       (SM5_DEOFDM_DEBUG_ADDR + SM5_DEOFDM_DEBUG_LEN)
+#define SM5_PUSCH_DEBUG_ADDR                       (SM5_PUCCH_DEBUG_ADDR + SM5_PUCCH_DEBUG_LEN)
+#define SM5_PRACH_DEBUG_ADDR                       (SM5_PUSCH_DEBUG_ADDR + SM5_PUSCH_DEBUG_LEN)
+#define SM5_SRS_DEBUG_ADDR                         (SM5_PRACH_DEBUG_ADDR + SM5_PRACH_DEBUG_LEN)
+
+#define SM5_ERROR_RECORD_CELL1_ADDR                (SM5_SRS_DEBUG_ADDR + SM5_SRS_DEBUG_LEN)
+#define SM5_NR_STATISTIC_CELL1_ADDR                (SM5_ERROR_RECORD_CELL1_ADDR + SM5_ERROR_RECORD_CELL1_LEN)
+#define SM5_STATE_RECORD_CELL1_ADDR                (SM5_NR_STATISTIC_CELL1_ADDR + SM5_NR_STATISTIC_CELL1_LEN)
+#define SM5_COMMON_DEBUG_CELL1_ADDR                (SM5_STATE_RECORD_CELL1_ADDR + SM5_STATE_RECORD_CELL1_LEN)
+#define SM5_PDCCH_DEBUG_CELL1_ADDR                 (SM5_COMMON_DEBUG_CELL1_ADDR + SM5_COMMON_DEBUG_CELL1_LEN)
+#define SM5_PDSCH_DEBUG_CELL1_ADDR                 (SM5_PDCCH_DEBUG_CELL1_ADDR + SM5_PDCCH_DEBUG_CELL1_LEN)
+#define SM5_SSB_DEBUG_CELL1_ADDR                   (SM5_PDSCH_DEBUG_CELL1_ADDR + SM5_PDSCH_DEBUG_CELL1_LEN)
+#define SM5_CSIRS_DEBUG_CELL1_ADDR                 (SM5_SSB_DEBUG_CELL1_ADDR + SM5_SSB_DEBUG_CELL1_LEN)
+#define SM5_DEOFDM_DEBUG_CELL1_ADDR                (SM5_CSIRS_DEBUG_CELL1_ADDR + SM5_CSIRS_DEBUG_CELL1_LEN)
+#define SM5_PUCCH_DEBUG_CELL1_ADDR                 (SM5_DEOFDM_DEBUG_CELL1_ADDR + SM5_DEOFDM_DEBUG_CELL1_LEN)
+#define SM5_PUSCH_DEBUG_CELL1_ADDR                 (SM5_PUCCH_DEBUG_CELL1_ADDR + SM5_PUCCH_DEBUG_CELL1_LEN)
+#define SM5_PRACH_DEBUG_CELL1_ADDR                 (SM5_PUSCH_DEBUG_CELL1_ADDR + SM5_PUSCH_DEBUG_CELL1_LEN)
+#define SM5_SRS_DEBUG_CELL1_ADDR                   (SM5_PRACH_DEBUG_CELL1_ADDR + SM5_PRACH_DEBUG_CELL1_LEN)
+
+#define SM5_RESERVED3_ADDR                         (SM5_SRS_DEBUG_CELL1_ADDR + SM5_SRS_DEBUG_CELL1_LEN)
+
+#define SM5_MAX_ADDR                               (SM5_RESERVED3_ADDR + SM5_RESERVED3_LEN)
+/**************************************DDR****************************************************/
+/*******************************PUSCH HARQ 0x14400000-0x84C00000******************************/
+#define DDR_NR_CELL0_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL0_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+#define DDR_NR_CELL1_SOFTBIT_PING_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_LEN       (0xAA000) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_LEN      (0x599400)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_LEN           (0x14CB8) //(85176)
+#define DDR_NR_CELL1_RNTI_LEN               (0x960)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_LEN          (0x2A5BA200)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_LEN          (0x7FF8690) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_LEN             (0x7D000)   //(500*1024)
+
+//0x14400000-0x4C800000
+#define DDR_NR_CELL0_SOFTBIT_PING_ADDR       (0x14400000) //(680*1024)
+#define DDR_NR_CELL0_SOFTBIT_PANG_ADDR       (DDR_NR_CELL0_SOFTBIT_PING_ADDR+DDR_NR_CELL0_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL0_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL0_SOFTBIT_PANG_ADDR+DDR_NR_CELL0_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL0_SCRAMBLE_ADDR           (DDR_NR_CELL0_MME_FREQ_CPTS_ADDR+DDR_NR_CELL0_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL0_RNTI_ADDR               (DDR_NR_CELL0_SCRAMBLE_ADDR+DDR_NR_CELL0_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL0_HARQ_INFO_ADDR          (DDR_NR_CELL0_RNTI_ADDR+DDR_NR_CELL0_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL0_TB_DECODE_ADDR          (DDR_NR_CELL0_HARQ_INFO_ADDR+DDR_NR_CELL0_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL0_DEOFDM_ADDR             (DDR_NR_CELL0_TB_DECODE_ADDR+DDR_NR_CELL0_TB_DECODE_LEN)   //(500*1024)
+
+//0x4C800000-0x84C00000
+#define DDR_NR_CELL1_SOFTBIT_PING_ADDR       (0x4C800000) //(680*1024)
+#define DDR_NR_CELL1_SOFTBIT_PANG_ADDR       (DDR_NR_CELL1_SOFTBIT_PING_ADDR+DDR_NR_CELL1_SOFTBIT_PING_LEN) //(680*1024)
+#define DDR_NR_CELL1_MME_FREQ_CPTS_ADDR      (DDR_NR_CELL1_SOFTBIT_PANG_ADDR+DDR_NR_CELL1_SOFTBIT_PANG_LEN)//(419328*14)
+#define DDR_NR_CELL1_SCRAMBLE_ADDR           (DDR_NR_CELL1_MME_FREQ_CPTS_ADDR+DDR_NR_CELL1_MME_FREQ_CPTS_LEN) //(85176)
+#define DDR_NR_CELL1_RNTI_ADDR               (DDR_NR_CELL1_SCRAMBLE_ADDR+DDR_NR_CELL1_SCRAMBLE_LEN)   //(2400)
+
+#define DDR_NR_CELL1_HARQ_INFO_ADDR          (DDR_NR_CELL1_RNTI_ADDR+DDR_NR_CELL1_RNTI_LEN)//(1200*16*86+670*1024*1024+1200*16*84*4)=710,648,320
+#define DDR_NR_CELL1_TB_DECODE_ADDR          (DDR_NR_CELL1_HARQ_INFO_ADDR+DDR_NR_CELL1_HARQ_INFO_LEN) //(120*14*79873)=134,186,640
+#define DDR_NR_CELL1_DEOFDM_ADDR             (DDR_NR_CELL1_TB_DECODE_ADDR+DDR_NR_CELL1_TB_DECODE_LEN)   //(500*1024)
+
+/*******************************共180+192M可用0x84C00000-0x9C000000***************************/
+//len
+#define DDR_NR_CELL0_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_CELL1_RX_LEN            (0x500000)//为多小区预留10M, NR单小区5M
+#define DDR_NR_DL_RECORD_LEN           (0x2000000)//DL 打点预留32M
+#define DDR_NR_UL_RECORD_LEN           (0x2000000)//UL 打点预留32M
+#define DDR_TEST_MAC_UL_IQ_DATA_LEN    (0xA00000)//为testmac测试模式下, UL的IQ数据预留10M空间
+#define DDR_TEST_MAC_DL_DATA_BUF_LEN   (0x1400000)//testmac需要预留20M空间,用来缓存DL的IQ数据
+#define DDR_WRITE_MONITOR_LEN          (0x400000)//预留4M空间给写DDR检查功能
+#define DDR_READ_MONITOR_LEN           (0X400000)//预留4M空间给读DDR检查功能
+
+//addr
+#define DDR_PHY_BASE                         (0x84C00000)
+#define DDR_TEST_MAC_NR_CELL0_RX_DATA_ADDR   (0x84C00000)//0x84C00000 ~ 0x85100000 
+#define DDR_TEST_MAC_NR_CELL1_RX_DATA_ADDR   (0x85100000)//0x85100000 ~ 0x85600000
+
+#define DDR_PHY_RECORD_ADDR                  (0x85600000)//0x85600000 ~ 0x86000000
+#define DDR_NR_DL_RECORD_ADDR                (0x85600000)//0x85600000 ~ 0x87600000 32M
+#define DDR_NR_UL_RECORD_ADDR                (0x87600000)//0x87600000 ~ 0x89600000 32M
+#define DDR_NR_DL1_RECORD_ADDR               (0x89600000)//0x89600000 ~ 0x8B600000 32M
+#define DDR_NR_UL1_RECORD_ADDR               (0x8B600000)//0x8B600000 ~ 0x8D600000 32M
+
+#define DDR_TEST_MAC_DL_DATA_BUF_ADDR        (0x8D600000)//testmac预留20M,缓存DL的IQ数据      		//0x8D600000 ~ 0x8EA00000
+
+#define DDR_WRITE_MONITOR_ADDR               (0x8EA00000)//预留4M空间给写DDR检查功能					//0x8B400000 ~ 0X8EE00000
+#define DDR_READ_MONITOR_ADDR                (0x8EE00000)//预留4M空间给读DDR检查功能
+
+#define DDR_MAX_ADDR                         (0x90000000)
+
+//void Config_Cpri_Csu_Lte(lte_cell_info_t* cell);
+//void Config_Cpri_Csu_Lte();
+void Config_Cpri_Csu_Nr(uint8_t slot_format);
+
+
+#endif

public/test/testcase_fh/case83/inc/phy_timer_csu_config.h

@@ -0,0 +1,113 @@
+/******************************************************************
+ * @file  phy_timer_csu_config.h
+ * @brief:    [file description] 
+ * @author: guicheng.liu
+ * @Date 2022年7月7日
+ * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. 
+ * Change_date         Owner         Change_content
+ * 2022年7月7日        guicheng.liu       create file
+
+*****************************************************************/
+
+#ifndef     FPHY_TIMER_CSU_CONFIG_H
+#define     FPHY_TIMER_CSU_CONFIG_H
+//#include <type_define.h>
+//#include "phy_nr_context.h"
+//#include "drv_rfm.h"
+
+
+#include "typedef.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+
+//#define CPRI_LINK_START_ADDR						0x721E000 //ECS SM后8K 0x721E000- 0x7220000
+#define CPRI_NR_FDD_LINK_START_ADDR                 SM5_CPRI_CSU_LINK_TABLE_ADDR//更换为SM的地址
+
+#define NR_LONGCP_SAM_CNT								4448
+#define NR_SHORTCP_SAM_CNT								4384
+
+typedef struct
+{
+    uint16_t period;//=t_us*num_t;
+    uint16_t rev;
+
+    uint16_t t_us;//物理层时隙定时长度, 125us, 250us, 500us, 1000us
+    uint16_t num_t;//timer周期内时隙个数5,10,20,40,80
+}timer_info_t;
+
+typedef struct
+{
+    uint8_t flag;//0:default timer, 1:inuse timer
+    uint8_t rev[3];
+
+    timer_info_t default_timer;
+    timer_info_t inuse_timer;
+}phy_timer_t;
+
+typedef struct
+{
+    uint8_t total_ants;
+    uint8_t scs;
+    uint8_t num_dl_symbols;
+    uint8_t rev;
+
+    uint16_t num_dl_tti;
+    uint16_t rev1;
+
+    phy_timer_config_ind_t jesd_timer;
+    phy_timer_config_ind_t cpri_timer;
+}phy_csu_timer_t;
+
+typedef struct
+{
+    uint32_t state;//0:idle, 1:configured
+
+    //tx的链表地址
+    uint32_t tx0_even_f7_link_addr;
+    uint32_t tx0_even_b7_link_addr;
+    uint32_t tx0_odd_f7_link_addr;
+    uint32_t tx0_odd_b7_link_addr;
+    uint32_t tx0_s_link_addr;
+    uint32_t tx0_1st_dummy_link_addr;
+    uint32_t tx0_2nd_dummy_link_addr;
+
+    //rx的链表地址
+    uint32_t rx0_first_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot尾部的数据
+    uint32_t rx0_dummy_link_addr;
+    uint32_t rx0_s_link_addr;
+    uint32_t rx0_normal0_link_addr;
+    uint32_t rx0_normal1_link_addr;
+    uint32_t rx0_last_link_addr;//上行帧头和数据头的偏移量,是上一个帧的最后一个slot头部的数据
+}phy_csu_link_info_t;
+
+
+void Phy_Timer_Csu_Init();
+
+//void Csu_Dma_Init();
+//void Config_Csu_Tx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Tx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_tx0_ants, 
+//                                uint16_t num_tx_tti);
+//void Config_Csu_Rx0_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx0_ants, 
+//                                uint16_t num_rx_tti);
+//void Config_Csu_Rx1_Dma(uint32_t sampling_rate, 
+//                                uint8_t num_rx1_ants, 
+//                                uint16_t num_rx_tti);
+void Config_Csu_Timer(uint16_t dl_bw,
+                            uint16_t num_tx_ants,
+                            uint8_t nrOfSlots,
+                            uint16_t num_dl_tti,
+                            uint8_t num_dl_symbols,
+                            uint8_t num_ul_symbols,
+                            uint8_t scs,
+                            uint32_t run_core_id_map);
+//void Update_Phy_Timer(uint8_t tdd_period);
+
+//void Phy_Timer_Csu_Config_Nr(nr_cell_info_t* cell);
+//void Phy_Timer_Csu_Config_Lte(phy_lte_cell_t* cell);
+
+
+#endif

public/test/testcase_fh/case83/readme.txt

@@ -0,0 +1,3 @@
+场景：OTIC协议中图12，10g速率下4T4R单NR小区
+模式：NR FDD
+256QAM测试

public/test/testcase_fh/case83/src/cpri_test_case83.s.c

@@ -0,0 +1,524 @@
+// +FHDR------------------------------------------------------------
+//                 Copyright (c) 2022 SmartLogic.
+//                       ALL RIGHTS RESERVED
+// -----------------------------------------------------------------
+// Filename      : cpri_test_case34.c
+// Author        : xinxin.li
+// Created On    : 2023-01-11s
+// Last Modified :
+// -----------------------------------------------------------------
+// Description:
+//
+//
+// -FHDR------------------------------------------------------------
+
+#include "typedef.h"
+#include "ucp_utility.h"
+//#include "cpri_csu_lte_fdd.h"
+#include "cpri_csu_api.h"
+
+#include "cpri_test_case83.h"
+#include "cpri_timer.h"
+#include "ape_csu.h"
+#include "cpri_test.h"
+#include "ucp_printf.h"
+#include "HeaderRam.h"
+#include "cpri_driver.h"
+#include "nr_mem_def.h"
+#include "phy_para.h"
+#include "hw_cpri.h"
+
+#include <malloc.h>
+//uint32_t srcImData[4*1024] = {0};	// 16KB
+extern uint32_t 		gCpriTestMode;
+extern stMtimerIntStat 	gMtimerIntCnt[SCS_MAX_NUM];
+
+extern stCpriCsuCmdFifoInfo txCmdFifo;
+extern stCpriCsuCmdFifoInfo rxCmdFifo;
+
+extern uint32_t         gCpriTestMode;
+//extern uint32_t         CPRI_OPTION;
+extern uint32_t			gCpriCsuDummyFlag;
+
+extern uint32_t compressData[1920];
+extern uint32_t antData0[61440];
+extern uint32_t antData1[61440];
+extern uint32_t antData2[61440];
+extern uint32_t antData3[61440];
+
+#define HeaderTestCnt   10
+
+int32_t fh_data_init(void)
+{
+	gCpriTestMode = CPRI_TEST_MODE;
+	gCpriCsuDummyFlag  = 1;
+	debug_write((DBG_DDR_IDX_DRV_BASE+192), gCpriTestMode); // 0x300
+
+//	Get_Cpri_OptionId();//get cpri option value
+//	debug_write((DBG_DDR_IDX_DRV_BASE+193), CPRI_OPTION); // 0x304
+		
+	Axc_data_init();//init axc data
+	UCP_PRINT_EMPTY("Axc data init.\r\n");
+	HeaderTxRam_data_init();
+	//HeaderTxRam_init();
+	AUX_Rx_init(0x50000000,0x60000000,0x10000,0x10000);
+	return 0;
+}
+
+int32_t fh_drv_init(void)
+{
+	cpri_init(CPRI_OPTION_8, OTIC_MAP_FIGURE12);//NR TDD和FDD的mapping是一样的
+	return 0;
+}
+
+int32_t fh_csu_test_init(void)
+{
+	Config_Cpri_Csu_Nr(0);
+	return 0;
+}
+
+void fh_test_case()
+{
+	UCP_API_CPRI_CSU_START(txCmdFifo, rxCmdFifo);
+}
+
+
+void HeaderTxRam_data_init()
+{
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr0 +i),0x12345678+i);
+	}
+#if 0
+	for(int i=0;i<16*HeaderTestCnt;i++)
+	{
+		do_write(((uint32_t *)HeaderTxDataAddr1 +i),0x87654321+i);
+	}
+#endif
+}
+
+void Axc_data_init()
+{
+	uint8_t idID = 0;
+	uint8_t idSlot = 0;			// even slot, odd slot
+	uint8_t idSymbolBlock = 0;	// symbol0~6, symbol7~13
+	uint32_t  srcAddr = 0;
+	uint32_t  dstAddr = 0;
+	uint32_t  dataLen = 0;
+	uint16_t  bfByteCnt = 0;
+	uint32_t  slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t  f7BfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*6)*2;
+	uint32_t  b7BfCnt = (SHORTCP_BF_CNT*7)*2;
+
+	uint32_t cpyCnt = 0;
+	// valid data
+	// compress factor
+	for (idSlot = 0; idSlot <= 1; idSlot++)
+	{
+		bfByteCnt = 2;
+		
+		if (0 == idSlot)	// even slot
+		{
+			srcAddr = (uint32_t)(&compressData[0]);
+			dstAddr = SM1_NR_CELL0_EVEN_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_EVEN_COMPRESS_ADDR;
+		}
+		else				// odd slot
+		{
+			srcAddr = (uint32_t)(&compressData[3840>>1]);
+			dstAddr = SM1_NR_CELL0_ODD_TX_COMP_FACTOR_ADDR;//CPRI_NR7DS2U_TX_SLOT_ODD_COMPRESS_ADDR;
+		}
+		dataLen = (bfByteCnt*slotBfCnt); 
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+		debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+		cpyCnt++;
+		memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+	}
+
+	// IQ data	
+	for (idID = 1; idID < 5; idID++)
+	{
+		bfByteCnt = 64;
+		for (idSlot = 0; idSlot <= 1; idSlot++)
+		{
+			for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
+			{
+				if ((0 == idSlot) && (0 == idSymbolBlock))	// even slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[0]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[0]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[0]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[0]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[0]);
+					if(idID < 3)
+					{
+						dstAddr = SM0_NR_CELL0_EVEN_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+					
+				}
+				else if ((0 == idSlot) && (1 == idSymbolBlock))	// even slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[15376*2]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[15376*2]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[15376*2]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[15376*2]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[15376]);
+					
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_EVEN_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (0 == idSymbolBlock))	// odd slot, symbol0~6
+				{
+					dataLen = bfByteCnt * f7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[0]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[0]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[0]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[0]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720]);
+					
+					if(idID < 3)
+					{
+						dstAddr = SM1_NR_CELL0_ODD_F7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				else if ((1 == idSlot) && (1 == idSymbolBlock))	// odd slot, symbol7~13
+				{
+					dataLen = bfByteCnt * b7BfCnt;
+					switch(idID)
+					{
+						case 1:
+							srcAddr = (uint32_t)(&antData0[15376*2]);break;
+						case 2:
+							srcAddr = (uint32_t)(&antData1[15376*2]);break;	
+						case 3:
+							srcAddr = (uint32_t)(&antData2[15376*2]);break;
+						case 4:
+							srcAddr = (uint32_t)(&antData3[15376*2]);break;
+					}
+					//srcAddr = (uint32_t)(&antData[30720+15376]);
+					
+					if(idID < 3)
+					{
+						dstAddr = SM4_NR_CELL0_ODD_B7_TX_DATA_ADDR + (idID-1)*dataLen;
+					}
+					else
+					{
+						dstAddr =CSU_TX_DUMMYBUFFER_ADDR;
+					}
+				}
+				
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x310
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
+				debug_write((DBG_DDR_IDX_DRV_BASE+196+((cpyCnt<<2)+2)), (uint32_t)dataLen);
+				cpyCnt++;
+				memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
+			}
+		}
+	}
+	
+}
+
+
+uint32_t Txdata[48] ={0};
+uint32_t Rxdata0[48] ={0};
+
+uint32_t Header_error0=0;
+uint32_t Header_error1 = 0;
+//uint32_t HeaderRxtimes = 0;
+extern uint32_t HeaderTxtimes;
+extern volatile uint32_t gVendorFlag;
+
+void Cpri_Header_Rx(void)
+{
+	uint32_t j= 0;
+	if(OTIC_MAP_FIGURE12 == gVendorFlag)
+	{
+//		HeaderRxtimes++;
+#if 1
+		while(1)
+		{
+			if((UCP_API_CPRI_GetRxHfnCnt() == (HeaderTxHFN0+2)))//BFN=112
+			{
+				break;
+			}
+		}
+#endif
+		debug_write((DBG_DDR_IDX_CPRI_BASE+142), do_read_volatile(&AUX_CNT0));
+		debug_write((DBG_DDR_IDX_CPRI_BASE+143), do_read_volatile(&AUX_CNT2));
+
+		for(j=0;j<4;j++)
+		{
+			Rxdata0[j*12]	= HeaderRam_Rx(8+64*j, 0);
+			Rxdata0[1+j*12] = HeaderRam_Rx(9+64*j, 0);
+			Rxdata0[2+j*12] = HeaderRam_Rx(10+64*j,0);
+			Rxdata0[3+j*12] = HeaderRam_Rx(11+64*j,0);
+			Rxdata0[4+j*12] = HeaderRam_Rx(12+64*j,0);
+			Rxdata0[5+j*12] = HeaderRam_Rx(13+64*j,0);
+			Rxdata0[6+j*12] = HeaderRam_Rx(14+64*j,0);
+			Rxdata0[7+j*12] = HeaderRam_Rx(15+64*j,0);
+			Rxdata0[8+j*12] = HeaderRam_Rx(16+64*j,0);
+			Rxdata0[9+j*12] = HeaderRam_Rx(17+64*j,0);
+			Rxdata0[10+j*12] = HeaderRam_Rx(18+64*j,0);
+			Rxdata0[11+j*12] = HeaderRam_Rx(19+64*j,0);
+
+		}
+		memcpy_ucp((uint32_t*)HeaderRxDataAddr0,(uint32_t*)Rxdata0, 48*4);
+	//	memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderRxtimes%2)*48*4)), 48*4);//NS=8~19
+		memcpy_ucp((uint32_t*)Txdata,(uint32_t*)(HeaderTxDataAddr0 + ((HeaderTxtimes%2)*48*4)), 48*4);//NS=8~19
+		for(j=0;j<48;j++)
+		{
+			if (Rxdata0[j] != Txdata[j])//vendor
+			{
+				Header_error0++;
+				Header_error1++;
+			}
+		}
+
+		
+		if(Header_error1!=0)
+		{
+			memcpy_ucp((uint32_t*)HeaderRxDataAddr1,(uint32_t*)Rxdata0, 64);
+			Header_error1 =0;
+		}
+		debug_write((DBG_DDR_IDX_CPRI_BASE+140), Header_error0);
+	}
+}
+
+
+uint32_t gCompWordCnt = 0;
+uint32_t gErrSlotIdCnt = 0;
+uint32_t gCompSlotIdCnt = 0;
+uint32_t gBfStartErr = 0;
+uint32_t cnt = 0;
+void fh_data_check(uint32_t times)
+{
+	stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
+	if (4 <= pMtimerInt->csuEnCnt)
+	{
+		gCompWordCnt = 0;
+		for (int32_t i = 0; i < (CPRI_CASE83_SLOT_NUM>>1); i++)
+		{
+			cpri_check_slot_data(i);
+		}
+		#if 0
+		if(24000 <= pMtimerInt->csuEnCnt)
+		{ 
+			
+			//if(0 == cnt)
+			{
+				if(0 == gErrSlotIdCnt)
+				{ 
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+80), (0x5a5a5a5a+cnt));
+					UCP_PRINT_WARN("cpri test pass!\r\n");
+				}
+				else
+				{
+					//debug_write((DBG_DDR_IDX_CPRI_BASE+81), (0x6a6a6a6a+cnt));
+					UCP_PRINT_WARN("cpri test fail!!!!!!!!!\r\n");
+				}
+				cnt++;				
+			}			
+		}
+		#endif
+		Cpri_Header_Rx();
+	}
+}
+
+
+void cpri_check_slot_data(uint32_t slotNum)
+{
+	uint32_t slotId = 0;
+	uint32_t srcAddr = 0;
+	uint32_t realSrcAddr = 0;
+//	uint32_t totalSlotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint32_t slotBfCnt = (LONGCP_BF_CNT+SHORTCP_BF_CNT*13)*2;
+	uint8_t	bfWordCnt = 0;
+	uint8_t slotVal = 0;
+	uint8_t idVal = 0;
+	int32_t bfStart = 0;
+
+	uint32_t compVal = 0;
+	uint32_t recvVal = 0;
+	uint32_t recvAddr = 0;
+	slotId = slotNum;	// get_tx_nr_slot(NR_SCS_30K);
+//	__ucps2_synch(0);
+	for (uint32_t i = 0; i < 6; i++)
+	{
+		gCompSlotIdCnt++;
+		idVal = i;
+		bfStart = 0;
+//		__ucps2_synch(0);
+		
+		if((slotId & 0x1) == 1) //奇时隙
+		{
+			slotVal = 1;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM3_NR_CELL0_ODD_RX_DATA_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM3_NR_CELL0_ODD_RX_DATA_ADDR + (2*slotBfCnt) + ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_ODD_RX_AGC_ADDR;
+			}
+		}
+		else//偶时隙
+		{
+			slotVal = 0;
+			if(0 == i)//NR :压缩因子和AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVEN_RX_DATA_ADDR;
+			}		
+			else if((1 <= i) && (2 >= i)) //NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = (SM1_NR_CELL0_EVEN_RX_DATA_ADDR + (2*slotBfCnt)+ ((i-1)*64*slotBfCnt));
+			}
+			else if((3 <= i) && (4 >= i))//NR :2条天线数据交织:64B
+			{
+				bfWordCnt = (64>>2);
+				srcAddr = CSU_RX_DUMMYBUFFER_ADDR;
+			}
+			else//NR :AGC:2B
+			{
+				bfWordCnt = 1;
+				srcAddr = SM1_NR_CELL0_EVNE_RX_AGC_ADDR;
+			}
+		}
+					
+		if (0 == i)	// compress factor:NR
+		{
+			for (int32_t idBf = 0; idBf < (slotBfCnt>>1); idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					compVal = do_read_volatile(compressData+idBf*bfWordCnt + idWord);//Nr_CompressData[idBf*bfWordCnt + idWord];
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;
+					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8))); 	// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt);		// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+//					__ucps2_synch(0);
+				}
+			}
+		}
+		else if((1 <= i) && (2 >= i))		// 天线0,1
+		{
+			for (int32_t idBf = 0; idBf < slotBfCnt; idBf++)
+			{
+				for (uint32_t idWord = 0; idWord < bfWordCnt; idWord++)
+				{
+					if(1 == i)//天线0
+					{
+						compVal = do_read_volatile(antData0+idBf*bfWordCnt + idWord);//Lte_antData[idBf*bfWordCnt + idWord];
+					}
+					else//天线1
+					{
+						compVal = do_read_volatile(antData1+idBf*bfWordCnt + idWord);//Nr_antData23[idBf*bfWordCnt + idWord];
+					}
+
+					debug_write((DBG_DDR_IDX_DRV_BASE+1026), gCompWordCnt); 
+					gCompWordCnt++;					
+					__ucps2_synch(0);
+					
+					recvAddr = (uint32_t)((uint32_t*)srcAddr + idBf*bfWordCnt + idWord);
+					realSrcAddr = srcAddr;
+//					__ucps2_synch(0);					
+					recvVal = do_read_volatile(recvAddr); // *((uint32_t*)recvAddr);
+					__ucps2_synch(0);
+					if (recvVal != compVal)
+					{
+						if (gErrSlotIdCnt < 0x100)
+						{
+							debug_write((DBG_DDR_IDX_DRV_BASE+1028+((gErrSlotIdCnt<<3)&0x7FF)), compVal);		// 0x320
+							debug_write((DBG_DDR_IDX_DRV_BASE+1029+((gErrSlotIdCnt<<3)&0x7FF)), recvVal);		// 0x324
+							debug_write((DBG_DDR_IDX_DRV_BASE+1030+((gErrSlotIdCnt<<3)&0x7FF)), recvAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1031+((gErrSlotIdCnt<<3)&0x7FF)), realSrcAddr);		// 0x32c
+							debug_write((DBG_DDR_IDX_DRV_BASE+1032+((gErrSlotIdCnt<<3)&0x7FF)), (slotId+(i<<4)+(idBf<<8)));		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1033+((gErrSlotIdCnt<<3)&0x7FF)), bfStart);		// 0x328
+							debug_write((DBG_DDR_IDX_DRV_BASE+1034+((gErrSlotIdCnt<<3)&0x7FF)), slotBfCnt); 	// 0x328
+						}
+						gErrSlotIdCnt++;
+//						break;
+//						break;
+					}
+				}
+			}
+		}
+		else
+		{
+		}
+	
+		debug_write((DBG_DDR_IDX_DRV_BASE+1024), gCompSlotIdCnt);	// 0x1000
+		debug_write((DBG_DDR_IDX_DRV_BASE+1025), gErrSlotIdCnt);	// 0x1004
+	}
+}

public/test/testcase_fh/case83/src/cpri_test_case83_AGC.s.c

@@ -0,0 +1,7 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+DDR0 uint32_t Agc_Data[2880] = {
+	0
+};
+

public/test/testcase_fh/case83/src/cpri_test_case83_NrAntdata2.s.c

@@ -0,0 +1,6 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+
+DDR0 uint32_t antData2[61440] = {0};
+

public/test/testcase_fh/case83/src/cpri_test_case83_NrAntdata3.s.c

@@ -0,0 +1,6 @@
+#include "typedef.h"
+#include "mem_sections.h"
+
+
+DDR0 uint32_t antData3[61440] = {0};
+