jinhong/YB_Platform
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

1. JESD 9.8g, UCP4008_SL_EVB, new feature #1028;

Browse Source 
2. cell setup/delete bug, UCP4008_SL_EVB, bug #1071;
3. task delete bug when deleting cell, bug #1061;
4. delete board direction;
5. add some cell setup parameters for FDD mode extend
This commit is contained in:
xinxin.li 2023-09-15 14:59:25 +08:00
parent febc9a0439
commit f3ff36cc8c
49 changed files with 2337311 additions and 491836 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
EVB/driver/inc/hw_gpio.h
View File

@ -1,26 +0,0 @@
#ifndef _HW_GPIO_H_
#define _HW_GPIO_H_
#include "dw_apb_gpio.h"
// ctrl pa/lna
// rx off tx on
#define TxOn() {GPIO1_SWPORTB_DR |= (GPIO_Pin_17|GPIO_Pin_16|GPIO_Pin_19|GPIO_Pin_18); GPIO1_SWPORTB_DR &= (~(GPIO_Pin_13|GPIO_Pin_12|GPIO_Pin_15|GPIO_Pin_14));}
// tx off
#define TxOff() {GPIO1_SWPORTB_DR |= (GPIO_Pin_13|GPIO_Pin_12|GPIO_Pin_15|GPIO_Pin_14); }
// tx off rx on
#define RxOn() {GPIO1_SWPORTB_DR |= (GPIO_Pin_13|GPIO_Pin_12|GPIO_Pin_15|GPIO_Pin_14); GPIO1_SWPORTB_DR &= (~(GPIO_Pin_17|GPIO_Pin_16|GPIO_Pin_19|GPIO_Pin_18));}
// rx off
#define RxOff() {GPIO1_SWPORTB_DR |= (GPIO_Pin_17|GPIO_Pin_16|GPIO_Pin_19|GPIO_Pin_18); }
//void hw_gpio_init();
void rfm1_set_trigger_high();
void rfm1_set_trigger_low();
#endif

28
EVB/driver/src/hw_gpio.s.c
View File

@ -1,28 +0,0 @@
#include "hw_gpio.h"
#include "dw_apb_gpio.h"
#include "ucp_utility.h"
#include "ucp_param.h"
#if 0
void hw_gpio_init()
{
do_write(RF_LVDS_PMUX1_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX1_REG_ADDR)|0x000F0000)); // pinmux, GPIO1B25 and GPIO1B24, gpio func, 0x3
do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25|BIT19|BIT18|BIT17|BIT16|BIT15|BIT14|BIT13|BIT12))); // GPIO1B25, output, 10ms trigger for phy
}
#endif
void rfm1_set_trigger_high()
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT25)); // GPIO1B25, high
//do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT24)); // GPIO1B24, high
}
void rfm1_set_trigger_low()
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT25)))); // GPIO1B25, low
//do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT24)))); // GPIO1B24, low
}

22
EVMY/driver/inc/hw_gpio.h
View File

@ -1,22 +0,0 @@
#ifndef _HW_GPIO_H_
#define _HW_GPIO_H_
#include "dw_apb_gpio.h"
// EVMY
// ctrl RF
#define TxOn() {GPIO1_SWPORTB_DR |= (GPIO_Pin_5|GPIO_Pin_4|GPIO_Pin_7|GPIO_Pin_6);}
#define TxOff() {GPIO1_SWPORTB_DR &= (~(GPIO_Pin_5|GPIO_Pin_4|GPIO_Pin_7|GPIO_Pin_6)); }
#define RxOn() {GPIO1_SWPORTB_DR &= (~(GPIO_Pin_24|GPIO_Pin_25)); }
#define RxOff() {GPIO1_SWPORTB_DR |= (GPIO_Pin_24|GPIO_Pin_25);}
//void hw_gpio_init();
void rfm1_set_trigger_high();
void rfm1_set_trigger_low();
#endif

25
EVMY/driver/src/hw_gpio.s.c
View File

@ -1,25 +0,0 @@
#include "hw_gpio.h"
#include "dw_apb_gpio.h"
#include "ucp_utility.h"
#include "ucp_param.h"
#if 0
void hw_gpio_init()
{
do_write(RF_LVDS_PMUX0_REG_ADDR, (do_read_volatile(RF_LVDS_PMUX0_REG_ADDR)|0x00030000)); // pinmux, GPIO1B8, gpio func, 0x3
do_write(GPIO1B_DIR_REG_ADDR, (do_read_volatile(GPIO1B_DIR_REG_ADDR)|(BIT25|BIT24|BIT8|BIT7|BIT6|BIT5|BIT4))); // GPIO1B8, output, 10ms trigger for phy
}
#endif
void rfm1_set_trigger_high()
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT8)); // GPIO1B8, high
}
void rfm1_set_trigger_low()
{
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT8)))); // GPIO1B8, low
}

19
inc/drv_rfm.h
View File

@ -87,19 +87,22 @@ int get_rx_slot_intflag(uint8_t scs);
typedef struct phy_timer_config_ind_t
{
uint32_t scsId;
uint32_t frameType; //0:FDD, 1:TDD, 2:TDD(双周期DDDSUDDSUU)
uint32_t scsId;
uint32_t runCoreId; // 此次需要建小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。
uint16_t bandWidth; //带宽:5M,10M,15M,20M,25M,30M,40M,50M,60M,80M,100M
uint16_t t_period; //timer周期=t_us*num_t, 500us, 625us, 1000us, 1250us, 2500us, 5000us, 10000us, 20000us
uint16_t t_period; //timer周期=t_us*num_tti, 500us, 625us, 1000us, 1250us, 2500us, 5000us, 10000us, 20000us
uint16_t t_us; //物理层时隙定时长度, 125us, 250us, 500us, 1000us
uint8_t num_t; //timer周期内时隙的个数5,10,20,40,80
uint8_t num_t_per_sfn; //一个SFN内的时隙个数
uint8_t num_tti; //timer周期内时隙的个数5,10,20,40,80
uint8_t num_tti_per_sfn; //一个SFN内的时隙个数
uint8_t num_t_dl; //下行时隙个数
uint8_t num_t_dl_symb; //时隙内下行符号个数
uint8_t num_t_ul_symb; //时隙内上行符号个数
uint8_t num_ants; //天线个数
uint8_t num_t_dl[2]; //下行时隙个数
uint8_t num_t_dl_symb[2]; //S时隙内下行符号个数
uint8_t num_t_ul_symb[2]; //S时隙内上行符号个数
uint8_t num_ants[2]; //天线个数
}phy_timer_config_ind_t;
typedef struct _tagPhyDelCell

2
inc/osp_ape.h
View File

@ -87,7 +87,7 @@ extern int osp_task_create(osp_task_info_ex *);
函数入参：scsId: scs id
函数功能：任务删除接口
*/
osp_del_task(int prio, int scsId);
extern void osp_del_task(int prio, int scsId);
/*
函数名称：osp_var_init

16
public/ape_spu/driver/src/ape_mtimer.s.c
View File

@ -398,7 +398,9 @@ int32_t get_rx_lte_subframe()
uint32_t get_tx_nr_slot_cycle()
{
int32_t offsetCycle = GET_STC_CNT() - gCellSfnPara[gMtimerId].txSlotTiming;
uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
__ucps2_synch(0);
int32_t offsetCycle = GET_STC_CNT() - txSlotTiming;
if (0 > offsetCycle)
{
uint32_t limitVal = 1000000000;
@ -410,7 +412,9 @@ uint32_t get_tx_nr_slot_cycle()
uint32_t get_tx_lte_subframe_cycle()
{
int32_t offsetCycle = GET_STC_CNT() - gCellSfnPara[gMtimerId].txSlotTiming;
uint32_t txSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].txSlotTiming;
__ucps2_synch(0);
int32_t offsetCycle = GET_STC_CNT() - txSlotTiming;
if (0 > offsetCycle)
{
uint32_t limitVal = 1000000000;
@ -422,7 +426,9 @@ uint32_t get_tx_lte_subframe_cycle()
uint32_t get_rx_nr_slot_cycle()
{
int32_t offsetCycle = GET_STC_CNT() - gCellSfnPara[gMtimerId].rxSlotTiming;
uint32_t rxSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].rxSlotTiming;
__ucps2_synch(0);
int32_t offsetCycle = GET_STC_CNT() - rxSlotTiming;
if (0 > offsetCycle)
{
uint32_t limitVal = 1000000000;
@ -434,7 +440,9 @@ uint32_t get_rx_nr_slot_cycle()
uint32_t get_rx_lte_subframe_cycle()
{
int32_t offsetCycle = GET_STC_CNT() - gCellSfnPara[gMtimerId].rxSlotTiming;
uint32_t rxSlotTiming = (uint32_t)gCellSfnPara[gMtimerId].rxSlotTiming;
__ucps2_synch(0);
int32_t offsetCycle = GET_STC_CNT() - rxSlotTiming;
if (0 > offsetCycle)
{
uint32_t limitVal = 1000000000;

7
public/ape_spu/driver/src/stc_timer.s.c
View File

@ -136,7 +136,12 @@ uint32_t stc_pclk_init()
// laneRate = IQ_sample_rate * M * N' * (10/8)/L // max_laneRate = 12.5Gbps
// serdesTxClk = laneRate/40;
// pClk = serdesTxClk;
pClk = (uint64_t)(122880000/4/40)*8*16*10/8;
uint32_t samClk = do_read_volatile(JESD_TX_SAMPLE_RATE);
uint32_t jesdPara = do_read_volatile(JESD_TX_CH_PARA);
uint8_t paraL = jesdPara & 0xFF;
uint8_t paraM = (jesdPara >> 8) & 0xFF;
uint8_t paraN = (jesdPara >> 16) & 0xFF;
pClk = (uint64_t)(samClk/paraL/40)*paraM*paraN*10/8; // (uint64_t)(122880000/4/40)*8*16*10/8;
}
else
{

5
public/ape_spu/osp/src/osp_task.s.c
View File

@ -783,6 +783,7 @@ void osp_del_task(int prio, int scsId)
tcb_handle = (osp_tcb*)g_tcb_handler_tbl[task_id];
/* 根据消息类型分别处理 */
#if 0
if (OSP_TIMER_TYPE == tcb_handle->task_type)
{
/* 只要删除定时点任务，那就清空所有定时点任务相关信息 */
@ -790,7 +791,9 @@ void osp_del_task(int prio, int scsId)
osp_timer_unsync(scsId);
return ;
}
else if (OSP_EVENT_TYPE == tcb_handle->task_type)
else
#endif
if (OSP_EVENT_TYPE == tcb_handle->task_type)
{
/* 事件任务，删除事件信号量和软件队列 */
osp_delete_sem(tcb_handle->event_sem);

44
public/common/driver/inc/phy_para.h
View File

@ -39,13 +39,22 @@
#define SERDES_INIT_FLAG_ADDR (SPU_DRV_SM_ADDR+0x240) // cpri or jesd clk init finished
#define STC_ONEPPS_OUT_ADDR (SPU_DRV_SM_ADDR+0x244)
#define DDR_MONITOR_ENABLE (SPU_DRV_SM_ADDR+0x250) // 开始监测ddr性能
#define DDR_MONITOR_CNT (SPU_DRV_SM_ADDR+0x254)
#define JESD_TX_CH_PARA (SPU_DRV_SM_ADDR+0x248)
#define JESD_TX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x24C)
#define JESD_RX_CH_PARA (SPU_DRV_SM_ADDR+0x250)
#define JESD_RX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x254)
#define JESD_ORX_CH_PARA (SPU_DRV_SM_ADDR+0x258)
#define JESD_ORX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x25C)
#define CPRI_TX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x260)
#define CPRI_RX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x264)
#define CPRI_TDD_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x268)
#define DDR_MONITOR_ENABLE (SPU_DRV_SM_ADDR+0x270) // 开始监测ddr性能
#define DDR_MONITOR_CNT (SPU_DRV_SM_ADDR+0x274)
// GPIO JESD TX/RX/ORX bit
#define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280)
#define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0)
@ -145,6 +154,14 @@ typedef enum _tagScsID
SCS_NULL = 0xFFFF
}numScsID;
typedef enum _tagFrameType
{
FDD_MODE = 0,
TDD_MODE = 1,
TDD_2500US_DOUBLE = 2,
FRAME_NULL = 0xFFFF
}numFrameType;
typedef struct _tagCoreInt
{
uint32_t intNum;
@ -172,7 +189,7 @@ typedef struct _tagPhyScsPara
// UINT64 rxSlotStcCnt;
// UINT64 txSlotStcCnt;
}stPhyScsPara;
#if 0
typedef struct phy_timer_config_ind_t
{
uint32_t scsId;
@ -189,6 +206,27 @@ typedef struct phy_timer_config_ind_t
uint8_t num_t_ul_symb; //时隙内上行符号个数
uint8_t num_ants; //天线个数
}phy_timer_config_ind_t;
#else
typedef struct phy_timer_config_ind_t
{
uint32_t frameType; //0:FDD, 1:TDD, 2:TDD(双周期DDDSUDDSUU)
uint32_t scsId;
uint32_t runCoreId; // 此次需要建小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。
uint16_t bandWidth; //带宽:5M,10M,15M,20M,25M,30M,40M,50M,60M,80M,100M
uint16_t t_period; //timer周期=t_us*num_tti, 500us, 625us, 1000us, 1250us, 2500us, 5000us, 10000us, 20000us
uint16_t t_us; //物理层时隙定时长度, 125us, 250us, 500us, 1000us
uint8_t num_tti; //timer周期内时隙的个数5,10,20,40,80
uint8_t num_tti_per_sfn; //一个SFN内的时隙个数
uint8_t num_t_dl[2]; //下行时隙个数
uint8_t num_t_dl_symb[2]; //S时隙内下行符号个数
uint8_t num_t_ul_symb[2]; //S时隙内上行符号个数
uint8_t num_ants[2]; //天线个数
}phy_timer_config_ind_t;
#endif
typedef struct _tagPhyDelCell
{

2
public/common/driver/src/ape_csu.s.c
View File

@ -813,7 +813,7 @@ uint32_t spu_csu_dma_1D_transfer(uint64_t addrSrc, uint64_t addrDst, uint32_t da
fifoNum = (temp>>8) & 0xFF;
tag = (temp>>16)&0xFF;
uint8_t offset_w = regGroup << 4;
uint16_t offset_w = regGroup << 4;
// src reg
do_write(((uint32_t*)(&APC_CSU_DMAADDRL0) + offset_w), addrSrc & 0xFFFFFFFF);
do_write(((uint32_t*)(&APC_CSU_DMAADDRH0) + offset_w), (uint32_t)(addrSrc >> 32));

6
public/common/ecs_dm/inc/gpio_drv.h
View File

@ -20,10 +20,10 @@ typedef enum _tagJesdGpioTRCH
JESD_TRCH_MAXNUM = 3
}jesdGpioTRch;
typedef enum _tagJesdGpioState
typedef enum _tagGpioState
{
JESD_GPIO_OFF = 0,
JESD_GPIO_ON = 1
GPIO_OFF = 0,
GPIO_ON = 1
}jesdGpioState;
typedef struct _tagGpioInfo

44
public/ecs_rfm_spu1/driver/inc/jesd_csu_lte_fdd.h Normal file
View File

@ -0,0 +1,44 @@
#ifndef _JESD_CSU_LTE_FDD_H_
#define _JESD_CSU_LTE_FDD_H_
#include "typedef.h"
// 4 ant, LTE
#define JESD_LTEFDD_ANT_NUM 2
#define JESD_LTEFDD_MARGIN 5
#define JESD_LTEFDD_SLOT_NUM 10
#define JESD_LTEFDD_TX_NODENUM 10
#define JESD_LTEFDD_RX_NODENUM 10
#define JESD_LTEFDD_SUBFRAME_SAM_CNT 61440
#define JESD_LTEFDD_TX_LIST_ADDR 0x8A000000
#define JESD_LTEFDD_RX_LIST_ADDR 0x8A008000
#if 0
#define JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x9F00000 // SM2
#define JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x9FF0400 // SM2
#define JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0xA380000 // SM5
#define JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0xA290400 // SM4
#else
#define JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR 0x60F00000 // 0xF0000
#define JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR 0x60FF0000 // 0xF0000
#endif
#define JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR 0x6BC00000 // 0xF0000
#define JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR 0x6BCF0000 // 0xF0000
int32_t jesd_csu_init_lte_fdd();
#if 0
int32_t jesd_csu_init_nr_7ds2u_iomode();
int32_t jesd_csu_init_nr_7ds2u_8t8r();
int32_t jesd_csu_init_nr_7ds2u_4t4r_98();
int32_t jesd_csu_start_nr_7ds2u();
int32_t jesd_csu_start_nr_7ds2u_8t8r();
#endif
#endif

9
public/ecs_rfm_spu1/driver/inc/jesd_csu_nr_7ds2u.h
View File

@ -45,6 +45,15 @@
#define JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x60F00000 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x60FF0400 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0x61380000 // SM5
#define JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0x61290400 // SM4
#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
int32_t jesd_csu_init_nr_7ds2u();
int32_t jesd_csu_init_nr_7d2u_slot0();
int32_t jesd_csu_init_nr_7ds2u_iomode();

46
public/ecs_rfm_spu1/driver/src/cpri_timer.s.c
View File

@ -21,7 +21,7 @@
#include "mtimer_drv.h"
#include "mtimer_cal.h"
#include "gtimer_drv.h"
#include "hw_gpio.h"
#include "gpio_drv.h"
#include "ape_csu.h"
#include "cpri_driver.h"
@ -142,18 +142,23 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
pCpriDelay->cpri10ms2PP1sRxOffset = gpsOffset - pCpriDelay->cpri10msRxOffset; // delay us
pCpriDelay->cpriTdd2PP1sOffset = gpsOffset + pCpriDelay->cpriTddOffset; // advance us as positive number
do_write(CPRI_TX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sTxOffset);
do_write(CPRI_RX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sRxOffset);
do_write(CPRI_TDD_ADVANCE_PP1S_ADDR, pCpriDelay->cpriTdd2PP1sOffset);
reCfgFlag = 1;
set_cpri_tx_rfp();
if (do_read_volatile(CPRI_ADVANCE_ADDR) != (FIBER_MIN_DELAY+INT_DELAY))
// if (do_read_volatile(CPRI_ADVANCE_ADDR) != (FIBER_MIN_DELAY+INT_DELAY))
if (do_read_volatile(CPRI_TX_ADVANCE_PP1S_ADDR) != pCpriDelay->cpri10ms2PP1sTxOffset)
{
while (1 == reCfgFlag);
while (1 == reCfgFlag);
}
else
{
gCpriIntStatus.cpriSyncFlag = 1;
}
do_write(CPRI_TX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sTxOffset);
do_write(CPRI_RX_ADVANCE_PP1S_ADDR, pCpriDelay->cpri10ms2PP1sRxOffset);
do_write(CPRI_TDD_ADVANCE_PP1S_ADDR, pCpriDelay->cpriTdd2PP1sOffset);
//set_cpri_tmr_period(); // set OVF value, every slot int and 10ms int, cevent0/2 for ape0, report link status
#ifdef PALLADIUM_TEST
flag++;
@ -163,18 +168,18 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
pMtimerPara->scsId = my_cpritmr->scsId;
pMtimerPara->runCoreId = (uint16_t)my_cpritmr->runCoreId;
pMtimerPara->tddPeriod = my_cpritmr->t_period; // us
pMtimerPara->tddSlotNum = my_cpritmr->num_t;
pMtimerPara->tddSlotNum = my_cpritmr->num_tti;
pMtimerPara->slotPeriod = my_cpritmr->t_us;
pMtimerPara->slotMaxNum = my_cpritmr->num_t_per_sfn;
pMtimerSfn->slotMaxNum = my_cpritmr->num_t_per_sfn;
pMtimerSfn->slotNumPP1s = (pCpriDelay->cpri10ms2PP1sTxOffset / my_cpritmr->t_us) % my_cpritmr->num_t_per_sfn;
pMtimerPara->slotMaxNum = my_cpritmr->num_tti_per_sfn;
pMtimerSfn->slotMaxNum = my_cpritmr->num_tti_per_sfn;
pMtimerSfn->slotNumPP1s = (pCpriDelay->cpri10ms2PP1sTxOffset / my_cpritmr->t_us) % my_cpritmr->num_tti_per_sfn;
gScsId = my_cpritmr->scsId;
gMtimerId = MTIMER_CPRI_ID;
gCellSfnPara[MTIMER_CPRI_ID].scsId = my_cpritmr->scsId;
do_write_short((&(phyPara[my_cpritmr->scsId].slotNumOfTdd)), my_cpritmr->num_t);
do_write_short((&(phyPara[my_cpritmr->scsId].slotNumOfTdd)), my_cpritmr->num_tti);
do_write_short((&(phyPara[my_cpritmr->scsId].mtimerId)), MTIMER_CPRI_ID);
__ucps2_synch(0);
@ -217,6 +222,11 @@ void cpri_timer_reconfig(phy_timer_config_ind_t *my_cpritmr)
void cpri_timer_clear_cell(uint8_t scsId)
{
stMtimerSfnCal* pSfnCal = &gMtimerSfnCalPara[MTIMER_CPRI_ID];
stMtimerIntStat* pMtimerInt = &gMtimerIntCnt[MTIMER_CPRI_ID];
pSfnCal->sfnCalFinished = 0;
pMtimerInt->csuEnCnt = 0;
UCP_API_CPRI_CSU_STOP(); // 是否需要等几个ms
clear_cpri_tdd_offset();
@ -712,7 +722,7 @@ debug_write((DBG_DDR_IDX_DRV_BASE+288), (GET_STC_CNT()-start)); // 0x480
debug_write((DBG_DDR_IDX_DRV_BASE+910), cEventFlag); // pMtimerInt->txSlotIntCnt); // 0xe38
debug_write((DBG_DDR_IDX_DRV_BASE+911), get_mtimer_rt_scr_value(MTIMER_CPRI_ID)); // pMtimerInt->tddOffsetIntCnt); // 0xe3C
}
rfm1_set_trigger_high();
set_trigger_state(GPIO_ON);
}
if (tEventFlag & (1<<MTMR_10ms_OFFSET)) // 10ms offset int
{
@ -955,13 +965,9 @@ uint32_t start = GET_STC_CNT();
pMtimerSfn->txSlotNum = 0;
}
// test for trigger
if (0 == pMtimerSfn->txSlotNum)
if ((pMtimerSfn->slotMaxNum >> 1) == pMtimerSfn->txSlotNum)
{
//rfm1_set_trigger_high();
}
else if ((pMtimerSfn->slotMaxNum >> 1) == pMtimerSfn->txSlotNum)
{
rfm1_set_trigger_low();
set_trigger_state(GPIO_OFF);
}
__ucps2_synch(0);
#if 0

8
public/ecs_rfm_spu1/driver/src/ecpri_timer.s.c
View File

@ -131,17 +131,17 @@ void ecpri_timer_reconfig(phy_timer_config_ind_t *my_ecpritmr)
pMtimerPara->scsId = my_ecpritmr->scsId;
pMtimerPara->tddPeriod = my_ecpritmr->t_period; // us
pMtimerPara->tddSlotNum = my_ecpritmr->num_t;
pMtimerPara->tddSlotNum = my_ecpritmr->num_tti;
pMtimerPara->slotPeriod = my_ecpritmr->t_us;
pMtimerPara->slotMaxNum = my_ecpritmr->num_t_per_sfn;
pMtimerSfn->slotMaxNum = my_ecpritmr->num_t_per_sfn;
pMtimerPara->slotMaxNum = my_ecpritmr->num_tti_per_sfn;
pMtimerSfn->slotMaxNum = my_ecpritmr->num_tti_per_sfn;
//gScsId = my_ecpritmr->scsId;
//gMtimerId = MTIMER_ECPRI_ID;
//gCellSfnPara[MTIMER_ECPRI_ID].scsId = my_ecpritmr->scsId;
do_write_short((&(phyPara[my_ecpritmr->scsId].slotNumOfTdd)), my_ecpritmr->num_t);
do_write_short((&(phyPara[my_ecpritmr->scsId].slotNumOfTdd)), my_ecpritmr->num_tti);
do_write_short((&(phyPara[my_ecpritmr->scsId].mtimerId)), MTIMER_ECPRI_ID);
__ucps2_synch(0);

118
public/ecs_rfm_spu1/driver/src/gpio_drv.s.c
View File

@ -85,7 +85,7 @@ int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState)
{
return -1;
}
if ((JESD_GPIO_ON != nState) && (JESD_GPIO_OFF != nState))
if ((GPIO_ON != nState) && (GPIO_OFF != nState))
{
return -1;
}
@ -113,11 +113,11 @@ int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState)
}
pinId = pinId & 0x1F;
dataAddr = gGpioDataAddr[pinGroup];
if (((LOW_AS_VALID == valid) && (JESD_GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (JESD_GPIO_OFF == nState)))
if (((LOW_AS_VALID == valid) && (GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_OFF == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)&(~(1<<pinId))));
}
else if (((LOW_AS_VALID == valid) && (JESD_GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (JESD_GPIO_ON == nState)))
else if (((LOW_AS_VALID == valid) && (GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_ON == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)|(1<<pinId)));
}
@ -132,7 +132,8 @@ int32_t set_jesd_rf_state(uint8_t nTRCh, uint8_t nState)
int32_t set_trigger_state(uint8_t nState)
{
if ((JESD_GPIO_ON != nState) && (JESD_GPIO_OFF != nState))
#ifdef INTEGRATED_BS
if ((GPIO_ON != nState) && (GPIO_OFF != nState))
{
return -1;
}
@ -154,11 +155,11 @@ int32_t set_trigger_state(uint8_t nState)
}
pinId = pinId & 0x1F;
dataAddr = gGpioDataAddr[pinGroup];
if (((LOW_AS_VALID == valid) && (JESD_GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (JESD_GPIO_OFF == nState)))
if (((LOW_AS_VALID == valid) && (GPIO_ON == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_OFF == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)&(~(1<<pinId))));
}
else if (((LOW_AS_VALID == valid) && (JESD_GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (JESD_GPIO_ON == nState)))
else if (((LOW_AS_VALID == valid) && (GPIO_OFF == nState)) || ((HIGH_AS_VALID == valid) && (GPIO_ON == nState)))
{
do_write(dataAddr, (do_read_volatile(dataAddr)|(1<<pinId)));
}
@ -166,107 +167,18 @@ int32_t set_trigger_state(uint8_t nState)
{
return -1;
}
return 0;
}
#if 0
int32_t set_tx_on()
{
return 0;
}
int32_t set_tx_off()
{
uint8_t pinGroup = 0;
uint8_t pinId = 0;
uint32_t addr = 0;
for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
#else
if (GPIO_ON == nState)
{
pinGroup = pGpioInfo->jesdGpioInfo.txGpioInfo[i].pinId >> 5;
if (3 < pinGroup)
{
return -1;
}
pinId = pGpioInfo->jesdGpioInfo.txGpioInfo[i].pinId & 0x1F;
addr = gGpioDataAddr[pinGroup];
if (LOW_AS_VALID == pGpioInfo->jesdGpioInfo.txGpioInfo[i].vaFlag)
{
do_write(addr, (do_read_volatile(addr)|(1<<pinId)));
}
else if (HIGH_AS_VALID == pGpioInfo->jesdGpioInfo.txGpioInfo[i].vaFlag)
{
do_write(addr, (do_read_volatile(addr)&(~(1<<pinId))));
}
else
{
return -1;
}
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)|BIT25)); // GPIO1B25, high
}
return 0;
}
int32_t set_rx_on()
{
uint8_t pinGroup = 0;
uint8_t pinId = 0;
uint32_t addr = 0;
for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
else
{
pinGroup = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId >> 5;
if (3 < pinGroup)
{
return -1;
}
pinId = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId & 0x1F;
addr = gGpioDataAddr[pinGroup];
if (LOW_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
{
do_write(addr, (do_read_volatile(addr)&(~(1<<pinId))));
}
else if (HIGH_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
{
do_write(addr, (do_read_volatile(addr)|(1<<pinId)));
}
else
{
return -1;
}
do_write(GPIO1B_DATA_REG_ADDR, (do_read_volatile(GPIO1B_DATA_REG_ADDR)&(~(BIT25)))); // GPIO1B25, low
}
return 0;
}
int32_t set_rx_off()
{
uint8_t pinGroup = 0;
uint8_t pinId = 0;
uint32_t addr = 0;
for (int32_t i = 0; i < JESD_RF_CH_NUM; i++)
{
pinGroup = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId >> 5;
if (3 < pinGroup)
{
return -1;
}
pinId = pGpioInfo->jesdGpioInfo.rxGpioInfo[i].pinId & 0x1F;
addr = gGpioDataAddr[pinGroup];
if (LOW_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
{
do_write(addr, (do_read_volatile(addr)|(1<<pinId)));
}
else if (HIGH_AS_VALID == pGpioInfo->jesdGpioInfo.rxGpioInfo[i].vaFlag)
{
do_write(addr, (do_read_volatile(addr)&(~(1<<pinId))));
}
else
{
return -1;
}
}
return 0;
}
#endif
return 0;
}

57
public/ecs_rfm_spu1/driver/src/jesd_csu_lte_fdd.s.c Normal file
View File

@ -0,0 +1,57 @@
#include "jesd_csu_lte_fdd.h"
#include "jesd_csu.h"
int32_t jesd_csu_init_lte_fdd()
{
jesd_csu_init(JESD_LTEFDD_ANT_NUM, JESD_LTEFDD_MARGIN);
stJesdCsuNodePara txCsuNode[JESD_LTEFDD_TX_NODENUM];
stJesdCsuNodePara rxCsuNode[JESD_LTEFDD_RX_NODENUM];
//tx的链表地址
uint32_t txListAddr = JESD_LTEFDD_TX_LIST_ADDR; // 0x8A000000
//rx的链表地址
uint32_t rxListAddr = JESD_LTEFDD_RX_LIST_ADDR; // 0x8A008000
int32_t i = 0;
// tx/rx, subframe 0~9
for (i = 0; i < JESD_LTEFDD_TX_NODENUM; i++)
{
if (0 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR;
txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<3);
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<3);
}
else if (1 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR;
txCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<3);
rxCsuNode[i].dataAddr = JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_LTEFDD_SUBFRAME_SAM_CNT<<3);
}
}
jesd_csu_tx_list_init(txListAddr, JESD_LTEFDD_TX_NODENUM, txCsuNode);
jesd_csu_tx_dmaReg_Cfg(JESD_CSU_CH0, txListAddr, JESD_LTEFDD_TX_NODENUM);
jesd_csu_rx_list_init(rxListAddr, JESD_LTEFDD_RX_NODENUM, rxCsuNode);
jesd_csu_rx_dmaReg_Cfg(JESD_CSU_CH0, rxListAddr, JESD_LTEFDD_RX_NODENUM);
return 0;
}
#if 0
int32_t jesd_csu_start_lte()
{
jesd_csu_start();
return 0;
}
#endif

16
public/ecs_rfm_spu1/driver/src/jesd_csu_nr_7ds2u.s.c
View File

@ -349,45 +349,45 @@ int32_t jesd_csu_init_nr_7ds2u_4t4r_98()
{
if (0 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR;
txCsuNode[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR; // JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR;
txCsuNode[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4)*2;
}
else if (1 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR;
txCsuNode[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR;
txCsuNode[i].yStep = ((7*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode[i].allNum = ((7*SHORTCP_SAM_CNT)<<4)*2;
}
else if (2 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode[i].allNum = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<4)*2;
}
else if (3 == (i&0x3))
{
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR;
txCsuNode[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR;
txCsuNode[i].yStep = ((7*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode[i].allNum = ((7*SHORTCP_SAM_CNT)<<4)*2;
}
}
// slot7, slots
txCsuNode[i].dataAddr = JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode[i].dataAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR;
txCsuNode[i].yStep = ((LONGCP_SAM_CNT+6*SHORTCP_SAM_CNT)<<2)*2;
txCsuNode[i].allNum = ((LONGCP_SAM_CNT+5*SHORTCP_SAM_CNT)<<4)*2;
// rx list nodes
// slot7, slots
rxCsuNode[0].dataAddr = JESD_NR7DS2U_RX_SLOTS_DATA_ADDR;
rxCsuNode[0].dataAddr = JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR;
rxCsuNode[0].yStep = ((SHORTCP_SAM_CNT*4)<<2)*2;
rxCsuNode[0].allNum = ((SHORTCP_SAM_CNT*4)<<4)*2;
// slot8
rxCsuNode[1].dataAddr = JESD_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode[1].dataAddr = JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode[1].yStep = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<2)*2;
rxCsuNode[1].allNum = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4)*2;
// slot9
rxCsuNode[2].dataAddr = JESD_NR7DS2U_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode[2].dataAddr = JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode[2].yStep = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<2)*2;
rxCsuNode[2].allNum = ((LONGCP_SAM_CNT + SHORTCP_SAM_CNT*13)<<4)*2;

76
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
View File

@ -19,7 +19,6 @@
#include "mtimer_cal.h"
#include "log_server.h"
#include "gtimer_drv.h"
#include "hw_gpio.h"
#include "gpio_drv.h"
#ifdef INTEGRATED_BS
@ -36,6 +35,7 @@ extern uint32_t gMtimerId;
uint32_t gJesdTestMode = 0;
uint32_t gJesdIOMode = JESD_CSU_CTRL;
uint32_t gJesdTFMode = TDD_MODE;
uint32_t gJesdAlarmSfnCnt = 0;
@ -181,12 +181,17 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
pMtimerPara->scsId = scsId;
pMtimerPara->runCoreId = (uint16_t)my_jesdtmr->runCoreId;
pMtimerPara->tddPeriod = my_jesdtmr->t_period; // us
pMtimerPara->tddSlotNum = my_jesdtmr->num_t;
pMtimerPara->tddSlotNum = my_jesdtmr->num_tti;
pMtimerPara->slotPeriod = my_jesdtmr->t_us;
pMtimerPara->slotMaxNum = my_jesdtmr->num_t_per_sfn;
pMtimerSfn->slotMaxNum = my_jesdtmr->num_t_per_sfn;
pMtimerPara->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
pMtimerSfn->slotMaxNum = my_jesdtmr->num_tti_per_sfn;
if (FDD_MODE == my_jesdtmr->frameType)
{
gJesdIOMode = JESD_IO_CTRL;
gJesdTFMode = FDD_MODE;
}
do_write_short((&(phyPara[scsId].slotNumOfTdd)), my_jesdtmr->num_t);
do_write_short((&(phyPara[scsId].slotNumOfTdd)), my_jesdtmr->num_tti);
do_write_short((&(phyPara[scsId].mtimerId)), nTmrId);
__ucps2_synch(0);
@ -353,9 +358,21 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), (1<<(4+(nTmrId>>1)))); //IO ctrl
if (MTIMER_JESD_RX0_ID == nTmrId)
{
set_jesd_rf_state(JESD_RF_RX, JESD_GPIO_OFF); // RxOff();
delay_us(5);
set_jesd_rf_state(JESD_RF_TX, JESD_GPIO_ON); // TxOn();
if (TDD_MODE == gJesdTFMode)
{
set_jesd_rf_state(JESD_RF_RX, GPIO_OFF); // RxOff();
delay_us(5);
set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
}
else if (FDD_MODE == gJesdTFMode)
{
set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_RF_RX, GPIO_ON); // RxOn();
}
else
{
return -1;
}
}
}
@ -580,8 +597,8 @@ void set_jesd_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
longcp_symbol_p = LONGCP_SAM_CNT; // 4448; //sample
shortcp_symbol_p = SHORTCP_SAM_CNT; // 4384;
gapSymbolCnt = 14-my_jesdtmr->num_t_dl_symb-my_jesdtmr->num_t_ul_symb; // 14-6-4=4
shortcp = my_jesdtmr->num_t_dl_symb + gapSymbolCnt - 1; // ul start point
gapSymbolCnt = 14-my_jesdtmr->num_t_dl_symb[0]-my_jesdtmr->num_t_ul_symb[0]; // 14-6-4=4
shortcp = my_jesdtmr->num_t_dl_symb[0] + gapSymbolCnt - 1; // ul start point
//ulStartSymbol = my_jesdtmr->num_t_dl_symb + gapSymbolCnt - 1; // ul start point, 6+4-1, symbol9
@ -597,7 +614,7 @@ void set_jesd_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+116+(nTmrId<<2)), val); // 0x1D0
#endif
val = 0xC0000000 |(my_jesdtmr->num_t_dl); // special slot
val = 0xC0000000 |(my_jesdtmr->num_t_dl[0]); // special slot
do_write((tmrBaseAddr+MTMR_RXEN2CSU0H_REG), val); /* enable jesd rxdma */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+117+(nTmrId<<2)), val); // 0x1D4
@ -611,7 +628,7 @@ void set_jesd_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+118+(nTmrId<<2)), val); // 0x1D8
#endif
val = 0x80000000 | (my_jesdtmr->num_t - 1); // last slot of tdd
val = 0x80000000 | (my_jesdtmr->num_tti - 1); // last slot of tdd
do_write((tmrBaseAddr+MTMR_RXEN2CSU1H_REG), val);
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+119+(nTmrId<<2)), val); // 0x1DC
@ -631,12 +648,12 @@ void set_jesd_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
val = ((1<<20) | (1<<22));
do_write(tmrBaseAddr+MTMR_CMSK_REG, val);
val = longcp_symbol_p+(my_jesdtmr->num_t_dl_symb-1)*shortcp_symbol_p - gCsuTxAdvanceSam - 1; // -TX_DELAY+g_rfc_1us*(1)-OFFSET;
val = longcp_symbol_p+(my_jesdtmr->num_t_dl_symb[0]-1)*shortcp_symbol_p - gCsuTxAdvanceSam - 1; // -TX_DELAY+g_rfc_1us*(1)-OFFSET;
do_write((tmrBaseAddr+MTMR_TXEN2CSU0L_REG), val); /* csu TxOff */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+116+(nTmrId<<2)), val); // 0x1F0
#endif
val = 0x80000000 |(my_jesdtmr->num_t_dl); // special slot
val = 0x80000000 |(my_jesdtmr->num_t_dl[0]); // special slot
do_write((tmrBaseAddr+MTMR_TXEN2CSU0H_REG), val);
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+117+(nTmrId<<2)), val); // 0x344
@ -650,7 +667,7 @@ void set_jesd_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+118+(nTmrId<<2)), val); // 0x348
#endif
val = 0xC0000000|(my_jesdtmr->num_t - 1); // last slot of tdd
val = 0xC0000000|(my_jesdtmr->num_tti - 1); // last slot of tdd
do_write((tmrBaseAddr+MTMR_TXEN2CSU1H_REG), val); /* enable jesd txdma */
#ifdef PALLADIUM_TEST
debug_write((DBG_DDR_IDX_DRV_BASE+119+(nTmrId<<2)), val); // 0x34C
@ -697,8 +714,8 @@ void set_jesd_txoff_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
uint32_t sSymbolStart = (LONGCP_SAM_CNT+13*SHORTCP_SAM_CNT)*my_jesdtmr->num_t_dl;
uint32_t gapSymbolStart = LONGCP_SAM_CNT + (my_jesdtmr->num_t_dl_symb-1) * SHORTCP_SAM_CNT;
uint32_t sSymbolStart = (LONGCP_SAM_CNT+13*SHORTCP_SAM_CNT)*my_jesdtmr->num_t_dl[0];
uint32_t gapSymbolStart = LONGCP_SAM_CNT + (my_jesdtmr->num_t_dl_symb[0]-1) * SHORTCP_SAM_CNT;
uint32_t tmr28Point = (sSymbolStart + gapSymbolStart) * 1000 / pMtimerPara->tmrMsPeriod;
set_mtimer_tmrpoint(nTmrId, MTMR_JESD_TXOFF, tmr28Point, MTIMER_MASK_48BIT);
@ -718,8 +735,8 @@ void set_jesd_rxon_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
EcsRfmDmLocalMgt_t* pEcsDmLocalMgt = get_ecs_rfm_dm_local_mgt();
stMtimerPara* pMtimerPara = pEcsDmLocalMgt->pMtimerPara[nTmrId];
uint32_t sSymbolStart = (LONGCP_SAM_CNT+13*SHORTCP_SAM_CNT)*my_jesdtmr->num_t_dl;
uint32_t gapSymbolStart = LONGCP_SAM_CNT + (my_jesdtmr->num_t_dl_symb-1) * SHORTCP_SAM_CNT;
uint32_t sSymbolStart = (LONGCP_SAM_CNT+13*SHORTCP_SAM_CNT)*my_jesdtmr->num_t_dl[0];
uint32_t gapSymbolStart = LONGCP_SAM_CNT + (my_jesdtmr->num_t_dl_symb[0]-1) * SHORTCP_SAM_CNT;
uint32_t tmr26Point = (sSymbolStart + gapSymbolStart) * 1000 / pMtimerPara->tmrMsPeriod + JESD_TXRX_CHANGE_GAP;
set_mtimer_tmrpoint(nTmrId, MTMR_JESD_RXON, tmr26Point, MTIMER_MASK_48BIT);
@ -971,6 +988,10 @@ void jesd_tdd_callback(uint8_t nTmrId)
{
// uint32_t startTick = GET_STC_CNT();
jesd_csu_start();
if (FDD_MODE == gJesdTFMode)
{
jesd_csu_rx_start();
}
// uint32_t cost = GET_STC_CNT() - startTick;
// do_write(DDR_ADDR_90, cost);
}
@ -983,7 +1004,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
gRxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+5), gRxOnCnt); // 0x114
//RxOn();
set_jesd_rf_state(JESD_RF_RX, JESD_GPIO_ON);
set_jesd_rf_state(JESD_RF_RX, GPIO_ON);
jesd_csu_rx_start();
}
if (tEventFlag & (1<<MTMR_JESD_RXOFF)) // rx off int
@ -993,7 +1014,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
gRxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+64+6), gRxOffCnt); // 0x118
//RxOff();
set_jesd_rf_state(JESD_RF_RX, JESD_GPIO_OFF);
set_jesd_rf_state(JESD_RF_RX, GPIO_OFF);
}
if (tEventFlag & (1<<MTMR_JESD_TXON)) // tx on int
{
@ -1002,7 +1023,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
gTxOnCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+76), gTxOnCnt); // 0x130
//TxOn();
set_jesd_rf_state(JESD_RF_TX, JESD_GPIO_ON);
set_jesd_rf_state(JESD_RF_TX, GPIO_ON);
//jesd_csu_start();
}
if (tEventFlag & (1<<MTMR_JESD_TXOFF)) // tx off int
@ -1012,7 +1033,7 @@ void jesd_tdd_callback(uint8_t nTmrId)
gTxOffCnt++;
debug_write((DBG_DDR_IDX_DRV_BASE+77), gTxOffCnt); // 0x134
//TxOff();
set_jesd_rf_state(JESD_RF_TX, JESD_GPIO_OFF);
set_jesd_rf_state(JESD_RF_TX, GPIO_OFF);
}
if (cEventFlag & BIT11)
{
@ -1105,13 +1126,11 @@ uint32_t start = GET_STC_CNT();
// test for trigger
if (0 == pMtimerSfn->txSlotNum)
{
//rfm1_set_trigger_high();
set_trigger_state(JESD_GPIO_ON);
set_trigger_state(GPIO_ON);
}
else if ((pMtimerSfn->slotMaxNum >> 1) == pMtimerSfn->txSlotNum)
{
//rfm1_set_trigger_low();
set_trigger_state(JESD_GPIO_OFF);
set_trigger_state(GPIO_OFF);
}
__ucps2_synch(0);
if (8 > pMtimerInt->txSlotIntCnt)
@ -1223,7 +1242,7 @@ void isr_jesd_slot_rx1(void)
jesd_slot_callback(tmrId);
}
#if 0
void jesd_tdd_start_csu()
{
//uint32_t tmrBaseAddr = JS_RX0_TMR_BASE;
@ -1247,6 +1266,7 @@ void jesd_tdd_start_csu()
pMtimerInt->csuEnCnt++;
}
}
#endif
#endif

2
public/ecs_rfm_spu1/driver/src/mtimer_drv.s.c
View File

@ -32,7 +32,7 @@ int32_t mtimer_para_init(uint8_t nTmrId, int32_t nScsId, int32_t nTddSlotNum)
coreClk = pEcsDmLocalMgt->pCpriPara->core_clk;
#endif
#ifdef INTEGRATED_BS
coreClk = 122880000;
coreClk = do_read_volatile(JESD_TX_SAMPLE_RATE); // 122880000;
#endif
pMtimerPara->tmrClk = coreClk;

1
public/ecs_rfm_spu1/driver/src/rfm1_drv.s.c
View File

@ -15,7 +15,6 @@
#include "rfm1_gtimer2.h"
#include "ecs_rfm_spu1_heap.h"
#include "mtimer_cell.h"
#include "hw_gpio.h"
#include "gpio_drv.h"
#ifdef DISTRIBUTED_BS

2
public/ecs_rfm_spu1/platform/src/phy_queue_proc.s.c
View File

@ -54,7 +54,7 @@ void phy_queue_polling(void)
else
{
phy_msg_proc(u32msg_addr, u32msg_size);//phy application func
check_phy_cell();
//check_phy_cell();
}
}

24
public/ecs_rfm_spu1/top/src/phy_init.s.c
View File

@ -112,13 +112,13 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t flag)
#endif
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_t = 10;
my_cpritmr.num_t_per_sfn = 20;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 20;
my_cpritmr.num_t_dl = 7; // dl slot num
my_cpritmr.num_t_dl_symb = 6; // dl symbol num
my_cpritmr.num_t_ul_symb = 4; // ul symbol num
my_cpritmr.num_ants = 4;
my_cpritmr.num_t_dl[0] = 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 4; // ul symbol num
my_cpritmr.num_ants[0] = 4;
}
else if (LTE_SCS_ID == scsId)
{
@ -137,13 +137,13 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t flag)
#endif
my_cpritmr.t_period = 10000;
my_cpritmr.t_us = 1000;
my_cpritmr.num_t = 10;
my_cpritmr.num_t_per_sfn = 10;
my_cpritmr.num_tti = 10;
my_cpritmr.num_tti_per_sfn = 10;
my_cpritmr.num_t_dl =10;// 7; // dl slot num
my_cpritmr.num_t_dl_symb = 14;//6; // dl symbol num
my_cpritmr.num_t_ul_symb = 14;//4; // ul symbol num
my_cpritmr.num_ants = 2;
my_cpritmr.num_t_dl[0] =10;// 7; // dl slot num
my_cpritmr.num_t_dl_symb[0] = 14;//6; // dl symbol num
my_cpritmr.num_t_ul_symb[0] = 14;//4; // ul symbol num
my_cpritmr.num_ants[0] = 2;
}
mtimer_init4phy(&my_cpritmr);

4
public/make/makefile.ecs_rfm_spu1
View File

@ -29,8 +29,8 @@ DIRS_SRC_FOLDER += $(DIR_COMMON)/app
DIRS_SRC_FOLDER += $(DIR_ECS_SPU1)/top
DIRS_SRC_FOLDER += $(DIR_ECS_SPU1)/driver
DIRS_SRC_FOLDER += $(DIR_ECS_SPU1)/platform
DIRS_SRC_FOLDER += $(BOARD_DIR)/driver
$(info "BOARD_DIR=" $(BOARD_DIR))
#DIRS_SRC_FOLDER += $(BOARD_DIR)/driver
#$(info "BOARD_DIR=" $(BOARD_DIR))
# Allow certain files to be excluded from the build
TOP_SRC_FILE := $(DIR_ECS_SPU1)/top/src/phy_init.s.c

27
public/test/testcase/case42/inc/jesd_test_case42.h Normal file
View File

@ -0,0 +1,27 @@
#ifndef _JESD_TEST_CASE42_H_
#define _JESD_TEST_CASE42_H_
#if 0
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x60F00000 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x60FF0400 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0x61380000 // SM5
#define JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0x61290400 // SM4
#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
#endif
void jesd_test_init();
void jesd_data_init();
void jesd_test_csu_init();
void jesd_tx_data_init();
void jesd_csu_config();
void jesd_test_case();
#endif

1
public/test/testcase/case42/note.txt Normal file
View File

@ -0,0 +1 @@
7ds2u, 带收发切换，发256QAM, 245.76M 采样率

127
public/test/testcase/case42/src/jesd_test_case42.s.c Normal file
View File

@ -0,0 +1,127 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case43.c
// Author : xinxin.li
// Created On : 2023-01-11s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case42.h"
extern uint32_t antDataPre7[246016];
extern uint32_t antDataPost7[245504];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
void jesd_test_init()
{
jesd_init();
}
void jesd_data_init()
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
jesd_tx_data_init();//init tx data
}
void jesd_test_csu_init()
{
jesd_csu_init_nr_7ds2u_4t4r_98();
jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
}
void jesd_tx_data_init()
{
uint8_t antNum = 4;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint8_t idSymbolBlock = 0; // symbol0~6, symbol7~13
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
// uint32_t slotSamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*13;
uint32_t f7SamCnt = (LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6)*2;;
uint32_t b7SamCnt = (SHORTCP_SAM_CNT*7)*2;
uint32_t cpyCnt = 0;
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
for (idSymbolBlock = 0; idSymbolBlock <= 1; idSymbolBlock++)
{
if ((0 == idSlot) && (0 == idSymbolBlock)) // even slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((0 == idSlot) && (1 == idSymbolBlock)) // even slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (0 == idSymbolBlock)) // odd slot, symbol0~6
{
dataLen = samByteCnt * f7SamCnt;
srcAddr = (uint32_t)(&antDataPre7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR + idAnt*dataLen;
}
else if ((1 == idSlot) && (1 == idSymbolBlock)) // odd slot, symbol7~13
{
dataLen = samByteCnt * b7SamCnt;
srcAddr = (uint32_t)(&antDataPost7[0]);
dstAddr = JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
}
//memset((void*)JESD_NR7DS2U_RX_SLOTS_DATA_ADDR, 0, 4*8*SHORTCP_SAM_CNT*samByteCnt);
memset((void*)JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
memset((void*)JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR, 0, 4*(f7SamCnt+b7SamCnt)*samByteCnt);
}
void jesd_csu_config()
{
}
void jesd_test_case()
{
jesd_csu_start_nr_7ds2u();
}

245510
public/test/testcase/case42/src/jesd_test_case42_antdata_post7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

246022
public/test/testcase/case42/src/jesd_test_case42_antdata_pre7.s.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
public/test/testcase/case44/src/jesd_test_case44.s.c
View File

@ -158,8 +158,8 @@ void jesd_test_csu_init()
jesd_csu_init_nr_7ds2u_iomode();
}
jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
}
void jesd_tx_data_init()

8
public/test/testcase/case49/data/data_read.asv Normal file
View File

@ -0,0 +1,8 @@
fd_in = fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant_all.dat', 'r');
data_in = fscanf(fd_in, '%x');
fclose(fd_in);
size_datain = size(data_in);
ant0_data = data_in(1:(size_datain(1)/4));
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0.dat', 'w+');

24
public/test/testcase/case49/data/data_read.m Normal file
View File

@ -0,0 +1,24 @@
fd_in = fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant_all.dat', 'r');
data_in = fscanf(fd_in, '%x', Inf);
fclose(fd_in);
size_datain = size(data_in);
ant0_data = data_in(1:(size_datain(1)/4));
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0.dat', 'w+');
for i=1:1:(size_datain(1)/4)
fprintf(fd_out, '0x%08x\n', ant0_data(i));
end
fclose(fd_out);
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0_preSymbol.dat', 'w+');
for i=1:1:61504
fprintf(fd_out, '0x%08x\n', ant0_data(i));
end
fclose(fd_out);
fd_out=fopen('D:\code\platform_v2.1_20230829_jesd98g\public\test\testcase\case49\data\dl_ant0_postSymbol.dat', 'w+');
for i=1:1:61376
fprintf(fd_out, '0x%08x\n', ant0_data(61504+i));
end
fclose(fd_out);

122880
public/test/testcase/case49/data/dl_ant0.dat Normal file
View File

File diff suppressed because it is too large Load Diff

61376
public/test/testcase/case49/data/dl_ant0_postSymbol.dat Normal file
View File

File diff suppressed because it is too large Load Diff

61377
public/test/testcase/case49/data/dl_ant0_postSymbol.dat.bak Normal file
View File

File diff suppressed because it is too large Load Diff

61504
public/test/testcase/case49/data/dl_ant0_preSymbol.dat Normal file
View File

File diff suppressed because it is too large Load Diff

61505
public/test/testcase/case49/data/dl_ant0_preSymbol.dat.bak Normal file
View File

File diff suppressed because it is too large Load Diff

491520
public/test/testcase/case49/data/dl_ant_all.dat Normal file
View File

File diff suppressed because it is too large Load Diff

245760
public/test/testcase/case49/data/dl_cpri_all.dat Normal file
View File

File diff suppressed because it is too large Load Diff

1920
public/test/testcase/case49/data/dl_cpri_comp.dat Normal file
View File

File diff suppressed because it is too large Load Diff

9
public/test/testcase/case49/inc/jesd_test_case49.h
View File

@ -1,15 +1,6 @@
#ifndef _JESD_TEST_CASE49_H_
#define _JESD_TEST_CASE49_H_
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x60F00000 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x60FF0400 // SM2
#define JESD_98_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0x61380000 // SM5
#define JESD_98_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0x61290400 // SM4
#define JESD_98_NR7DS2U_RX_SLOTS_DATA_ADDR 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_EVEN_DATA_ADDR 0x6BC44800 // 0x6BC00000
#define JESD_98_NR7DS2U_RX_SLOT_ODD_DATA_ADDR 0x6BD34800 // 0x6BC78200
void jesd_data_init();

3
public/test/testcase/case49/src/jesd_test_case49.s.c
View File

@ -27,7 +27,6 @@ extern uint32_t antDataPost7[245504];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
void jesd_data_init()
{
@ -58,7 +57,7 @@ void jesd_tx_data_init()
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
// uint32_t slotSamCnt = LONGCP_SAM_CNT+SHORTCP_SAM_CNT*13;
uint32_t f7SamCnt = (LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6)*2;;
uint32_t f7SamCnt = (LONGCP_SAM_CNT+SHORTCP_SAM_CNT*6)*2;
uint32_t b7SamCnt = (SHORTCP_SAM_CNT*7)*2;
uint32_t cpyCnt = 0;

491008
public/test/testcase/case49/src/jesd_test_case49_antdata_post7.s.c
View File

File diff suppressed because it is too large Load Diff

492033
public/test/testcase/case49/src/jesd_test_case49_antdata_pre7.s.c
View File

File diff suppressed because it is too large Load Diff

44
public/test/testcase/case90/inc/jesd_test_case90.h Normal file
View File

@ -0,0 +1,44 @@
#ifndef _JESD_TEST_CASE90_H_
#define _JESD_TEST_CASE90_H_
#define JESD_CASE41_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE41_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE41_RX_SLOTD_DATA_LEN 0xF0000
#define JESD_CASE41_TDD_DATA_LEN 0x960000
#define JESD_CASE41_RX1_DUMMY_DATA_ADDR 0xB4BA4800
#define JESD_CASE41_RX1_SLOTS_DATA_ADDR ((JESD_CASE41_RX1_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
#define JESD_CASE41_RX1_SLOT8_DATA_ADDR ((JESD_CASE41_RX1_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
#define JESD_CASE41_RX1_SLOT9_DATA_ADDR ((JESD_CASE41_RX1_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
#define JESD_CASE41_RX2_DUMMY_DATA_ADDR 0xB5504800
#define JESD_CASE41_RX2_SLOTS_DATA_ADDR ((JESD_CASE41_RX2_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
#define JESD_CASE41_RX2_SLOT8_DATA_ADDR ((JESD_CASE41_RX2_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
#define JESD_CASE41_RX2_SLOT9_DATA_ADDR ((JESD_CASE41_RX2_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
#define JESD_CASE41_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define JESD_CASE41_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define JESD_CASE41_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define JESD_CASE41_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define JESD_CASE41_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define JESD_CASE41_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE41_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE41_RX_SLOT_ODD_B7SYMBOL_TAG 7
void jesd_data_init();
void jesd_test_csu_init();
void jesd_tx_data_init();
void jesd_csu_config();
void jesd_test_case();
#endif

1
public/test/testcase/case90/note.txt Normal file
View File

@ -0,0 +1 @@
LTE FDD，发单音

102
public/test/testcase/case90/src/jesd_test_case90.s.c Normal file
View File

@ -0,0 +1,102 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case44.c
// Author : xinxin.li
// Created On : 2023-03-22s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_lte_fdd.h"
#include "jesd_test.h"
#include "jesd_test_case90.h"
extern uint32_t antDataLte[122880];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
extern uint32_t gJesdTFMode;
void jesd_data_init()
{
gJesdTestMode = JESD_TEST_MODE;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
jesd_tx_data_init();//init tx data
}
void jesd_test_csu_init()
{
jesd_csu_init_lte_fdd();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
}
void jesd_tx_data_init()
{
uint8_t antNum = 2;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
uint32_t slotSamCnt = JESD_LTEFDD_SUBFRAME_SAM_CNT;
uint32_t cpyCnt = 0;
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
if (0 == idSlot) // even slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataLte[0]) + idAnt*slotSamCnt;
dstAddr = JESD_LTEFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
}
else if (1 == idSlot) // odd slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataLte[0]) + idAnt*slotSamCnt;
dstAddr = JESD_LTEFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
memset((void*)JESD_LTEFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset((void*)JESD_LTEFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
}
void jesd_csu_config()
{
}
void jesd_test_case()
{
//jesd_csu_start_nr_7ds2u();
}

245773
public/test/testcase/case90/src/jesd_test_case90_antdata.s.c Normal file
View File

File diff suppressed because it is too large Load Diff