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1. UCP4008_SL new feature #1412;

Browse Source 
2. fdd 122.88M, 4 ants;
3. test case: case41,case44
This commit is contained in:
xinxin.li 2023-12-20 12:24:27 +08:00
parent 6a139ec2b8
commit f4dd3ccf8c
20 changed files with 615179 additions and 59 deletions
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2
public/common/driver/inc/mtimer_com.h
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@ -5,7 +5,7 @@
#define FIBER_MIN_DELAY 2 // 10 //
#define INT_DELAY 4 // 6 // // us
#define EDMA_OFFSET 50 // 6 // 8 // 2 // us
#define EDMA_OFFSET 10 // 6 // 8 // 2 // us
#define CPRI_RE_TOFFSET 0 // 100 // 200 // ns // Toffset, to be change
#define CPRI_T2A 100 // 1 // 10 // ns

47
public/ecs_rfm_spu1/driver/inc/jesd_csu_nr_fdd.h Normal file
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@ -0,0 +1,47 @@
#ifndef _JESD_CSU_NR_FDD_H_
#define _JESD_CSU_NR_FDD_H_
#include "typedef.h"
// 4 ant, NR
#define JESD_NRFDD_ANT_NUM 4 // 2 //
#define JESD_NRFDD_MARGIN 5
#define JESD_NRFDD_SLOT_NUM 10
#define JESD_NRFDD_TX_NODENUM 10
#define JESD_NRFDD_RX_NODENUM 10
#define JESD_NRFDD_SLOT_SAM_CNT 61440
#define JESD_NRFDD_TX_LIST_ADDR 0x8A000000 // 0x0a4f4000//
#define JESD_NRFDD_RX_LIST_ADDR 0x8A008000 // 0x0a4f4800//
#if 0
#define JESD_NR7DS2U_TX_SLOT_EVEN_F7SYMBOL_ADDR 0x9F00000 // SM2
#define JESD_NR7DS2U_TX_SLOT_ODD_F7SYMBOL_ADDR 0x9FF0400 // SM2
#define JESD_NR7DS2U_TX_SLOT_EVEN_B7SYMBOL_ADDR 0xA380000 // SM5
#define JESD_NR7DS2U_TX_SLOT_ODD_B7SYMBOL_ADDR 0xA290400 // SM4
#else
#define JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR 0x60F00000 // 0xF0000
#define JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR 0x60FF0000 // 0xF0000
#endif
#define JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR 0x6BC00000 // 0x9F00000 // 0xF0000
#define JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR 0x6BCF0000 // 0xA380000 // 0xF0000
int32_t jesd_csu_init_nr_fdd();
int32_t jesd_csu_init_nr_fdd_slot0();
#if 0
int32_t jesd_csu_init_nr_7ds2u_iomode();
int32_t jesd_csu_init_nr_7ds2u_8t8r();
int32_t jesd_csu_init_nr_7ds2u_4t4r_98();
int32_t jesd_csu_start_nr_7ds2u();
int32_t jesd_csu_start_nr_7ds2u_8t8r();
#endif
#endif

46
public/ecs_rfm_spu1/driver/src/jesd_csu.s.c
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@ -6,12 +6,16 @@
#include "ucp_drv_common.h"
#include "gpio_drv.h"
#include "inter_vector.h"
#include "phy_para.h"
stJesdCsuPara gJesdCsuPara;
stJesdListPara gJesdTxListPara[JESD_CH_NUM][JESD_LIST_NUM];
stJesdListPara gJesdRxListPara[JESD_CH_NUM][JESD_LIST_NUM];
uint32_t gJesdOrxCsuIntCnt = 0;
extern uint32_t gJesdTFMode;
void isr_jesd_orx_csu()
{
if (JS_CSU_ALLPENDEVENT1 & BIT14)
@ -82,11 +86,17 @@ int32_t jesd_csu_init(uint8_t antNum, uint8_t margin)
gJesdCsuPara.seq = gJesdCsuPara.seq >> 1;
}
uint32_t val = (((gJesdCsuPara.m>>1)-1)<<26)+((gJesdCsuPara.seq-1)<<24)+(((gJesdCsuPara.nTotal*gJesdCsuPara.m)/gJesdCsuPara.seq)<<16)+((gJesdCsuPara.n-8)<<8)+(margin<<4)+gJesdCsuPara.cs;
debug_write((DBG_DDR_IDX_DRV_BASE+216), val); // 0x360
do_write((&JS_CSU_JESDRX0SET), val);
do_write((&JS_CSU_JESDTX0SET), val);
//debug_write((DBG_DDR_IDX_DRV_BASE+216), val); // 0x360
if (2 >= antNum)
{
uint8_t seqRx = 1;
val = (((gJesdCsuPara.m>>1)-1)<<26)+((seqRx-1)<<24)+(((gJesdCsuPara.nTotal*gJesdCsuPara.m)/seqRx)<<16)+((gJesdCsuPara.n-8)<<8)+(margin<<4)+gJesdCsuPara.cs;
}
do_write((&JS_CSU_JESDRX0SET), val);
do_write((&JS_CSU_FINDDMATAG), 0x60); // st wait wr resp
do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00040010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit
//do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00040010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit
do_write((&JS_CSU_ALMOSTFULLSENDTHRED), 0x00000010); // [30:16]sendthred,<4, stop write; [14:0]almostfull, >=0x400,start write, 256bit as unit
do_write((&JS_CSU_EM_BS_SMSEL_PREDATANUM), ((0x1<<14) | (0x5<<5) | 0x8));
if (4 < antNum)
{
@ -235,6 +245,8 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
// 前7个下行时隙+特殊时隙的前6个符号
int32_t i = 0;
for(i = 0; i < nodeNum; i++)
{
if (FDD_MODE != gJesdTFMode)
{
if (0 == i)
{
@ -244,6 +256,7 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
{
rxListCmdL = (1<<4)+(0<<5)+(3<<6);
}
}
uint32_t yStep = (1 == orxFlag) ? (0x20 * (1<<mrg)) : (pListNode[i].yStep);
// src
pLinkDesc = (stCsuLinkDesc1L3D*)listAddr + 2*i;
@ -256,7 +269,16 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
stLinkDesc.dmaYNum = 1;
stLinkDesc.dmaZStep = 0x20;
stLinkDesc.dmaAllNum = pListNode[i].allNum;
if (FDD_MODE == gJesdTFMode)
{
stLinkDesc.dmaCGran = 0;
}
else
{
stLinkDesc.dmaCGran = 1;
}
stLinkDesc.dmaGran = 0;
stLinkDesc.nAddrMode = 0; // list addr is contiguous
memcpy_ext(pLinkDesc, &stLinkDesc, sizeof(stCsuLinkDesc1L3D));
@ -267,9 +289,18 @@ int32_t jesd_csu_rx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
stLinkDesc.cmdFifoH = rxListCmdH & 0x3FFF;
stLinkDesc.dmaAddrL = pListNode[i].dataAddr;
stLinkDesc.dmaXNum = 0x20 * (1<<mrg); // 32*(2^margin)
if (2 >= gJesdCsuPara.antNum)
{
stLinkDesc.dmaYStep = stLinkDesc.dmaXNum;
stLinkDesc.dmaYNum = pListNode[i].allNum / stLinkDesc.dmaXNum;
stLinkDesc.dmaZStep = pListNode[i].allNum;
}
else
{
stLinkDesc.dmaYStep = yStep; // pListNode[i].yStep;
stLinkDesc.dmaYNum = seq;
stLinkDesc.dmaZStep = 0x20 * (1<<mrg); // 32*(2^margin)
}
stLinkDesc.dmaAllNum = pListNode[i].allNum;
stLinkDesc.dmaSize = 0xF; // write global
stLinkDesc.nAddrMode = 0; // list addr is contiguous
@ -326,7 +357,15 @@ int32_t jesd_csu_tx_list_init(uint32_t listAddr, uint32_t nodeNum, stJesdCsuNode
stLinkDesc.dmaZStep = 0x20;
stLinkDesc.dmaAllNum = pListNode[i].allNum;
stLinkDesc.dmaSize = 0; // 0x8;//
if (FDD_MODE == gJesdTFMode)
{
stLinkDesc.dmaCGran = 0; //1;
}
else
{
stLinkDesc.dmaCGran = 1;
}
stLinkDesc.dmaGran = 0;
stLinkDesc.nAddrMode = 0; // list addr is contiguous
memcpy_ext(pLinkDesc, &stLinkDesc, sizeof(stCsuLinkDesc1L3D));
@ -379,6 +418,7 @@ int32_t jesd_csu_rx_start_ch(uint8_t nChId, uint8_t nListId)
cpriCmdL.rCmd = 1;
cpriCmdL.wCmd = 1;
cpriCmdL.dmaType = 1;
//cpriCmdL.cacheMode = 1;
cpriCmdL.continueLast = 0;
cpriCmdL.continueNext = 0;
cpriCmdL.idSrc = nRegId;

107
public/ecs_rfm_spu1/driver/src/jesd_csu_nr_fdd.s.c Normal file
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@ -0,0 +1,107 @@
#include "jesd_csu_nr_fdd.h"
#include "jesd_csu.h"
int32_t jesd_csu_init_nr_fdd()
{
jesd_csu_init(JESD_NRFDD_ANT_NUM, JESD_NRFDD_MARGIN);
stJesdCsuNodePara txCsuNode[JESD_NRFDD_TX_NODENUM];
stJesdCsuNodePara rxCsuNode[JESD_NRFDD_RX_NODENUM];
//tx的链表地址
uint32_t txListAddr = JESD_NRFDD_TX_LIST_ADDR; // 0x8A000000
//rx的链表地址
uint32_t rxListAddr = JESD_NRFDD_RX_LIST_ADDR; // 0x8A008000
int32_t i = 0;
// tx/rx, subframe 0~9
for (i = 0; i < JESD_NRFDD_TX_NODENUM; i++)
{
if (0 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR;
txCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
rxCsuNode[i].dataAddr = JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
}
else if (1 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR;
txCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
rxCsuNode[i].dataAddr = JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
}
}
jesd_csu_tx_cfg(txListAddr, JESD_NRFDD_TX_NODENUM, txCsuNode, JESD_CSU_CH0, 0);
jesd_csu_rx_cfg(rxListAddr, JESD_NRFDD_RX_NODENUM, rxCsuNode, JESD_CSU_CH0, 0);
#if 0
jesd_csu_tx_list_init(txListAddr, JESD_LTEFDD_TX_NODENUM, txCsuNode);
jesd_csu_tx_dmaReg_Cfg(JESD_CSU_CH0, txListAddr, JESD_LTEFDD_TX_NODENUM);
jesd_csu_rx_list_init(rxListAddr, JESD_LTEFDD_RX_NODENUM, rxCsuNode);
jesd_csu_rx_dmaReg_Cfg(JESD_CSU_CH0, rxListAddr, JESD_LTEFDD_RX_NODENUM);
#endif
return 0;
}
int32_t jesd_csu_init_nr_fdd_slot0()
{
jesd_csu_init(JESD_NRFDD_ANT_NUM, JESD_NRFDD_MARGIN);
stJesdCsuNodePara txCsuNode[JESD_NRFDD_TX_NODENUM];
stJesdCsuNodePara rxCsuNode[JESD_NRFDD_RX_NODENUM];
//tx的链表地址
uint32_t txListAddr = JESD_NRFDD_TX_LIST_ADDR; // 0x8A000000
//rx的链表地址
uint32_t rxListAddr = JESD_NRFDD_RX_LIST_ADDR; // 0x8A008000
int32_t i = 0;
// tx/rx, subframe 0~9
for (i = 0; i < JESD_NRFDD_TX_NODENUM; i++)
{
if (0 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR;
txCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
rxCsuNode[i].dataAddr = JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
}
else if (1 == (i&0x1))
{
txCsuNode[i].dataAddr = JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR;
txCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
txCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
rxCsuNode[i].dataAddr = JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR;
rxCsuNode[i].yStep = (JESD_NRFDD_SLOT_SAM_CNT<<2);
rxCsuNode[i].allNum = (JESD_NRFDD_SLOT_SAM_CNT<<2)*JESD_NRFDD_ANT_NUM;
}
}
jesd_csu_tx_cfg(txListAddr, 1, txCsuNode, JESD_CSU_CH0, 0);
jesd_csu_rx_cfg(rxListAddr, 1, rxCsuNode, JESD_CSU_CH0, 0);
#if 0
jesd_csu_tx_list_init(txListAddr, JESD_LTEFDD_TX_NODENUM, txCsuNode);
jesd_csu_tx_dmaReg_Cfg(JESD_CSU_CH0, txListAddr, JESD_LTEFDD_TX_NODENUM);
jesd_csu_rx_list_init(rxListAddr, JESD_LTEFDD_RX_NODENUM, rxCsuNode);
jesd_csu_rx_dmaReg_Cfg(JESD_CSU_CH0, rxListAddr, JESD_LTEFDD_RX_NODENUM);
#endif
return 0;
}
#if 0
int32_t jesd_csu_start_lte()
{
jesd_csu_start();
return 0;
}
#endif

39
public/ecs_rfm_spu1/driver/src/jesd_timer.s.c
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@ -208,6 +208,21 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
//tdd = tdd>>1;
}
if (FDD_MODE == gJesdTFMode)
{
pMtimerTxPara->txCsuOn[0].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY; // pJesdDelay->jesd_10ms2pp1s_txoffset;
get_jesd_timer_point_para(nTmrId+2, pMtimerTxPara->txCsuOn[0].timerPoint, &pMtimerTxPara->txCsuOn[0].pointL,
&pMtimerTxPara->txCsuOn[0].pointM, &pMtimerTxPara->txCsuOn[0].pointH);
pMtimerPara->rxCsuOn[0].timerPoint = tdd - gCsuTxAdvanceNs/1000 - pJesdDelay->gps_offset - INT_DELAY;
get_jesd_timer_point_para(nTmrId, pMtimerPara->rxCsuOn[0].timerPoint, &pMtimerPara->rxCsuOn[0].pointL,
&pMtimerPara->rxCsuOn[0].pointM, &pMtimerPara->rxCsuOn[0].pointH);
debug_write((DBG_DDR_IDX_DRV_BASE+108+(0<<2)), pMtimerTxPara->txCsuOn[0].timerPoint); // 0x1b0
debug_write((DBG_DDR_IDX_DRV_BASE+110+(0<<2)), pMtimerPara->rxCsuOn[0].timerPoint); // 0x1b8
}
else
{
for (int i = 0; i < 2; i++)
{
if ((TDD_2500US_DOUBLE == pMtimerPara->frameType) && (i&0x1))
@ -241,6 +256,7 @@ int32_t jesd_timer_get_csu_point(int32_t nTmrId, phy_timer_config_ind_t *my_jesd
debug_write((DBG_DDR_IDX_DRV_BASE+110+(i<<2)), pMtimerPara->rxCsuOn[i].timerPoint); // 0x1b8
debug_write((DBG_DDR_IDX_DRV_BASE+111+(i<<2)), pMtimerPara->rxCsuOff[i].timerPoint); // 0x1bc
}
}
return 0;
}
@ -356,7 +372,7 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
if (FDD_MODE == my_jesdtmr->frameType)
{
gJesdIOMode = JESD_IO_CTRL;
//gJesdIOMode = JESD_IO_CTRL;
gJesdTFMode = FDD_MODE;
}
else if (TDD_2500US_DOUBLE == my_jesdtmr->frameType)
@ -430,6 +446,14 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
gCsuRxAdvanceNs = JESD_RX_ADVANCE_NS - do_read_volatile(CSU_RX_TD_SAMPLE);
gCsuTxAdvanceNs = do_read_volatile(CSU_TX_ADVANCE_SAMPLE);
if (FDD_MODE == gJesdTFMode)
{
jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
set_jesd_csuon_point(MTIMER_JESD_RX0_ID, 0);
set_jesd_csuon_point(MTIMER_JESD_TX0_ID, 0);
}
else
{
jesd_timer_get_csu_point(nTmrId, my_jesdtmr);
jesd_timer_get_rf_point(nTmrId, my_jesdtmr);
@ -442,6 +466,7 @@ int32_t jesd_timer_reconfig(int32_t nTmrId, phy_timer_config_ind_t *my_jesdtmr)
set_jesd_rxoff_point(nTmrId, 0);
set_jesd_txon_point(nTmrId, 0);
set_jesd_txoff_point(nTmrId, 0);
}
#ifdef PALLADIUM_TEST
flag++;
debug_write((DBG_DDR_IDX_DRV_BASE+3+(apeId<<2)), flag); // 0xBC
@ -552,6 +577,18 @@ int32_t jesd_pin_ctrl(int32_t nTmrId)
{
do_write((tmrBaseAddr+MTMR_PIN_CTRL_REG), 0x3); //CTRL_SEL
do_write((tmrBaseAddr+MTMR_IO_CTRL_REG), 0); //IO ctrl
if (FDD_MODE == gJesdTFMode)
{
set_jesd_rf_state(JESD_TRANS_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_RF_TX, GPIO_ON); // TxOn();
set_jesd_rf_state(JESD_ANT_TX, GPIO_ON); // TxOn();
//set_jesd_rf_state(JESD_ANT_RX, GPIO_OFF); // RxOn();
//set_jesd_rf_state(JESD_RF_RX, GPIO_OFF); // RxOn();
//set_jesd_rf_state(JESD_TRANS_RX, GPIO_OFF); // RxOn();
set_jesd_rf_state(JESD_ANT_RX, GPIO_ON); // RxOn();
set_jesd_rf_state(JESD_RF_RX, GPIO_ON); // RxOn();
set_jesd_rf_state(JESD_TRANS_RX, GPIO_ON); // RxOn();
}
}
else
{

3
public/ecs_rfm_spu1/top/src/phy_init.s.c
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@ -161,7 +161,8 @@ void ecs_rfm1_build_cell(uint32_t scsId, uint32_t cellId, uint32_t coreId, uint3
{
if (NR_SCS_30K == scsId)
{
my_cpritmr.frameType = TDD_MODE;
//my_cpritmr.frameType = TDD_MODE;
my_cpritmr.frameType = FDD_MODE;
my_cpritmr.t_period = 5000;
my_cpritmr.t_us = 500;
my_cpritmr.num_tti = 10;

122753
public/test/testcases/case41/fronthaul/DATA/265_slot0_jesd/dl_ant_post7.dat Normal file
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File diff suppressed because it is too large Load Diff

123009
public/test/testcases/case41/fronthaul/DATA/265_slot0_jesd/dl_ant_pre7.dat Normal file
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File diff suppressed because it is too large Load Diff

45
public/test/testcases/case41/fronthaul/inc/jesd_test_case41.h Normal file
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@ -0,0 +1,45 @@
#ifndef _JESD_TEST_CASE41_H_
#define _JESD_TEST_CASE41_H_
#if 0
#define JESD_CASE44_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE44_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE44_RX_SLOTD_DATA_LEN 0xF0000
#define JESD_CASE44_TDD_DATA_LEN 0x960000
#define JESD_CASE44_RX1_DUMMY_DATA_ADDR 0xB4BA4800
#define JESD_CASE44_RX1_SLOTS_DATA_ADDR ((JESD_CASE44_RX1_DUMMY_DATA_ADDR)+(JESD_CASE44_RX_DUMMY_DATA_LEN))
#define JESD_CASE44_RX1_SLOT8_DATA_ADDR ((JESD_CASE44_RX1_SLOTS_DATA_ADDR)+(JESD_CASE44_RX_SLOTS_DATA_LEN))
#define JESD_CASE44_RX1_SLOT9_DATA_ADDR ((JESD_CASE44_RX1_SLOT8_DATA_ADDR)+(JESD_CASE44_RX_SLOTD_DATA_LEN))
#define JESD_CASE44_RX2_DUMMY_DATA_ADDR 0xB5504800
#define JESD_CASE44_RX2_SLOTS_DATA_ADDR ((JESD_CASE44_RX2_DUMMY_DATA_ADDR)+(JESD_CASE44_RX_DUMMY_DATA_LEN))
#define JESD_CASE44_RX2_SLOT8_DATA_ADDR ((JESD_CASE44_RX2_SLOTS_DATA_ADDR)+(JESD_CASE44_RX_SLOTS_DATA_LEN))
#define JESD_CASE44_RX2_SLOT9_DATA_ADDR ((JESD_CASE44_RX2_SLOT8_DATA_ADDR)+(JESD_CASE44_RX_SLOTD_DATA_LEN))
#define JESD_CASE44_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define JESD_CASE44_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define JESD_CASE44_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define JESD_CASE44_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define JESD_CASE44_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define JESD_CASE44_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE44_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE44_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case41/fronthaul/note.txt Normal file
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@ -0,0 +1 @@
7ds2u, 带收发切换，发宽带信号

125
public/test/testcases/case41/fronthaul/src/jesd_test_case41.s.c Normal file
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@ -0,0 +1,125 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case44.c
// Author : xinxin.li
// Created On : 2023-03-22s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_fdd.h"
#include "jesd_test.h"
#include "jesd_test_case41.h"
#include "rfm1_drv.h"
extern uint32_t antDataNr[122880];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
extern uint32_t gJesdTFMode;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
gJesdTFMode = FDD_MODE;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stFrontHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fhDrvPara.rateOption = JESD_OPTION_204B;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
jesd_csu_init_nr_fdd_slot0();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = JESD_NRFDD_ANT_NUM;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
uint32_t slotSamCnt = JESD_NRFDD_SLOT_SAM_CNT;
uint32_t cpyCnt = 0;
memset_ucp((void*)JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset_ucp((void*)JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
if (0 == idSlot) // even slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataNr[0]); // + idAnt*slotSamCnt;
dstAddr = JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
}
else if (1 == idSlot) // odd slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataNr[0]); // + idAnt*slotSamCnt;
dstAddr = JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
memset((void*)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset((void*)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
}

122887
public/test/testcases/case41/fronthaul/src/jesd_test_case41_antdata.s.c Normal file
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60
public/test/testcases/case41/osp/src/ape_test_case41.s.c Normal file
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@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

4
public/test/testcases/case44/fronthaul/src/jesd_test_case44.s.c
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@ -28,14 +28,16 @@ extern uint32_t antDataPost7[122752];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
//extern stJesdTimerPara gJesdTmrPara;
extern uint32_t gJesdTFMode;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL;
//gJesdTFMode = FDD_MODE;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
jesd_tx_data_init();//init tx data

45
public/test/testcases/case46/fronthaul/inc/jesd_test_case46.h Normal file
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@ -0,0 +1,45 @@
#ifndef _JESD_TEST_CASE46_H_
#define _JESD_TEST_CASE46_H_
#if 0
#define JESD_CASE41_RX_DUMMY_DATA_LEN 0x73B800 // 0xF0000*7+0xAB800
#define JESD_CASE41_RX_SLOTS_DATA_LEN 0x44800 // 0x44800
#define JESD_CASE41_RX_SLOTD_DATA_LEN 0xF0000
#define JESD_CASE41_TDD_DATA_LEN 0x960000
#define JESD_CASE41_RX1_DUMMY_DATA_ADDR 0xB4BA4800
#define JESD_CASE41_RX1_SLOTS_DATA_ADDR ((JESD_CASE41_RX1_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
#define JESD_CASE41_RX1_SLOT8_DATA_ADDR ((JESD_CASE41_RX1_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
#define JESD_CASE41_RX1_SLOT9_DATA_ADDR ((JESD_CASE41_RX1_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
#define JESD_CASE41_RX2_DUMMY_DATA_ADDR 0xB5504800
#define JESD_CASE41_RX2_SLOTS_DATA_ADDR ((JESD_CASE41_RX2_DUMMY_DATA_ADDR)+(JESD_CASE41_RX_DUMMY_DATA_LEN))
#define JESD_CASE41_RX2_SLOT8_DATA_ADDR ((JESD_CASE41_RX2_SLOTS_DATA_ADDR)+(JESD_CASE41_RX_SLOTS_DATA_LEN))
#define JESD_CASE41_RX2_SLOT9_DATA_ADDR ((JESD_CASE41_RX2_SLOT8_DATA_ADDR)+(JESD_CASE41_RX_SLOTD_DATA_LEN))
#define JESD_CASE41_TX_SLOT_EVEN_F7SYMBOL_TAG 0
#define JESD_CASE41_TX_SLOT_ODD_F7SYMBOL_TAG 1
#define JESD_CASE41_TX_SLOT_EVEN_B7SYMBOL_TAG 2
#define JESD_CASE41_TX_SLOT_ODD_B7SYMBOL_TAG 3
#define JESD_CASE41_RX_SLOT_EVEN_F7SYMBOL_TAG 4
#define JESD_CASE41_RX_SLOT_ODD_F7SYMBOL_TAG 5
#define JESD_CASE41_RX_SLOT_EVEN_B7SYMBOL_TAG 6
#define JESD_CASE41_RX_SLOT_ODD_B7SYMBOL_TAG 7
#endif
int32_t fh_data_init(void);
int32_t fh_drv_init(void);
int32_t fh_csu_test_init(void);
void fh_test_case();
void jesd_tx_data_init();
void jesd_csu_config();
#endif

1
public/test/testcases/case46/fronthaul/note.txt Normal file
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@ -0,0 +1 @@
NR FDD，发单音

126
public/test/testcases/case46/fronthaul/src/jesd_test_case46.s.c Normal file
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@ -0,0 +1,126 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : cpri_test_case44.c
// Author : xinxin.li
// Created On : 2023-03-22s
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "ucp_printf.h"
#include "ucp_utility.h"
#include "ape_csu.h"
#include "jesd_csu.h"
#include "jesd_timer.h"
#include "jesd_csu_nr_fdd.h"
#include "jesd_csu_nr_7ds2u.h"
#include "jesd_test.h"
#include "jesd_test_case46.h"
#include "rfm1_drv.h"
extern uint32_t antDataNr[122880];
extern uint32_t gJesdTestMode;
extern uint32_t gJesdIOMode;
extern uint32_t gJesdTFMode;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_CSU_CTRL; // JESD_IO_CTRL;
gJesdTFMode = FDD_MODE;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
debug_write((DBG_DDR_IDX_DRV_BASE+194), gJesdTFMode); // 0x308
jesd_tx_data_init();//init tx data
return 0;
}
int32_t fh_drv_init(void)
{
stFrontHaulDrvPara fhDrvPara;
memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fhDrvPara.rateOption = JESD_OPTION_204B;
fronthaul_drv_cfg(&fhDrvPara);
return 0;
}
int32_t fh_csu_test_init(void)
{
jesd_csu_init_nr_fdd();
//jesd_csu_init_nr_7d2u_slot0();
//jesd_pin_ctrl(MTIMER_JESD_RX0_ID);
//jesd_pin_ctrl(MTIMER_JESD_TX0_ID);
return 0;
}
void fh_test_case()
{
//jesd_csu_start_nr_7ds2u();
}
void fh_data_check(uint32_t times)
{
return;
}
void jesd_tx_data_init()
{
uint8_t antNum = JESD_NRFDD_ANT_NUM;
uint8_t idAnt = 0;
uint8_t idSlot = 0;
uint32_t srcAddr = 0;
uint32_t dstAddr = 0;
uint32_t dataLen = 0;
uint16_t samByteCnt = 4;
uint32_t slotSamCnt = JESD_NRFDD_SLOT_SAM_CNT;
uint32_t cpyCnt = 0;
memset_ucp((void*)JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset_ucp((void*)JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
// valid data
// IQ data
samByteCnt = 4;
for (idAnt = 0; idAnt < antNum; idAnt++)
{
for (idSlot = 0; idSlot <= 1; idSlot++)
{
if (0 == idSlot) // even slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataNr[0]); // + idAnt*slotSamCnt;
dstAddr = JESD_NRFDD_TX_SLOT_EVEN_DATA_ADDR + idAnt*dataLen;
}
else if (1 == idSlot) // odd slot
{
dataLen = samByteCnt * slotSamCnt;
srcAddr = (uint32_t)(&antDataNr[0]); // + idAnt*slotSamCnt;
dstAddr = JESD_NRFDD_TX_SLOT_ODD_DATA_ADDR + idAnt*dataLen;
}
//debug_write((DBG_DDR_IDX_DRV_BASE+256+(cpyCnt<<2)), (uint32_t)srcAddr); // 0x400
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+1)), (uint32_t)dstAddr);
//debug_write((DBG_DDR_IDX_DRV_BASE+256+((cpyCnt<<2)+2)), (uint32_t)dataLen);
// memcpy_ucp((void*)dstAddr,(void*)srcAddr, dataLen);
ape_csu_dma_1D_G2L_ch0ch1_transfer(srcAddr, dstAddr, dataLen, cpyCnt, 1);
cpyCnt++;
}
}
memset((void*)JESD_NRFDD_RX_SLOT_EVEN_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
memset((void*)JESD_NRFDD_RX_SLOT_ODD_DATA_ADDR, 0, antNum*slotSamCnt*samByteCnt);
}

245773
public/test/testcases/case46/fronthaul/src/jesd_test_case46_antdata.s.c Normal file
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60
public/test/testcases/case46/osp/src/ape_test_case46.s.c Normal file
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@ -0,0 +1,60 @@
// +FHDR------------------------------------------------------------
// Copyright (c) 2022 SmartLogic.
// ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename : ape_test_case1.s.c
// Author :
// Created On : 2022-10-26
// Last Modified :
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------
#include "typedef.h"
#include "osp_task.h"
#include "osp_timer.h"
#include "ucp_printf.h"
void ape0_test_task_reg(void)
{
return ;
}
void ape1_test_task_reg(void)
{
return ;
}
void ape2_test_task_reg(void)
{
return ;
}
void ape3_test_task_reg(void)
{
return ;
}
void ape4_test_task_reg(void)
{
return ;
}
void ape5_test_task_reg(void)
{
return ;
}
void ape6_test_task_reg(void)
{
return ;
}
void ape7_test_task_reg(void)
{
return ;
}

3
public/test/testcases/case47/fronthaul/src/jesd_test_case47.s.c
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@ -32,7 +32,7 @@ extern uint32_t gJesdTFMode;
int32_t fh_data_init(void)
{
gJesdTestMode = JESD_TEST_MODE;
gJesdIOMode = JESD_IO_CTRL;
gJesdIOMode = JESD_CSU_CTRL; // JESD_IO_CTRL;
gJesdTFMode = FDD_MODE;
debug_write((DBG_DDR_IDX_DRV_BASE+192), gJesdTestMode); // 0x300
debug_write((DBG_DDR_IDX_DRV_BASE+193), gJesdIOMode); // 0x304
@ -49,6 +49,7 @@ int32_t fh_drv_init(void)
memset_ucp(&fhDrvPara, 0, sizeof(stFrontHaulDrvPara));
fhDrvPara.protocolSel = PROTOCOL_JESD;
fhDrvPara.rateOption = JESD_OPTION_204B;
fronthaul_drv_cfg(&fhDrvPara);