xinxin.li
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a9180edc85
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1.commit normalization drv version;
2.add ecpri code;
3.test case: case34,case44,case21(CPRI/JESD mode)
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2023-09-22 19:47:02 +08:00 |
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yonglin.gui
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842d1d638d
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删除了ul方向数据包是否及时被RC读取的判断
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2023-09-09 10:10:39 +08:00 |
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yonglin.gui
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cf575de36e
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add RC control EP pcie log
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2023-08-05 08:18:36 +08:00 |
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yonglin.gui
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99f4310ae8
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modify the pcie tranfic bug
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2023-08-02 17:55:39 +08:00 |
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yonglin.gui
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d7eb9d91d7
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merge pcie code to v2.1
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2023-07-27 18:46:09 +08:00 |
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chao1.wang
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d74566ec2c
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First commit
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2023-07-13 11:27:03 +08:00 |
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