1. modified the function of void handshake_master_with_slave(uint32_t u32_core_mask) add the input parameter.
2. phy should support the function of uint32_t get_core_mask_by_phy(void).
3. Test:
3.1 spu_case0_arm_case0_cpri: Pass
3.2 spu_case14_arm_case20_cpri:Pass
3.3 spu_case20_arm_case20_cpri:Pass
3.4 spu_case21_arm_case21_cpri:Pass
3.5 spu_case34_arm_case5: Pass
3.6 spu_case44_arm_case5: Pass
2. disable rf switch int after all of cells are deleted;
3. adjust slot offset, csu offset, rf switch offset;
4. add init para about 204C;
5. test case: case21, case34, case44.
2. update New Feature#1347 to dev_ck_v2.1
3. add new interface for ecs rfm1 and ape: spu_get_oam_handle_id for get oam handle_id by inst_id
4. Move Mem_init() from ape to ecs rfm1
5. TEST:
5.1 spu(case0)+arm(case0): pass
5.2 spu(case14)+arm(case20):pass
5.3 spu(case20)+arm(case20):pass
5.4 spu(case21)+arm(case21):pass
5.5 spu(case34)+arm(case5): pass
5.6 spu(case44)+arm(case5): pass
1. SPU and ARM both update
2. 8 APE and 3 RFM(no pet_rfm_spu0) support hearbeat
3. ARM support new function get_heartbeat_status() to get the cores status
4. test:
4.1 spu(case34)+arm(case5): Pass
4.2 spu(case44)+arm(case5): Pass --> spu(case44)should use previous version
4.3 spu(case21)+arm(case21):Pass
4.4 spu(case14)+arm(case3): Pass
2.move check_phy_cell to mtimer_init4phy function;
3.delete jesd rx1 timer init;
4.delete some test code in the cpri/jesd timer isr function;
5.add some necessary function declaration in the interface folder;
6.test case: case21(cpri and jesd), case34, case44.
