/****************************************************************** * @file cpri_csu_api.h * @brief: [file description] * @author: bo.liu * @Date 2022年12月14日 * COPYRIGHT NOTICE: (c) smartlogictech. All rights reserved. * Change_date Owner Change_content * 2022年12月14日 bo.liu create file *****************************************************************/ #ifndef CPRI_CSU_API_H #define CPRI_CSU_API_H #include #define CPRIEND_ADDR (0) //CPRI端固定地址为0 #define CSU_TX_DUMMYBUFFER_ADDR 0x8651000 #define CSU_RX_DUMMYBUFFER_ADDR 0x8653000 #define CPRIENDFLAG 1 //CPRI端 #define NONCPRIENDFLAG 0 //非CPRI端 #define SINGLE_END_MD_DMA 0 //单边链式多维DMA #define DUAL_END_MD_DMA 1 //双边链式多维DMA #define LINKLIST_NODE_TYPE_SRC 0 //源节点 #define LINKLIST_NODE_TYPE_DST 1 //目的节点 #define DMA_PARAM_MODE_NORMAL 0 //普通寄存器模式 #define DMA_PARAM_MODE_LINKLIST 1 //链表模式 typedef enum _tagCpriDummyFlag { CPRI_DUMMY_USE_DUMMY_ADDR = 0, CPRI_DUMMY_USE_DDR_ADDR = 1 }numCpriDummyFlag; typedef struct { uint32_t cmd32l; uint32_t cmd14h; }stCpriCsuCmd; typedef struct { uint32_t cmd_num; stCpriCsuCmd cmd[10]; }stCpriCsuCmdFifo; typedef struct { uint32_t cmdFifo_num; stCpriCsuCmdFifo cmdFifo[8]; }stCpriCsuCmdFifoInfo; extern uint32_t UCP_API_CPRI_CSU_Init(uint32_t Cfg_BusRegNum, uint32_t Clr_CpriDmaRegGroup, uint32_t DmaTagMask); extern void UCP_API_CPRI_CSU_RxInLatch_Cfg(uint32_t AxcIdNum, uint32_t *Rx0Portinfo, uint32_t InlatchNum, uint32_t *Rx0InLatchinfoL, uint32_t *Rx0InLatchinfoH, uint32_t *Rx0CycleNum); extern uint32_t UCP_API_CPRI_CSU_RxInLatchThres_Cfg(uint32_t Inlatch_index, uint32_t WriteOrRead, uint32_t send_threshold, uint32_t almostfull_threshold); extern void UCP_API_CPRI_CSU_TxOutLatch_Cfg(uint32_t AxcIdNum, uint32_t Tx0RfpBfSet, uint32_t *Tx0Portinfo, uint32_t OutlatchNum, uint32_t *Tx0LatchinfoL, uint32_t *Tx0LatchinfoM, uint32_t *Tx0latchinfoH); extern int32_t UCP_API_CPRI_CSU_MdDma_LinkNodeGen( stCsuLinkDesc1L3D *LinkDesc, uint32_t LinkType, uint32_t NodeType, uint32_t CpriEndFlag, uint32_t Addr, uint32_t AxcId, uint32_t Xnum, uint32_t Allnum, uint32_t LatchId, uint32_t RxFirstDmaFlag, uint32_t TxLastDmaFlag, uint32_t NextNodeAddr); extern void UCP_API_CPRI_CSU_DmaParamReg_Cfg(uint32_t DmaRegIdx, uint32_t DmaMode, uint32_t DmaAddrL, uint32_t Xnum, uint32_t Ynum, uint32_t YstepL, uint32_t ZsetpL, uint32_t SizeGranAllnum); extern void UCP_API_CPRI_CSU_TxCtrlAxc_Interleaver (uint32_t cpri_option, uint32_t ctrl_axc_bytenum, uint32_t origin_ctrlaxc, uint32_t interleaver_ctrlaxc); extern void UCP_API_CPRI_CSU_RxCtrkAxc_Deinterleaver(uint32_t cpri_option, uint32_t ctrl_axc_bytenum, uint32_t origin_ctrlaxc, uint32_t deinterleaver_ctrlaxc); extern void UCP_API_CPRI_CSU_RxAxcCtrl_Fifo2Cmd(uint32_t Cmdhigh14bit,uint32_t Cmdlow32bit); extern void UCP_API_CPRI_CSU_TxAxcData_Fifo1Cmd(uint32_t Cmdhigh14bit, uint32_t Cmdlow32bit); extern void UCP_API_CPRI_CSU_TxAxcCtrl_Fifo3Cmd(uint32_t Cmdhigh14bit,uint32_t Cmdlow32bit); extern void UCP_API_CPRI_CSU_RxAxcData_Fifo0Cmd(uint32_t Cmdhigh14bit,uint32_t Cmdlow32bit); extern uint32_t UCP_API_CPRI_CSU_TagLookUp(uint32_t Cmdtag); extern void UCP_API_CPRI_CSU_TXAxcData_ChannelCtrl(uint32_t Tx0_enable, uint32_t TxAxcIdNum, uint32_t OutlatchNum); extern void UCP_API_CPRI_CSU_RXAxcData_ChannelCtrl(uint32_t Rx0_enable, uint32_t InlatchNum); extern void UCP_API_CPRI_CSU_TXCtrlAxc_ChannelCtrl(uint32_t Tx1_enable, uint32_t Tx1_capstartnum); extern void UCP_API_CPRI_CSU_RXCtrlAxc_ChannelCtrl(uint32_t Rx1_enable, uint32_t Rx1_capstartnum, uint32_t Rx1_rfpstartnum); extern void UCP_API_CPRI_CSU_Set_AxcIdNum(uint32_t nAxcIdNum); extern void UCP_API_CPRI_CSU_Set_LatchNum(uint32_t nLatchNum); extern void UCP_API_CPRI_CSU_Get_CmdFIFO(stCpriCsuCmdFifoInfo* pTxCmdFifo, stCpriCsuCmdFifoInfo* pRxCmdFifo); #ifdef CPRI_API_TEST extern void cpri_csu_axc_init_timing_apitest( ); extern void cpri_csu_axc_linknodegen_timing_apitest( ); #endif #endif