//******************** (C) COPYRIGHT 2020 SmartLogic******************************* // FileName : cci550.h // Author : lijian, jian.li@smartlogictech.com // Date First Issued : 2021-10-30 06:54:48 PM // Last Modified : 2022-03-18 09:33:57 PM // Description : // ------------------------------------------------------------ // Modification History: // Version Date Author Modification Description // //********************************************************************************** #ifndef __CCI550_H__ #define __CCI550_H__ #define CCI550_BASE 0X04608000 #define CCI_CTRL_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X00000))) #define CCI_SECR_ACC (*((volatile uint32_t *)(CCI550_BASE + 0X00008))) #define CCI_STATUS (*((volatile uint32_t *)(CCI550_BASE + 0X0000C))) #define CCI_IMPR_ERR (*((volatile uint32_t *)(CCI550_BASE + 0X00010))) #define CCI_QOS_THRESHOLD (*((volatile uint32_t *)(CCI550_BASE + 0X00014))) #define CCI_PMU_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X00100))) #define CCI_DEBUG_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X00104))) #define CCI_PERIPHERAL_ID4 (*((volatile uint32_t *)(CCI550_BASE + 0X00FD0))) #define CCI_PERIPHERAL_ID5 (*((volatile uint32_t *)(CCI550_BASE + 0X00FD4))) #define CCI_PERIPHERAL_ID6 (*((volatile uint32_t *)(CCI550_BASE + 0X00FD8))) #define CCI_PERIPHERAL_ID7 (*((volatile uint32_t *)(CCI550_BASE + 0X00FDC))) #define CCI_PERIPHERAL_ID0 (*((volatile uint32_t *)(CCI550_BASE + 0X00FE0))) #define CCI_PERIPHERAL_ID1 (*((volatile uint32_t *)(CCI550_BASE + 0X00FE4))) #define CCI_PERIPHERAL_ID2 (*((volatile uint32_t *)(CCI550_BASE + 0X00FE8))) #define CCI_PERIPHERAL_ID3 (*((volatile uint32_t *)(CCI550_BASE + 0X00FEC))) #define CCI_COMPONENT_ID0 (*((volatile uint32_t *)(CCI550_BASE + 0X00FF0))) #define CCI_COMPONENT_ID1 (*((volatile uint32_t *)(CCI550_BASE + 0X00FF4))) #define CCI_COMPONENT_ID2 (*((volatile uint32_t *)(CCI550_BASE + 0X00FF8))) #define CCI_COMPONENT_ID3 (*((volatile uint32_t *)(CCI550_BASE + 0X00FFC))) #define SLV0_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X01000))) #define SLV0_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X01004))) #define SLV0_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X01100))) #define SLV0_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X01104))) #define SLV0_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X01110))) #define SLV1_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X02000))) #define SLV1_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X02004))) #define SLV1_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X02100))) #define SLV1_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X02104))) #define SLV1_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X02110))) #define SLV2_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X03000))) #define SLV2_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X03004))) #define SLV2_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X03100))) #define SLV2_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X03104))) #define SLV2_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X03110))) #define SLV3_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X04000))) #define SLV3_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X04004))) #define SLV3_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X04100))) #define SLV3_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X04104))) #define SLV3_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X04110))) #define SLV4_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X05000))) #define SLV4_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X05004))) #define SLV4_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X05100))) #define SLV4_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X05104))) #define SLV4_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X05110))) #define SLV5_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X06000))) #define SLV5_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X06004))) #define SLV5_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X06100))) #define SLV5_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X06104))) #define SLV5_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X07110))) #define SLV6_SNOOP_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X07000))) #define SLV6_SHARE_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X07004))) #define SLV6_ARQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X07100))) #define SLV6_AWQOS_OVR (*((volatile uint32_t *)(CCI550_BASE + 0X07104))) #define SLV6_QOS_MAX_OT (*((volatile uint32_t *)(CCI550_BASE + 0X07110))) #define PMU0_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X10000))) #define PMU0_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X10004))) #define PMU0_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X10008))) #define PMU0_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X1000C))) #define PMU1_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X20000))) #define PMU1_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X20004))) #define PMU1_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X20008))) #define PMU1_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X2000C))) #define PMU2_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X30000))) #define PMU2_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X30004))) #define PMU2_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X30008))) #define PMU2_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X3000C))) #define PMU3_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X40000))) #define PMU3_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X40004))) #define PMU3_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X40008))) #define PMU3_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X4000C))) #define PMU4_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X50000))) #define PMU4_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X50004))) #define PMU4_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X50008))) #define PMU4_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X5000C))) #define PMU5_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X60000))) #define PMU5_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X60004))) #define PMU5_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X60008))) #define PMU5_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X6000C))) #define PMU6_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X70000))) #define PMU6_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X70004))) #define PMU6_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X70008))) #define PMU6_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X7000C))) #define PMU7_EVNT_SEL (*((volatile uint32_t *)(CCI550_BASE + 0X80000))) #define PMU7_ECNT_DATA (*((volatile uint32_t *)(CCI550_BASE + 0X80004))) #define PMU7_ECNT_CTRL (*((volatile uint32_t *)(CCI550_BASE + 0X80008))) #define PMU7_ECNT_CLR_OVFL (*((volatile uint32_t *)(CCI550_BASE + 0X8000C))) #define SLAVE0_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90000))) #define SLAVE1_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90004))) #define SLAVE2_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90008))) #define SLAVE3_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X9000C))) #define SLAVE4_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90010))) #define SLAVE5_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90014))) #define SLAVE6_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90018))) #define MASTER0_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90100))) #define MASTER1_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90104))) #define MASTER2_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90108))) #define MASTER3_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X9010C))) #define MASTER4_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90110))) #define MASTER5_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90114))) #define MASTER6_DEBUG (*((volatile uint32_t *)(CCI550_BASE + 0X90118))) #endif