//******************** (C) COPYRIGHT 2019 SmartLogic******************************* // FileName : ucp_param.h // Author : lijian, jian.li@smartlogictech.com // Date First Issued : 2019-03-29 02:37:50 PM // Last Modified : 2022-01-18 06:26:21 PM // Description : // ------------------------------------------------------------ // Modification History: // Version Date Author Modification Description // //********************************************************************************** #ifndef __UCP_PARAM_H__ #define __UCP_PARAM_H__ #define BIT0 (0x1<<0ul) #define BIT1 (0x1<<1ul) #define BIT2 (0x1<<2ul) #define BIT3 (0x1<<3ul) #define BIT4 (0x1<<4ul) #define BIT5 (0x1<<5ul) #define BIT6 (0x1<<6ul) #define BIT7 (0x1<<7ul) #define BIT8 (0x1<<8ul) #define BIT9 (0x1<<9ul) #define BIT10 (0x1<<10ul) #define BIT11 (0x1<<11ul) #define BIT12 (0x1<<12ul) #define BIT13 (0x1<<13ul) #define BIT14 (0x1<<14ul) #define BIT15 (0x1<<15ul) #define BIT16 (0x1<<16ul) #define BIT17 (0x1<<17ul) #define BIT18 (0x1<<18ul) #define BIT19 (0x1<<19ul) #define BIT20 (0x1<<20ul) #define BIT21 (0x1<<21ul) #define BIT22 (0x1<<22ul) #define BIT23 (0x1<<23ul) #define BIT24 (0x1<<24ul) #define BIT25 (0x1<<25ul) #define BIT26 (0x1<<26ul) #define BIT27 (0x1<<27ul) #define BIT28 (0x1<<28ul) #define BIT29 (0x1<<29ul) #define BIT30 (0x1<<30ul) #define BIT31 (0x1<<31ul) #define S64B 0x00000040ul #define S128B 0x00000080ul #define S256B 0x00000100ul #define S512B 0x00000200ul #define S1KB 0x00000400ul #define S2KB 0x00000800ul #define S4KB 0x00001000ul #define S8KB 0x00002000ul #define S16KB 0x00004000ul #define S32KB 0x00008000ul #define S64KB 0x00010000ul #define S128KB 0x00020000ul #define S256KB 0x00040000ul #define S512KB 0x00080000ul #define S1MB 0x00100000ul #define S15MB 0x00180000ul #define S2MB 0x00200000ul #define S4MB 0x00400000ul //m3 -> apsm0 apsm -> apsm1 #define M3_SRAM_BASE 0x043c8000ul #define APSM0_BASE 0x04768000ul #define APSM1_BASE 0x04778000ul #define CPSM_BASE 0x09300000ul #define DDR_BASE 0x10000000ul #define APSM0_SIZE S64KB #define APSM1_SIZE S64KB #define CPSM_SIZE S128KB #define M3_SRAM_SIZE S32KB #define JS_SM_BASE 0x04d80000ul #define JECS_SM_BASE 0x07200000ul #define PET_SM_BASE 0x08700000ul #define JS_SM_SIZE S128KB #define JECS_SM_SIZE S128KB #define PET_SM_SIZE S128KB #define SM0_BASE 0x09d00000ul #define SM1_BASE 0x09e00000ul #define SM2_BASE 0x09f00000ul #define SM3_BASE 0x0a080000ul #define SM4_BASE 0x0a200000ul #define SM5_BASE 0x0a380000ul #define SM0_SIZE S1MB #define SM1_SIZE S1MB #define SM2_SIZE S15MB #define SM3_SIZE S15MB #define SM4_SIZE S15MB #define SM5_SIZE S15MB #define PET_PET_CTC_INTER 0 #define JECS_JECS_CTC_INTER 0 #define APC_CPSPACC0_INTR 0 #define APC_TMAC_INTR 1 #define APC_JESD204A_WRAPPER_INTR 2 #define APC_JESD204B_WRAPPER_INTR 3 #define APC_JS_SM_EMPTY_INTR0 4 #define APC_JS_SM_EMPTY_INTR1 5 #define APC_JS_SM_EMPTY_INTR2 6 #define APC_JS_SM_EMPTY_INTR3 7 #define APC_JS_SM_EMPTY_INTR4 8 #define APC_JS_SM_EMPTY_INTR5 9 #define APC_JS_SM_EMPTY_INTR6 10 #define APC_JS_SM_EMPTY_INTR7 11 #define APC_JS_SM_FULL_INTR0 12 #define APC_JS_SM_FULL_INTR1 13 #define APC_JS_SM_FULL_INTR2 14 #define APC_JS_SM_FULL_INTR3 15 #define APC_JS_SM_FULL_INTR4 16 #define APC_JS_SM_FULL_INTR5 17 #define APC_JS_SM_FULL_INTR6 18 #define APC_JS_SM_FULL_INTR7 19 #define APC_SRIO_SUB0_INTR 20 #define APC_SRIO_SUB1_INTR 21 #define APC_CPSPACC2_INTR 22 #define APC_PET_SM_EMPTY_INTR0 23 #define APC_PET_SM_EMPTY_INTR1 24 #define APC_PET_SM_EMPTY_INTR2 25 #define APC_PET_SM_EMPTY_INTR3 26 #define APC_PET_SM_EMPTY_INTR4 27 #define APC_PET_SM_EMPTY_INTR5 28 #define APC_PET_SM_EMPTY_INTR6 29 #define APC_PET_SM_EMPTY_INTR7 30 #define APC_PET_SM_FULL_INTR0 31 #define APC_PET_SM_FULL_INTR1 32 #define APC_PET_SM_FULL_INTR2 33 #define APC_PET_SM_FULL_INTR3 34 #define APC_PET_SM_FULL_INTR4 35 #define APC_PET_SM_FULL_INTR5 36 #define APC_PET_SM_FULL_INTR6 37 #define APC_PET_SM_FULL_INTR7 38 #define APC_JECS_SM_EMPTY_INTR0 39 #define APC_JECS_SM_EMPTY_INTR1 40 #define APC_JECS_SM_EMPTY_INTR2 41 #define APC_JECS_SM_EMPTY_INTR3 42 #define APC_JECS_SM_EMPTY_INTR4 43 #define APC_JECS_SM_EMPTY_INTR5 44 #define APC_JECS_SM_EMPTY_INTR6 45 #define APC_JECS_SM_EMPTY_INTR7 46 #define APC_JECS_SM_FULL_INTR0 47 #define APC_JECS_SM_FULL_INTR1 48 #define APC_JECS_SM_FULL_INTR2 49 #define APC_JECS_SM_FULL_INTR3 50 #define APC_JECS_SM_FULL_INTR4 51 #define APC_JECS_SM_FULL_INTR5 52 #define APC_JECS_SM_FULL_INTR6 53 #define APC_JECS_SM_FULL_INTR7 54 #define APC_MBX0_HPRI_INTR0 55 #define APC_MBX0_HPRI_INTR1 56 #define APC_MBX0_HPRI_INTR2 57 #define APC_MBX0_HPRI_INTR3 58 #define APC_MBX0_LPRI_INTR0 59 #define APC_MBX0_LPRI_INTR1 60 #define APC_MBX0_LPRI_INTR2 61 #define APC_MBX0_LPRI_INTR3 62 #define APC_MBX1_HPRI_INTR0 63 #define APC_MBX1_HPRI_INTR1 64 #define APC_MBX1_HPRI_INTR2 65 #define APC_MBX1_HPRI_INTR3 66 #define APC_MBX1_LPRI_INTR0 67 #define APC_MBX1_LPRI_INTR1 68 #define APC_MBX1_LPRI_INTR2 69 #define APC_MBX1_LPRI_INTR3 70 #define APC_SSI2_INTR 71 #define APC_SSI3_INTR 72 #define APC_TIMER10_INTR 73 #define APC_TIMER11_INTR 74 #define APC_TIMER12_INTR 75 #define APC_TIMER13_INTR 76 #define APC_TIMER14_INTR 77 #define APC_TIMER15_INTR 78 #define APC_TIMER16_INTR 79 #define APC_TIMER17_INTR 80 #define APC_TIMER20_INTR 81 #define APC_TIMER21_INTR 82 #define APC_TIMER22_INTR 83 #define APC_TIMER23_INTR 84 #define APC_TIMER24_INTR 85 #define APC_TIMER25_INTR 86 #define APC_TIMER26_INTR 87 #define APC_TIMER27_INTR 88 #define APC_JS_CRG_INTR 89 #define APC_RFC_INTR0 90 #define APC_RFC_INTR1 91 #define APC_RFC_INTR2 92 #define APC_PETSPACC0_INTR 93 #define APC_RFCSU_RX_INTR 94 #define APC_RFCSU_TX_INTR 95 #define APC_JESD_RX0_SBU0_TMR_INTR0 96 #define APC_JESD_RX0_SBU0_TMR_INTR1 97 #define APC_JESD_RX0_SBU0_TMR_INTR2 98 #define APC_JESD_RX0_SBU0_TMR_INTR3 99 #define APC_JESD_RX0_SBU0_TMR_INTR4 100 #define APC_JESD_RX0_SBU0_TMR_INTR5 101 #define APC_JESD_RX0_SBU0_TMR_INTR6 102 #define APC_JESD_RX0_SBU0_TMR_INTR7 103 #define APC_JESD_RX0_SBU0_TMR_INTR8 104 #define APC_JESD_RX0_SBU0_TMR_INTR9 105 #define APC_JESD_RX0_SBU0_TMR_INTR10 106 #define APC_JESD_RX0_SBU0_TMR_INTR11 107 #define APC_SLAVE_INTERRUPT_RX0_SUB0 108 #define APC_SLAVE_INTERRUPT_RX0_SUB1 109 #define APC_SLAVE_INTERRUPT_RX1_SUB0 110 #define APC_SLAVE_INTERRUPT_RX1_SUB1 111 #define APC_SLAVE_INTERRUPT_TX_SUB0 112 #define APC_SLAVE_INTERRUPT_TX_SUB1 113 #define APC_JECS_CTC_INTER 114 #define APC_PET_CTC_INTER 115 #define APC_SPACC0_INTR 116 #define APC_CPSM_EMPTY_INTR0 120 #define APC_CPSM_EMPTY_INTR1 121 #define APC_CPSM_EMPTY_INTR2 122 #define APC_CPSM_EMPTY_INTR3 123 #define APC_CPSM_EMPTY_INTR4 124 #define APC_CPSM_EMPTY_INTR5 125 #define APC_CPSM_EMPTY_INTR6 126 #define APC_CPSM_EMPTY_INTR7 127 #define APC_CPSM_FULL_INTR0 128 #define APC_CPSM_FULL_INTR1 129 #define APC_CPSM_FULL_INTR2 130 #define APC_CPSM_FULL_INTR3 131 #define APC_CPSM_FULL_INTR4 132 #define APC_CPSM_FULL_INTR5 133 #define APC_CPSM_FULL_INTR6 134 #define APC_CPSM_FULL_INTR7 135 #define APC_RFC_DMA_INTR 136 #define APC_JESD_CSU_RX0_INTR 137 #define APC_JESD_CSU_TX_INTR 138 #define APC_JESD_CSU_RX1_INTR 139 #define APC_JESDA_CSU_TX_INTR1 140 #define APC_JESDB_CSU_RX_INTR0 141 #define APC_JESDB_CSU_RX_INTR1 142 #define APC_JESDB_CSU_TX_INTR0 143 #define APC_JESDB_CSU_TX_INTR1 144 #define APC_PETRFM_OUT_INTR0 205 #define APC_PETRFM_OUT_INTR1 206 #define APC_PETRFM_OUT_INTR2 207 #define APC_PETRFM_OUT_INTR3 208 #define APC_PETRFM_OUT_INTR4 209 #define APC_PETRFM_OUT_INTR5 210 #define APC_PETRFM_OUT_INTR6 211 #define APC_PETRFM_OUT_INTR7 212 #define APC_PETRFM_OUT_INTR8 213 #define APC_PETRFM_OUT_INTR9 214 #define APC_PETRFM_OUT_INTR10 215 #define APC_PETRFM_OUT_INTR11 216 #define APC_PETRFM_OUT_INTR12 217 #define APC_PETRFM_OUT_INTR13 218 #define APC_PETRFM_OUT_INTR14 219 #define APC_PETRFM_OUT_INTR15 220 #define APC_PETRFM_OUT_INTR16 221 #define APC_PETRFM_OUT_INTR17 222 #define APC_PETRFM_OUT_INTR18 223 #define APC_PETRFM_OUT_INTR19 224 #define APC_JECSRFM_OUT_INTR0 225 #define APC_JECSRFM_OUT_INTR1 226 #define APC_JECSRFM_OUT_INTR2 227 #define APC_JECSRFM_OUT_INTR3 228 #define APC_JECSRFM_OUT_INTR4 229 #define APC_JECSRFM_OUT_INTR5 230 #define APC_JECSRFM_OUT_INTR6 231 #define APC_JECSRFM_OUT_INTR7 232 #define APC_JECSRFM_OUT_INTR8 233 #define APC_JECSRFM_OUT_INTR9 234 #define APC_JECSRFM_OUT_INTR10 235 #define APC_JECSRFM_OUT_INTR11 236 #define APC_JECSRFM_OUT_INTR12 237 #define APC_JECSRFM_OUT_INTR13 238 #define APC_JECSRFM_OUT_INTR14 239 #define APC_JECSRFM_OUT_INTR15 240 #define APC_JECSRFM_OUT_INTR16 241 #define APC_JECSRFM_OUT_INTR17 242 #define APC_JECSRFM_OUT_INTR18 243 #define APC_JECSRFM_OUT_INTR19 244 #define APC_ECPRI_SUB_INTR0 245 #define APC_ECPRI_SUB_INTR1 246 #define APC_ECPRI_SUB_INTR2 247 #define APC_ECPRI_SUB_INTR3 248 #define APC_ECPRI_SUB_INTR4 249 #define APC_ECPRI_SUB_INTR5 250 #define APC_ECPRI_SUB_INTR6 251 #define APC_ECPRI_SUB_INTR7 252 #define APC_ECPRI_SUB_INTR8 253 #define APC_ECPRI_SUB_INTR9 254 #define APC_ECPRI_SUB_INTR10 255 #define APC_ECPRI_SUB_INTR11 256 #define APC_ECPRI_SUB_INTR12 257 #define APC_ECPRI_SUB_INTR13 258 #define APC_ECPRI_SUB_INTR14 259 #define APC_ECPRI_SUB_INTR15 260 #define APC_ECPRI_SUB_INTR16 261 #define APC_ECPRI_SUB_INTR17 262 #define APC_ECPRI_SUB_INTR18 263 #define APC_ECPRI_SUB_INTR19 264 #define APC_ECPRI_SUB_INTR20 265 #define APC_ECPRI_SUB_INTR21 266 #define APC_ECPRI_SUB_INTR22 267 #define APC_ECPRI_SUB_INTR23 268 #define APC_ECPRI_SUB_INTR24 269 #define APC_ECPRI_SUB_INTR25 270 #define APC_ECPRI_SUB_INTR26 271 #define APC_ECPRI_SUB_INTR27 272 #define APC_ECPRI_SUB_INTR28 273 #define APC_ECPRI_SUB_INTR29 274 #define APC_ECPRI_SUB_INTR30 275 #define APC_ECPRI_SUB_INTR31 276 #define APC_PETSPACC1_INTR 277 #define APC_CPRI_SUB_INTR0 278 #define APC_CPRI_SUB_INTR1 279 #define APC_STC_INTR0 280 #define APC_STC_INTR1 281 #define APC_STC_INTR2 282 #define APC_STC_INTR3 283 #define APC_STC_INTR4 284 #define APC_STC_INTR5 285 #define APC_STC_INTR6 286 #define APC_STC_INTR7 287 #define APC_STC_INTR8 288 #define APC_STC_INTR9 289 #define APC_STC_INTR10 290 #define APC_CPRI_TMR_INTR0 291 #define APC_CPRI_TMR_INTR1 292 #define APC_CPRI_TMR_INTR2 293 #define APC_CPRI_TMR_INTR3 294 #define APC_CPRI_TMR_INTR4 295 #define APC_CPRI_TMR_INTR5 296 #define APC_CPRI_TMR_INTR6 297 #define APC_CPRI_TMR_INTR7 298 #define APC_CPRI_TMR_INTR8 299 #define APC_CPRI_TMR_INTR9 300 #define APC_CPRI_TMR_INTR10 301 #define APC_CPRI_TMR_INTR11 302 #define APC_SSI0_INTR (310+0) #define APC_SSI1_INTR (310+1) #define APC_UART0_INTR (310+2) #define APC_UART1_INTR (310+3) #define APC_WDT0_INTR (310+4) #define APC_WDT1_INTR (310+5) #define APC_TIMER0_INTR (310+6) #define APC_GPIO0_INTR (310+7) #define APC_AP_CSU_INTR0 (310+28) #define APC_AP_CSU_INTR1 (310+29) #define APC_AP_CSU_INTR2 (310+30) #define APC_AP_CSU_INTR3 (310+31) #define APC_AP_CSU_INTR4 (310+32) #define APC_AP_CSU_INTR5 (310+33) #define APC_AP_CSU_INTR6 (310+34) #define APC_AP_CSU_INTR7 (310+35) #define APC_SYSC_CTC10_INTR0 (310+36) #define APC_SYSC_CTC11_INTR0 (310+37) #define APC_SYSC_CTC12_INTR0 (310+38) #define APC_SYSC_CTC13_INTR0 (310+39) #define APC_SYSC_CTC14_INTR0 (310+40) #define APC_SYSC_CTC15_INTR0 (310+41) #define APC_SYSC_CTC16_INTR0 (310+42) #define APC_SYSC_CTC17_INTR0 (310+43) #define APC_SYSC_CTC18_INTR0 (310+44) #define APC_SYSC_CTC19_INTR0 (310+45) #define APC_SYSC_CTC20_INTR0 (310+46) #define APC_SYSC_CTC21_INTR0 (310+47) #define APC_SYSC_CTC22_INTR0 (310+48) #define APC_SYSC_CTC23_INTR0 (310+49) #define APC_SYSC_CTC24_INTR0 (310+50) #define APC_SYSC_CTC25_INTR0 (310+51) #define APC_SYSC_CTC26_INTR0 (310+52) #define APC_SYSC_CTC27_INTR0 (310+53) #define APC_SYSC_CTC28_INTR0 (310+54) #define APC_SYSC_CTC29_INTR0 (310+55) #define APC_SYSC_CTC30_INTR0 (310+56) #define APC_SYSC_CTC31_INTR0 (310+57) #define APC_SYSC_CTC32_INTR0 (310+58) #define APC_SYSC_CTC33_INTR0 (310+59) #define APC_SYSC_CTC34_INTR0 (310+60) #define APC_SYSC_CTC35_INTR0 (310+61) #define APC_SYSC_CTC36_INTR0 (310+62) #define APC_SYSC_CTC37_INTR0 (310+63) #define APC_SYSC_CTC38_INTR0 (310+64) #define APC_SYSC_CTC39_INTR0 (310+65) #define APC_SYSC_CTC40_INTR0 (310+66) #define APC_SYSC_CTC41_INTR0 (310+67) #define APC_SYSC_CTC42_INTR0 (310+68) #define APC_SYSC_CTC43_INTR0 (310+69) #define APC_SYSC_CTC44_INTR0 (310+70) #define APC_SYSC_CTC45_INTR0 (310+71) #define APC_SYSC_CTC46_INTR0 (310+72) #define APC_SYSC_CTC47_INTR0 (310+73) #define APC_SYSC_CTC48_INTR0 (310+74) #define APC_SYSC_CTC49_INTR0 (310+75) #define APC_SYSC_CTC50_INTR0 (310+76) #define APC_SYSC_CTC51_INTR0 (310+77) #define APC_SYSC_CTC52_INTR0 (310+78) #define APC_SYSC_CTC53_INTR0 (310+79) #define APC_SYSC_CTC54_INTR0 (310+80) #define APC_SYSC_CTC55_INTR0 (310+81) #define APC_SYSC_CTC56_INTR0 (310+82) #define APC_SYSC_CTC57_INTR0 (310+83) #define APC_SYSC_CTC58_INTR0 (310+84) #define APC_SYSC_CTC59_INTR0 (310+85) #define APC_SYSC_CTC60_INTR0 (310+86) #define APC_SYSC_CTC61_INTR0 (310+87) #define APC_SYSC_CTC62_INTR0 (310+88) #define APC_SYSC_CTC63_INTR0 (310+89) #define APC_SYSC_CTC64_INTR0 (310+90) #define APC_SYSC_CTC65_INTR0 (310+91) #define APC_SYSC_CTC66_INTR0 (310+92) #define APC_SYSC_CTC67_INTR0 (310+93) #define APC_SYSC_CTC68_INTR0 (310+94) #define APC_SYSC_CTC69_INTR0 (310+95) #define APC_SYSC_CTC70_INTR0 (310+96) #define APC_SYSC_CTC71_INTR0 (310+97) #define APC_JESD_TX0_SBU0_TMR_INTR0 408 #define APC_JESD_TX0_SBU0_TMR_INTR1 409 #define APC_JESD_TX0_SBU0_TMR_INTR2 410 #define APC_JESD_TX0_SBU0_TMR_INTR3 411 #define APC_JESD_TX0_SBU0_TMR_INTR4 412 #define APC_JESD_TX0_SBU0_TMR_INTR5 413 #define APC_JESD_TX0_SBU0_TMR_INTR6 414 #define APC_JESD_TX0_SBU0_TMR_INTR7 415 #define APC_JESD_TX0_SBU0_TMR_INTR8 416 #define APC_JESD_TX0_SBU0_TMR_INTR9 417 #define APC_JESD_TX0_SBU0_TMR_INTR10 418 #define APC_JESD_TX0_SBU0_TMR_INTR11 419 #define APC_JESD_TX_SBU1_TMR_INTR0 420 #define APC_JESD_TX_SBU1_TMR_INTR1 421 #define APC_JESD_TX_SBU1_TMR_INTR2 422 #define APC_JESD_TX_SBU1_TMR_INTR3 423 #define APC_JESD_TX_SBU1_TMR_INTR4 424 #define APC_JESD_TX_SBU1_TMR_INTR5 425 #define APC_JESD_TX_SBU1_TMR_INTR6 426 #define APC_JESD_TX_SBU1_TMR_INTR7 427 #define APC_JESD_TX_SBU1_TMR_INTR8 428 #define APC_JESD_TX_SBU1_TMR_INTR9 429 #define APC_JESD_TX_SBU1_TMR_INTR10 430 #define APC_JESD_TX_SBU1_TMR_INTR11 431 #define APC_JESD_TX1_SBU0_TMR_INTR0 266 #define APC_JESD_TX1_SBU0_TMR_INTR1 267 #define APC_JESD_TX1_SBU0_TMR_INTR2 268 #define APC_JESD_TX1_SBU0_TMR_INTR3 269 #define APC_JESD_TX1_SBU0_TMR_INTR4 270 #define APC_JESD_TX1_SBU0_TMR_INTR5 271 #define APC_JESD_TX1_SBU0_TMR_INTR6 272 #define APC_JESD_TX1_SBU0_TMR_INTR7 273 #define APC_JESD_TX1_SBU0_TMR_INTR8 274 #define APC_JESD_TX1_SBU0_TMR_INTR9 275 #define APC_JESD_TX1_SBU0_TMR_INTR10 276 #define APC_JESD_TX1_SBU0_TMR_INTR11 277 #define APC_JS_CSU_TXRX1_INTR0 432 #define APC_JS_CSU_TXRX1_INTR1 433 #define APC_JS_CSU_TXRX1_INTR2 434 #define APC_JS_CSU_TXRX1_INTR3 435 #define APC_JS_CSU_TXRX1_INTR4 436 #define APC_JS_CSU_TXRX1_INTR5 437 #define APC_JS_CSU_TXRX1_INTR6 438 #define APC_JS_CSU_TXRX1_INTR7 439 #define APC_JECS_CSU_INTR0 440 #define APC_JECS_CSU_INTR1 441 #define APC_JECS_CSU_INTR2 442 #define APC_JECS_CSU_INTR3 443 #define APC_JECS_CSU_INTR4 444 #define APC_JECS_CSU_INTR5 445 #define APC_JECS_CSU_INTR6 446 #define APC_JECS_CSU_INTR7 447 #define APC_JECS_CSU_TXRX1_INTR0 448 #define APC_JECS_CSU_TXRX1_INTR1 449 #define APC_JECS_CSU_TXRX1_INTR2 450 #define APC_JECS_CSU_TXRX1_INTR3 451 #define APC_JECS_CSU_TXRX1_INTR4 452 #define APC_JECS_CSU_TXRX1_INTR5 453 #define APC_JECS_CSU_TXRX1_INTR6 454 #define APC_JECS_CSU_TXRX1_INTR7 455 #define APC_EIP0_GLOBLE_INT 117 #define APC_EIP0_RING0_INT 118 #define APC_EIP0_RING1_INT 119 #define APC_EIP0_RING2_INT 456 #define APC_EIP0_RING3_INT 457 #define APC_EIP1_GLOBLE_INT 458 #define APC_EIP1_RING0_INT 459 #define APC_EIP1_RING1_INT 460 #define APC_EIP1_RING2_INT 461 #define APC_EIP1_RING3_INT 462 #define APC_GMAC0SDB_INT 463 #define APC_GMAC0PMT_INT 464 #define APC_GMAC0LPI_INT 465 #define APC_JESD_RX0_SBU1_TMR_INTR0 471 #define APC_JESD_RX0_SBU1_TMR_INTR1 472 #define APC_JESD_RX0_SBU1_TMR_INTR2 473 #define APC_JESD_RX0_SBU1_TMR_INTR3 474 #define APC_JESD_RX0_SBU1_TMR_INTR4 475 #define APC_JESD_RX0_SBU1_TMR_INTR5 476 #define APC_JESD_RX0_SBU1_TMR_INTR6 477 #define APC_JESD_RX0_SBU1_TMR_INTR7 478 #define APC_JESD_RX0_SBU1_TMR_INTR8 479 #define APC_JESD_RX0_SBU1_TMR_INTR9 480 #define APC_JESD_RX0_SBU1_TMR_INTR10 481 #define APC_JESD_RX0_SBU1_TMR_INTR11 482 #define APC_JESD_RX1_SBU0_TMR_INTR0 483 #define APC_JESD_RX1_SBU0_TMR_INTR1 484 #define APC_JESD_RX1_SBU0_TMR_INTR2 485 #define APC_JESD_RX1_SBU0_TMR_INTR3 486 #define APC_JESD_RX1_SBU0_TMR_INTR4 487 #define APC_JESD_RX1_SBU0_TMR_INTR5 488 #define APC_JESD_RX1_SBU0_TMR_INTR6 489 #define APC_JESD_RX1_SBU0_TMR_INTR7 490 #define APC_JESD_RX1_SBU0_TMR_INTR8 491 #define APC_JESD_RX1_SBU0_TMR_INTR9 492 #define APC_JESD_RX1_SBU0_TMR_INTR10 493 #define APC_JESD_RX1_SBU0_TMR_INTR11 494 #define APC_JESD_RX1_SBU1_TMR_INTR0 495 #define APC_JESD_RX1_SBU1_TMR_INTR1 496 #define APC_JESD_RX1_SBU1_TMR_INTR2 497 #define APC_JESD_RX1_SBU1_TMR_INTR3 498 #define APC_JESD_RX1_SBU1_TMR_INTR4 499 #define APC_JESD_RX1_SBU1_TMR_INTR5 500 #define APC_JESD_RX1_SBU1_TMR_INTR6 501 #define APC_JESD_RX1_SBU1_TMR_INTR7 502 #define APC_JESD_RX1_SBU1_TMR_INTR8 503 #define APC_JESD_RX1_SBU1_TMR_INTR9 504 #define APC_JESD_RX1_SBU1_TMR_INTR10 505 #define APC_JESD_RX1_SBU1_TMR_INTR11 506 #define APC_EIP2_GLOBLE_INT 93 #define APC_EIP2_RING0_INT 507 #define APC_EIP2_RING1_INT 508 #define APC_EIP2_RING2_INT 509 #define APC_EIP2_RING3_INT 510 #define APC_INPUT0 145 #define APC_INPUT1 165 #define APC_INPUT2 185 #define APC_INPUT3 205 #define APC_INPUT4 225 #define APC_INPUT5 310+8 //APC interconnect int #define APC_INPUT0_INTR0 (0+ APC_INPUT0) #define APC_INPUT0_INTR1 (1+ APC_INPUT0) #define APC_INPUT0_INTR2 (2+ APC_INPUT0) #define APC_INPUT0_INTR3 (3+ APC_INPUT0) #define APC_INPUT0_INTR4 (4+ APC_INPUT0) #define APC_INPUT0_INTR5 (5+ APC_INPUT0) #define APC_INPUT0_INTR6 (6+ APC_INPUT0) #define APC_INPUT0_INTR7 (7+ APC_INPUT0) #define APC_INPUT0_INTR8 (8+ APC_INPUT0) #define APC_INPUT0_INTR9 (9+ APC_INPUT0) #define APC_INPUT0_INTR10 (10+APC_INPUT0) #define APC_INPUT0_INTR11 (11+APC_INPUT0) #define APC_INPUT0_INTR12 (12+APC_INPUT0) #define APC_INPUT0_INTR13 (13+APC_INPUT0) #define APC_INPUT0_INTR14 (14+APC_INPUT0) #define APC_INPUT0_INTR15 (15+APC_INPUT0) #define APC_INPUT0_INTR16 (16+APC_INPUT0) #define APC_INPUT0_INTR17 (17+APC_INPUT0) #define APC_INPUT0_INTR18 (18+APC_INPUT0) #define APC_INPUT0_INTR19 (19+APC_INPUT0) #define APC_INPUT1_INTR0 (0+ APC_INPUT1) #define APC_INPUT1_INTR1 (1+ APC_INPUT1) #define APC_INPUT1_INTR2 (2+ APC_INPUT1) #define APC_INPUT1_INTR3 (3+ APC_INPUT1) #define APC_INPUT1_INTR4 (4+ APC_INPUT1) #define APC_INPUT1_INTR5 (5+ APC_INPUT1) #define APC_INPUT1_INTR6 (6+ APC_INPUT1) #define APC_INPUT1_INTR7 (7+ APC_INPUT1) #define APC_INPUT1_INTR8 (8+ APC_INPUT1) #define APC_INPUT1_INTR9 (9+ APC_INPUT1) #define APC_INPUT1_INTR10 (10+APC_INPUT1) #define APC_INPUT1_INTR11 (11+APC_INPUT1) #define APC_INPUT1_INTR12 (12+APC_INPUT1) #define APC_INPUT1_INTR13 (13+APC_INPUT1) #define APC_INPUT1_INTR14 (14+APC_INPUT1) #define APC_INPUT1_INTR15 (15+APC_INPUT1) #define APC_INPUT1_INTR16 (16+APC_INPUT1) #define APC_INPUT1_INTR17 (17+APC_INPUT1) #define APC_INPUT1_INTR18 (18+APC_INPUT1) #define APC_INPUT1_INTR19 (19+APC_INPUT1) #define APC_INPUT2_INTR0 (0+ APC_INPUT2) #define APC_INPUT2_INTR1 (1+ APC_INPUT2) #define APC_INPUT2_INTR2 (2+ APC_INPUT2) #define APC_INPUT2_INTR3 (3+ APC_INPUT2) #define APC_INPUT2_INTR4 (4+ APC_INPUT2) #define APC_INPUT2_INTR5 (5+ APC_INPUT2) #define APC_INPUT2_INTR6 (6+ APC_INPUT2) #define APC_INPUT2_INTR7 (7+ APC_INPUT2) #define APC_INPUT2_INTR8 (8+ APC_INPUT2) #define APC_INPUT2_INTR9 (9+ APC_INPUT2) #define APC_INPUT2_INTR10 (10+APC_INPUT2) #define APC_INPUT2_INTR11 (11+APC_INPUT2) #define APC_INPUT2_INTR12 (12+APC_INPUT2) #define APC_INPUT2_INTR13 (13+APC_INPUT2) #define APC_INPUT2_INTR14 (14+APC_INPUT2) #define APC_INPUT2_INTR15 (15+APC_INPUT2) #define APC_INPUT2_INTR16 (16+APC_INPUT2) #define APC_INPUT2_INTR17 (17+APC_INPUT2) #define APC_INPUT2_INTR18 (18+APC_INPUT2) #define APC_INPUT2_INTR19 (19+APC_INPUT2) #define APC_INPUT3_INTR0 (0+ APC_INPUT3) #define APC_INPUT3_INTR1 (1+ APC_INPUT3) #define APC_INPUT3_INTR2 (2+ APC_INPUT3) #define APC_INPUT3_INTR3 (3+ APC_INPUT3) #define APC_INPUT3_INTR4 (4+ APC_INPUT3) #define APC_INPUT3_INTR5 (5+ APC_INPUT3) #define APC_INPUT3_INTR6 (6+ APC_INPUT3) #define APC_INPUT3_INTR7 (7+ APC_INPUT3) #define APC_INPUT3_INTR8 (8+ APC_INPUT3) #define APC_INPUT3_INTR9 (9+ APC_INPUT3) #define APC_INPUT3_INTR10 (10+APC_INPUT3) #define APC_INPUT3_INTR11 (11+APC_INPUT3) #define APC_INPUT3_INTR12 (12+APC_INPUT3) #define APC_INPUT3_INTR13 (13+APC_INPUT3) #define APC_INPUT3_INTR14 (14+APC_INPUT3) #define APC_INPUT3_INTR15 (15+APC_INPUT3) #define APC_INPUT3_INTR16 (16+APC_INPUT3) #define APC_INPUT3_INTR17 (17+APC_INPUT3) #define APC_INPUT3_INTR18 (18+APC_INPUT3) #define APC_INPUT3_INTR19 (19+APC_INPUT3) #define APC_INPUT4_INTR0 (0+ APC_INPUT4) #define APC_INPUT4_INTR1 (1+ APC_INPUT4) #define APC_INPUT4_INTR2 (2+ APC_INPUT4) #define APC_INPUT4_INTR3 (3+ APC_INPUT4) #define APC_INPUT4_INTR4 (4+ APC_INPUT4) #define APC_INPUT4_INTR5 (5+ APC_INPUT4) #define APC_INPUT4_INTR6 (6+ APC_INPUT4) #define APC_INPUT4_INTR7 (7+ APC_INPUT4) #define APC_INPUT4_INTR8 (8+ APC_INPUT4) #define APC_INPUT4_INTR9 (9+ APC_INPUT4) #define APC_INPUT4_INTR10 (10+APC_INPUT4) #define APC_INPUT4_INTR11 (11+APC_INPUT4) #define APC_INPUT4_INTR12 (12+APC_INPUT4) #define APC_INPUT4_INTR13 (13+APC_INPUT4) #define APC_INPUT4_INTR14 (14+APC_INPUT4) #define APC_INPUT4_INTR15 (15+APC_INPUT4) #define APC_INPUT4_INTR16 (16+APC_INPUT4) #define APC_INPUT4_INTR17 (17+APC_INPUT4) #define APC_INPUT4_INTR18 (18+APC_INPUT4) #define APC_INPUT4_INTR19 (19+APC_INPUT4) #define APC_INPUT5_INTR0 (0+ APC_INPUT5) #define APC_INPUT5_INTR1 (1+ APC_INPUT5) #define APC_INPUT5_INTR2 (2+ APC_INPUT5) #define APC_INPUT5_INTR3 (3+ APC_INPUT5) #define APC_INPUT5_INTR4 (4+ APC_INPUT5) #define APC_INPUT5_INTR5 (5+ APC_INPUT5) #define APC_INPUT5_INTR6 (6+ APC_INPUT5) #define APC_INPUT5_INTR7 (7+ APC_INPUT5) #define APC_INPUT5_INTR8 (8+ APC_INPUT5) #define APC_INPUT5_INTR9 (9+ APC_INPUT5) #define APC_INPUT5_INTR10 (10+APC_INPUT5) #define APC_INPUT5_INTR11 (11+APC_INPUT5) #define APC_INPUT5_INTR12 (12+APC_INPUT5) #define APC_INPUT5_INTR13 (13+APC_INPUT5) #define APC_INPUT5_INTR14 (14+APC_INPUT5) #define APC_INPUT5_INTR15 (15+APC_INPUT5) #define APC_INPUT5_INTR16 (16+APC_INPUT5) #define APC_INPUT5_INTR17 (17+APC_INPUT5) #define APC_INPUT5_INTR18 (18+APC_INPUT5) #define APC_INPUT5_INTR19 (19+APC_INPUT5) #define APRFM_SYSC_CTC8_INTR0 570 #define APRFM_SYSC_CTC9_INTR0 571 #define APRFM_SYSC_CTC10_INTR0 572 #define APRFM_SYSC_CTC11_INTR0 573 #define APRFM_SYSC_CTC12_INTR0 574 #define APRFM_SYSC_CTC13_INTR0 575 #define APRFM_SYSC_CTC14_INTR0 576 #define APRFM_SYSC_CTC15_INTR0 577 //define ARM INTERRUPT NUM #define PETRFM2SYS_INTR0 (175+280) #define PETRFM2SYS_INTR1 (175+281) #define PETRFM2SYS_INTR2 (175+282) #define PETRFM2SYS_INTR3 (175+283) #define PETRFM2SYS_INTR4 (175+284) #define PETRFM2SYS_INTR5 (175+285) #define PETRFM2SYS_INTR6 (175+286) #define PETRFM2SYS_INTR7 (175+287) #define PETRFM2SYS_INTR8 (175+288) #define PETRFM2SYS_INTR9 (175+289) #define PETRFM2SYS_INTR10 (175+290) #define PETRFM2SYS_INTR11 (175+291) #define PETRFM2SYS_INTR12 (175+292) #define PETRFM2SYS_INTR13 (175+293) #define PETRFM2SYS_INTR14 (175+294) #define PETRFM2SYS_INTR15 (175+295) #define PETRFM2SYS_INTR16 (175+296) #define PETRFM2SYS_INTR17 (175+297) #define PETRFM2SYS_INTR18 (175+298) #define PETRFM2SYS_INTR19 (175+299) #define JECS_RFM_OUT_INTR0 (175+300) #define JECS_RFM_OUT_INTR1 (175+301) #define JECS_RFM_OUT_INTR2 (175+302) #define JECS_RFM_OUT_INTR3 (175+303) #define JECS_RFM_OUT_INTR4 (175+304) #define JECS_RFM_OUT_INTR5 (175+305) #define JECS_RFM_OUT_INTR6 (175+306) #define JECS_RFM_OUT_INTR7 (175+307) #define JECS_RFM_OUT_INTR8 (175+308) #define JECS_RFM_OUT_INTR9 (175+309) #define JECS_RFM_OUT_INTR10 (175+310) #define JECS_RFM_OUT_INTR11 (175+311) #define JECS_RFM_OUT_INTR12 (175+312) #define JECS_RFM_OUT_INTR13 (175+313) #define JECS_RFM_OUT_INTR14 (175+314) #define JECS_RFM_OUT_INTR15 (175+315) #define JECS_RFM_OUT_INTR16 (175+316) #define JECS_RFM_OUT_INTR17 (175+317) #define JECS_RFM_OUT_INTR18 (175+318) #define JECS_RFM_OUT_INTR19 (175+319) #define RFC_INTR0 (175+320) #define RFC_INTR1 (175+321) #define RFC_INTR2 (175+322) #define RFCSU_RX_INTR (175+323) #define RFCSU_TX_INTR (175+324) #define JESD_RX0_SBU0_TMR_INTR0 (175+162+325-162) #define JESD_RX0_SBU0_TMR_INTR1 (175+163+325-162) #define JESD_RX0_SBU0_TMR_INTR2 (175+164+325-162) #define JESD_RX0_SBU0_TMR_INTR3 (175+165+325-162) #define JESD_RX0_SBU0_TMR_INTR4 (175+166+325-162) #define JESD_RX0_SBU0_TMR_INTR5 (175+167+325-162) #define JESD_RX0_SBU0_TMR_INTR6 (175+168+325-162) #define JESD_RX0_SBU0_TMR_INTR7 (175+169+325-162) #define JESD_RX0_SBU0_TMR_INTR8 (175+170+325-162) #define JESD_RX0_SBU0_TMR_INTR9 (175+171+325-162) #define JESD_RX0_SBU0_TMR_INTR10 (175+172+325-162) #define JESD_RX0_SBU0_TMR_INTR11 (175+173+325-162) //#define JESD_RX0_SBU1_TMR_INTR0 (175+162+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR1 (175+163+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR2 (175+164+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR3 (175+165+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR4 (175+166+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR5 (175+167+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR6 (175+168+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR7 (175+169+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR8 (175+170+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR9 (175+171+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR10 (175+172+424-162)tie 0 //#define JESD_RX0_SBU1_TMR_INTR11 (175+173+424-162)tie 0 #define JESD_RX1_SBU0_TMR_INTR0 (175+162+436-162) #define JESD_RX1_SBU0_TMR_INTR1 (175+163+436-162) #define JESD_RX1_SBU0_TMR_INTR2 (175+164+436-162) #define JESD_RX1_SBU0_TMR_INTR3 (175+165+436-162) #define JESD_RX1_SBU0_TMR_INTR4 (175+166+436-162) #define JESD_RX1_SBU0_TMR_INTR5 (175+167+436-162) #define JESD_RX1_SBU0_TMR_INTR6 (175+168+436-162) #define JESD_RX1_SBU0_TMR_INTR7 (175+169+436-162) #define JESD_RX1_SBU0_TMR_INTR8 (175+170+436-162) #define JESD_RX1_SBU0_TMR_INTR9 (175+171+436-162) #define JESD_RX1_SBU0_TMR_INTR10 (175+172+436-162) #define JESD_RX1_SBU0_TMR_INTR11 (175+173+436-162) //#define JESD_RX1_SBU1_TMR_INTR0 (175+162+448-162) //#define JESD_RX1_SBU1_TMR_INTR1 (175+163+448-162) //#define JESD_RX1_SBU1_TMR_INTR2 (175+164+448-162) //#define JESD_RX1_SBU1_TMR_INTR3 (175+165+448-162) //#define JESD_RX1_SBU1_TMR_INTR4 (175+166+448-162) //#define JESD_RX1_SBU1_TMR_INTR5 (175+167+448-162) //#define JESD_RX1_SBU1_TMR_INTR6 (175+168+448-162) //#define JESD_RX1_SBU1_TMR_INTR7 (175+169+448-162) //#define JESD_RX1_SBU1_TMR_INTR8 (175+170+448-162) //#define JESD_RX1_SBU1_TMR_INTR9 (175+171+448-162) //#define JESD_RX1_SBU1_TMR_INTR10 (175+172+448-162) //#define JESD_RX1_SBU1_TMR_INTR11 (175+173+448-162) #define SLAVE_INTERRUPT_RX0 (175+337) #define SLAVE_INTERRUPT_RX0_SUB1 (175+338) #define SLAVE_INTERRUPT_RX1 (175+339) #define SLAVE_INTERRUPT_RX1_SUB1 (175+340) #define SLAVE_INTERRUPT_TX (175+341) #define SLAVE_INTERRUPT_TX_SUB1 (175+342) #define JECS_CTC_INTR0 (175+343) #define JECS_CTC_INTR1 (175+344) #define PET_CTC_INTR0 (175+345) #define PET_CTC_INTR1 (175+346) #define EIP2_RING2_INT (175+347) #define EIP2_RING3_INT (175+348) #define RFC_DMA_INTR (175+349) #define JESDA_CSU_INTR (175+350) #define JESDA_CSU_TX_INTR (175+351) #define JECS_CSU_INTR (175+352) #define JESDB_CSU_TX_INTR (175+353) #define ECPRI_SUB_INTR0 (175+360) #define ECPRI_SUB_INTR1 (175+361) #define ECPRI_SUB_INTR2 (175+362) #define ECPRI_SUB_INTR3 (175+363) #define ECPRI_SUB_INTR4 (175+364) #define ECPRI_SUB_INTR5 (175+365) #define ECPRI_SUB_INTR6 (175+366) #define ECPRI_SUB_INTR7 (175+367) #define ECPRI_SUB_INTR8 (175+368) #define ECPRI_SUB_INTR9 (175+369) #define ECPRI_SUB_INTR10 (175+370) #define ECPRI_SUB_INTR11 (175+371) #define ECPRI_SUB_INTR12 (175+372) #define ECPRI_SUB_INTR13 (175+373) #define ECPRI_SUB_INTR14 (175+374) #define ECPRI_SUB_INTR15 (175+375) #define ECPRI_SUB_INTR16 (175+376) #define ECPRI_SUB_INTR17 (175+377) #define ECPRI_SUB_INTR18 (175+378) #define ECPRI_SUB_INTR19 (175+379) #define ECPRI_SUB_INTR20 (175+380) #define ECPRI_SUB_INTR21 (175+381) #define ECPRI_SUB_INTR22 (175+382) #define ECPRI_SUB_INTR23 (175+383) #define ECPRI_SUB_INTR24 (175+384) #define ECPRI_SUB_INTR25 (175+385) #define ECPRI_SUB_INTR26 (175+386) #define ECPRI_SUB_INTR27 (175+387) #define ECPRI_SUB_INTR28 (175+388) #define ECPRI_SUB_INTR29 (175+389) #define ECPRI_SUB_INTR30 (175+390) #define ECPRI_SUB_INTR31 (175+391) #define CPRI_SUB_INTR0 (175+392) #define CPRI_SUB_INTR1 (175+393) #define STC_INTR0 (175+394) #define STC_INTR1 (175+395) #define STC_INTR2 (175+396) #define STC_INTR3 (175+397) #define STC_INTR4 (175+398) #define STC_INTR5 (175+399) #define STC_INTR6 (175+400) #define STC_INTR7 (175+401) #define STC_INTR8 (175+402) #define STC_INTR9 (175+403) #define STC_INTR10 (175+404) #define CPRI_TMR_INTR0 (175+405) #define CPRI_TMR_INTR1 (175+406) #define CPRI_TMR_INTR2 (175+407) #define CPRI_TMR_INTR3 (175+408) #define CPRI_TMR_INTR4 (175+409) #define CPRI_TMR_INTR5 (175+410) #define CPRI_TMR_INTR6 (175+411) #define CPRI_TMR_INTR7 (175+412) #define CPRI_TMR_INTR8 (175+413) #define CPRI_TMR_INTR9 (175+414) #define CPRI_TMR_INTR10 (175+415) #define CPRI_TMR_INTR11 (175+416) #define APC3OUT_INTR0 (175+260) #define APC3OUT_INTR1 (175+261) #define APC3OUT_INTR2 (175+262) #define APC3OUT_INTR3 (175+263) #define APC3OUT_INTR4 (175+264) #define APC3OUT_INTR5 (175+265) #define APC3OUT_INTR6 (175+266) #define APC3OUT_INTR7 (175+267) #define APC3OUT_INTR8 (175+268) #define APC3OUT_INTR9 (175+269) #define APC3OUT_INTR10 (175+270) #define APC3OUT_INTR11 (175+271) #define APC3OUT_INTR12 (175+272) #define APC3OUT_INTR13 (175+273) #define APC3OUT_INTR14 (175+274) #define APC3OUT_INTR15 (175+275) #define APC3OUT_INTR16 (175+276) #define APC3OUT_INTR17 (175+277) #define APC3OUT_INTR18 (175+278) #define APC3OUT_INTR19 (175+279) #define APC2OUT_INTR0 (175+240) #define APC2OUT_INTR1 (175+241) #define APC2OUT_INTR2 (175+242) #define APC2OUT_INTR3 (175+243) #define APC2OUT_INTR4 (175+244) #define APC2OUT_INTR5 (175+245) #define APC2OUT_INTR6 (175+246) #define APC2OUT_INTR7 (175+247) #define APC2OUT_INTR8 (175+248) #define APC2OUT_INTR9 (175+249) #define APC2OUT_INTR10 (175+250) #define APC2OUT_INTR11 (175+251) #define APC2OUT_INTR12 (175+252) #define APC2OUT_INTR13 (175+253) #define APC2OUT_INTR14 (175+254) #define APC2OUT_INTR15 (175+255) #define APC2OUT_INTR16 (175+256) #define APC2OUT_INTR17 (175+257) #define APC2OUT_INTR18 (175+258) #define APC2OUT_INTR19 (175+259) #define APC1OUT_INTR0 (175+220) #define APC1OUT_INTR1 (175+221) #define APC1OUT_INTR2 (175+222) #define APC1OUT_INTR3 (175+223) #define APC1OUT_INTR4 (175+224) #define APC1OUT_INTR5 (175+225) #define APC1OUT_INTR6 (175+226) #define APC1OUT_INTR7 (175+227) #define APC1OUT_INTR8 (175+228) #define APC1OUT_INTR9 (175+229) #define APC1OUT_INTR10 (175+230) #define APC1OUT_INTR11 (175+231) #define APC1OUT_INTR12 (175+232) #define APC1OUT_INTR13 (175+233) #define APC1OUT_INTR14 (175+234) #define APC1OUT_INTR15 (175+235) #define APC1OUT_INTR16 (175+236) #define APC1OUT_INTR17 (175+237) #define APC1OUT_INTR18 (175+238) #define APC1OUT_INTR19 (175+239) #define APC0OUT_INTR0 (175+200) #define APC0OUT_INTR1 (175+201) #define APC0OUT_INTR2 (175+202) #define APC0OUT_INTR3 (175+203) #define APC0OUT_INTR4 (175+204) #define APC0OUT_INTR5 (175+205) #define APC0OUT_INTR6 (175+206) #define APC0OUT_INTR7 (175+207) #define APC0OUT_INTR8 (175+208) #define APC0OUT_INTR9 (175+209) #define APC0OUT_INTR10 (175+210) #define APC0OUT_INTR11 (175+211) #define APC0OUT_INTR12 (175+212) #define APC0OUT_INTR13 (175+213) #define APC0OUT_INTR14 (175+214) #define APC0OUT_INTR15 (175+215) #define APC0OUT_INTR16 (175+216) #define APC0OUT_INTR17 (175+217) #define APC0OUT_INTR18 (175+218) #define APC0OUT_INTR19 (175+219) #define UART3_INTR (175+197) #define UART2_INTR (175+196) #define TIMER27_INTR (175+195) #define TIMER26_INTR (175+194) #define TIMER25_INTR (175+193) #define TIMER24_INTR (175+192) #define TIMER23_INTR (175+191) #define TIMER22_INTR (175+190) #define TIMER21_INTR (175+189) #define TIMER20_INTR (175+188) #define TIMER17_INTR (175+187) #define TIMER16_INTR (175+186) #define TIMER15_INTR (175+185) #define TIMER14_INTR (175+184) #define TIMER13_INTR (175+183) #define TIMER12_INTR (175+182) #define TIMER11_INTR (175+181) #define TIMER10_INTR (175+180) #define SPI3_INTR (175+179) #define SPI2_INTR (175+178) //175+174 175+177 tie 0 #define JESD_TX0_SBU0_TMR_INTR0 (175+162) #define JESD_TX0_SBU0_TMR_INTR1 (175+163) #define JESD_TX0_SBU0_TMR_INTR2 (175+164) #define JESD_TX0_SBU0_TMR_INTR3 (175+165) #define JESD_TX0_SBU0_TMR_INTR4 (175+166) #define JESD_TX0_SBU0_TMR_INTR5 (175+167) #define JESD_TX0_SBU0_TMR_INTR6 (175+168) #define JESD_TX0_SBU0_TMR_INTR7 (175+169) #define JESD_TX0_SBU0_TMR_INTR8 (175+170) #define JESD_TX0_SBU0_TMR_INTR9 (175+171) #define JESD_TX0_SBU0_TMR_INTR10 (175+172) #define JESD_TX0_SBU0_TMR_INTR11 (175+173) #define JESD_TX_SBU1_TMR_INTR0 (175+174) #define JESD_TX_SBU1_TMR_INTR1 (175+175) #define JESD_TX_SBU1_TMR_INTR2 (175+176) #define JESD_TX_SBU1_TMR_INTR3 (175+177) #define JESD_TX_SBU1_TMR_INTR4 (175+198) #define JESD_TX_SBU1_TMR_INTR5 (175+199) #define JESD_TX_SBU1_TMR_INTR6 (175+354) #define JESD_TX_SBU1_TMR_INTR7 (175+355) #define JESD_TX_SBU1_TMR_INTR8 (175+356) #define JESD_TX_SBU1_TMR_INTR9 (175+357) #define JESD_TX_SBU1_TMR_INTR10 (175+358) #define JESD_TX_SBU1_TMR_INTR11 (175+359) #define JESD_TX1_SBU0_TMR_INTR0 (175+371) #define JESD_TX1_SBU0_TMR_INTR1 (175+372) #define JESD_TX1_SBU0_TMR_INTR2 (175+373) #define JESD_TX1_SBU0_TMR_INTR3 (175+374) #define JESD_TX1_SBU0_TMR_INTR4 (175+375) #define JESD_TX1_SBU0_TMR_INTR5 (175+376) #define JESD_TX1_SBU0_TMR_INTR6 (175+377) #define JESD_TX1_SBU0_TMR_INTR7 (175+378) #define JESD_TX1_SBU0_TMR_INTR8 (175+379) #define JESD_TX1_SBU0_TMR_INTR9 (175+380) #define JESD_TX1_SBU0_TMR_INTR10 (175+381) #define JESD_TX1_SBU0_TMR_INTR11 (175+382) #define MBX1_LPRI_INTR24 (175+164-16) #define MBX1_LPRI_INTR25 (175+165-16) #define MBX1_LPRI_INTR26 (175+166-16) #define MBX1_LPRI_INTR27 (175+167-16) #define MBX1_LPRI_INTR28 (175+168-16) #define MBX1_LPRI_INTR29 (175+169-16) #define MBX1_LPRI_INTR30 (175+170-16) #define MBX1_LPRI_INTR31 (175+171-16) #define MBX1_LPRI_INTR32 (175+172-16) #define MBX1_LPRI_INTR33 (175+173-16) #define MBX1_LPRI_INTR34 (175+174-16) #define MBX1_LPRI_INTR35 (175+175-16) #define MBX1_LPRI_INTR36 (175+176-16) #define MBX1_LPRI_INTR37 (175+177-16) #define MBX1_HPRI_INTR24 (175+146-12) #define MBX1_HPRI_INTR25 (175+147-12) #define MBX1_HPRI_INTR26 (175+148-12) #define MBX1_HPRI_INTR27 (175+149-12) #define MBX1_HPRI_INTR28 (175+150-12) #define MBX1_HPRI_INTR29 (175+151-12) #define MBX1_HPRI_INTR30 (175+152-12) #define MBX1_HPRI_INTR31 (175+153-12) #define MBX1_HPRI_INTR32 (175+154-12) #define MBX1_HPRI_INTR33 (175+155-12) #define MBX1_HPRI_INTR34 (175+156-12) #define MBX1_HPRI_INTR35 (175+157-12) #define MBX1_HPRI_INTR36 (175+158-12) #define MBX1_HPRI_INTR37 (175+159-12) #define MBX0_LPRI_INTR24 (175+128-8) #define MBX0_LPRI_INTR25 (175+129-8) #define MBX0_LPRI_INTR26 (175+130-8) #define MBX0_LPRI_INTR27 (175+131-8) #define MBX0_LPRI_INTR28 (175+132-8) #define MBX0_LPRI_INTR29 (175+133-8) #define MBX0_LPRI_INTR30 (175+134-8) #define MBX0_LPRI_INTR31 (175+135-8) #define MBX0_LPRI_INTR32 (175+136-8) #define MBX0_LPRI_INTR33 (175+137-8) #define MBX0_LPRI_INTR34 (175+138-8) #define MBX0_LPRI_INTR35 (175+139-8) #define MBX0_LPRI_INTR36 (175+140-8) #define MBX0_LPRI_INTR37 (175+141-8) #define MBX0_HPRI_INTR24 (175+110-4) #define MBX0_HPRI_INTR25 (175+111-4) #define MBX0_HPRI_INTR26 (175+112-4) #define MBX0_HPRI_INTR27 (175+113-4) #define MBX0_HPRI_INTR28 (175+114-4) #define MBX0_HPRI_INTR29 (175+115-4) #define MBX0_HPRI_INTR30 (175+116-4) #define MBX0_HPRI_INTR31 (175+117-4) #define MBX0_HPRI_INTR32 (175+118-4) #define MBX0_HPRI_INTR33 (175+119-4) #define MBX0_HPRI_INTR34 (175+120-4) #define MBX0_HPRI_INTR35 (175+121-4) #define MBX0_HPRI_INTR36 (175+122-4) #define MBX0_HPRI_INTR37 (175+123-4) #define GPIO1_INTR0 (175+74) #define GPIO1_INTR1 (175+75) #define GPIO1_INTR2 (175+76) #define GPIO1_INTR3 (175+77) #define GPIO1_INTR4 (175+78) #define GPIO1_INTR5 (175+79) #define GPIO1_INTR6 (175+80) #define GPIO1_INTR7 (175+81) #define GPIO1_INTR8 (175+82) #define GPIO1_INTR9 (175+83) #define GPIO1_INTR10 (175+84) #define GPIO1_INTR11 (175+85) #define GPIO1_INTR12 (175+86) #define GPIO1_INTR13 (175+87) #define GPIO1_INTR14 (175+88) #define GPIO1_INTR15 (175+89) #define GPIO1_INTR16 (175+90) #define GPIO1_INTR17 (175+91) #define GPIO1_INTR18 (175+92) #define GPIO1_INTR19 (175+93) #define GPIO1_INTR20 (175+94) #define GPIO1_INTR21 (175+95) #define GPIO1_INTR22 (175+96) #define GPIO1_INTR23 (175+97) #define GPIO1_INTR24 (175+98) #define GPIO1_INTR25 (175+99) #define GPIO1_INTR26 (175+100) #define GPIO1_INTR27 (175+101) #define GPIO1_INTR28 (175+102) #define GPIO1_INTR29 (175+103) #define GPIO1_INTR30 (175+104) #define GPIO1_INTR31 (175+105) #define DMAS1_INTR (175+73) #define DPLL_LOCK_INTR (175+72) #define CPSM_FULL7_INTR (175+71) #define CPSM_FULL6_INTR (175+70) #define CPSM_FULL5_INTR (175+69) #define CPSM_FULL4_INTR (175+68) #define CPSM_FULL3_INTR (175+67) #define CPSM_FULL2_INTR (175+66) #define CPSM_FULL1_INTR (175+65) #define CPSM_FULL0_INTR (175+64) #define CPSM_EMPTY7_INTR (175+63) #define CPSM_EMPTY6_INTR (175+62) #define CPSM_EMPTY5_INTR (175+61) #define CPSM_EMPTY4_INTR (175+60) #define CPSM_EMPTY3_INTR (175+59) #define CPSM_EMPTY2_INTR (175+58) #define CPSM_EMPTY1_INTR (175+57) #define CPSM_EMPTY0_INTR (175+56) #define JECSSM_FULL7_INTR (175+54+1) #define JECSSM_FULL6_INTR (175+53+1) #define JECSSM_FULL5_INTR (175+52+1) #define JECSSM_FULL4_INTR (175+51+1) #define JECSSM_FULL3_INTR (175+50+1) #define JECSSM_FULL2_INTR (175+49+1) #define JECSSM_FULL1_INTR (175+48+1) #define JECSSM_FULL0_INTR (175+47+1) #define JECSSM_EMPTY7_INTR (175+46+1) #define JECSSM_EMPTY6_INTR (175+45+1) #define JECSSM_EMPTY5_INTR (175+44+1) #define JECSSM_EMPTY4_INTR (175+43+1) #define JECSSM_EMPTY3_INTR (175+42+1) #define JECSSM_EMPTY2_INTR (175+41+1) #define JECSSM_EMPTY1_INTR (175+40+1) #define JECSSM_EMPTY0_INTR (175+39+1) #define PETSM_FULL7_INTR (175+38+1) #define PETSM_FULL6_INTR (175+37+1) #define PETSM_FULL5_INTR (175+36+1) #define PETSM_FULL4_INTR (175+35+1) #define PETSM_FULL3_INTR (175+34+1) #define PETSM_FULL2_INTR (175+33+1) #define PETSM_FULL1_INTR (175+32+1) #define PETSM_FULL0_INTR (175+31+1) #define PETSM_EMPTY7_INTR (175+30+1) #define PETSM_EMPTY6_INTR (175+29+1) #define PETSM_EMPTY5_INTR (175+28+1) #define PETSM_EMPTY4_INTR (175+27+1) #define PETSM_EMPTY3_INTR (175+26+1) #define PETSM_EMPTY2_INTR (175+25+1) #define PETSM_EMPTY1_INTR (175+24+1) #define PETSM_EMPTY0_INTR (175+23+1) #define ES_ETHPLL_LOCK_INTR (175+23) #define EIP2_RING0_INT (175+21) #define EIP2_RING1_INT (175+22) #define PET_TMAC_INTR (175+20) #define PET_PCIE_INTR (175+19) #define EIP2_GLOBLE_INT (175+18) #define SRIO1_RAB_INTR (175+17) #define SRIO0_RAB_INTR (175+16) #define JSSM_FULL7_INTR (175+15) #define JSSM_FULL6_INTR (175+14) #define JSSM_FULL5_INTR (175+13) #define JSSM_FULL4_INTR (175+12) #define JSSM_FULL3_INTR (175+11) #define JSSM_FULL2_INTR (175+10) #define JSSM_FULL1_INTR (175+9) #define JSSM_FULL0_INTR (175+8) #define JSSM_EMPTY7_INTR (175+7) #define JSSM_EMPTY6_INTR (175+6) #define JSSM_EMPTY5_INTR (175+5) #define JSSM_EMPTY4_INTR (175+4) #define JSSM_EMPTY3_INTR (175+3) #define JSSM_EMPTY2_INTR (175+2) #define JSSM_EMPTY1_INTR (175+1) #define JSSM_EMPTY0_INTR (175+0) #define TRNG_INTR 174 #define SPACC0_INTR 173 #define PKA_INTR 172 #define SYSC_CTC9_INTR1 171 #define SYSC_CTC9_INTR0 170 #define SYSC_CTC8_INTR1 169 #define SYSC_CTC8_INTR0 168 #define SYSC_CTC7_INTR1 167 #define SYSC_CTC7_INTR0 166 #define SYSC_CTC6_INTR1 165 #define SYSC_CTC6_INTR0 164 #define SYSC_CTC5_INTR1 163 #define SYSC_CTC5_INTR0 162 #define SYSC_CTC4_INTR1 161 #define SYSC_CTC4_INTR0 160 #define SYSC_CTC3_INTR1 159 #define SYSC_CTC3_INTR0 158 #define SYSC_CTC2_INTR1 157 #define SYSC_CTC2_INTR0 156 #define SYSC_CTC1_INTR1 155 #define SYSC_CTC1_INTR0 154 #define SYSC_CTC0_INTR1 153 #define SYSC_CTC0_INTR0 152 #define SYSCTRL_INTR 151 #define SDIOH_INTR 150 #define PVT_INTR 149 #define SMMU_S_INTR 148 #define SMMU_NS_INTR 147 #define GICECCFATAL_INTR 146 #define GICAXIERR_INTR 145 #define CCINERR_INTR 144 //112-143 tie0 #define WDT1_INTR 111 #define WDT0_INTR 110 #define USB_INTR 109 #define UART1_INTR 108 #define UART0_INTR 107 #define TIMER07_INTR 106 #define TIMER06_INTR 105 #define TIMER05_INTR 104 #define TIMER04_INTR 103 #define TIMER03_INTR 102 #define TIMER02_INTR 101 #define TIMER01_INTR 100 #define TIMER00_INTR 99 #define SPI1_INTR 98 #define SPI0_INTR 97 #define RTC_INTR 96 #define I2C1_INTR 95 #define I2C0_INTR 94 #define GPIO0_INTR0 62 #define GPIO0_INTR1 63 #define GPIO0_INTR2 64 #define GPIO0_INTR3 65 #define GPIO0_INTR4 66 #define GPIO0_INTR5 67 #define GPIO0_INTR6 68 #define GPIO0_INTR7 69 #define GPIO0_INTR8 70 #define GPIO0_INTR9 71 #define GPIO0_INTR10 72 #define GPIO0_INTR11 73 #define GPIO0_INTR12 74 #define GPIO0_INTR13 75 #define GPIO0_INTR14 76 #define GPIO0_INTR15 77 #define GPIO0_INTR16 78 #define GPIO0_INTR17 79 #define GPIO0_INTR18 80 #define GPIO0_INTR19 81 #define GPIO0_INTR20 82 #define GPIO0_INTR21 83 #define GPIO0_INTR22 84 #define GPIO0_INTR23 85 #define GPIO0_INTR24 86 #define GPIO0_INTR25 87 #define GPIO0_INTR26 88 #define GPIO0_INTR27 89 #define GPIO0_INTR28 90 #define GPIO0_INTR29 91 #define GPIO0_INTR30 92 #define GPIO0_INTR31 93 //53 - 61 tie 0 #define EIP0_GLOBLE_INT 43 #define EIP0_RING0_INT 44 #define EIP0_RING1_INT 45 #define EIP0_RING2_INT 46 #define EIP0_RING3_INT 47 #define EIP1_GLOBLE_INT 48 #define EIP1_RING0_INT 49 #define EIP1_RING1_INT 50 #define EIP1_RING2_INT 51 #define EIP1_RING3_INT 52 //#define SPACC1_INTR 38 TIE0 //#define SPACC2_INTR 39 TIE0 //#define SPACC3_INTR 40 TIE0 #define A72NEXTERR_INTR_1 42 #define A72NINTERR_INTR_1 41 #define APCSU_INTR0 30 #define APCSU_INTR1 31 #define APCSU_INTR2 32 #define APCSU_INTR3 33 #define APCSU_INTR4 34 #define APCSU_INTR5 35 #define APCSU_INTR6 36 #define APCSU_INTR7 37 #define GMAC1SDB_INTR 29 #define GMAC1PMT_INTR 28 #define GMAC1LPI_INTR 27 #define GMAC0SDB_INTR 26 #define GMAC0PMT_INTR 25 #define GMAC0LPI_INTR 24 #define EFUSE_INTR 23 #define DDRPHY_INTR 22 #define DDRC_INTR 21 #define DMAS0_INTR 20 //#define CSUDMA_INTR 19 tie 0 #define CRG_INTR 18 #define APSM1_FULL7_INTR 17 #define APSM1_FULL6_INTR 16 #define APSM1_FULL5_INTR 15 #define APSM1_FULL4_INTR 14 #define APSM1_FULL3_INTR 13 #define APSM1_FULL2_INTR 12 #define APSM1_FULL1_INTR 11 #define APSM1_FULL0_INTR 10 #define APSM1_EMPTY7_INTR 9 #define APSM1_EMPTY6_INTR 8 #define APSM1_EMPTY5_INTR 7 #define APSM1_EMPTY4_INTR 6 #define APSM1_EMPTY3_INTR 5 #define APSM1_EMPTY2_INTR 4 #define APSM1_EMPTY1_INTR 3 #define APSM1_EMPTY0_INTR 2 #define A72NEXTERR_INTR 1 #define A72NINTERR_INTR 0 #endif /* End of __IO_UCP_H */