#ifndef COMMON_INC_PHY_PARA_H_ #define COMMON_INC_PHY_PARA_H_ #include "ucp_drv_common.h" #define PHY_SCS_MAX_NUM 4 #define SFN_PERIOD 10000 // 10ms #define SLOT_SYMBOL_NUM 14 #define SPU_DRV_SM_ADDR (0x0A4F2000) // (0x0A4D7000) // #define PROTO_SEL_ADDR (SPU_DRV_SM_ADDR+0x0) #define PROTO_OPT_ADDR (SPU_DRV_SM_ADDR+0x4) #define PHY_PARA_ADDR (SPU_DRV_SM_ADDR+0x8) #define PHY_CELL_ADDR (SPU_DRV_SM_ADDR+0x100) #define ORX_ADJUST_FLAG_ADDR (SPU_DRV_SM_ADDR+0x140) #define ORX_ADJUST_VAL_ADDR (SPU_DRV_SM_ADDR+0x144) #define STC_TOD_INT_ADDR (SPU_DRV_SM_ADDR+0x200) #define STC_RT_ADDR (SPU_DRV_SM_ADDR+0x204) #define STC_CTW_EN_ADDR (SPU_DRV_SM_ADDR+0x208) #define CPRI_DELAY_ADDR (SPU_DRV_SM_ADDR+0x210) #define CPRI_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x214) #define CPRI_TDD_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x218) #define CTC_INT_TYPE_ADDR (SPU_DRV_SM_ADDR+0x21C) #define ARM_SFN_VALID_ADDR (SPU_DRV_SM_ADDR+0x220) // 0xAA not valid, 0x55 valid #define ARM_SFN_NUM_ADDR (SPU_DRV_SM_ADDR+0x224) #define ARM_SFN_FLIP_ADDR (SPU_DRV_SM_ADDR+0x228) #define ARM_LOCK_FLAG_ADDR (SPU_DRV_SM_ADDR+0x22C) #define ARM_SFN_VALID_FLAG (0x55) #define ARM_SFN_NOTVALID_FLAG (0xAA) #define CSU_STOP_CMD_ADDR (SPU_DRV_SM_ADDR+0x230) #define CSU_UL_HEADER_DATA_OFFSET (SPU_DRV_SM_ADDR+0x234) // ul, the interval of frame header and frame data, ns as unit #define CSU_RX_TD_SAMPLE (SPU_DRV_SM_ADDR+0x238) #define CSU_TX_ADVANCE_SAMPLE (SPU_DRV_SM_ADDR+0x23C) #define SERDES_INIT_FLAG_ADDR (SPU_DRV_SM_ADDR+0x240) // cpri or jesd clk init finished #define STC_ONEPPS_OUT_ADDR (SPU_DRV_SM_ADDR+0x244) #define JESD_RX_CH_PARA (SPU_DRV_SM_ADDR+0x248) #define JESD_RX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x24C) #define JESD_ORX_CH_PARA (SPU_DRV_SM_ADDR+0x250) #define JESD_ORX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x254) #define JESD_TX_CH_PARA (SPU_DRV_SM_ADDR+0x258) #define JESD_TX_SAMPLE_RATE (SPU_DRV_SM_ADDR+0x25C) #define CPRI_TX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x260) #define CPRI_RX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x264) #define CPRI_TDD_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x268) #define DDR_MONITOR_ENABLE (SPU_DRV_SM_ADDR+0x270) // 开始监测ddr性能 #define DDR_MONITOR_CNT (SPU_DRV_SM_ADDR+0x274) #define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // us as unit #define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C) // GPIO JESD TX/RX/ORX bit #define GPIO_FROM_CFG_FILE (SPU_DRV_SM_ADDR+0x280) #define GPIO_JESD_RF_BIT (GPIO_FROM_CFG_FILE+0x0) #define GPIO_JESD_RF_VALID (GPIO_FROM_CFG_FILE+0x10) #define GPIO_JESD_TRIGGER_BIT (GPIO_FROM_CFG_FILE+0x60) #define GPIO_JESD_TRIGGER_VALID (GPIO_FROM_CFG_FILE+0x70) #define SLOT_NUM_DEBUG_ADDR (0x0A4D7300) #define APE_INT_INFO_ADDR (0x0A4D7400) #define PHY_CELL_FLAG 0xAFAFAFAF #define ARM_SFN_UPDATE_FLAG 0xA5A5A5A5 #define ENABLE_SFNCAL // 使能与arm的帧号校准功能 //#define DISTRIBUTED_BS //#define INTEGRATION_BS //#define GPS_PP1S_SYNC #define GPS_LTE_OFFSET 0 // 700 // us #define GPS_NR_OFFSET 0 // 2700 // us #define LTE_NR_OFFSET 0 // 2000 // us #define SCS_MAX_NUM 2 #define MTIMER_INTEGRATED_MAX_NUM 4 #define MTIMER_DISTRIBUTED_MAX_NUM 2 typedef enum _tagScsId { SCS_1st_MTIMER_ID = 0, SCS_2nd_MTIMER_ID = 1, MTIMER_NULL = 0xFFFF }cellScsId; typedef enum _tagMtimerDistributeOptId { MTIMER_CPRI_ID = 0, MTIMER_ECPRI_ID }mtimerDistributeOptId; typedef enum _tagMtimerIntegrateOptId { MTIMER_JESD_RX0_ID = 0, MTIMER_JESD_RX1_ID, MTIMER_JESD_TX0_ID, MTIMER_JESD_TX1_ID }mtimerIntegrateOptId; typedef enum _tagAPEIntInfoId { APE_INT_TX_SLOT = 0, APE_INT_RX_SLOT = 1, APE_INT_STC_0US = 2, APE_INT_STC = 3, APE_INT_MAXNUM = 8 }numAPEIntInfoId; typedef enum _tagCtcIntType { CTC_INT_TYPE_NULL = 0, CTC_INT_TYPE_CAL_SCS0 = 1, CTC_INT_TYPE_CAL_SCS1 = 2, }numCtcIntType; typedef enum _tagProtocolID { PROTOCOL_NULL = 0, PROTOCOL_CPRI = 1, PROTOCOL_ECPRI, PROTOCOL_JESD }numProtoID; #define PROTO_OPTION_NULL 0 typedef enum _tagCpriOptionID { CPRI_OPTION_7 = 7, CPRI_OPTION_8 = 8, CPRI_OPTION_9 = 9, CPRI_OPTION_10 = 10 }CpriOptID; typedef enum _tagEcpriOptionID { ECPRI_OPTION_10G = 10, ECPRI_OPTION_25G = 25 }EcpriOptID; typedef enum _tagScsID { LTE_SCS_ID = 0, NR_SCS_30K, NR_SCS_60K, NR_SCS_120K, SCS_NULL = 0xFFFF }numScsID; typedef enum _tagFrameType { FDD_MODE = 0, TDD_MODE = 1, TDD_2500US_DOUBLE = 2, FRAME_NULL = 0xFFFF }numFrameType; typedef struct _tagCoreInt { uint32_t intNum; uint32_t intCnt; }stCoreInt; typedef struct _tagPhyScsPara { uint16_t scsId; uint16_t runCoreId; uint16_t mtimerId; uint16_t gpsOffset; // us as unit uint16_t slotPeriod; uint16_t slotNumOfTdd; uint16_t slotNumOfSfn; uint16_t reserved; uint32_t rxSlotNum; uint32_t txSlotNum; uint32_t rxSfnNum; uint32_t txSfnNum; uint32_t rxSetVal; uint32_t txSetVal; uint32_t txSlotIntFlag; uint32_t rxSlotIntFlag; // UINT64 rxSlotStcCnt; // UINT64 txSlotStcCnt; }stPhyScsPara; typedef struct _tagFrontHaulDrvPara { uint32_t protocolSel; // numProtoID uint32_t rateOption; // CpriOptID/EcpriOptID uint32_t mapOption; // CpriMapType }stFrontHaulDrvPara; typedef struct phy_timer_config_ind_t { uint32_t frameType; //0:FDD, 1:TDD, 2:TDD(双周期DDDSUDDSUU) uint32_t scsId; uint32_t runCoreId; // 此次需要建小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。 uint16_t bandWidth; //带宽:5M,10M,15M,20M,25M,30M,40M,50M,60M,80M,100M uint16_t t_period; //timer周期=t_us*num_tti, 500us, 625us, 1000us, 1250us, 2500us, 5000us, 10000us, 20000us uint16_t t_us; //物理层时隙定时长度, 125us, 250us, 500us, 1000us uint8_t num_tti; //timer周期内时隙的个数5,10,20,40,80 uint8_t num_tti_per_sfn; //一个SFN内的时隙个数 uint8_t num_t_dl[2]; //下行时隙个数 uint8_t num_t_dl_symb[2]; //S时隙内下行符号个数 uint8_t num_t_ul_symb[2]; //S时隙内上行符号个数 uint8_t num_ants[2]; //天线个数 }phy_timer_config_ind_t; typedef struct _tagPhyDelCell { uint32_t scsId; uint32_t delCoreId; // 此次需要删除小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。 }stPhyDelCell; typedef struct _tagPhyCellPara { uint32_t flag; phy_timer_config_ind_t phyPara; }stPhyCellPara; typedef struct _tagSfnPara { uint32_t scsId; uint32_t slotPeriod; // slot period, us as unit uint32_t tddPeriod; // tdd period, us as unit uint32_t tddSlotNum; // slot num of every tdd period uint32_t slotMaxNum; uint32_t ctcIntFlag; uint32_t txSlotNum; uint32_t rxSlotNum; uint32_t txSfnNum; uint32_t rxSfnNum; uint32_t symbolMaxNum; uint32_t txSymbolNum; uint32_t txSlotIntCnt; uint32_t rxSlotIntCnt; uint32_t txSymbolIntCnt; uint64_t txSlotTiming; uint64_t rxSlotTiming; }stSfnPara; typedef enum _tagCpriMapType { OTIC_MAP_FIGURE10 = 0, //option8,双模，4T4R NR小区 + 2T2R LTE小区 OTIC_MAP_FIGURE12, //option8,NR 4T4R单小区 OTIC_MAP_FIGURE16 //option10,NR 4T4R的2小区 }CpriMapType; typedef enum _tagCpriMode { NR_MODE = 0, LTE_MODE }CpriMode; void sfn_para_init(void); void phy_para_init(int32_t protocol, int32_t option); void phy_scs_para_init(int32_t scsId); int32_t get_protocol_sel(); int32_t get_protocol_opt(); void set_tx_slot_intflag(uint8_t scs, int32_t flag); int32_t get_tx_slot_intflag(uint8_t scs); void set_rx_slot_intflag(uint8_t scs, int32_t flag); int32_t get_rx_slot_intflag(uint8_t scs); void get_cpri_delay(uint32_t* delay); void get_cpri_advance(uint32_t* advance); int32_t send_cpri_csu_stop_cmd(); int32_t send_cpri_csu_start_cmd(); #endif /* COMMON_INC_PHY_PARA_H_ */