ab192ce627
2. modify timing precision from us to ns; 3. test case: case24, case34, case44, case45, case48, case41, case42.
311 lines
8.1 KiB
C
311 lines
8.1 KiB
C
#ifndef COMMON_INC_PHY_PARA_H_
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#define COMMON_INC_PHY_PARA_H_
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#include "ucp_drv_common.h"
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#define PHY_SCS_MAX_NUM 4
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#define SFN_PERIOD 10000 // 10ms
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#define SLOT_SYMBOL_NUM 14
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#define SPU_DRV_SM_ADDR (0x0A4F2000) // (0x0A4D7000) //
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#define SPU_DRV_SM_LEN (56*1024) // 56KB
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#define PROTO_SEL_ADDR (SPU_DRV_SM_ADDR+0x0)
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#define PROTO_OPT_ADDR (SPU_DRV_SM_ADDR+0x4)
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#define PHY_PARA_ADDR (SPU_DRV_SM_ADDR+0x8)
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#define PHY_CELL_ADDR (SPU_DRV_SM_ADDR+0x100)
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#define ORX_ADJUST_FLAG_ADDR (SPU_DRV_SM_ADDR+0x140)
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#define ORX_ADJUST_VAL_ADDR (SPU_DRV_SM_ADDR+0x144)
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#define STC_TOD_INT_ADDR (SPU_DRV_SM_ADDR+0x200)
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#define STC_RT_ADDR (SPU_DRV_SM_ADDR+0x204)
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#define STC_CTW_EN_ADDR (SPU_DRV_SM_ADDR+0x208)
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#define CPRI_DELAY_ADDR (SPU_DRV_SM_ADDR+0x210)
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#define CPRI_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x214)
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#define CPRI_TDD_ADVANCE_ADDR (SPU_DRV_SM_ADDR+0x218)
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#define CTC_INT_TYPE_ADDR (SPU_DRV_SM_ADDR+0x21C)
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#define ARM_SFN_VALID_ADDR (SPU_DRV_SM_ADDR+0x220) // 0xAA not valid, 0x55 valid
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#define ARM_SFN_NUM_ADDR (SPU_DRV_SM_ADDR+0x224)
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#define ARM_SFN_FLIP_ADDR (SPU_DRV_SM_ADDR+0x228)
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#define ARM_LOCK_FLAG_ADDR (SPU_DRV_SM_ADDR+0x22C)
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#define ARM_SFN_VALID_FLAG (0x55)
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#define ARM_SFN_NOTVALID_FLAG (0xAA)
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#define CSU_STOP_CMD_ADDR (SPU_DRV_SM_ADDR+0x230)
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#define CSU_UL_HEADER_DATA_OFFSET (SPU_DRV_SM_ADDR+0x234) // ul, the interval of frame header and frame data, ns as unit
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#define CSU_RX_TD_SAMPLE (SPU_DRV_SM_ADDR+0x238)
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#define CSU_TX_ADVANCE_SAMPLE (SPU_DRV_SM_ADDR+0x23C)
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#define SERDES_INIT_FLAG_ADDR (SPU_DRV_SM_ADDR+0x240) // cpri or jesd clk init finished
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#define STC_ONEPPS_OUT_ADDR (SPU_DRV_SM_ADDR+0x244)
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#define CPRI_TX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x260)
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#define CPRI_RX_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x264)
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#define CPRI_TDD_ADVANCE_PP1S_ADDR (SPU_DRV_SM_ADDR+0x268)
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#define DDR_MONITOR_ENABLE (SPU_DRV_SM_ADDR+0x270) // 开始监测ddr性能
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#define DDR_MONITOR_CNT (SPU_DRV_SM_ADDR+0x274)
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#define JESD_RF_TXOFF2RXON (SPU_DRV_SM_ADDR+0x278) // ns as unit
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#define JESD_RF_TXON2PP1S (SPU_DRV_SM_ADDR+0x27C)
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#define SLOT_NUM_DEBUG_ADDR (SPU_DRV_SM_ADDR+0x300)
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#define APE_INT_INFO_ADDR (SPU_DRV_SM_ADDR+0x400)
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// GPIO JESD TX/RX/ORX bit
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#define JESD_CFG_ADDR (SPU_DRV_SM_ADDR+0x1000) // 4KB
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#define JESD_RX_CH_PARA (JESD_CFG_ADDR+0x10)
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#define JESD_RX_SAMPLE_RATE (JESD_CFG_ADDR+0x20)
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#define JESD_RX_CLK_RATIO (JESD_CFG_ADDR+0x24) // byte0: SAM_CLK/sample_clk, byte1: CHA_CLK_sample_clk
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#define JESD_ORX_CH_PARA (JESD_CFG_ADDR+0x30)
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#define JESD_ORX_SAMPLE_RATE (JESD_CFG_ADDR+0x40)
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#define JESD_ORX_CLK_RATIO (JESD_CFG_ADDR+0x44)
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#define JESD_TX_CH_PARA (JESD_CFG_ADDR+0x50)
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#define JESD_TX_SAMPLE_RATE (JESD_CFG_ADDR+0x60)
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#define JESD_TX_CLK_RATIO (JESD_CFG_ADDR+0x64)
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#define JESD_TX1_CH_PARA (JESD_CFG_ADDR+0x70)
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#define JESD_TX1_SAMPLE_RATE (JESD_CFG_ADDR+0x80)
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#define JESD_TX1_CLK_RATIO (JESD_CFG_ADDR+0x84)
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#define GPIO_JESD_TRIGGER_BIT (JESD_CFG_ADDR+0x100)
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#define GPIO_JESD_TRIGGER_VALID (JESD_CFG_ADDR+0x110)
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#define GPIO_JESD_RF_BIT (JESD_CFG_ADDR+0x120)
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#define GPIO_JESD_RF_VALID (JESD_CFG_ADDR+0x130)
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#define PHY_CELL_FLAG 0xAFAFAFAF
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#define ARM_SFN_UPDATE_FLAG 0xA5A5A5A5
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#define ENABLE_SFNCAL // 使能与arm的帧号校准功能
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//#define DISTRIBUTED_BS
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//#define INTEGRATION_BS
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//#define GPS_PP1S_SYNC
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#define GPS_LTE_OFFSET 0 // 700 // us
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#define GPS_NR_OFFSET 0 // 2700 // us
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#define LTE_NR_OFFSET 0 // 2000 // us
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#define SCS_MAX_NUM 2
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#define MTIMER_INTEGRATED_MAX_NUM 4
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#define MTIMER_DISTRIBUTED_MAX_NUM 2
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typedef enum _tagScsId
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{
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SCS_1st_MTIMER_ID = 0,
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SCS_2nd_MTIMER_ID = 1,
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MTIMER_NULL = 0xFFFF
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}cellScsId;
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typedef enum _tagMtimerDistributeOptId
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{
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MTIMER_CPRI_ID = 0,
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MTIMER_ECPRI_ID
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}mtimerDistributeOptId;
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typedef enum _tagMtimerIntegrateOptId
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{
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MTIMER_JESD_RX0_ID = 0,
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MTIMER_JESD_RX1_ID,
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MTIMER_JESD_TX0_ID,
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MTIMER_JESD_TX1_ID
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}mtimerIntegrateOptId;
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typedef enum _tagAPEIntInfoId
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{
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APE_INT_TX_SLOT = 0,
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APE_INT_RX_SLOT = 1,
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APE_INT_STC_0US = 2,
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APE_INT_STC = 3,
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APE_INT_MAXNUM = 8
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}numAPEIntInfoId;
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typedef enum _tagCtcIntType
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{
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CTC_INT_TYPE_NULL = 0,
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CTC_INT_TYPE_CAL_SCS0 = 1,
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CTC_INT_TYPE_CAL_SCS1 = 2,
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}numCtcIntType;
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typedef enum _tagProtocolID
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{
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PROTOCOL_NULL = 0,
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PROTOCOL_CPRI = 1,
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PROTOCOL_ECPRI,
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PROTOCOL_JESD
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}numProtoID;
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#define PROTO_OPTION_NULL 0
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typedef enum _tagCpriOptionID
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{
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CPRI_OPTION_7 = 7,
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CPRI_OPTION_8 = 8,
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CPRI_OPTION_9 = 9,
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CPRI_OPTION_10 = 10
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}CpriOptID;
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typedef enum _tagEcpriOptionID
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{
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ECPRI_OPTION_10G = 10,
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ECPRI_OPTION_25G = 25
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}EcpriOptID;
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typedef enum _tagJesdOptionID
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{
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JESD_OPTION_204B = 0,
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JESD_OPTION_204C = 1
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}JesdOptID;
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typedef enum _tagScsID
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{
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LTE_SCS_ID = 0,
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NR_SCS_30K,
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NR_SCS_60K,
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NR_SCS_120K,
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SCS_NULL = 0xFFFF
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}numScsID;
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typedef enum _tagFrameType
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{
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FDD_MODE = 0,
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TDD_MODE = 1,
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TDD_2500US_DOUBLE = 2,
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FRAME_NULL = 0xFFFF
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}numFrameType;
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typedef struct _tagCoreInt
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{
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uint32_t intNum;
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uint32_t intCnt;
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}stCoreInt;
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typedef struct _tagPhyScsPara
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{
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uint16_t scsId;
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uint16_t runCoreId;
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uint16_t mtimerId;
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uint16_t gpsOffset; // us as unit
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uint16_t slotPeriod;
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uint16_t slotNumOfTdd;
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uint16_t slotNumOfSfn;
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uint16_t reserved;
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uint32_t rxSlotNum;
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uint32_t txSlotNum;
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uint32_t rxSfnNum;
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uint32_t txSfnNum;
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uint32_t rxSetVal;
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uint32_t txSetVal;
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uint32_t txSlotIntFlag;
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uint32_t rxSlotIntFlag;
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// UINT64 rxSlotStcCnt;
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// UINT64 txSlotStcCnt;
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}stPhyScsPara;
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typedef struct _tagFrontHaulDrvPara
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{
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uint32_t protocolSel; // numProtoID
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uint32_t rateOption; // CpriOptID/EcpriOptID
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uint32_t mapOption; // CpriMapType
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}stFrontHaulDrvPara;
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typedef struct phy_timer_config_ind_t
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{
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uint32_t frameType; //0:FDD, 1:TDD, 2:TDD(双周期DDDSUDDSUU)
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uint32_t scsId;
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uint32_t runCoreId; // 此次需要建小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。
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uint16_t bandWidth; //带宽:5M,10M,15M,20M,25M,30M,40M,50M,60M,80M,100M
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uint16_t t_period; //timer周期=t_us*num_tti, 500us, 625us, 1000us, 1250us, 2500us, 5000us, 10000us, 20000us
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uint16_t t_us; //物理层时隙定时长度, 125us, 250us, 500us, 1000us
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uint8_t num_tti; //timer周期内时隙的个数5,10,20,40,80
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uint8_t num_tti_per_sfn; //一个SFN内的时隙个数
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uint8_t num_t_dl[2]; //下行时隙个数
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uint8_t num_t_dl_symb[2]; //S时隙内下行符号个数
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uint8_t num_t_ul_symb[2]; //S时隙内上行符号个数
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uint8_t num_ants[2]; //天线个数
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}phy_timer_config_ind_t;
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typedef struct _tagPhyDelCell
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{
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uint32_t scsId;
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uint32_t delCoreId; // 此次需要删除小区的ape core id，bitmap方式，bit0对应ape0，bit1对应ape1，。。。
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}stPhyDelCell;
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typedef struct _tagPhyCellPara
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{
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uint32_t flag;
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phy_timer_config_ind_t phyPara;
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}stPhyCellPara;
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typedef struct _tagSfnPara
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{
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uint32_t scsId;
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uint32_t slotPeriod; // slot period, us as unit
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uint32_t tddPeriod; // tdd period, us as unit
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uint32_t tddSlotNum; // slot num of every tdd period
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uint32_t slotMaxNum;
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uint32_t ctcIntFlag;
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uint32_t txSlotNum;
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uint32_t rxSlotNum;
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uint32_t txSfnNum;
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uint32_t rxSfnNum;
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uint32_t symbolMaxNum;
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uint32_t txSymbolNum;
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uint32_t txSlotIntCnt;
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uint32_t rxSlotIntCnt;
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uint32_t txSymbolIntCnt;
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uint64_t txSlotTiming;
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uint64_t rxSlotTiming;
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}stSfnPara;
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typedef enum _tagCpriMapType
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{
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OTIC_MAP_FIGURE10 = 0, //option8,双模，4T4R NR小区 + 2T2R LTE小区
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OTIC_MAP_FIGURE12, //option8,NR 4T4R单小区
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OTIC_MAP_FIGURE16 //option10,NR 4T4R的2小区
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}CpriMapType;
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typedef enum _tagCpriMode
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{
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NR_MODE = 0,
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LTE_MODE
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}CpriMode;
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void sfn_para_init(void);
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void drv_sm_init();
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void phy_para_init(uint32_t protocol, uint32_t option);
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void phy_scs_para_init(int32_t scsId);
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int32_t get_protocol_sel();
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int32_t get_protocol_opt();
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void set_tx_slot_intflag(uint8_t scs, int32_t flag);
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int32_t get_tx_slot_intflag(uint8_t scs);
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void set_rx_slot_intflag(uint8_t scs, int32_t flag);
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int32_t get_rx_slot_intflag(uint8_t scs);
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int32_t send_cpri_csu_stop_cmd();
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int32_t send_cpri_csu_start_cmd();
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#endif /* COMMON_INC_PHY_PARA_H_ */
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